VHDL设计举例

entity mult4X4 is port(Clk, St: in bit; Mplier, Mcand: in unsigned(3 downto 0); Done: out bit);
end mult4X4; architecture behave1 of mult4X4 is
signal State: integer range 0 to 9; signal ACC: unsigned(8 downto 0); -- accumulator alias M: bit is ACC(0); -- M is bit 0 of ACC begin process(Clk) begin if Clk'event and Clk = '1' then -- executes on rising edge of clock case State is
component mult2C port(CLK, St: in bit; Mplier, Mcand: in unsigned(3 downto 0); Product: out unsigned(6 downto 0); Done: out bit);
end component;
测试器
St
乘数 被乘数 Done
DUT
数字系统VHDL设计
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11、 键盘扫描器
DUT
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键盘
DUT
4位全加器 二进制反码 被乘数
DUT
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10、 有符号整数/分数的乘法器
DUT
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10、 有符号整数/分数的乘法器
DUT
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library IEEE; use IEEE.numeric_bit.all;
entity testmult is end testmult; architecture test1 of testmult is
DUT
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10、 有符号整数/分数的乘法器
总之，有符号二进制补码小数乘法的计算过程与二进制正 小数乘法的计算过程是相同的，除了在每一步需要注意保 持部分积的符号，且如果乘数的符号为负时，在最后一步 对被乘数进行VHDL设计
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else
ACC <= '0' & ACC(8 downto 1); -- shift accumulator right
State <= State + 2;
end if;
when 2 | 4 | 6 | 8 =>
-- "shift" State
ACC <= '0' & ACC(8 downto 1); -- right shift
DUT
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HA1: HalfAdder port map (XY0(1), XY1(0), C1(0), S1(0)); HA2: HalfAdder port map (XY1(3), C1(2), C1(3), S1(3)); HA3: HalfAdder port map (S1(1), XY2(0), C2(0), S2(0)); HA4: HalfAdder port map (S2(1), XY3(0), C3(0), S3(0)); P(0) <= XY0(0); P(1) <= S1(0); P(2) <= S2(0); P(3) <= S3(0); P(4) <= S3(1); P(5) <= S3(2); P(6) <= S3(3); P(7) <= C3(3); end Behavioral;
积 CLK
乘法器
DUT
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constant N: integer := 11; type arr is array(1 to N) of unsigned(3 downto 0); type arr2 is array(1 to N) of unsigned(6 downto 0); constant Mcandarr: arr := ("0111", "1101", "0101", "1101", "0111",
St
乘数
测试器
被乘数 Done
积 CLK
乘法器
DUT
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begin
St
CLK <= not CLK after 10 ns;
乘数
process
被乘数
begin for i in 1 to N loop Mcand <= Mcandarr(i); Mplier <= Mplierarr(i);
report "Incorrect Product"
severity error;
end loop;
report "TEST COMPLETED";
end process;
mult1: mult2c port map(CLK, St, Mplier, Mcand, Product, Done);
end test1;
end if;
when 1 | 3 | 5 | 7 => -- "add/shift" State
if M = '1' then -- add multiplicand
ACC(8 downto 4) <= '0' & ACC(7 downto 4) + Mcand;
State <= State + 1;
begin XY0(0) <= X(0) and Y(0); XY0(1) <= X(1) and Y(0); XY0(2) <= X(2) and Y(0); XY0(3) <= X(3) and Y(0); XY2(0) <= X(0) and Y(2); XY2(1) <= X(1) and Y(2); XY2(2) <= X(2) and Y(2); XY2(3) <= X(3) and Y(2);
DUT
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FA1: FullAdder port map (XY0(2), XY1(1), C1(0), C1(1), S1(1)); FA2: FullAdder port map (XY0(3), XY1(2), C1(1), C1(2), S1(2)); FA3: FullAdder port map (S1(2), XY2(1), C2(0), C2(1), S2(1)); FA4: FullAdder port map (S1(3), XY2(2), C2(1), C2(2), S2(2)); FA5: FullAdder port map (C1(3), XY2(3), C2(2), C2(3), S2(3)); FA6: FullAdder port map (S2(2), XY3(1), C3(0), C3(1), S3(1)); FA7: FullAdder port map (S2(3), XY3(2), C3(1), C3(2), S3(2)); FA8: FullAdder port map (C2(3), XY3(3), C3(2), C3(3), S3(3));
DUT
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when 0=>
-- initial State
if St='1' then
ACC(8 downto 4) <= "00000"; -- begin cycle
ACC(3 downto 0) <= Mplier; -- load the multiplier
State <= 1;
"0001001", "0110001", "1001000", "1001000", "1000000", "0000000", "0000001", "0000000"); signal CLK, St, Done: bit; signal Mplier, Mcand: unsigned(3 downto 0); signal Product: unsigned(6 downto 0);
XY1(0) <= X(0) and Y(1); XY1(1) <= X(1) and Y(1); XY1(2) <= X(2) and Y(1); XY1(3) <= X(3) and Y(1); XY3(0) <= X(0) and Y(3); XY3(1) <= X(1) and Y(3); XY3(2) <= X(2) and Y(3); XY3(3) <= X(3) and Y(3);
测试器
Done 积
CLK
乘法器
St <= '1';
wait until CLK = '1' and CLK'event;
St <= '0';
wait until Done = '0' and Done'event;
assert Product = Productarr(i)
-- compare with expected answer
architecture Behavioral of Array_Mult is signal C1, C2, C3: bit_vector(3 downto 0); signal S1, S2, S3: bit_vector(3 downto 0); signal XY0, XY1, XY2, XY3: bit_vector(3 downto 0); component FullAdder
"1000", "0111", "1000", "0000", "1111", "1011"); constant Mplierarr: arr := ("0101", "0101", "1101", "1101", "0111",
"0111", "1000", "1000", "1101", "1111", "0000"); constant Productarr: arr2 := ("0100011", "1110001", "1110001",
State <= State + 1;
when 9 =>
-- end of cycle
State <= 0;
end case;
end if;
end process;
Done <= '1' when State = 9 else '0';
DUT
end behave1;
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9、 阵列乘法器
数字系统的VHDL设计
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DUT
2009年 夏季
数字系统VHDL设计
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4.8 移位-加法结构乘法器
部分积只能是被乘数(1101)进行适当移位后的结果或者0 每个部分积一形成立刻加到一起，而不是等得到所有的部分积后再加到
一起，这样做避免了一次计算两个以上的二进制数加法。
被乘数 乘数
部分积
DUT
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连续-并行乘法器
积
控 制
控 制 DUT
积
4位加法器
乘数
积
被乘数
控
制
4位加法器
乘数
4位加法器 数字系乘统数VHDL设计
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积
积
控
制
4位加法器
乘数
积
被乘数
控 制 4位加法器 被乘数
DUT
4位加法乘器 积寄存器乘初数始值
(由于M=1，所以加被乘数)
求和后结果
port(X, Y, Cin: in bit; Cout, Sum: out bit);
end component; component HalfAdder
port(X, Y: in bit; Cout, Sum: out bit);
end component;
DUT
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乘数
移位后结果
被(由乘数于M=1，所以加被乘数)
求和后结果
移位后结果
(由于M=0，所以跳过加法)
移位后结果
(由于M=1，所以加被乘数)
求和后结果
移位后结果(最终结果)
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积和乘数的分隔线
DUT
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library IEEE; use IEEE.numeric_bit.all;
DUT
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延迟:8tad+tg
DUT
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entity Array_Mult is port(X, Y: in bit_vector(3 downto 0); P: out bit_vector(7 downto 0));
end Array_Mult;