DSPBuilder设计入门
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Optimized For High-Performance, Repetitive and Numerically Intensive Tasks
Hardware – Fixed & Floating Point Multipliers – Co-Processors – Special Memory Structures Multiple Access Memories For Faster Computations
内容与要点
主要内容：
– DSP Builder 工具介绍；设计流Байду номын сангаас；设计规范；模 块库；设计实例。
本章要点：
– DSP Builder 设计流程、规范；Simulink模型仿真； 利用MATLAB建模工具和DSP Builder开发环境， 认识如何将算法级仿真向硬件模块实现过渡的设计 过程。
目录(1)
that Can Be Programmed for Various Functions “Glue” Logic Customizable Hardware Solution Configurable Processors
DSP Processors vs. FPGAs
High Speed DSP Processor
Complete Hardware Implementation
FPGA / DSP Challenges
Designing With FPGAs Is Different!!
– Different Set of Tools – C-Code vs. VHDL / Verilog
Extending Range of Altera Reconfigurable DSP Solutions
New!
Performance (MMACs/sec)
600 100 -
Embedded Processors
Embedded Processors Hardware Acceleration
Nios®, Nios II
Tools
– Quartus® II Software – SOPC Builder – DSP Builder – Nios II IDE
Agenda
Overview Designing with DSP Builder Library Blocks Simulating & Debugging with DSP Builder Intellectual Property (IP) Implementation FIR, NCO and FFT IP Functions
High Level of Parallel Processing in FPGA
MAC MAC
MAC MAC
1-8 Multipliers
Needs looping for more than 8 multiplications
Needs multiple clock cycles because of serial computation
Implementing DSP Designs in FPGA
Overview
The Programmable Solutions Company®
Devices
– Stratix® II™ – Cyclone™ II – Stratix GX – Stratix – Cyclone
Devices (continued)
Appendix Introduction to Altera Devices Hardware Acceleration Using Nios II
What Is a DSP Processor?
Microprocessor With Specialized Instructions & Hardware for DSP Applications
200 Tap FIR Filter would need 25+ clock cycles per sample with an 8 MAC unit processor
MAC MAC MAC MAC MAC MAC MAC MAC
MAC MAC MAC MAC MAC MAC MAC MAC
MAC MAC MAC MAC MAC MAC MAC MAC
– MAX® II – Mercury™ Devices – ACEX® Devices – FLEX® Devices – MAX Devices
Intellectual Property (IP)
– Signal Processing – Communications – Embedded Processors
第一节、 DSP Builder概述
– DSP Builder概述 – DSP Builder特性 – DSP Builder设计流程 – DSP Builder软件安装 – 实例
目录(2)
第二节、 Altera DSP Builder模块库
– AltLab库 – 算术库 – 总线控制库 – 复信号处理库 – Rate Change模块库 – 状态机函数库 – 存储器(Storage）模块库 – MegaCore函数支持 – 其它库
MAC MAC MAC MAC MAC MAC MAC MAC
Can implement hundreds of MAC functions in an FPGA
Parallel implementation allows for faster throughput
– 200 Tap FIR Filter would need 1 clock cycle per sample
Run Arithmetic Calculations Faster than General Processors
What Is an FPGA?
Field Programmable Gate Array Device that Has a Regular Architecture (Set of Blocks)
Hardware – Fixed & Floating Point Multipliers – Co-Processors – Special Memory Structures Multiple Access Memories For Faster Computations
内容与要点
主要内容：
– DSP Builder 工具介绍；设计流Байду номын сангаас；设计规范；模 块库；设计实例。
本章要点：
– DSP Builder 设计流程、规范；Simulink模型仿真； 利用MATLAB建模工具和DSP Builder开发环境， 认识如何将算法级仿真向硬件模块实现过渡的设计 过程。
目录(1)
that Can Be Programmed for Various Functions “Glue” Logic Customizable Hardware Solution Configurable Processors
DSP Processors vs. FPGAs
High Speed DSP Processor
Complete Hardware Implementation
FPGA / DSP Challenges
Designing With FPGAs Is Different!!
– Different Set of Tools – C-Code vs. VHDL / Verilog
Extending Range of Altera Reconfigurable DSP Solutions
New!
Performance (MMACs/sec)
600 100 -
Embedded Processors
Embedded Processors Hardware Acceleration
Nios®, Nios II
Tools
– Quartus® II Software – SOPC Builder – DSP Builder – Nios II IDE
Agenda
Overview Designing with DSP Builder Library Blocks Simulating & Debugging with DSP Builder Intellectual Property (IP) Implementation FIR, NCO and FFT IP Functions
High Level of Parallel Processing in FPGA
MAC MAC
MAC MAC
1-8 Multipliers
Needs looping for more than 8 multiplications
Needs multiple clock cycles because of serial computation
Implementing DSP Designs in FPGA
Overview
The Programmable Solutions Company®
Devices
– Stratix® II™ – Cyclone™ II – Stratix GX – Stratix – Cyclone
Devices (continued)
Appendix Introduction to Altera Devices Hardware Acceleration Using Nios II
What Is a DSP Processor?
Microprocessor With Specialized Instructions & Hardware for DSP Applications
200 Tap FIR Filter would need 25+ clock cycles per sample with an 8 MAC unit processor
MAC MAC MAC MAC MAC MAC MAC MAC
MAC MAC MAC MAC MAC MAC MAC MAC
MAC MAC MAC MAC MAC MAC MAC MAC
– MAX® II – Mercury™ Devices – ACEX® Devices – FLEX® Devices – MAX Devices
Intellectual Property (IP)
– Signal Processing – Communications – Embedded Processors
第一节、 DSP Builder概述
– DSP Builder概述 – DSP Builder特性 – DSP Builder设计流程 – DSP Builder软件安装 – 实例
目录(2)
第二节、 Altera DSP Builder模块库
– AltLab库 – 算术库 – 总线控制库 – 复信号处理库 – Rate Change模块库 – 状态机函数库 – 存储器(Storage）模块库 – MegaCore函数支持 – 其它库
MAC MAC MAC MAC MAC MAC MAC MAC
Can implement hundreds of MAC functions in an FPGA
Parallel implementation allows for faster throughput
– 200 Tap FIR Filter would need 1 clock cycle per sample
Run Arithmetic Calculations Faster than General Processors
What Is an FPGA?
Field Programmable Gate Array Device that Has a Regular Architecture (Set of Blocks)