CMOS芯片原理和产品介绍

• Radiation hardness
• Color

CMOS 芯片的特性功能
Features Region of Interest: Makes it possible to address a certain area of the sensor and read this part out with a higher speed. Typically full row addressing, column addressing if required. Binning: Gives higher DR and speed with a reduced resolution. Typically 2x2 binning: +50% DR and 2.5 x more speed

CMOS 图像传感器基本结构
Row Decoder
Pixel
Column Amplifiers (and ADC)
Column Mux
Output Amplifier
Spatial information accessed through direct addressing – each pixel has its own sense node and sense amplifier

CMOS 芯片的特性功能
Features Color: Application of on-chip color filters allows color imaging. Typically RGGB Bayer pattern.

V-CCD PD PD+amp MOS switch
Row selection
amp
H CCD
Column selection
Interline Transfer CCD
CMOS Active Pixel Sensor

CMOS Imager vs. CCD

CMOS 芯片的特性功能
Features
Multi slope linear:
Gives the opportunity to extend the Dynamic Range. The sensor mimics a logarithmic response by multiple linear slopes. Typically: 4 knees, fully programmable, + 30 dB Dynamic Range
I
COL

CMOS 图像传感器基本结构- 有源 (6T) 像元结构
6T-pixel
light
Metal screen
PR VDD SPL VDD Cps VDD
data column
Vref VSS
Csn
ROW
3T pixel with in-pixel sample-and-hold (S/H)
CMOS Imager Architecture
Row address decoder + Timing & Control drivers
Pixel array
Output buffer Column amplifiers
analog out
Clock
Column address decoder+ multiplexer
CMOS allows high system integration Level
CCD Image Sensor
ic3
Timing Generator
ic1
Drivers
ic2
ASP
ic4
ADC
ic5
DSP
ic6
1- or 2-Chip CMOS Camera


CMOS 芯片实例
Digital Unit
Row Address Decoder
10-bit A-D Converter
Programmable Gain Amplifier Biasing & Voltage Refrence Column Address Decoder Analog Processing Unit
COL

CMOS 图像传感器基本结构- 有源 (3T) 像元结构
RST VDD
ROW
I
One amplifier per pixel – actively drive column data bus High CCE No internal charge transfer Correlated Double Sampling (CDS) not possible – high reset noise
Dark current
900
900
No difference expected

CMOS 芯片的特性功能
Features • Region of Interest • Binning • Multi slope linear • Anti blooming
CMOS芯片分类标准
Blemishes
Dark Pixel Defect in dark, signal >300 DN higher than neighboring pixels (nominal gain) at 50% saturation, signal deviates by more than ±30% from neighboring pixels (nominal gain) ≤5 pixel defects within a sub-area of 3*3 pixels >5 pixel defects within a sub-area of 3*3 pixels >8 pixel defects in a 1*12 kernel (minimum 3 good columns between defective columns) >8 pixel defects in a 12*1 kernel (minimum 3 good rows between defective rows)
CDS
ADC
OIF
Timing generator
division between “sensor” and “camera” is adjustable – driven by application requirements

IT-CCD and Basic CMOS Architecture
COL

CMOS 图像传感器基本结构- 有源 (4T) 像元结构
RST VDD
ROW TCK
I
PPD photosite – charge transfer within pixel Mode #1: CDS possible – eliminate reset noise Mode #2: Global Shutter possible – eliminate motion artifacts

CMOS 图像传感器基本结构- 无源 (1T) 像元结构
ROW
No amplifier in pixel – share photocharge on column data bus Low “Charge Conversion Efficiency (CCE)”

CMOS 图像传感器基本结构
5T vs. 6T (e.g. for 6 µ m pixel)
5T PPD
QExFF, w. ML Read noise PRNU FPN Voltage swing Power 60% 60el 1.5% 100 el 1V 100%
Readout signal
Multi-Slope Response
IIlumination

CMOS 芯片的特性功能
Features Anti blooming: Allows the excess charge in overexposure condition to be removed without affecting the surrounding pixels: Typically 1000x antiblooming. Radiation hardness: Is mainly determined by the photo diode. Device needs to withstand single events. Typically PPD devices can reach a 50-100 krad hardness.
Light Pixel Defect
Cluster Defect Spot Defect Column Defect
Row Defect

CMOS 相机结构
CMOS CCD
Vertical drivers Vert. Addr.
Pixel Array
Column Circuits Hor. addressing
AGC
ADCDig.outDAC源自Address Counter
Int. time control
DSP
Average & black ref.

Main Challenges in CMOS Pixels
Extremely low leakage current and FPN (imager is the most critical device for CMOS technology) Low noise adding of “charge packets” (=binning), used for resolution reduction (pre-view, etc.). Easy to implement in CCD (operates in charge domain) but not straightforward in CMOS (voltage or current domain). In an extreme this is also used for TDI devices (step too far for CMOS?) Improved light angle dependency by stack height lowering, preventing cross color: ore severe for small pixels Scanning: CCD takes a snapshot (all pixels integrate at the same time); basic CMOS has a rolling shutter (all pixels integrate for the same time, but starting
COL

CMOS 图像传感器基本结构- 有源 (5T) 像元结构
PRST RST VDD
ROW TCK
PPD photosite – charge transfer within pixel Add switch to independently reset photosite Global Shutter with Electronic Exposure Control possible Mirrors functionality of CCD Interline Transfer (ILT) technology
6T PPD
50% 65el 2% 300 el 0.5V 120%
Why different?
Due to reduced FF 6T Due to limited voltage swing 6T Additional amp 6T For simul. Read-out/Integration DS unable in 6T Due to double voltage drop in 6T Double number of Current Sources