SoC设计方法和实现第二章 设计流程
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.db .lib
Synthesis
Design Compiler Power Compiler
PrimeTime
ห้องสมุดไป่ตู้Constraints
.def .lef .tlf .ctl
Pre-layout Function Timing
Layout
Post-layout Function Timing
SDF
Astro SoC Encounter
D e s ig n
S p e c ific a tio n
F lo a tin g /F ix e d P o in t M o d e lin g
C /C + + S ystem C M A TLA B C ow are spw S e a m le s s
T est V ecto rs
B e h a v io ra l F u n c tio n
《SoC设计方法与实现》
郭炜 郭筝 谢憬
第二章
SoC设计流程
Outlines
• Hardware/software (HW/SW) co-
design flow
• Standard cell based design flow
Duality of Software and Hardware
• The hardware and software in an
功耗分析 信号完整性
优化 寄生参数提取 布局后仿真
形式验证 形式验证
Detailed Design Flow – cont.
静态时序分析
No
OK? No
ECO修改
后仿真
OK? Yes
物理验证
交付芯片制造厂
Yes
形式验证
《SoC设计方法与实现》
郭炜 郭筝 谢憬
Thank you
embedded system work together to solve a problem
• How to partition is usually dictated by
speed and cost
Dedicated hardware is fast, inflexible and expensive
Can be factors of 10X, 100X or greater speed increase Requires less processor complexity, so overall system is
simpler Less software design time required Unless hardware bug is fatal, workarounds might be
doable in software
• Hardware solution: CON
Large NRE charges Potentially long development cycle Little or no margin for error
Only 50% of ASIC ICs work the first time IP Royalty charges Hardware design tools can be very costly
HW/SW
ESL Co-design Flow
SoC Design Flow
• Hardware/software co-design flow • Detailed hardware design flow
Standard Cell Based ASIC Design Flow
S ystem A rc h ite c tu re
HW/SW – Pro and Con
• Software solution: PRO
No additional impact on materials costs, power requirements, circuit complexity
Bugs are easily dealt with, even in the field! Software design tools are relatively inexpensive Not sensitive to sales volumes
• ESL design make co-design easier
HW/SW partitioning Co-specification, co-analysis, co-simulation,
co-verification Interface synthesis Verification of complete system – both
Reconfigurable hardware is fast, flexible and more expensive
Software is slower, more flexible and cheaper
HW/SW – Pro and Con
• Hardware solution: PRO
RTL F u n c tio n
V e rilo g /V H D L
VCS M o d e ls im N C -V e rilo g /V H D L
Traditional ASIC Design Flow – cont.
Test Vectors
Hardware Backend Design
A rc h ite c tu ra l D e fin itio n a n d A n a ly s is
H a rd w a re /S o ftw a re P a rtitio n in g
H ardw are F ro n ten d D e s ig n
R T L c o d in g
Bigger, faster, processors More memory Bigger power supply
RTOS may be necessary (royalties) More uncertainty in software development schedule
HW/SW Co-Design: New Design Methodology
• Software solutions: CON
Relative performance versus hardware is generally far inferior
Additional algorithmic requirements forces more processing power
SDF
GDSII
Detailed Design Flow
硬件设计定义
模块设计及IP复用 顶层模块集成
前仿真
逻辑综合
静态时序分析
版图布局规划
电源网络功耗分析
单元布局和优化
Detailed Design Flow – cont.
静态时序分析
网表 、SDF文件
静态时序分析
DFT插入 时钟树综合 布线设计
Synthesis
Design Compiler Power Compiler
PrimeTime
ห้องสมุดไป่ตู้Constraints
.def .lef .tlf .ctl
Pre-layout Function Timing
Layout
Post-layout Function Timing
SDF
Astro SoC Encounter
D e s ig n
S p e c ific a tio n
F lo a tin g /F ix e d P o in t M o d e lin g
C /C + + S ystem C M A TLA B C ow are spw S e a m le s s
T est V ecto rs
B e h a v io ra l F u n c tio n
《SoC设计方法与实现》
郭炜 郭筝 谢憬
第二章
SoC设计流程
Outlines
• Hardware/software (HW/SW) co-
design flow
• Standard cell based design flow
Duality of Software and Hardware
• The hardware and software in an
功耗分析 信号完整性
优化 寄生参数提取 布局后仿真
形式验证 形式验证
Detailed Design Flow – cont.
静态时序分析
No
OK? No
ECO修改
后仿真
OK? Yes
物理验证
交付芯片制造厂
Yes
形式验证
《SoC设计方法与实现》
郭炜 郭筝 谢憬
Thank you
embedded system work together to solve a problem
• How to partition is usually dictated by
speed and cost
Dedicated hardware is fast, inflexible and expensive
Can be factors of 10X, 100X or greater speed increase Requires less processor complexity, so overall system is
simpler Less software design time required Unless hardware bug is fatal, workarounds might be
doable in software
• Hardware solution: CON
Large NRE charges Potentially long development cycle Little or no margin for error
Only 50% of ASIC ICs work the first time IP Royalty charges Hardware design tools can be very costly
HW/SW
ESL Co-design Flow
SoC Design Flow
• Hardware/software co-design flow • Detailed hardware design flow
Standard Cell Based ASIC Design Flow
S ystem A rc h ite c tu re
HW/SW – Pro and Con
• Software solution: PRO
No additional impact on materials costs, power requirements, circuit complexity
Bugs are easily dealt with, even in the field! Software design tools are relatively inexpensive Not sensitive to sales volumes
• ESL design make co-design easier
HW/SW partitioning Co-specification, co-analysis, co-simulation,
co-verification Interface synthesis Verification of complete system – both
Reconfigurable hardware is fast, flexible and more expensive
Software is slower, more flexible and cheaper
HW/SW – Pro and Con
• Hardware solution: PRO
RTL F u n c tio n
V e rilo g /V H D L
VCS M o d e ls im N C -V e rilo g /V H D L
Traditional ASIC Design Flow – cont.
Test Vectors
Hardware Backend Design
A rc h ite c tu ra l D e fin itio n a n d A n a ly s is
H a rd w a re /S o ftw a re P a rtitio n in g
H ardw are F ro n ten d D e s ig n
R T L c o d in g
Bigger, faster, processors More memory Bigger power supply
RTOS may be necessary (royalties) More uncertainty in software development schedule
HW/SW Co-Design: New Design Methodology
• Software solutions: CON
Relative performance versus hardware is generally far inferior
Additional algorithmic requirements forces more processing power
SDF
GDSII
Detailed Design Flow
硬件设计定义
模块设计及IP复用 顶层模块集成
前仿真
逻辑综合
静态时序分析
版图布局规划
电源网络功耗分析
单元布局和优化
Detailed Design Flow – cont.
静态时序分析
网表 、SDF文件
静态时序分析
DFT插入 时钟树综合 布线设计