LD7126中文资料

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W681512S中文资料

7.1. Transmit Path ................................................................................................................................ 8 7.2. Receive Path ................................................................................................................................. 9 7.3. Power Management..................................................................................................................... 10
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM .............................................................................................................................. 3 4. TABLE OF CONTENTS ...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 6 6. PIN DESCRIPTION ............................................................................................................................. 7 7. FUNCTIONAL DESCRIPTION............................................................................................................ 8

ICL7129CPL中文资料

元器件交易网
ICL7129
August 1997
41/2 Digit LCD, Single-Chip A/D Converter
Features
• ±19,999 Count A/D Converter Accurate to ±4 Count • 10µV Resolution on 200mV Scale • 110dB CMRR • Direct LCD Display Drive • True Differential Input and Reference • Low Power Consumption • Decimal Point Drive Outputs • Overrange and Underrange Outputs • Low Battery Detection and Indication • 10:1 Range Change Input
LOW BATTERY CONTINUITY
OR UR DP2 DP1 DP3 DP3
V+ 5pF (MICA)
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ICL7129ຫໍສະໝຸດ 120kHz4039
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560pF
1.2kΩ
144 43 42 41 40
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AD5689R AD5687R AD5689 AD5687 AD5697R nanoDAC+双通道数

Document FeedbackTechnical Support One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Information furnished by Analog Devices is believed to be accurate and reliable. However , noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Speci cations subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.ADI 中文版数据手册是英文版数据手册的译文，敬请谅解翻译中可能存在的语言组织或翻译错误，ADI 不对翻译中存在的差异或由此产生的错误负责。

如需确认任何词语的准确性，请参考ADI 提供的最新英文版数据手册。

R ev. 0Tel: 781.329.4700 ©2013Analog Devices, Inc. All rights reserved.功能框图图1.表1. 双通道nanoDAC+器件接口基准电压源 16位 12位 SPI 内部 AD5689R AD5687R 外部 AD5689AD5687I 2C 内部 AD5697R外部SCLV LOGICSDAA1A0INPUT REGISTER DAC REGISTER STRING DAC ABUFFERV OUT AINPUT REGISTER DAC REGISTER STRING DAC BBUFFERV OUT BV REFGNDV DDPOWER-DOWN LOGICPOWER-ON RESET GAIN =×1/×2I N T E R F A C E L O G I CRSTSEL GAINLDAC RESET AD5697R2.5VREFERENCE11253-001产品特性低漂移2.5 V 基准电压源：2 ppm/°C(典型值) 小型封装：3 mm × 3 mm 、16引脚LFCSP 总不可调整误差(TUE)：±0.1% FSR(最大值)偏置误差：±1.5 mV(最大值) 增益误差：±0.1% FSR(最大值)高驱动能力：20 mA ，0.5 V(供电轨)用户可选增益：1或2(GAIN 引脚)复位到零电平或中间电平(RSTSEL 引脚)1.8 V 逻辑兼容低毛刺：0.5 nV-sec400 kHz I2C 兼容型串行接口鲁棒的HBM(额定值为3.5 kV)和FICDM ESD(额定值为1.5 kV)性能低功耗：3.3 mW(3 V)2.7 V 至5.5 V 电源温度范围：−40°C 至+105°C应用基站功率放大器过程控制(可编程逻辑控制器[PLC] I/O 卡)工业自动化数据采集系统概述AD5697R 属于nano DAC+™系列，是一款低功耗、双通道、12位缓冲电压输出数模转换器(DAC)。

关于LM7806详细中文资料

关于LM7‎806详细‎中文资料目录1.lm780‎6介绍2.实际应用3.引脚序号、引脚功能4.lm780‎6应用电路‎5.7806电‎参数三端稳压集‎成电路lm‎7806。

电子产品中‎，常见的三端‎稳压集成电‎路有正电压‎输出的lm‎78 ×× 系列和负电‎压输出的l‎m79××系列。

顾名思义，三端IC是‎指这种稳压‎用的集成电‎路，只有三条引‎脚输出，分别是输入‎端、接地端和输‎出端。

它的样子象‎是普通的三‎极管，TO- 220 的标准封装‎，也有lm9‎013样子‎的TO-92封装。

1.lm780‎6介绍用lm78‎/lm79系‎列三端稳压‎I C来组成‎稳压电源所‎需的外围元‎件极少，电路内部还‎有过流、过热及调整‎管的保护电‎路，使用起来可‎靠、方便，而且价格便‎宜。

该系列集成‎稳压IC型‎号中的lm‎78或lm‎79后面的‎数字代表该‎三端集成稳‎压电路的输‎出电压，如lm78‎06表示输‎出电压为正‎6V，lm790‎9表示输出‎电压为负9‎V。

因为三端固‎定集成稳压‎电路的使用‎方便，电子制作中‎经常采用。

最大输出电‎流1.5A，LM78X‎X系列输出‎电压分别为‎5V;6V;8V;9V;10V;12V;15V;18V;24V。

2.实际应用在实际应用‎中，应在三端集‎成稳压电路‎上安装足够‎大的散热器‎（当然小功率‎7806I‎C内部电路‎图.的条件下不‎用）。

当稳压管温‎度过高时，稳压性能将‎变差，甚至损坏。

当制作中需‎要一个能输‎出1.5A以上电‎流的稳压电‎源，通常采用几‎块三端稳压‎电路并联起‎来，使其最大输‎出电流为N‎个1.5A，但应用时需‎注意：并联使用的‎集成稳压电‎路应采用同‎一厂家、同一批号的‎产品，以保证参数‎的一致。

另外在输出‎电流上留有‎一定的余量‎，以避免个别‎集成稳压电‎路失效时导‎致其他电路‎的连锁烧毁‎。

在lm78‎** 、lm79 ** 系列三端稳‎压器中最常‎应用的是T‎O-220 和TO-202 两种封装。

LD7552芯片内部结构及工作原理

一、LD7552芯片内部结构及工作原理图1是LD7552的内部结构图。

主要由欠压锁定电路（UVLO）、工作振荡器和绿色模式振荡器、前沿消隐电路、斜率补偿电路、末级驱动电路等组成。

欠压锁定电路也叫低压关断模式，芯片内部的电压检测器对供电电压进行监测，以确保电压当供电电压低于IC的开启门限电压时进行保护。

欠压关断模式可保证IC在供电电压不足时不至于被损坏。

也保证后级电路不至于因为激励不足而出问题。

对于LD7552来讲，供电电压低于11.4V时，欠压保护模式启动，只有当供电电压再次恢复到16V以上时，芯片才重新开始输出激励信号。

LD7552内部有两个振荡器，一个是正常工作振荡器，一个是绿色模式振荡器。

在正常工作时绿色模式振荡器不启动，确保输出频率和波形的稳定。

在待机或者空载情况下，绿色模式振荡器启动，降低开关频率，有效减少功耗，降低温度，能够确保在待机状态系统功耗小于0.3W以下，符合欧洲节能标准要求。

前沿消隐电路是对反馈电流信号和电压信号的峰值进行监测，在250ns内不予通过，防止控制电路误触发造成输出大幅度波动。

+ b4 B/ t$ ~) B5 _# M由于电流控制模式的固有缺陷，在占空比达到50％时，斜率补偿是必要的，因此芯片内置了斜坡振荡器，进行斜率补偿，简化了外围电路设计。

引脚功能介绍：3 i+ [( @6 Q" D①接地。

内部电路公共接地端。

②比较电压反馈引脚。

（补偿过程类似uc384x 芯片），由连接的光电耦合器反馈电压信号，实现控制。

同时该脚还兼任开关机控制功能，当反馈电压低于 1.2V 时，系统处于待机模式。

, {7 H& O; F, X! l7 J2 G5 p. h7 K③电源供电。

LD7552的典型供电电压是36V。

外接高压启动电阻和高频变压器的反馈供电。

在启动瞬间，由于供电电压低于UVLO 的门槛电压，所以没有激励脉冲产生，通过高压启动电阻为LD7552提供必要的启动电流（25μA），直到高频变压器的辅助绕组产生反馈供电。

ADC12062CIVF中文资料

TL H 11490ADC12062 12-Bit1 MHz 75 mW A D Converter with Input Multiplexer and Sample HoldDecember1994 ADC1206212-Bit 1MHz 75mW A D Converterwith Input Multiplexer and Sample HoldGeneral DescriptionUsing an innovative multistep conversion technique the12-bit ADC12062CMOS analog-to-digital converter digitizessignals at a1MHz sampling rate while consuming a maxi-mum of only75mW on a single a5V supply TheADC12062performs a12-bit conversion in three lower-res-olution‘‘flash’’conversions yielding a fast A D without thecost and power dissipation associated with true flash ap-proachesThe analog input voltage to the ADC12062is tracked andheld by an internal sampling circuit allowing high frequencyinput signals to be accurately digitized without the need foran external sample-and-hold circuit The multiplexer outputis available to the user in order to perform additional exter-nal signal processing before the signal is digitizedWhen the converter is not digitizing signals it can be placedin the Standby mode typical power consumption in thismode is100m WFeaturesY Built-in sample-and-holdY Single a5V supplyY Single channel or2channel multiplexer operationY Low Power Standby modeKey SpecificationsY Sampling rate1MHz(min)Y Conversion time740ns(typ)Y Signal-to-Noise Ratio f IN e100kHz69 5dB(min)Y Power dissipation(f s e1MHz)75mW(max)Y No missing codes over temperature GuaranteedApplicationsY Digital signal processor front endsY InstrumentationY Disk drivesY Mobile telecommunicationsY Waveform digitizersBlock DiagramTL H 11490–1 Ordering InformationIndustrial(b40 C s T A s a85 )PackageADC12062BIV V44Plastic Leaded Chip CarrierADC12062BIVF VGZ44A Plastic Quad Flat PackageADC12062CIV V44Plastic Leaded Chip CarrierADC12062CIVF VGZ44A Plastic Quad Flat PackageADC12062EVAL Evaluation BoardTRI-STATE is a registered trademark of National Semiconductor CorporationC1995National Semiconductor Corporation RRD-B30M75 Printed in U S AAbsolute Maximum Ratings(Notes1 2)If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage(V CC e DV CC e AV CC)b0 3V to a6V Voltage at Any Input or Output b0 3V to V CC a0 3V Input Current at Any Pin(Note3)25mA Package Input Current(Note3)50mA Power Dissipation(Note4)875mW ESD Susceptibility(Note5)2000V Soldering Information(Note6)V Package Infrared 15seconds a300 C VF PackageVapor Phase(60seconds)a215 C Infrared(15seconds)a220 C Storage Temperature Range b65 C to a150 C Maximum Junction Temperature(T JMAX)150 C Operating Ratings(Notes1 2)Temperature Range T MIN s T A s T MAX ADC12062BIV ADC12062CIVADC12062BIVF ADC12062CIVF b40 C s T A s a85 C Supply Voltage Range(DV CC e AV CC)4 5V to5 5VConverter Characteristics The following specifications apply for DV CC e AV CC e a5V V REF a(SENSE)e a4 096V V REF b(SENSE)e AGND and f s e1MHz unless otherwise specified Boldface limits apply for T A e T J from T MIN to T MAX all other limits T A e T J e a25 CSymbol Parameter ConditionsTyp Limit Units (Note7)(Note8)(Limit)Resolution12BitsDifferential Linearity Error T A e25 C g0 4g0 8LSB(max)T MIN to T MAX g0 95LSB(max)Integral Linearity Error T MIN to T MAX(BIV Suffix)g0 4g1 0LSB(max) (Note9)TA e a25 C(CIV Suffix)g0 4g1 0LSB(max)T MIN to T MAX(CIV Suffix)g1 5LSB(max) Offset Error T MIN to T MAX(BIV Suffix)g0 3g1 25LSB(max)T A e a25 C(CIV Suffix)g0 3g1 25LSB(max)T MIN to T MAX(CIV Suffix)g2 0LSB(max) Full Scale Error T MIN to T MAX(BIV Suffix)g0 2g1 0LSB(max)T A e a25 C(CIV Suffix)g0 2g1 0LSB(max)T MIN to T MAX(CIV Suffix)g1 5LSB(max) Power Supply Sensitivity DV CC e AV CC e5V g10%g1 0LSB(max) (Note15)R REF Reference Resistance750500X(min) 1000X(max)V REF(a)V REF a(SENSE)Input Voltage AV CC V(max)V REF(b)V REF b(SENSE)Input Voltage AGND V(min)V IN Input Voltage Range To V IN1 V IN2 or ADC IN AV CC a0 05V V(max)AGND b0 05V V(min) ADC IN Input Leakage AGND to AV CC b0 3V0 13m A(max) C ADC ADC IN Input Capacitance25pFMUX On-Channel Leakage AGND to AV CC b0 3V0 13m A(max)MUX Off-Channel Leakage AGND to AV CC b0 3V0 13m A(max) C MUX Multiplexer Input Cap7pFMUX Off Isolation f IN e100kHz92dB2Dynamic Characteristics(Note10)The following specifications apply for DV CC e AV CC e a5V V REF a(SENSE)e a4 096V V REF b(SENSE)e AGND R S e25X f IN e100kHz 0dB from fullscale and f s e1MHz unless otherwise specified Boldface limits apply for T A e T J from T MIN to T MAX all other limits T A e T J e a25 CSymbol Parameter ConditionsTyp Limit Units (Note7)(Note8)(Limit)SINAD Signal-to-Noise Plus T MIN to T MAX7168 0dB(min) Distortion RatioSNR Signal-to-Noise Ratio T MIN to T MAX7269 5dB(min) (Note11)THD Total Harmonic Distortion T A e a25 C b82b74dBc(max) (Note12)T MIN to T MAX b70dBc(max) ENOB Effective Number of Bits T MIN to T MAX11 511 0Bits(min) (Note13)IMD Intermodulation Distortion f IN e102 3kHz 102 7kHz b80dBc DC Electrical Characteristics The following specifications apply for DV CC e AV CC e a5V V REF a(SENSE)e a4 096V V REF b(SENSE)e AGND and f s e1MHz unless otherwise specified Boldface limits apply for T A e T J from T MIN to T MAX all other limits T A e T J e a25 CSymbol Parameter ConditionsTyp Limit Units (Note7)(Note8)(Limit)V IN(1)Logical‘‘1’’Input Voltage DV CC e AV CC e a5 5V2 0V(min)V IN(0)Logical‘‘0’’Input Voltage DV CC e AV CC e a4 5V0 8V(max) I IN(1)Logical‘‘1’’Input Current0 11 0m A(max) I IN(0)Logical‘‘0’’Input Current0 11 0m A(max)V OUT(1)Logical‘‘1’’Output Voltage DV CC e AV CC e a4 5VI OUT e b360m A2 4V(min)I OUT e b100m A4 25V(min) V OUT(0)Logical‘‘0’’Output Voltage DV CC e AV CC e a4 5V0 4V(max)I OUT e1 6mAI OUT TRI-STATE Output Pins DB0–DB110 13m A(max)Leakage CurrentC OUT TRI-STATE Output Capacitance Pins DB0–DB115pFC IN Digital Input Capacitance4pFDI CC DV CC Supply Current23mA(max) AI CC AV CC Supply Current1012mA(max) I STANDBY Standby Current(DI CC a AI CC)PD e0V20m A3AC Electrical Characteristics The following specifications apply for DV CC e AV CC e a5V V REF a(SENSE)e a4 096V V REF b(SENSE)e AGND and f s e1MHz unless otherwise specified Boldface limits apply for T A e T J from T MIN to T MAX all other limits T A e T J e a25 CSymbol Parameter ConditionsTyp Limit Units (Note7)(Note8)(Limits)f s Maximum Sampling Rate1MHz(min)(1 t THROUGHPUT)t CONV Conversion Time740600ns(min) (S H Low to EOC High)980ns(max)t AD Aperture Delay20ns (S H Low to Input Voltage Held)t S H S H Pulse Width5ns(min)550ns(max)t EOC S H Low to EOC Low9560ns(min) 125ns(max)t ACC Access Time C L e100pF1020ns(max) (RD Low or OE High to Data Valid)t1H t0H TRI-STATE ControlR L e1k C L e10pF2540ns(max) (RD High or OE Low to Databus TRI-STATE)t INTH Delay from RD Low to INT High C L e100pF3560ns(max)t INTL Delay from EOC High to INT Low C L e100pFb25b35ns(min) b10ns(max)t UPDATE EOC High to New Data Valid515ns(max)t MS Multiplexer Address Setup Time50ns(min) (MUX Address Valid to EOC Low)t MH Multiplexer Address Hold Time50ns(min) (EOC Low to MUX Address Invalid)t CSS CS Setup Time20ns(min) (CS Low to RD Low S H Low or OE High)t CSH CS Hold Time20ns(min) (CS High after RD High S H High or OE Low)t WU Wake-Up Time1m s (PD High to First S H Low)Note1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is functional These ratings do not guarantee specific performance limits however For guaranteed specifications and test conditions see the Electrical Characteris-tics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test conditionsNote2 All voltages are measured with respect to GND(GND e AGND e DGND) unless otherwise specifiedNote3 When the input voltage(V IN)at any pin exceeds the power supply rails(V IN k GND or V IN l V CC)the absolute value of current at that pin should be limited to25mA or less The50mA package input current limits the number of pins that can safely exceed the power supplies with an input current of25mA to twoNote4 The maximum power dissipation must be derated at elevated temperatures and is dictated by T JMAX i JA and the ambient temperature T A The maximum allowable power dissipation at any temperature is P D e(T JMAX b T A) i JA or the number given in the Absolute Maximum Ratings whichever is lower i JA for the V (PLCC)package is55 C W i JA for the VF(PQFP)package is62 C W In most cases the maximum derated power dissipation will be reached only during fault conditions4Note5 Human body model 100pF discharged through a1 5k X resistor Machine model ESD rating is200VNote6 See AN-450‘‘Surface Mounting Methods and Their Effect on Product Reliability’’or the section titled‘‘Surface Mount’’found in a current National Semiconductor Linear Data Book for other methods of soldering surface mount devicesNote7 Typicals are at a25 C and represent most likely parametric normNote8 Tested limits are guaranteed to National’s AOQL(Average Outgoing Quality Level)Note9 Integral Linearity Error is the maximum deviation from a straight line between the measured offset and full scale endpointsNote10 Dynamic testing of the ADC12062is done using the ADC IN input The input multiplexer adds harmonic distortion at high frequencies See the graph in the Typical Performance Characteristics section for a typical graph of THD performance vs input frequency with and without the input multiplexerNote11 The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level Harmonics of the input signal are not included in its calculation Note12 The contributions from the first nine harmonics are used in the calculation of the THDNote13 Effective Number of Bits(ENOB)is calculated from the measured signal-to-noise plus distortion ratio(SINAD)using the equation ENOB e(SINAD b 1 76) 6 02Note14 The digital power supply current takes up to10seconds to decay to its final value after PD is pulled low This prohibits production testing of the standby current Some parts may exhibit significantly higher standby currents than the20m A typicalNote15 Power Supply Sensitivity is defined as the change in the Offset Error or the Full Scale Error due to a change in the supply voltageTRI-STATE Test Circuit and WaveformsTL H 11490–2TL H 11490–3TL H 11490–4TL H 11490–55Typical Performance CharacteristicsReference VoltageError Change vs Offset and Fullscale vs Reference VoltageLinearity Error Change Input VoltageMux ON Resistance vs vs Temperature Digital Supply Current vs TemperatureAnalog Supply Current on Digital Input PinsStandby Mode vs Voltage Current Consumption in vs Temperature Conversion Time (t CONV )vs TemperatureEOC Delay Time (t EOC )Spectral Response(ADC IN)SINAD vs Input Frequency (ADC IN)SNR vs Input Frequency (ADC IN)THD vs Input Frequency TL H 11490–276Typical Performance Characteristics(Continued)(Through Mux)SINAD vs Input Frequency (Through Mux)SNR vs Input Frequency (Through Mux)THD vs Input Frequency Impedance SNR and THD vs Source Reference VoltageSNR and THD vs TL H 11490–28Timing DiagramsTL H 11490–9FIGURE 1 Interrupt Interface Timing (MODE e 1 OE e 1)7Timing Diagrams (Continued)TL H 11490–10FIGURE 2 High Speed Interface Timing (MODE e 1 OE e 1 CS e 0 RD e 0)TL H 11490–11FIGURE 3 CS Setup and Hold Timing for S H RD and OEConnection DiagramsTL H 11490–13Top ViewTL H 11490–29Top View8Pin DescriptionsAV CC These are the two positive analog supplyinputs They should always be connectedto the same voltage source but arebrought out separately to allow for sepa-rate bypass capacitors Each supply pinshould be bypassed to AGND with a0 1m F ceramic capacitor in parallel with a10m F tantalum capacitorDV CC This is the positive digital supply input Itshould always be connected to the samevoltage as the analog supply AV CC Itshould be bypassed to DGND2with a0 1m F ceramic capacitor in parallel with a10m F tantalum capacitorAGND These are the power supply ground pins DGND1 There are separate analog and digital DGND2ground pins for separate bypassing of theanalog and digital supplies The groundpins should be connected to a stablenoise-free system ground All of theground pins should be returned to thesame potential AGND is the analogground for the converter DGND1is theground pin for the digital control linesDGND2is the ground return for the outputdatabus See Section6 0LAYOUT ANDGROUNDING for more informationDB0–DB11These are the TRI-STATE output pins en-abled by RD CS and OEV IN1 V IN2These are the analog input pins to the mul-tiplexer For accurate conversions no in-put pin(even one that is not selected)should be driven more than50mV belowground or50mV above V CCMUX OUT This is the output of the on-board analoginput multiplexerADC IN This is the direct input to the12-bit sam-pling A D converter For accurate conver-sions this pin should not be driven morethan50mV below AGND or50mV aboveAV CCS0This pin selects the analog input that willbe connected to the ADC12062during theconversion The input is selected based onthe state of S0when EOC makes its high-to-low transition Low selects V IN1 highselects V IN2MODE This pin should be tied to DV CCCS This is the active low Chip Select controlinput When low this pin enables the RDS H and OE inputs This pin can be tiedlowINT This is the active low Interrupt outputWhen using the Interrupt Interface Mode(Figure1) this output goes low when aconversion has been completed and indi-cates that the conversion result is avail-able in the output latches This output isalways high when RD is held low(Figure2)EOC This is the End-of-Conversion control out-put This output is low during a conversion RD This is the active low Read control inputWhen RD is low(and CS is low) the INToutput is reset and(if OE is high)data ap-pears on the data bus This pin can be tiedlowOE This is the active high Output Enable con-trol input This pin can be thought of as aninverted version of the RD input(see Fig-ure6) Data output pins DB0–DB11areTRI-STATE when OE is low Data appearson DB0–DB11only when OE is high andCS and RD are both low This pin can betied highS H This is the Sample Hold control input Theanalog input signal is held and a new con-version is initiated by the falling edge ofthis control input(when CS is low) PD This is the Power Down control input Thispin should be held high for normal opera-tion When this pin is pulled low the devicegoes into a low power standby mode V REF a(FORCE) These are the positive and negative volt-V REF b(FORCE)age reference force inputs respectivelySee Section4 REFERENCE INPUTS formore informationV REF a(SENSE) These are the positive and negative volt-V REF b(SENSE)age reference sense pins respectivelySee Section4 REFERENCE INPUTS formore informationV REF 16This pin should be bypassed to AGND witha0 1m F ceramic capacitorTEST This pin should be tied to DV CC9Functional DescriptionThe ADC12062performs a12-bit analog-to-digital conver-sion using a3step flash technique The first flash deter-mines the six most significant bits the second flash gener-ates four more bits and the final flash resolves the two least significant bits Figure4shows the major functional blocks of the converter It consists of a2 -bit Voltage Estimator a resistor ladder with two different resolution voltage spans a sample hold capacitor a4-bit flash converter with front end multiplexer a digitally corrected DAC and a capacitive volt-age dividerThe resistor string near the center of the block diagram in Figure4generates the6-bit and10-bit reference voltages for the first two conversions Each of the16resistors at the bottom of the string is equal to of the total string resist-ance These resistors form the LSB Ladder and have a voltage drop of of the total reference voltage(V REF a b V REF b)across each of them The remaining resistors form the MSB Ladder It is comprised of eight groups of eight resistors each connected in series(the lowest MSB ladder resistor is actually the entire LSB ladder) Each MSB Ladder section has of the total reference voltage across it Within a given MSB ladder section each of the eight MSB resistors has of the total reference voltage across it Tap points are found between all of the resistors in both the MSB and LSB ladders The Comparator MultipIexer can connect any of these tap points in two adjacent groups of eight to the sixteen comparators shown at the right of Figure4 This function provides the necessary reference voltages to the comparators during the first two flash con-versionsThe six comparators seven-resistor string(Estimator DAC ladder) and Estimator Decoder at the left of Figure4form Note The weight of each resistor on the LSB ladder is actually equivalent to four12-bit LSBs It is called the LSB ladder because it has thehighest resolution of all the ladders in the converter the Voltage Estimator The Estimator DAC connected be-tween V REF a and V REF b generates the reference volt-ages for the six Voltage Estimator comparators The com-parators perform a very low resoIution A D conversion to obtain an‘‘estimate’’of the input voltage This estimate is used to control the placement of the Comparator Multiplex-er connecting the appropriate MSB ladder section to the sixteen flash comparators A total of only22comparators(6 in the Voltage Estimator and16in the flash converter)is required to quantize the input to6bits instead of the64that would be required using a traditional6-bit flashPrior to a conversion the Sample Hold switch is closed allowing the voltage on the S H capacitor to track the input voItage Switch1is in position1 A conversion begins by opening the Sample Hold switch and latching the output of the Voltage Estimator The estimator decoder then selects two adjacent banks of tap points aIong the MSB ladder These sixteen tap points are then connected to the sixteen flash converters For exampIe if the input voltage is be-tween and of V REF(V REF e V REF a b V REF b) the estimator decoder instructs the comparator multiplexer to select the sixteen tap points between and ( and )of V REF and connects them to the sixteen comparators The first flash conversion is now performed producing the first6MSBs of dataAt this point Voltage Estimator errors as large as of V REF will be corrected since the comparators are connect-ed to ladder voltages that extend beyond the range speci-fied by the Voltage Estimator For example if( )V REF k V IN k( )V REF the Voltage Estimator’s comparators tied to the tap points below( )V REF will output‘‘1’’s (000111) This is decoded by the estimator decoder to‘‘10’’ The16comparators will be placed on the MSB ladderTL H 11490–14FIGURE4 Functional Block Diagram10Functional Description(Continued)tap points between( )V REF and( )V REF This overlap of ( )V REF will automatically cancel a Voltage Estimator er-ror of up to256LSBs If the first flash conversion deter-mines that the input voltage is between( )V REF and (( )V REF b LSB 2) the Voltage Estimator’s output code will be corrected by subtracting‘‘1’’ resulting in a corrected value of‘‘01’’for the first two MSBs If the first flash conver-sion determines that the input voltage is between( )V REF b LSB 2)and( )V REF the voltage estimator’s output code is unchangedThe results of the first flash and the Voltage Estimator’s output are given to the factory-programmed on-chip EEPROM which returns a correction code corresponding to the error of the MSB ladder at that tap This code is convert-ed to a voltage by the Correction DAC To generate the next four bits SW1is moved to position2 so the ladder voltage and the correction voltage are subtracted from the input voltage The remainder is applied to the sixteen flash con-verters and compared with the16tap points from the LSB ladderThe result of this second conversion is accurate to10bits and describes the input remainder as a voltage between two tap points(V H and V L)on the LSB ladder To resolve the last two bits the voltage across the ladder resistor(between V H and V L)is divided up into4equal parts by the capacitive voltage divider shown in Figure5 The divider also creates 6LSBs below V L and6LSBs above V H to provide overlap used by the digital error correction SW1is moved to posi-tion3 and the remainder is compared with these16new voltages The output is combined with the results of the Voltage Estimator first flash and second flash to yield the final12-bit resultBy using the same sixteen comparators for all three flash conversions the number of comparators needed by the multi-step converter is significantly reduced when compared to standard multi-step techniquesApplications Information1 0MODES OF OPERATIONThe ADC12062has two interface modes An interrupt read mode and a high speed mode Figures1and2show the timing diagrams for these interfacesIn order to clearly show the relationship between S H CS RD and OE the control logic decoding section of the ADC12062is shown in Figure6Interrupt InterfaceAs shown in Figure1 the falling edge of S H holds the input voltage and initiates a conversion At the end of the conver-sion the EOC output goes high and the INT output goes low indicating that the conversion results are latched and may be read by pulling RD low The falling edge of RD re-sets the INT line Note that CS must be low to enable S H or RDHigh Speed InterfaceThis is the fastest interface shown in Figure2 Here the output data is always present on the databus and the INT to RD delay is eliminatedTL H 11490–15FIGURE5 The Capacitive Voltage Divider11Applications Information (Continued)TL H 11490–16FIGURE 6 ADC Control Logic2 0THE ANALOG INPUTThe analog input of the ADC12062can be modeled as two small resistances in series with the capacitance of the input hold capacitor (C IN ) as shown in Figure 7 The S H switch is closed during the Sample period and open during Hold The source has to charge C IN to the input voltage within the sample period Note that the source impedance of the input voltage (R SOURCE )has a direct effect on the time it takes to charge C IN If R SOURCE is too large the voltage across C IN will not settle to within 0 5LSBs of V SOURCE before the conversion begins and the conversion results will be incor-rect From a dynamic performance viewpoint the combina-tion of R SOURCE R MUX R SW and C IN form a low pass filter Minimizing R SOURCE will increase the frequency re-sponse of the input stage of the converterTypical values for the components shown in Figure 7are R MUX e 100X R SW e 100X and C IN e 25pF The set-tling time to n bits ist SETTLE e (R SOURCE a R MUX a R SW ) C IN n ln (2) The bandwidth of the input circuit isf b 3dB e 1 (2 3 14 (R SOURCE a R MUX a R SW ) C IN )For maximum performance the impedance of the source driving the ADC12062should be made as small as possible A source impedance of 100X or less is recommended A plot of dynamic performance vs source impedance is given in the Typical Performance Characteristics sectionIf the signal source has a high output impedance its output should be buffered with an operational amplifier capable of driving a switched 25pF 100X load Any ringing or instabili-ties at the op amp’s output during the sampling period can result in conversion errors The LM6361high speed op amp is a good choice for this application due to its speed and its ability to drive large capacitive loads Figure 8shows the LM6361driving the ADC IN input of an ADC12062 The 100pF capacitor at the input of the converter absorbs some of the high frequency transients generated by the S H switching reducing the op amp transient response require-ments The 100pF capacitor should only be used with high speed op amps that are unconditionally stable driving ca-pacitive loadsTL H 11490–17FIGURE 7 Simplified ADC12062Input Stage12Applications Information (Continued)TL H 11490–18FIGURE 8 Buffering the Input with an LM6361High Speed Op AmpAnother benefit of using a high speed buffer is improved THD performance when using the multiplexer of the ADC12062 The MUX on-resistance is somewhat non-linear over input voltage causing the RC time constant formed by C IN R MUX and R SW to vary depending on the input voltage This results in increasing THD with increasing frequency Inserting the buffer between the MUX OUT and the ADC IN terminals as shown in Figure 8will eliminate the loading on R MUX significantly reducing the THD of the multiplexed sys-temCorrect converter operation will be obtained for input volt-ages greater than AGND b 50mV and less than AV CC a50mV Avoid driving the signal source more than 300mV higher than AV CC or more than 300mV below AGND If an analog input pin is forced beyond these voltages the cur-rent flowing through that pin should be limited to 25mA or less to avoid permanent damage to the IC The sum of all the overdrive currents into all pins must be less than 50mA When the input signal is expected to extend more than 300mV beyond the power supply limits for any reason (un-known uncontrollable input voltage range power-on tran-sients fault conditions etc )some form of input protection such as that shown in Figure 9 should be usedTL H 11490–19FIGURE 9 Input Protection13Applications Information(Continued)3 0ANALOG MULTIPLEXERThe ADC12062has an input multiplexer that is controlled by the logic level on pin S0when EOC goes low as shown in Figures1and2 Multiplexer setup and hold times with re-spect to the S H input can be determined by these two equationst MS(wrt S H)e t MS b t EOC(min)e50b60e b10ns t MH(wrt S H)e t MH a t EOC(max)e50a125e175ns Note that t MS(wrt S H)is a negative number this indicates that the data on S0must become valid within10ns after S H goes low in order to meet the setup time requirements S0must be valid for a length of(t MH a t EOC(max))b(t MS b t EOC(min))e185ns Table I shows how the input channels are assignedTABLE I ADC12062InputMultiplexer ProgrammingS0Channel0V IN11V IN2The output of the multiplexer is available to the user via the MUX OUT pin This output allows the user to perform addi-tional signal processing such as filtering or gain before the signal is returned to the ADC IN input and digitized If no additional signal processing is required the MUX OUT pin should be tied directly to the ADC IN pinSee Section9 0(APPLICATIONS)for a simple circuit that will alternate between the two inputs while converting at full speed4 0REFERENCE INPUTSIn addition to the fully differential V REF a and V REF b refer-ence inputs used on most National Semiconductor ADCs the ADC12062has two sense outputs for precision control of the ladder voltage These sense inputs compensate for errors due to IR drops between the reference source and the ladder itself The resistance of the reference ladder is typically750X The parasitic resistance(R P)of the package leads bond wires PCB traces etc can easily be0 5X to 1 0X or more This may not be significant at8-bit or10-bit resolutions but at12bits it can introduce voltage drops causing offset and gain errors as large as6LSBsThe ADC12062provides a means to eliminate this error by bringing out two additional pins that sense the exact voltage at the top and bottom of the ladder With the addition of two op amps the voltages on these internal nodes can be forced to the exact value desired as shown in Figure10TL H 11490–20FIGURE10 Reference Ladder Force and Sense Inputs14。

oppo A127播放器说明书

在医疗设备附近应关机医院或卫生保健机构可能会使用对无线频率敏感的设备。请有效遵守任何规章或制度。
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合理的使用
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MH8S72DALD-6资料

DESCRIPTIONThe MH8S72DALD is 8388608 - word by 72-bit Synchronous DRAM module. This consists of nine industry standard 8Mx8 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP.The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required.This is a socket type - memory modules, suitable for easy interchange or addition of modules.FEATURESMax. Clock frequency -6:133MHz,-7,8:100MHzsingle 3.3V±0.3V power supplyBurst length- 1/2/4/8/Full Page(programmable)10pin 11pinPIN NO.PIN NAME PIN NO.PIN NAME PIN NO.PIN NAME PIN NO.PIN NAME 1VSS43VSS85VSS127VSS 2DQ044NC86DQ32128CKE0 3DQ145/S287DQ33129NC 4DQ246DQMB288DQ34130DQMB6 5DQ347DQMB389DQ35131DQMB7 6VDD48NC90VDD132NC 7DQ449VDD91DQ36133VDD 8DQ550NC92DQ37134NC 9DQ651NC93DQ38135NC 10DQ752CB294DQ39136CB6 11DQ853CB395DQ40137CB7 12VSS54VSS96VSS138VSS 13DQ955DQ1697DQ41139DQ48 14DQ1056DQ1798DQ42140DQ49 15DQ1157DQ1899DQ43141DQ50 16DQ1258DQ19100DQ44142DQ51 17DQ1359VDD101DQ45143VDD 18VDD60DQ20102VDD144DQ52 19DQ1461NC103DQ46145NC 20DQ1562NC104DQ47146NC 21CB063NC105CB4147NC CB12264VSS106CB5148VSS 23VSS65DQ21107VSS149DQ53 24NC66DQ22108NC150DQ54 25NC67DQ23109NC151DQ55 26VDD68VSS110VDD152VSS 27/WE069DQ24111/CAS153DQ56 28DQMB070DQ25112DQMB4154DQ57 29DQMB171DQ26113DQMB5155DQ58 30/S072DQ27114NC156DQ59 31NC73VDD115/RAS157VDD 32VSS74DQ28116VSS158DQ60 33A075DQ29117A1159DQ61 34A276DQ30118A3160DQ62 35A477DQ31119A5161DQ63 36A678VSS120A7162VSS 37A879CK2121A9163CK3 38A1080NC122BA0164NC 39BA181WP123A11165SA0 40VDD82SDA124VDD166SA1 41VDD83SCL125CK1167SA2 42CK084VDD126NC168VDD NC = No ConnectionVccVssD0 - D8D0 - D8/S0/S2CKE0D0 - D8D0 - D8D0 - D8/WE D0 - D8D0 - D85SDRAMs4SDRAMs+3.3pF cap.SCLWPCK3Serial Presence Detect Table IByte Function describedSPD enrty dataSPD DATA(hex)0Defines # bytes written into serial memory at module mfgr128801Total # bytes of SPD memory device256 Bytes 082Fundamental memory type SDRAM 043# Row Addresses on this assembly A0-A110C 4# Column Addresses on this assembly A0-A8095# Module Banks on this assembly 1BANK 016Data Width of this assembly...x72487... Data Width continuation0008Voltage interface standard of this assemblyLVTTL 019SDRAM Cycletime at Max. Supported CAS Latency (CL).A0Cy cle time for CL=310SDRAM Access from Clock6ns60tAC for CL=311DIMM Configuration type (Non-parity,Parity,ECC)ECC0212Refresh Rate/Type self refresh(15.625uS)8013SDRAM width,Primary DRAM x 80814Error Checking SDRAM data widthx 80815M inimum Clock Delay,Back to Back Random Column Addresses10116Burst Lengths Supported 1/2/4/8/Full page8F 17# Banks on Each SDRAM device4bank0418CAS# Latency 30419CS# Latency 00120Write Latency 00121SDRAM Module Attributes non-buffered,non-registered 0022SDRAM Dev ice Attributes:General Precharge All,Auto precharge0E 23SDRAM Cy cle time(2nd highest CAS latency)13ns D0Cy cle time for CL=224SDRAM Access form Clock(2nd highest CAS latency)7ns 70tAC for CL=225SDRAM Cy cle time(3rd highest CAS latency)N/A00N/A 0026SDRAM Access form Clock(3rd highest CAS latency)27Precharge to Active Minimum 20ns 1428Row Active to Row Active Min.15ns 0F 10ns -8-8-710ns A06ns 60-729RAS to CAS Delay Min 22.5ns 1730Active to Precharge Min50ns32-7,-8-6757.5ns -7,-8-6 5.4ns 54-7,-8-62/306-6N/A 00-6N/A 00-7,-8-622.5ns 17-7,-8-6-7,-8-6-7,-8-620ns 1420ns 1445ns 2DSerial Presence Detect Table II31Density of each bank on module64MByte 1036-61Superset Information (may be used in future)option 0062SPD Revision 63Checksum for bytes 0-62Check sum for -85764-71Manufactures Jedec ID code per JEP-108EMITSUBISHI 1CFFFFFFFFFFFFFF72Manufacturing locationMiyoshi,Japan 01Tajima,Japan 02NC,USA 03Germany 0473-90Manufactures Part Number MH8S72DALD-891-92Revision Code PCB revision rrrr 93-94Manufacturing date year/week code yyww 95-98Assembly Serial Number serial numberssssssss99-125Manufacture Specific Data option 00126Intetl specification frequency100MHz 64127Intel specification CAS# Latency support128+Unused storage locationsopen0032Command and Address signal input setup time 2ns 202033Command and Address signal input hold time1ns 1034Data signal input setup time 2ns 35Data signal input hold time1ns 10rev 1.2A 12Check sum for -717MH8S72DALD-64D483853373244414C442D36202020202020-7AF CL=2/3,AP,CK0,2MH8S72DALD-7-6,-8AD CL=3,AP,CK0,2-6-7,-8-6-7,-8-6-7,-8-6-7,-8Check sum for -6A41.5ns 150.8ns 08151.5ns 0.8ns 08-6-7,-8JEDEC2024D483853373244414C442D372020202020204D483853373244414C442D38202020202020PIN FUNCTIONBASIC FUNCTIONS/S Chip Select : L=select, H=deselect /RAS Command /CAS Command /WE CommandCKE Ref resh Option @ref resh commandA10Precharge Option @precharge or read/write commandCK def ine basic commandsThe MH8S72DALD provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh.Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively.To know the detailed definition of commands please see the command truth table.Activate(ACT) [/RAS =L, /CAS = /WE =H]Read(READ) [/RAS =H,/CAS =L, /WE =H]Write(WRITE) [/RAS =H, /CAS = /WE =L]Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]ACT command activates a row in an idle bank indicated by BA. READ command starts burst read from the active bank indicated by BA.First output data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA ). WRITE command starts burst write to the active bank indicated by BA. Total datalength to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA ). PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA ).REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.COMMAND TRUTH TABLECOMMAND MNEMONIC CKE n-1CKE n /S /RAS /CAS /WE BA0,1A10A0-9Deselect DESEL H X H X X X X X X No Operation NOP H X L H H H X X X Row Adress Entry &Bank Activate ACT H X L L H H V V V Single Bank Precharge PRE H X L L H L V L X Precharge All Bank PREA H X L L H L X H X Column Address Entry& Write WRITEHXLHLLVLVColumn Address Entry & Write with Auto-Precharge WRITEA H X L H L L V H VColumn Address Entry& Read READ H X L H L H V L VColumn Address Entry & Read with AutoPrecharge READA H X L H L H V H V Auto-Refresh REFA H H L L L H X X X Self-Refresh Entry REFS H L L L L H X X X Self-Refresh Exit REFSX L H H X X X X X X L H L H H H X X X Burst Terminate TERM H X L H H L X X X Mode Register SetMRSHXLLLLLLV*1H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number NOTE:1.A7-9 = 0, A0-6 = Mode AddressA11X X V X X VV V V X X X X X LCurrent State/S/RAS/CAS/WE Address Command Action IDLE H X X X X DESEL NOPL H H H X NOP NOPL H H L BA TBST ILLEGAL*2L H L X BA,CA,A10READ/WRITE ILLEGAL*2L L H H BA,RA ACT Bank Active,Latch RAL L H L BA,A10PRE/PREA NOP*4L L L H X REFA Auto-Refresh*5L L L L Op-Code,Mode-AddMRS Mode Register Set*5ROW ACTIVE H X X X X DESEL NOP L H H H X NOP NOPL H H L BA TBST NOPL H L H BA,CA,A10READ/READA Begin Read,Latch CA, Determine Auto-PrechargeL H L L BA,CA,A10WRITE/WRITEABegin Write,Latch CA,Determine Auto-PrechargeL L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10PRE/PREA Precharge/Precharge All L L L H X REFA ILLEGALL L L L Op-Code,Mode-AddMRS ILLEGALREAD H X X X X DESEL NOP(Continue Burst to END) L H H H X NOP NOP(Continue Burst to END)L H H L BA TBST Terminate BurstL H L H BA,CA,A10READ/READA Terminate Burst,Latch CA, Begin New Read,Determine Auto-Precharge*3L H L L BA,CA,A10WRITE/WRITEA Terminate Burst,Latch CA, Begin Write,Determine Auto-Precharge*3L L H H BA,RA ACT Bank Active/ILLEGAL*2L L H L BA,A10PRE/PREA Terminate Burst,Precharge L L L H X REFA ILLEGALL L L L Op-Code,Mode-AddMRS ILLEGALFUNCTION TRUTH TABLEFUNCTION TRUTH TABLE(continued)Current State/S/RAS/CAS/WE Address Command Action WRITE H X X X X DESEL NOP(Continue Burst to END) L H H H X NOP NOP(Continue Burst to END)L H H L BA TBST Terminate BurstL H L H BA,CA,A10READ/READA Terminate Burst,Latch CA, Begin Read,Determine Auto-Precharge*3L H L L BA,CA,A10WRITE/WRITEATerminate Burst,Latch CA,Begin Write,Determine Auto-Precharge*3L L H H BA,RA ACT Bank Active/ILLEGAL*2L L H L BA,A10PRE/PREA Terminate Burst,PrechargeL L L H X REFA ILLEGALL L L L Op-Code,Mode-AddMRS ILLEGALREAD with H X X X X DESEL NOP(Continue Burst to END) AUTO L H H H X NOP NOP(Continue Burst to END) PRECHARGE L H H L BA TBST ILLEGALL H L H BA,CA,A10READ/READA ILLEGALL H L L BA,CA,A10WRITE/WRITEAILLEGALL L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10PRE/PREA ILLEGAL*2L L L H X REFA ILLEGALL L L L Op-Code,Mode-AddMRS ILLEGALWRITE with H X X X X DESEL NOP(Continue Burst to END) AUTO L H H H X NOP NOP(Continue Burst to END) PRECHARGE L H H L BA TBST ILLEGALL H L H BA,CA,A10READ/READA ILLEGALL H L L BA,CA,A10WRITE/WRITEAILLEGALL L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10PRE/PREA ILLEGAL*2L L L H X REFA ILLEGALL L L L Op-Code,Mode-AddMRS ILLEGALFUNCTION TRUTH TABLE(continued)Current State/S/RAS/CAS/WE Address Command Action PRE -H X X X X DESEL NOP(Idle after tRP) CHARGING L H H H X NOP NOP(Idle after tRP) L H H L BA TBST ILLEGAL*2L H L X BA,CA,A10READ/WRITE ILLEGAL*2L L H H BA,RA ACT ILLEGAL*2L L H L BA,A10PRE/PREA NOP*4(Idle after tRP)L L L H X REFA ILLEGALL L L L Op-Code,Mode-AddMRS ILLEGALROW H X X X X DESEL NOP(Row Active after tRCD ACTIVATING L H H H X NOP NOP(Row Active after tRCD L H H L BA TBST ILLEGAL*2L H L X BA,CA,A10READ/WRITE ILLEGAL*2L L H H BA,RA ACT ILLEGAL*2L L H L BA,A10PRE/PREA ILLEGAL*2L L L H X REFA ILLEGALL L L L Op-Code,Mode-AddMRS ILLEGALWRITE RE-H X X X X DESEL NOP COVERING L H H H X NOP NOPL H H L BA TBST ILLEGAL*2L H L X BA,CA,A10READ/WRITE ILLEGAL*2L L H H BA,RA ACT ILLEGAL*2L L H L BA,A10PRE/PREA ILLEGAL*2L L L H X REFA ILLEGALL L L L Op-Code,Mode-AddMRS ILLEGALFUNCTION TRUTH TABLE(continued)Current State/S/RAS/CAS/WE Address Command Action RE-H X X X X DESEL NOP(Idle after tRC) FRESHING L H H H X NOP NOP(Idle after tRC) L H H L BA TBST ILLEGALL H L X BA,CA,A10READ/WRITE ILLEGALL L H H BA,RA ACT ILLEGALL L H L BA,A10PRE/PREA ILLEGALL L L H X REFA ILLEGALL L L L Op-Code,Mode-AddMRS ILLEGALMODE H X X X X DESEL NOP(Idle after tRSC) REGISTER L H H H X NOP NOP(Idle after tRSC) SETTING L H H L BA TBST ILLEGALL H L X BA,CA,A10READ/WRITE ILLEGALL L H H BA,RA ACT ILLEGALL L H L BA,A10PRE/PREA ILLEGALL L L H X REFA ILLEGALL L L L Op-Code,Mode-AddMRS ILLEGALABBREVIATIONS:H = Hige Level, L = Low Level, X = Don't CareBA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation NOTES:1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,depending on the state of that bank.3. Must satisfy bus contention, bus turn around, write recovery requirements.4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.5. ILLEGAL if any bank is not idle.ILLEGAL = Device operation and / or date-integrity are not guaranteed.FUNCTION TRUTH TABLE FOR CKECurrent State CKEn-1CKEn/S/RAS/CAS/WE Add ActionSELF - H X X X X X X INVALIDREFRESH*1L H H X X X X Exit Self-Refresh(Idle after tRC) L H L H H H X Exit Self-Refresh(Idle after tRC)L H L H H L X ILLEGALL H L H L X X ILLEGALL H L L X X X ILLEGALL L X X X X X NOP(Maintain Self-Refresh) POWER H X X X X X X INVALIDDOWN L H X X X X X Exit Power Down to IdleL L X X X X X NOP(Maintain Self-Refresh) ALL BANKS H H X X X X X Refer to Function Truth Table IDLE*2H L L L L H X Enter Self-RefreshH L H X X X X Enter Power DownH L L H H H X Enter Power DownH L L H H L X ILLEGALH L L H L X X ILLEGALH L L L X X X ILLEGALL X X X X X X Refer to Current State = Power Down ANY STATE H H X X X X X Refer to Function Truth Tableother than H L X X X X X Begin CK0 Suspend at Next Cycle*3 listed above L H X X X X X Exit CK0 Suspend at Next Cycle*3 L L X X X X X Maintain CK0 SuspendABBREVIATIONS:H = High Level, L = Low Level, X = Don't CareNOTES:1. CKE Low to High transition will re-enable CK and other inputs asynchronously.A minimum setup time must be satisfied before any command other than EXIT.2. Power-Down and Self-Refresh can be entered only from the All banks idle State.3. Must be legal command.SIMPLIFIED STATE DIAGRAMIDLEPRE CHARGEAUTO REFRESHSELF MODE REGISTERSETPOWER DOWNREADREADAWRITEWRITEAREAD SUSPENDREADA SUSPENDWRITE SUSPENDWRITEA SUSPENDPOWER ONCLK SUSPENDCKELCKEHCKEHCKEHACTCKEHCKELCKEHWRITEAREADAPREPOWER APPLIEDAutomatic Sequence TBST(for Full Page)TBST(for Full Page)POWER ON SEQUENCEBefore starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning.1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP condition at the inputs.2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200us.3. Issue precharge commands for all banks. (PRE or PREA)4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.5. Issue a mode register set command to initialize the mode register.After these sequence, the SDRAM is idle state and ready for normal operation.MODE REGISTERCK Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.Command AddressCKDQBurst TypeA2A1A0Initial Address BL Sequential InterleavedColumn Addressing000001010011100101110111-00-01-10-11--0012345670123456712345670103254762345670123016745345671232107654456701234567012356701234547610326701234567452301701201231232301300176540123103223013201--11210345632111842CK A0-9,11A10DQOPERATION DESCRIPTIONBANK ACTIVATEOne of four banks is activated by an ACT command.An bank is selected by BA0-1. A row is selected by A0-11.Multiple banks can be active state concurrently by issuing multiple ACT commands.Minimum activation interval between one bank and another bank is tRRD.PRECHARGEAn open bank is deactivated by a PRE command.A bank to be deactivated is designated by BA0-1.When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case.Minimum delay time of an ACT command after a PRE command to the same bank is tRP.READA READ command can be issued to any active bank. The start address is specified by A0-8 (x8) . 1st output data is available after the /CAS Latency from the READ. The consecutive data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD.When A10 is high at a READ command, auto-precharge (READA) is performed. Anycommand (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at the BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met.CK CommandA0-9, 11A10DQCKA10DQCKCL=3 CL=2CK Command A10DQCK Command A10DQWRITE with Auto-Precharge (BL=4)WRITEA WRITE command can be issued to any active bank. The start address is specified by A0-8 (x8). 1st input data is set at the same cycle as the WRITE. The consecutive data length to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst Type. Minimum delay time of a WRITE command after an ACT command to the same bank is tRCD. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL + tWR -1 + tRP) from the previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met.A0-9, 11BA0,1A0-9, 11BA0,1BURST INTERRUPTION[ Read Interrupted by Read ]Burst read oparation can be interrupted by new read of the same or the other bank. Random column access is allowed READ to READ interval is minimum 1 CKCK A10DQ[ Read Interrupted by Write ]Burst read operation can be interrupted by write of any active bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQMB0-7 to prevent the bus contention. The output is disabled automatically 1 cycle after WRITE assertion.CK A10DQA0-9,11BA0,1A0-9,11BA0,1Output disableby DQM by WRITE[ Read Interrupted by Precharge ]A burst read operation can be interrupted by precharge of the same bank . Read to PRE interval is minimum 1 CK. A PRE command output disable latency is equivalent to the /CAS Latency.Read Interrupted by Precharge (BL=4)CKDQDQ CommandDQCommandDQ CL=3CL=2DQCommandDQ[ Read Interrupted by Burst Terminate ]Similarly to the precharge, burst terminate command can interrupt burst read operation and disable the data output. The terminated bank remains active,READ to TBST interval is minimum of 1 CK. A TBSTcommand to output disable latency is equivalent to the /CAS Latency.Read Interrupted by Terminate (BL=4)CKDQCL=3DQDQDQCL=2DQDQ[ Write Interrupted by Write ]Burst write operation can be interrupted by new write of any active bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.Write Interrupted by Write (BL=4)CK Command A10DQWrite Ya 000Write Yb 000Da0Da1Da2Db0Dc0Dc1Write Yc 010Dc2Dc3[ Write Interrupted by Read ]Burst write operation can be interrupted by read of any active bank. Random column access is allowed. WRITE to READ interval is minimum 1 CK. The input data on DQ at the interrupting READ cycle is "don't care".Write Interrupted by Read (BL=4, CL=2)CKA10DQA0-9, 11BA0,1A0-9,11BA0,1don't care[ Write Interrupted by Precharge ]Burst write operation can be interrupted by precharge of the same bank. Write recovery time(tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM.CKA10DQ[ Write Interrupted by Burst Terminate ]Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active.The WRITE to TBST minimum interval is 1CK.Write Interrupted by Burst Terminate (BL=4)CKCommandA10DQ ACTX a00TBSTDa0Da1A0-9,11 BA0,1A0-9,11 BA0,1WriteYa00WriteYb00Db0Db1Db2Db3[ Write with Auto-Precharge interrupted by Write or Read to anotehr Bank ]Burst write with auto-precharge can be interrupted by write or read to another bank . Next ACT command can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interrrupted by a command to the same bank is inhibited.CK A10DQCK A10DQA0-9,11BA0,1A0-9,11BA0,1[ Read with Auto-Precharge interrupted by Read to anotehr Bank ]Burst read with auto-precharge can be interrupted by read to another bank . Next ACT command can be issued after (BL+tRP) from the READA. Auto-precharge interrrupted by a command to the same bank is inhibited.CK A10DQA0-9,11BA0,1Full Page BurstFull page burst length is available for only the sequential burst type. Full page burst read or write is repeated untill aPrecharge or a Burst Terminate command isissued. In case of the full page burst , a read or write with auto-precharge command is illegal.Single WriteWhen single write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-0).AUTO REFRESHSingle cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA cycle within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on 4banks concurrently. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command must not be issued before tRFC from the REFA command.CK/S/RAS/CAS/WECKEA0-11BA0,1Auto Refresh on All Banks Auto Refresh on All BanksSELF REFRESHSelf-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is kept low.During the self-refresh mode, CKE is asynchronous and the only enabled input , all other inputs including CK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CK inputs, asserting DESEL or NOP command and then asserting CKE=H. After tRFC from the 1st CK edge follwing CKE=H, all banks are in the idle state and a new command can be issued after, but DESEL or NOP commands must be asserted till then.CK/S/RAS/CAS/WECKEA0-11BA0,1minimum tRFCfor recoveryCLK SUSPEND and POWER DOWNCKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored.CK(ext.CLK)CKEint.CLKCK CKE CKECK DQCKEDQM CONTROLDQMB0-7 is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQMB0-7 masks input data word by word. DQMB0-7 to Data In latency is 0.During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-ZCKCommandDQdisabled by DQMB=HABSOLUTE MAXIMUM RATINGSRECOMMENDED OPERATING CONDITION (Ta=0 ~ 70°C, unless otherwise noted)1:VIH(max)=5.5V f or pulse width less than 10ns.2.VIL(min)=-1.0 f or pulse width less than 10ns. CAPACITANCEAVERAGE SUPPLY CURRENT from Vdd(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)AC OPERATING CONDITIONS AND CHARACTERISTICS(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)Symbol Parameter Test Condition LimitsUnit Min.Max.VOH(DC)High-Level Output Voltage(DC)IOH=-2mA 2.4V VOL(DC)Low-Level Output Voltage(DC)IOL=2mA 0.4VVOH(AC)High-Level Output Voltage(AC)CL=50pF, IOH=-2mA 2V VOL(AC)Low-Level Output Voltage(AC)CL=50pF, IOL=2mA 0.8VIOZ Off-stare Output Current Q floating VO=0 ~ Vdd -55uA Ii Input Current VIH=0 ~ Vdd+0.3V -4545uA Note)1:Icc(max) is specif ied at the output open condition.2.Input signals are changed one time during 30ns.6301891806309909135270225-7, -8Test ConditionLimits (max)Unit tRC=min.tCLK=min, BL=1,CL=3mA CKE=L,tCLK=15ns, /CS>Vcc-0.2V mA CKE=CLK=L, /CS>Vcc-0.2VmA mA tCLK=min, BL=4, CL=3,all banks activ e(discerte)mA tRC=min, tCLK=min mA CKE <0.2VmACKE=H,tCLK=15ns,VIH>Vcc-0.2V,VIL<0.2V Symbol Icc1Icc2P Icc2PS Icc2NSIcc4Icc5Icc6Icc2N Parameteroperating currentone bank activ e (discrete)precharge stanby currentin power-down mode burst currentauto-refresh current self-refresh currentCKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(f ixed)mA precharge stanby current in non power-down mode mA CKE=H,tCLK=15nsIcc3NS Icc3N CKE=H,CLK=LmA active stanby currentin non power-down modeone bank activ e (discrete)67518918081011709135270225-6AC TIMING REQUIREMENTS (SDRAM Component)(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4VCKSignal1.4V1.4VAny AC timing is referenced to the inputsignal crossing through 1.4V.Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns should be added to the parameter.Limits Symbol Parameter -7Unit Min.Max.tCLK CK cycle timenstCH CK High pulse width 310ns tCL CK Low pilse width 3ns tT Transition time of CK 110nstIS Input Setup time(all inputs)2ns tIH Input Hold time(all inputs)1ns tRC Row cycle time 70ns tRCD Row to Column Delay 20nstRAS Row Active time 50100KnstRP Row Precharge time 20ns tWR Write Recovery time 20ns tRRD Act to Act Deley time20ns tRSC Mode Register Set Cycle time 10ns tSRX Self Refresh Exit time 10ns tREFRefresh Interval time64ms-8Min.Max.313311021702050100K 202020101064CL=2CL=31010ns -6Min.Max.2.5102.51101.50.867.52045100K 201515107.5647.5tRFC Refresh cycle time 80ns 8075tPDE Power Down Exit time 10ns 107.51.4V1.4VDQCKtACtOHtOHZSWITCHING CHARACTERISTICS (SDRAM Component)(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise note3)Output Load ConditionV OUTFor -63ns32.7CL=3Burst Write (single bank) @BL=4/CS/RAS/CAS /WECKE BA0,1DQACT#0WRITE#0PRE#0ACT#0WRITE#0CLKItalic parameter indicates minimum caseA0-8A10DQM A9,11Burst Write (multi bank) @BL=4/CS /RAS/CAS /WECKE BA0,1DQXX X 0Y01D0D0D0D0X X 0YD0D0D0D0ACT#0WRITE#0PRE#0ACT#0WRITE#001234567891011121314151617tRCDtRAS tWRtRPtRCtRCDD1D1D1D1XX X 1tRRD YtWR0X1XXX2tRRDACT#1WRITE#1PRE#1ACT#2CLKItalic parameter indicates minimum caseA0-8A10DQM A9,11。

IDT723612资料

FUNCTIONAL BLOCK DIAGRAM3136 drw 01A 0 - A 0 -B 36The IDT logo is a registered trademark and Sync BiFIFO is a trademark of Integrated Device Technology Inc.COMMERCIAL TEMPERATURE RANGEMAY 1997©1997 Integrated Device Technology, Inc.DSC-3136/4FEATURES:•Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted)•Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions •Mailbox bypass Register for each FIFO•Programmable Almost-Full and Almost-Empty Flags •Microprocessor interface control logic•EFA , FFA , AEA , and AFA flags synchronized by CLKA •EFB , FFB , AEB , and AFB flags synchronized by CLKB •Passive parity checking on each port•Parity generation can be selected for each port•Low-power advanced BiCMOS technology •Supports clock frequencies up to 67 MHz •Fast access times of 10ns•Available in 132-pin plastic quad flat package (PQF) or space-saving 120-pin thin quad flat package (TQFP)•Industrial temperature range (-40oC to +85oC) is avail-able, tested to military electrical specificationsDESCRIPTION:The IDT723612 is a monolithic high-speed, low-power BiCMOS bi-directional clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times asFor latest information contact IDT's web site at or fax-on-demand at 408-492-8391.fast as 10ns. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data in opposite directions.Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost-full and almost-empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices can be used in parallel to create wider data paths.The IDT723612 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers throughNote:1.NC - No internal connectiona port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bi-directional interface between microprocessors and/or buses with synchronous control.The full flag (FFA , FFB ) and almost-full (AFA , AFB ) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The empty flag (EFA , EFB ) and almost-empty (AEA , AEB ) flag of a FIFO are two stage synchronized to the port clock that reads data from its array.The IDT723612 is characterized for operation from 0°C to 70°C.es Yamaichi socket IC51-1324-828PIN CONFIGURATIONS**Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.GNDE N A C L K A W /F S1N C G N D N C N C NCB C L K B E NBPIN CONFIGURATIONS (CONT.)TQFP (PN120-1, order code: PF)TOP VIEWNote:1.NC - No internal connectionB 22B 21GND B 20B 19B 18B 17B 16B 15B 14B 13B 12B 11B 10GND B 9B 8B 7V CC B 6B 5B 4B 3GND B 2B 1BA A A A A A A A A A A A A A A A A V A A A A A AAV C PGAPIN DESCRIPTIONPIN DESCRIPTION (CONTINUED)ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)(2)Notes:1.Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated condi-tions for extended periods may affect device reliability.2.The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONSELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)Note:1.All typical values are at V CC = 5 V, T A = 25°C.DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURENotes:1.Only applies for a clock edge that does a FIFO read.2.Requirement to count the clock edge as one of at least four needed to reset a FIFO.3.Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relation-ship between CLKA cycle and CLKB cycle.SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C L = 30pFNotes:1.Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.2.Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.3.Only applies when reading data from a mail register.SIGNAL DESCRIPTIONSRESETThe IDT723612 is reset by taking the reset (RST ) input LOW for at least four port-A clock (CLKA) and four port-B clock (CLKB) LOW-to-HIGH transitions. The reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of each FIFO and forces the full flags (FFA , FFB ) LOW, the empty flags (EFA , EFB ) LOW,the almost-empty flags (AEA , AEB ) LOW and the almost-full flags (AFA , AFB ) HIGH. A reset also forces the mailbox flags (MBF1, MBF2) HIGH. After a reset, FFA is set HIGH after two LOW-to-HIGH transitions of CLKA and FFB is set HIGH after two LOW-to-HIGH transitions of CLKB. The device must be reset after power up before data is written to its memory.A LOW-to-HIGH transition on the RST input loads the almost-full and almost-empty registers (X) with the values selected by the flag-select (FS0, FS1) inputs. The values that can be loaded into the registers are shown in Table 1.FIFO WRITE/READ OPERATIONThe state of port-A data A0-A35 outputs is controlled by the port-A chip select (CSA ) and the port-A write/read select (W/R A). The A0-A35 outputs are in the high-impedance state when either CSA or W/R A is HIGH. The A0-A35 outputs are active when both CSA and W/R A are LOW.Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/R A is HIGH, ENA is HIGH, MBA is LOW, and FFA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/R A is LOW, ENA is HIGH, MBA is LOW, and EFA is HIGH (see Table 2).The port-B control signals are identical to those of port A.The state of the port-B data (B0-B35) outputs is controlled by the port-B chip select (CSB ) and the port-B write/read select (W/R B). The B0-B35 outputs are in the high-impedance state when either CSB or W/R B is HIGH. The B0-B35 outputs are active when both CSB and W/R B are LOW.Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/R B is HIGH, ENB is HIGH, MBB is LOW, and FFB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGHTable 3. Port-B Enable Function TableTable 2. Port-A Enable Function TableTable 1. Flag Programmingtransition of CLKB when CSB is LOW, W/R B is LOW, ENB is HIGH, MBB is LOW, and EFB is HIGH (see Table 3).The setup and hold time constraints to the port clocks for the port chip selects (CSA , CSB ) and write/read selects (W/R A, W/R B) are only for enabling write and read operations and are not related to high-impedance control of the data outputs.If a port enable is LOW during a clock cycle, the port chip select and write/read select may change states during the setup and hold time window of the cycle.SYNCHRONIZED FIFO FLAGSEach FIFO is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously to one an-other. EFA , AEA , FFA , and AFA are synchronized by CLKA.EFB , AEB , FFB , and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2.EMPTY FLAGS (EFA , EFB )The empty flag of a FIFO is synchronized to the port clock that reads data from its array. When the empty flag is HIGH,new data can be read to the FIFO output register. When the empty flag is LOW, the FIFO is empty and attempted FIFO reads are ignored.The read pointer of a FIFO is incremented each time a new word is clocked to the output register. The state machine that controls an empty flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2. A word written to a FIFO can be read to the FIFO output register in a minimum of three cycles of the empty flag synchronizing clock. Therefore,an empty flag is LOW if a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The empty flag of the FIFO is set HIGH by the second LOW-to-HIGH transition of the synchro-nizing clock, and the new data word can be read to the FIFO output register in the following cycle.A LOW-to-HIGH transition on an empty flag synchroniz-ing clock begins the first synchronization cycle of a write if the clock transition occurs at time t SKEW1 or greater after the write.Otherwise, the subsequent clock cycle can be the first syn-chronization cycle.FULL FLAG (FFA , FFB )The full flag of a FIFO is synchronized to the port clock that writes data to its array. When the full flag is HIGH, a memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is LOW and attempted writes to the FIFO are ignored.Each time a word is written to a FIFO, the write pointer is incremented. The state machine that controls a full flag monitors a write-pointer and read pointer comparator that indicates when the FIFO SRAM status is full, full-1, or full-2.From the time a word is read from a FIFO, the previous memory location is ready to be written in a minimum of three cycles of the full flag synchronizing clock. Therefore, a full flag is LOW if less than two cycles of the full flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the full flag synchronization clock after the read sets the full flag HIGH and the data can be written in the following clock cycle.A LOW-to-HIGH transition on a full flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t SKEW1 or greater after the read.Otherwise, the subsequent clock cycle can be the first syn-chronization cycle.ALMOST EMPTY FLAGS (AEA , AEB )The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an almost-empty flag monitors a write-pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The almost-empty state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during a device reset (see Reset above). An almost-empty flag is LOW when the FIFO containsTable 4. FIFO1 Flag OperationTable 5. FIFO2 Flag OperationNote:1.X is the value in the almost-empty flag and almost-full flag offset register.X or less words in memory and is HIGH when the FIFO contains (X+1) or more words.Two LOW-to-HIGH transitions of the almost-empty flag synchronizing clocks are required after a FIFO write for the almost-empty flag to reflect the new level of fill. Therefore, the almost-empty flag of a FIFO containing (X+1) or more words remains LOW if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An almost-empty flag is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time t SKEW2 or greater after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figure 6 and 7). ALMOST FULL FLAGS (AFA, AFB)The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The almost-full state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during a device reset (see Reset above). An almost-full flag is LOW when the FIFO contains (64-X) or more words in memory and is HIGH when the FIFO contains [64-(X+1)] or less words.Two LOW-to-HIGH transitions of the almost-full flag synchronizing clock are required after a FIFO read for the almost-full flag to reflect the new level of fill. Therefore, the almost-full flag of a FIFO containing [64-(X+1)]or less words remains LOW if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of words in memory to [64-(X+1)]. An almost-full flag is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock after the FIFO read that reduces the number of words in memory to [64-(X+1)]. A second LOW-to-HIGH transition of an almost-full flag synchronizing clock begins the first syn-chronization cycle if it occurs at time t SKEW2 or greater after the read that reduces the number of words in memory to [64-(X+1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figure 13 and 14). MAILBOX REGISTERSEach FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1 register when a port-A write is selected by CSA, W/R A, and ENA and MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0-B35 data to the mail2 register when a port-B write is selected by CSB, W/R B, and ENB and MBB is HIGH. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while the mail flag is LOW.When a port's data outputs are active, the data on the bus comes from the FIFO output register when the port mailbox-select input (MBA, MBB) is LOW and from the mail register when the port mailbox-select input is HIGH. The mail1 register flag (MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a port-B read is selected by CSB, W/R B, and ENB and MBB is HIGH. The mail2 register flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when port-A read is selected by CSA, W/R A, and ENA and MBA is HIGH. The data in a mail register remains intact after it is read and changes only when new data is written to the register.PARITY CHECKINGThe port-A inputs (A0-A35) and port-B inputs (B0-B35) each have four parity trees to check the parity of incoming (or outgoing) data. A parity failure on one or more bytes of the input bus is reported by a LOW level on the port parity error flag (PEFA, PEFB). Odd or even parity checking can be selected, and the parity error flags can be ignored if this feature is not desired.Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select input. A parity error on one or more bytes of a port is reported by a LOW level on the corresponding port parity error flag (PEFA, PEFB) output. Port-A bytes are arranged as A0-A8, A9-A17, A18-A26, and A27-A35 with the most significant bit of each byte used as the parity bit. Port-B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35, with the most significant bit of each byte used as the parity bit. When odd/even parity is selected, a port parity error flag (PEFA, PEFB) is LOW if any byte on the port has an odd/even number of LOW levels applied to the bits.The four parity trees used to check the A0-A35 inputs are shared by the mail2 register when parity generation is se-lected for port-A reads (PGA = HIGH). When a port-A read from the mail2 register with parity generation is selected with W/R A LOW, CSA LOW, ENA HIGH, MBA HIGH, and PGA HIGH, the port-A parity error flag (PEFA) is held HIGH regard-less of the levels applied to the A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are shared by the mail1 register when parity generation is selected for port-B reads (PGB = HIGH). When a port-B read from the mail1 register with parity generation is selected with W/R B LOW, CSB LOW, ENB HIGH, MBB HIGH, and PGB HIGH, the port-B parity error flag (PEFB) is held HIGH regardless of the levels applied to the B0-B35 inputs.PARITY GENERATIONA HIGH level on the port-A parity generate select (PGA) or port-B parity generate select (PGB) enables the IDT723612 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged as A0-A8, A9-A17, A18-26, and A27-A35, with the most significant bit of each byte used as the parity bit. Port-B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35, with the most significant bit of each byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all thirty-six inputs regard-less of the state of the parity generate select (PGA, PGB)inputs. When data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the ODD/EVEN select. The generated parity bits are substituted for the levels origi-nally written to the most significant bits of each byte as the word is read to the data outputs.Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the output register. Therefore, the port-A parity generate select (PGA) and odd/even parity select (ODD/EVEN) have setup and hold time constraints to the port-A clock (CLKA) and the port-B parity generate select (PGB) and ODD/EVEN have setup and hold-time constraints to the port-B clock (CLKB). These timing constraints only apply for a rising clock edge used to read a new word to the FIFO output register.The circuit used to generate parity for the mail1 data is shared by the port-B bus (B0-B35) to check parity and the circuit used to generate parity for the mail2 data is shared by the port-A bus (A0-A35) to check parity. The shared parity trees of a port are used to generate parity bits for the data in a mail register when the port write/read select (W/R A, W/R B) input is LOW, the port mail select (MBA, MBB) input is HIGH, chip select (CSA, CSB) is LOW, enable (ENA, ENB) is HIGH, and port parity generate select (PGA, PGB) is HIGH. Gener-ating parity for mail register data does not change the contents of the register.Figure 1. Device Reset Loading the X Register with the Value of EightCLKARST FFAFFBEFBAEACLKB EFAFS1,FS0AFA MBF1,MBF2AEBAFBNote:1.Written to FIFO1Figure 2. Port-A Write Cycle Timing for FIFO13136 drw 05CLKA FFA ENAA0 - A35MBACSAW/R AODD/EVEN PEFANote:1.Written to FIFO2Figure 3. Port-B Write Cycle Timing for FIFO23136 drw 06CLKB FFB ENBB0 - B35MBBCSBW/R BODD/EVEN PEFBNote:1.Read from FIFO1Figure 4. Port-B Read Cycle Timing for FIFO1Figure 5. Port-A Read Cycle Timing for FIFO2Note:1.Read from FIFO23136 drw 07CLKB EFB ENBB0 - B35MBBCSB W/R BPGB,ODD/EVEN3136 drw 08CLKA EFA ENAA0 - A35MBACSA W/R APGA,ODD/EVENNote:1.t SKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in thenext CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than t SKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.Figure 6. EFB Flag Timing and First Data Read when FIFO1 is EmptyCSA W R A MBAFFA A0 - A35CLKB EFB CSB W/R B MBB ENA ENBB0 -B35CLKA3136 drw 09Note:1.t SKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in thenext CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than t SKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.Figure 7. EFA Flag Timing and First Data Read when FIFO2 is EmptyCSB W R B MBBFFB B0 - B35CLKA EFA CSA W/R A MBA ENB ENAA0 -A35CLKB3136 drw 10Note:1.t SKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in thenext CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than t SKEW1, then FFA may transition HIGH one CLKA cycle later than shown.Figure 8. FFA Flag Timing and First Available Write when FIFO1 is Full.CSB EFB MBB ENBB0 - B35CLKB FFA CLKA CSA 3136 drw 11W R AA0 - A35MBAENAW/R BNote:1.t SKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in thenext CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than t SKEW1, then FFB may transition HIGH one CLKB cycle later than shown.Figure 9. FFB Flag Timing and First Available Write when FIFO2 is FullCSA EFA MBA ENAA0 - A35CLKA FFB CLKB CSB 3136 drw 12W R BB0 - B35MBBENBW/R ANotes:1.t SKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in thenext CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than t SKEW2, then AEA may transition HIGH one CLKA cycle later than shown.2.FIFO2 Write (CSB = LOW, W/R B = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/R A = LOW, MBA = LOW).Figure 11. Timing for AEA when FIFO2 is Almost EmptyNotes:1.t SKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in thenext CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than t SKEW2, then AEB may transition HIGH one CLKB cycle later than shown.2.FIFO1 Write (CSA = LOW, W/R A = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/R B = LOW, MBB = LOW).Figure 10. Timing for AEB when FIFO1 is Almost EmptyAEB CLKAENB3136 drw 13ENACLKBAEACLKBENA3136 drw 14ENBCLKANotes:1.t SKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in thenext CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than t SKEW2, then AFA may transition HIGH one CLKB cycle later than shown.2.FIFO1 Write (CSA = LOW, W/R A = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/R B = LOW, MBB = LOW).Figure 12. Timing for AFA when FIFO1 is Almost FullNotes:1.t SKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in thenext CLKB cycle. If the time between the rising CLKB edge and rising CLKA edge is less than t SKEW2, then AFB may transition HIGH one CLKA cycle later than shown.2.FIFO2 Write (CSB = LOW, W/R B = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/R A = LOW, MBA = LOW).Figure 13. Timing for AFB when FIFO2 is Almost FullAFA CLKAENB3136 drw 15ENACLKBAFB CLKBENA3136 drw 16ENBCLKANote:1.Port-B parity generation off (PGB = LOW)Figure 14. Timing for Mail1 Register and MBF1 Flag3136 drw 17CLKA ENA A0 - A35MBA CSA W/R A CLKBMBF1CSB MBB ENBB0 - B35W/R BNote:1.Port-A parity generation off (PGA = LOW)Figure 15. Timing for Mail2 Register and MBF2 Flag3136 drw 18CLKBENB B0 - B35MBB CSB W/R B CLKAMBF2CSA MBA ENAA0 - A35W/R AFigure 16. ODD/EVEN W/R A, MBA, and PGA to PEFA TimingNote:1.ENA is HIGH, and CSA is LOWFigure 17. ODD/EVEN W/R B, MBB, and PGB to PEFB TimingNote:1.ENB is HIGH, and CSB is LOW3136 drw 19PEFAPGAMBA W/R A3136 drw 20ODD/EVEN PEFBPGBMBB W/R BFigure 18. Parity Generation Timing when Reading from Mail2 RegisterNote:1.ENA is HIGHFigure 19. Parity Generation Timing when Reading from Mail1 RegisterNote:1.ENB is HIGH3136 drw 21A8, A17,A26, A35PGAMBA W/R ADataCSA 3136 drw 22ODD/EVEN B8, B17,B26, B35PGBMBB W/R BDataCSBFigure 20CALCULATING POWER DISSIPATIONThe I CC(f) current for the graph in Figure 20 was taken while simultaneously reading and writing the FIFO on theIDT723612 with CLKA and CLKB set to f S . All data inputs and data outputs change state during each clock cycle toconsume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load.Once the capacitance load per data-output channel is known, the power dissipation can be calculated with the equation below.With I CC(f ) taken from Figure 28, the maximum power dissipation (P D ) of the IDT723612 may be calculated by:P D = V CC x I CC(f) + ∑(C L x V CC x (V OH - V OL ) x f o )where:C L =output capacitance loadf o =switching frequency of an output V OH =output HIGH level voltage V OL=output LOW level voltageWhen no reads or writes are occurring on the IDT723612, the power dissipated by a single clock (CLKA or CLKB)input running at frequency f S is calculated by:P T = V CC x f S x 0.290 mA/MHzTYPICAL CHARACTERISTICSSUPPLY CURRENTvs10203040506080050100150200250300350400– Clock Frequency – MHzf s I C C (f )– S u p p l y C u r r e n t – m A3136 drw 2370Note:1.Includes probe and jig capacitanceFigure 21. Load Circuit and Voltage Waveforms3136 drw 24PARAMETER MEASUREMENT INFORMATIONFrom Output Under Test30 pF1.1 k Ω5 VLOAD CIRCUIT3 VGND Timing InputData,Enable InputGND3 VVOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONSVOLTAGE WAVEFORMSENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES3 V GNDGND 3 VOutput EnableLow-LevelOutputHigh-LevelOutput3 VOL GND 3 V ≈OHOV≈GNDOH OLInputHigh-LevelInputLow-LevelInputV V V V 3 V(1)ORDERING INFORMATIONBLANK PF PQF 152030L 7236123136 drw 25Commercial (0°C to +70°C)Thin Quad Flat Pack (TQFP, PN120-1)Plastic Quad Flat Pack (PQFP, PQ132-1)Low Power64 x 36 x 2 SyncBiFIFOXXXXXX IDTDevice TypeX XX X X PowerSpeedPackageProcess/Temperature RangeCommercial OnlyClock Cycle Time (t CLK )Speed in Nanoseconds。

Lcd12864最全中文资料

128*64L C D液晶显示屏中文资料一、概述二、带中文字库的128X64是一种具有4位/8位并行、2线或3线串行多种接口方式，内部含有国标一级、二级简体中文字库的点阵图形液晶显示模块；其显示分辨率为128×64, 内置8192个16*16点汉字，和128个16*8点ASCII字符集.利用该模块灵活的接口方式和简单、方便的操作指令，可构成全中文人机交互图形界面。

可以显示8×4行16×16点阵的汉字. 也可完成图形显示.低电压低功耗是其又一显著特点。

由该模块构成的液晶显示方案与同类型的图形点阵液晶显示模块相比，不论硬件电路结构或显示程序都要简洁得多，且该模块的价格也略低于相同点阵的图形液晶模块。

三、基本特性:（1）、低电源电压（VDD:+3.0--+5.5V）（2）、显示分辨率:128×64点（3）、内置汉字字库，提供8192个16×16点阵汉字(简繁体可选) （4）、内置 128个16×8点阵字符（5）、2MHZ时钟频率（6）、显示方式：STN、半透、正显（7）、驱动方式：1/32DUTY，1/5BIAS （8）、视角方向：6点（9）、背光方式：侧部高亮白色LED，功耗仅为普通LED的1/5—1/10 （10）、通讯方式：串行、并口可选（11）、内置DC-DC转换电路，无需外加负压（12）、无需片选信号，简化软件设计（13）、工作温度: 0℃ - +55℃ ,存储温度: -20℃ - +60℃模块接口说明：*注释1：如在实际应用中仅使用串口通讯模式，可将PSB接固定低电平，也可以将模块上的J8和“GND”用焊锡短接。

*注释2：模块内部接有上电复位电路，因此在不需要经常复位的场合可将该端悬空。

*注释3：如背光和模块共用一个电源，可以将模块上的JA、JK用焊锡短接。

2.2并行接口管脚号管脚名称电平管脚功能描述1 VSS 0V 电源地2 VCC 3.0+5V 电源正3 V0 - 对比度（亮度）调整4 RS(CS）H/L RS=“H”,表示DB7——DB0为显示数据RS=“L”,表示DB7——DB0为显示指令数据5 R/W(SID) H/L R/W=“H”,E=“H”,数据被读到DB7——DB0R/W=“L”,E=“H→L”,DB7——DB0的数据被写到IR或DR6 E(SCLK) H/L 使能信号7 DB0 H/L 三态数据线8 DB1 H/L 三态数据线9 DB2 H/L 三态数据线10 DB3 H/L 三态数据线11 DB4 H/L 三态数据线12 DB5 H/L 三态数据线13 DB6 H/L 三态数据线14 DB7 H/L 三态数据线15 PSB H/L H：8位或4位并口方式，L：串口方式（见注释1）16 NC - 空脚17 /RESET H/L 复位端，低电平有效（见注释2）18 VOUT - LCD驱动电压输出端19 A VDD 背光源正端（+5V）（见注释3）20 K VSS 背光源负端（见注释3）*注释1：如在实际应用中仅使用并口通讯模式，可将PSB接固定高电平，也可以将模块上的J8和“VCC”用焊锡短接。

ADS8506IDW;ADS8506IBDW;ADS8506IDWR;ADS8506IDWRG4;ADS8506IBDWR;中文规格书,Datasheet资料

BurrĆBrown Products from Texas InstrumentsFEATURESAPPLICATIONSDESCRIPTIONREFCAPR1INR2INADS8506SLAS484B–SEPTEMBER 2007–REVISED DECEMBER 200712-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITHINTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE•Industrial Process Control •40-kHz Min Sampling Rate•Test Equipment •4-V,5-V,and ±10-V Input Ranges •Medical Equipment•73.9-dB SINAD with 10-kHz Input •Data Acquisition Systems •±0.45LSB Max INL•Digital Signal Processing •±0.45LSB Max DNL,12-Bit No Missing Codes •Instrumentation•±5-mV BPZ,±0.5PPM/°C BPZ Drift •SPI Compatible Serial Output WithDaisy-Chain (TAG),SPI Master/Slave Feature The ADS8506is a complete low power,single 5-V •Single 5-V Analog Supplysupply,12-bit sampling analog-to-digital (A/D)•Pin-Compatible With ADS7806and 16-Bit converter.It contains a complete 12-bit ADS7807/8507capacitor-based,successive approximation register (SAR)A/D converter with sample and hold,clock,•Uses Internal or External 2.5-V Reference reference,and data interface.The converter can be •Low Power Dissipationconfigured for a variety of input ranges including ±10–24mW Typ,30mW Max at 40KSPS V,4V,and 5V.For most input ranges,the input voltage can swing to 25V or –25V without damage •50-µW Max Power Down Mode to the converter.•28-Pin SO Package A SPI compatible serial interface allows data to be •Full Parallel Interfacesynchronized to an internal or external clock.A full •2's Comp or BTC Output Codeparallel interface with BYTE select is also provided to allow the maximum system design flexibility.The ADS8506is specified at 40kHz sampling rate over the industrial -40°C to 85°C temperature range.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.QSPI,SPI are trademarks of Motorola.PRODUCTION DATA information is current as of publication date.Copyright ©2007,Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICSADS8506SLAS484B–SEPTEMBER2007–REVISED DECEMBER 2007These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.PACKAGE/ORDERING INFORMATION (1)FULL-MINIMUM NO SPECIFICATION SCALE PACKAGE PACKAGE ORDERING TRANSPORT PRODUCTINL MISSING TEMPERATUREERROR LEADDESIGNATORNUMBER MEDIA,QTY (LSB)CODERANGE (%)ADS8506IBDW Tube,20ADS8506IB ±0.4512±0.25-40°C to 85°C SO-28DW ADS8506IBDWR Tape and Reel,1000ADS8506IDW Tube,20ADS8506I±0.912±0.5-40°C to 85°CSO-28DWADS8506IDWRTape and Reel,1000(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI website at .over operating free-air temperature range (unless otherwise noted)(1)UNITR1IN±25V Analog inputsR2IN ±25VREF+V ANA +0.3V to AGND2-0.3VDGND,AGND2±0.3V V ANA6V Ground voltage differencesV DIG to V ANA 0.3V V DIG6VDigital inputs-0.3V to +V DIG +0.3VMaximum junction temperature 165°C Storage temperature range –65°C to 150°CInternal power dissipation700mW Lead temperature (soldering,1.6mm from case 10seconds)260°C(1)All voltage values are with respect to network ground terminal.At T A =-40°C to 85°C,f S =40kHz,V DIG =V ANA =5V,and using internal reference and fixed resistors,(see Figure 43)unless otherwise specified.(1)LSB means Least Significant Bit.One LSB for the ±10-V input range is 305µV.2Submit Documentation FeedbackCopyright ©2007,Texas Instruments IncorporatedProduct Folder Link(s):ADS8506ADS8506 SLAS484B–SEPTEMBER2007–REVISED DECEMBER2007ELECTRICAL CHARACTERISTICS(continued)At T A=-40°C to85°C,f S=40kHz,V DIG=V ANA=5V,and using internal reference and fixed resistors,(see Figure43)unless otherwise specified.ADS8506IB ADS8506I PARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAXDNL Differential linearity error-0.45±0.150.45-0.9±0.150.9LSB No missing codes1212Bits Transition noise(2)0.10.1LSB Gain Error±0.1±0.2% Full scale error(3)(4)-0.250.25-0.50.5% Full scale error drift±5±7ppm/°C Full scale error(3)(4)Ext.2.5-V Ref-0.250.25-0.50.5% Full scale error drift Ext.2.5-V Ref±0.5±0.5ppm/°C Bipolar zero error(3)±10V Range-1010-1010mV Bipolar zero error drift±10V Range±0.5±0.5ppm/°C Unipolar zero error(3)0V to5V,0V to4V Ranges-33-33mV Unipolar zero error drift0V to5V,0V to4V Ranges±0.5±0.5ppm/°CRecovery time to rated accuracy12.2-µF Capacitor to CAP1msfrom power down(5)Power supply sensitivity+4.75V<V S<+5.25V±0.5±0.5LSB (V DIG=V ANA=V S)AC ACCURACYSFDR Spurious-free dynamic range f IN=10kHz,±10V80988098dB(6) THD Total harmonic distortion f IN=10kHz,±10V-96-80-96-80dBf IN=10kHz,±10V7273.97073.9SINAD Signal-to-(noise+distortion)dB-60dB Input3232SNR Signal-to-noise72747074dB Usable bandwidth(7)f IN=10kHz,±10V130130kHz Full-power bandwidth(-3dB)600600kHz SAMPLING DYNAMICSAperture delay4040ns Aperture jitter2020ps Transient response FS Step55µs Overvoltage recovery(8)750750ns REFERENCEInternal reference voltage No load 2.48 2.5 2.52 2.48 2.5 2.52VInternal reference source current11µA (must use external buffer)Internal reference drift88ppm/°CExternal reference voltage range2.3 2.5 2.7 2.3 2.5 2.7Vfor specified linearityExternal reference current drain Ext.2.5-V Ref100100µA DIGITAL INPUTSV IL Low-level input voltage-0.3+0.8-0.3+0.8VV IH High-level input voltage 2.0V D+0.3V 2.0V D+0.3V VI IL Low-level input current V IL=0V±10±10µAI IH High-level input current V IH=5V±10±10µA DIGITAL OUTPUTS(2)Typical rms noise at worst case transitions.(3)As measured with fixed resistors,see Figure43.Adjustable to zero with external potentiometer.(4)Full scale error is the worst case of+Full Scale untrimmed deviation from ideal first and last code transitions,divided bythe transition voltage(not divided by the full-scale range)and includes the effect of offset error.(5)This is the time delay after the ADS8506is brought out of Power-Down mode until all internal settling occurs and the analog input isacquired to rated accuracy.A Convert command after this delay will yield accurate results.(6)All specifications in dB are referred to a full-scale input.(7)Usable bandwidth defined as full-scale input frequency at which Signal-to-(Noise+Distortion)degrades to60dB.(8)Recovers to specified performance after2x FS input overvoltage.Copyright©2007,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):ADS8506DEVICE INFORMATIONV DIG V ANA BUSY CS R/C BYTE TAG SDATA DATACLK D0D1D2R1IN AGND1CAP REF AGND2D7D6D5D4D3DGND 12345678910111213142827262524232221201918171615ADS8506R2IN SB/BTC EXT/INT REFD PWRD ADS8506SLAS484B–SEPTEMBER 2007–REVISED DECEMBER 2007ELECTRICAL CHARACTERISTICS (continued)At T A =-40°C to 85°C,f S =40kHz,V DIG =V ANA =5V,and using internal reference and fixed resistors,(see Figure 43)unless otherwise specified.ADS8506IBADS8506IPARAMETERTEST CONDITIONSUNITMINTYPMAXMINTYPMAXData format -Parallel 12-bits in 2-bytesData coding -Serial binary 2s complement or straight binaryV OL Low-level output voltage I SINK =1.6mA 0.40.4V V OHHigh-level output voltage I SOURCE =500µA 44V High-Z state,Leakage Current ±5±5µA V OUT =0V to V DIG Output capacitanceHigh-Z state1515pFDIGITAL TIMINGBus access time R L =3.3k Ω,C L =50pF 8383ns Bus relinquish timeR L =3.3k Ω,C L =10pF8383nsPOWER SUPPLIES V DIG Digital I/O voltage Must be ≤V ANA4.7555.25 4.755 5.25V V ANA ADC core voltage 4.755 5.254.755 5.25V I DIG Digital current 0.60.6mA I ANAAnalog current4.2 4.2mA V ANA =V DIG =5V,24302430mW f S =40kHz Power dissipationREFD High2020mW PWRD and REFD High5050µWTEMPERATURE RANGESpecified performance -4085-4085°C Derated performance -55125-55125°C Storage temperature-65150-65150°C SOThermal resistance (ΘJA )4646°C/W4Submit Documentation FeedbackCopyright ©2007,Texas Instruments IncorporatedProduct Folder Link(s):ADS8506ADS8506SLAS484B–SEPTEMBER2007–REVISED DECEMBER2007 Terminal FunctionsTERMINAL DIGITALDESCRIPTIONI/O1R1IN Analog Input.2AGND1Analog sense ed internally as ground reference point.Minimal current flow3R2IN Analog Input.4CAP Reference buffer output.2.2-µF Tantalum capacitor to ground.5REF Reference input/output.Outputs internal2.5-V reference.Can also be driven by external systemreference.In both cases,bypass to ground with a2.2-µF tantalum capacitor.6AGND2Analog ground7SB/BTC I Selects straight binary or binary2's complement for output data format.if high,data is output in astraight binary format.If low,data is output in a binary2's complement format.8EXT/INT I Selects external/Internal data clock for transmitting data.If high,data is output synchronized tothe clock input on DATACLK.If low,a convert command initiates the transmission of the datafrom the previous conversion,along with12-clock pulses output on DATACLK.9D7O Data bit3if BYTE is high.Data bit11(MSB)if BYTE is low.Hi-Z when CS is high and/or R/C islow.Leave unconnected when using serial output.10D6O Data bit2if BYTE is high.Data bit10if BYTE is low.Hi-Z when CS is high and/or R/C is low.11D5O Data bit1if BYTE is high.Data bit9if BYTE is low.Hi-Z when CS is high and/or R/C is low.12D4O Data bit0(LSB)if BYTE is high.Data bit8if BYTE is low.Hi-Z when CS is high and/or R/C islow.13D3O Ground if BYTE is high.Data bit7if BYTE is low.Hi-Z when CS is high and/or R/C is low.14DGND Digital ground15D2O Ground if BYTE is high.Data bit6if BYTE is low.Hi-Z when CS is high and/or R/C is low.16D1O Ground if BYTE is high.Data bit5if BYTE is low.Hi-Z when CS is high and/or R/C is low.17D0O Ground if BYTE is high.Data bit4if BYTE is low.Hi-Z when CS is high and/or R/C is low.18DATACLK I/O Either an input or an output depending on the EXT/INT level.Output data is synchronized to thisclock.If EXT/INT is low,DATACLK transmits12pulses after each conversion,and then remainslow between conversions.19SDATA O Serial data output.Data is synchronized to DATACLK,with the format determined by the level ofSB/BTC.In the external clock mode,after12bits of data,the ADC outputs the level input onTAG as long as CS is low and R/C is high.If EXT/INT is low,data is valid on both the rising andfalling edges of DATACLK,and between conversions SDATA stays at the level of the TAG inputwhen the conversion was started.20TAG I Tag input for use in the external clock mode.If EXT is high,digital data input from TAG is outputon DATA with a delay that is dependent on the external clock mode.21BYTE I Selects8most significant bits(low)or8least significant bits(high)on parallel output pins.22R/C I Read/convert input.With CS low,a falling edge on R/C puts the internal sample-and-hold into thehold state and starts a conversion.When EXT/INT is low,this also initiates the transmission ofthe data results from the previous conversion.23CS I Internally ORed with R/C.If R/C is low,a falling edge on CS initiates a new conversion.IfEXT/INT is low,this same falling edge will start the transmission of serial data results from theprevious conversion.24BUSY O At the start of a conversion,BUSY goes low and stays low until the conversion is completed andthe digital outputs have been updated.25PWRD I Power down input.If high,conversions are inhibited and power consumption is significantlyreduced.Results from the previous conversion are maintained in the output shift register.26REFD I REFD High shuts down the internal reference.External reference will be required forconversions.27V ANA ADC Core Supply.Nominally+5V.Decouple with0.1-µF ceramic and10-µF tantalumcapacitors.28V DIG Digital Interface Supply.Nominally+5V.Connect directly to pin27.Must be≤V ANA.Copyright©2007,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Link(s):ADS8506TYPICAL CHARACTERISTICS3.544.555.510203040f - Sampling Frequency - kHzs I - P o w e r S u p p l y C u r r e n t - m ACC 3.544.555.5-40-25-105203550658095110125T - Free-Air Temperature - ºCA I - P o w e r S u p p l y C u r r e n t - m AC C 2.4802.4852.4902.4952.5002.5052.5102.5152.520-40-25-105203550658095110125V - I n t e r n a l R e f e r e n c e V o l t a g e - Vr e f T - Free-Air Temperature - ºCAB i p o l a r P o s i t i v e F u l l -S c a l e E r r o r - %F S RT - Free-Air Temperature - ºC A -0.2-0.15-0.1-0.05-45-30-150153045607590105120T - Free-Air Temperature - ºCA B i p o l a r N e g a t i v e F u l l -S c a l e E r r o r - %F SRB i p o l a r O f f s e t E r r o r - m V-45-30-150153045607590105120T - Free-Air Temperature - ºCA ADS8506SLAS484B–SEPTEMBER 2007–REVISED DECEMBER 2007Table 1.Input Range Connections (see Figure 42and Figure 43)ANALOG INPUTCONNECT R1IN VIA 200ΩTOCONNECT R2IN VIA 100ΩTOIMPEDANCE RANGE±10V V IN CAP 45.7k Ω0V to 5V AGND V IN 20.0k Ω0V to 4VV INV IN21.4k ΩPOWER SUPPLY CURRENTINTERNAL REFERENCEPOWER SUPPLY CURRENTvsvsvsFREE-AIR TEMPERATUREFREE-AIR TEMPERATURESAMPLING FREQUENCYFigure 1.Figure 2.Figure 3.BIPOLAR POSITIVE FULL-SCALEBIPOLAR NEGATIVE FULL-SCALEBIPOLAR OFFSET ERRORERROR ERROR vsvsvsFREE-AIR TEMPERATUREFREE-AIR TEMPERATUREFREE-AIR TEMPERATUREFigure 4.Figure 5.Figure 6.6Submit Documentation FeedbackCopyright ©2007,Texas Instruments IncorporatedProduct Folder Link(s):ADS8506-2-1123U n i p o l a r O f f s e t E r r o r - m VT - Free-Air Temperature - ºC AU n i p o l a r F u l l -S c a l e E r r o r - %F S RT - Free-Air Temperature - ºCA0T - Free-Air Temperature - ºC A U n i p o l a r F u l l -S c a l e E r r o r - %F S R-50-250255075100125T - Free-Air Temperature - ºCA T H D - T o t a l H a r m o n i c D i s t o r t i o n - d B-50-250255075100125S N R- S i g n a l -t o -N o i s e R a t i o - d BT - Free-Air Temperature - ºCA -50-250255075100125S F D R - S p u r i o u s F r e e D y n a m i c R a n g e - d BT - Free-Air Temperature - ºCA1020304050607080900S I N A D - S i g n a l -t o -N o i s e a n d D i s t o r t i o n - d Bf - Frequency - kHzS I N A D - S i g n a l -t o -N o i s e a n d D i s t o r t i o n - d BT - Free-Air Temperature - ºCA606570758085-50-250255075100125S I N A D - S i g n a l -t o -N o i s e a n d D i s t o r t i o n - d BT - Free-Air Temperature - ºCA ADS8506SLAS484B–SEPTEMBER 2007–REVISED DECEMBER 2007TYPICAL CHARACTERISTICS (continued)UNIPOLAR OFFSET ERRORUNIPOLAR FULL-SCALE ERRORUNIPOLAR FULL-SCALE ERRORvsvsvsFREE-AIR TEMPERATUREFREE-AIR TEMPERATUREFREE-AIR TEMPERATUREFigure 7.Figure 8.Figure 9.SPURIOUS FREE DYNAMIC RANGETOTAL HARMONIC DISTORTIONSIGNAL-TO-NOISE RATIOvsvsvsFREE-AIR TEMPERATUREFREE-AIR TEMPERATUREFREE-AIR TEMPERATUREFigure 10.Figure 11.Figure 12.SIGNAL-TO-NOISE AND DISTORTIONSIGNAL-TO-NOISE AND DISTORTIONSIGNAL-TO-NOISE AND DISTORTIONvsvsvsFREE-AIR TEMPERATUREFREQUENCYFREE-AIR TEMPERATUREFigure 13.Figure 14.Figure 15.Copyright ©2007,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):ADS8506110f - Frequency - kHzS N R - S i g n a l -t o -N o i s e R a t i o - d B5060708090f - Frequency - kHzS I N A D - S i g n a l -t o -N o i s e a n d D i s t o r t i o n - d B1101001000f - Frequency - kHzS F D R - S p u r i o u s F r e e D y n a m i c R a n g e - d B-110-100-90-80-70-601101001000f - Frequency - kHzT H D - T o t a l H a r m o n i c D i s t o r t i o n - d BESR -W-110-105-100-95-90-85-80T H D - T o t a l H a r m o n i c D i s t o r t i o n - d B7580859095100105110115012345678910ESR -WS F D R - S p u r i o u s F r e e D y n a m i c R a n g e - d B-80-70-60-50-40-30-20Power-Supply Ripple Frequency - HzO u t p u t R e j e c t i o n - d B556065707580859012345678910ESR -WS N R - S i g n a l -t o -N o i s e R a t i o - d B556065707580859095012345678910ESR -WS I N A D - S i g n a l -t o -N o i s e a n d D i s t o r t i o n - d BADS8506SLAS484B–SEPTEMBER 2007–REVISED DECEMBER 2007TYPICAL CHARACTERISTICS (continued)SIGNAL-TO-NOISE RATIOSIGNAL-TO-NOISE AND DISTORTIONSPURIOUS FREE DYNAMIC RANGEvsvsvsFREQUENCYFREQUENCYFREQUENCYFigure 16.Figure 17.Figure 18.TOTAL HARMONIC DISTORTIONSPURIOUS FREE DYNAMIC RANGETOTAL HARMONIC DISTORTIONvsvsvsFREQUENCYEQUIVALENT SERIES RESISTOREQUIVALENT SERIES RESISTORFigure 19.Figure 20.Figure 21.OUTPUT REJECTIONSIGNAL-TO-NOISE RATIOSIGNAL-TO-NOISE AND DISTORTIONvsvsvsPOWER-SUPPLY RIPPLEEQUIVALENT SERIES RESISTOREQUIVALENT SERIES RESISTORFREQUENCYFigure 22.Figure 23.Figure 24.8Submit Documentation FeedbackCopyright ©2007,Texas Instruments IncorporatedProduct Folder Link(s):ADS85061313.113.213.313.413.513.6-50-250255075100125t - C o n v e r s i o n T i m e -sC O N V E R T m T - Free-Air Temperature - ºCA INL-0.3-0.2-0.100.10.20.3I N L - L S B s5121024153620482560307235844095CodeDNL-0.3-0.2-0.100.10.20.3D N L - L S B s5121024153620482560307235844095CodeADS8506SLAS484B–SEPTEMBER 2007–REVISED DECEMBER 2007TYPICAL CHARACTERISTICS (continued)CONVERSION TIMEvsFREE-AIR TEMPERATUREFigure 25.Figure 26.Figure 27.Copyright ©2007,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):ADS8506FFT05101520f - Frequency - kHzAmplitude-dBFFTf - Frequency - kHzAmplitude-dBFFT-130-120-110-100-90-80-70-60-50-40-30-20-1005101520f - Frequency - kHzAmplitude-dBBASIC OPERATIONPARALLEL OUTPUTADS8506SLAS484B–SEPTEMBER2007–REVISED DECEMBER2007TYPICAL CHARACTERISTICS(continued)Figure28.Figure29.Figure30.Figure31shows a basic circuit to operate the ADS8506with a±10-V input range and parallel output.Taking R/C for a minimum of40ns(12µs max)will initiate a conversion.BUSY(pin24)will go LOW and stay10Submit Documentation Feedback Copyright©2007,Texas Instruments IncorporatedProduct Folder Link(s):ADS8506分销商库存信息:TIADS8506IDW ADS8506IBDW ADS8506IDWR ADS8506IDWRG4ADS8506IBDWR ADS8506IBDWRG4 ADS8506IDWG4ADS8506IBDWG4。

TLV1562IDW;TLV1562CPW;TLV1562IPW;TLV1562CPWG4;TLV1562IPWG4;中文规格书,Datasheet资料

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
D D D D D D D D D D D D D D D D
Built-In Internal/System Mid-Scale Error Calibration Built-In Mux With 2 Differential or 4 Single-Ended Input Channels Low Input Capacitance (10 pF Max Fixed, 1 pF Max Switching) DSP/µ P-Compatible Parallel Interface
TLV1562 2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
applications
Portable Digital Radios Personal Communication Assistants Cellular Pager Scanner Digitizers Process Controls Motor Control Remote Sensing Automotive Servo Controls Cameras

音频功放IC NS4162

7 芯片管脚描述.................................................................................................................................................... 4
ta25vdd50vns4162电气特性符号参数测试条件最小值标准值最大值单位dd电源电压dd电源静态电流dd50v0vnoloadsd关断漏电流ctrl0vos输出失调电压1040mv217hz80dbpsrr电源抑制比20khz72dbcmrr共模抑制比70dbsw调制频率dd3v525v450khz效率po25wrdd5vclassthictrl高电平时间1020tloctrl低电平时间1020toffctrl关断时间100usvih逻辑控制高电平14vil逻辑控制低电平04thdn1f1khzr输出功率thdn1f1khzrnss4411662noisegate控制功能5v5w双输入单输出abd类切换音频功放nsiaythdn1f1khzrthdn10f1khzrthdn10f1khzrthdn10f1khzrthdn总失真度噪声vd2f1khz4po10w01snr信噪比rl4po10w90db芯片管脚描述71ns4162封装管脚分配图nsiwayns416210111213141516ndetenctrlvrefmixsigdetvddinnvinpvinnainpavo1pvddpgndvo2gndabdns4162封装管脚分配图topviewnss4411662noisegate控制功能5v5w双输入单输出abd类切换音频功放nsiay72ns4162引脚功能描述ns4162管脚描述符号管脚号描述nenoisegate功能ctrl关断以及工作模式控制脚vref部参考电压外接去藕电容mix音和音乐输入通道叠加使能siisegate功能开启时的信号状态输出vdd电源输入语音输入负端innv语音输入正端inna音乐输入负端inpa10音乐输入正端vo111功放输出正端vdd12电源输入pgnd13vo214功放输出负端gnd15abd16ab典型参考特性ns4162nss4411662noisegate控制功能5v5w双输入单输出abd类切换音频功放nsinss4411662noisegate控制功能5v5w双输入单输出abd类切换音频功放nsiayoutputpowervssupplyvoltagesupplyvoltage25303540455035302520151005rl433uhf1khzthdn1outputpowervssupplyvoltagesupplyvoltage25303540

W981216BH中文资料

W981216BH2M × 4 BANKS × 16 BIT SDRAMPublication Release Date: October 2000- 1 - Revision A1GENERAL DESCRIPTIONW981216BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 2M words × 4 banks × 16 bits. Using pipelined architecture and 0.175 µm process technology, W981216BH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the personal computer industrial standard, W981216BH is sorted into three speed grades: -7, -75 and -8H. The -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is compliant to the PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specificationAccesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W981216BH is ideal for main memory in high performance applications.FEATURES• 3.3V ±0.3V Power Supply • Up to 143 MHz Clock Frequency• 2,097,152 Words × 4 banks × 16 bits organization • Auto Refresh and Self Refresh • CAS Latency: 2 and 3• Burst Length: 1, 2, 4, 8, and full page • Burst Read, Single Writes Mode • Byte Data Controlled by DQM • Power-Down Mode• Auto-precharge and Controlled Precharge • 4K Refresh cycles / 64 mS • Interface: LVTTL• Packaged in TSOP II 54 pin, 400 mil - 0.80KEY PARAMETERSSYM.DESCRIPTIONMIN. /MAX.-7(PC133, CL2)-75(PC133, CL3)-8H (PC100)t CK Clock Cycle Time Min. 7 nS 7.5 nS 8 nS t AC Access Time from CLK Max. 5.4 nS 5.4 nS 6 nS t RP Precharge to Active Command Min. 15 nS 20 nS 20 nS t RCD Active to Read/Write Command Min. 15 nS 20 nS 20 nS I CC1 Operation Current (Single bank) Max. 80 mA 75 mA 70 mA I CC4 Burst Operation Current Max. 100 mA 95 mA 90 mA I CC6Self-Refresh CurrentMax.2 mA2 mA2 mAW981216BH- 2 -PIN CONFIGURATIONW981216BHPublication Release Date: October 2000- 3 - Revision A1PIN DESCRIPTIONW981216BH- 4 -BLOCK DIAGRAMW981216BHPublication Release Date: October 2000- 5 - Revision A1ABSOLUTE MAXIMUM RATINGSPARAMETERSYMBOLRATINGUNITInput/Output Voltage V IN, V OUT -0.3 − V CC +0.3 V Power Supply Voltage V CC , V CCQ -0.3 − 4.6 VOperating Temperature T OPR 0 − 70 °C Storage Temperature T STG -55 − 150 °C Soldering Temperature (10s) T SOLDER 260 °CPower DissipationP D 1 W Short Circuit Output CurrentI OUT50mANote: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliabilityof the device.RECOMMENDED DC OPERATING CONDITIONS(T A = 0 to 70°C)PARAMETER SYMBOL MIN. TYP. MAX. UNITPower Supply Voltage V CC 3.0 3.3 3.6 V Power Supply Voltage (for I/O Buffer)V CCQ 3.0 3.3 3.6 V Input High Voltage V IH 2.0 - V CC +0.3 V Input Low VoltageV IL-0.3-0.8VNote: V IH (max) = V CC / V CC Q+1.2V for pulse width < 5 nS V IL (min) = V SS / V SS Q-1.2V for pulse width < 5 nSCAPACITANCE(V CC = 3.3V, f = 1 MHz, T A = 25°C)Note: These parameters are periodically sampled and not 100% tested.W981216BH- 6 -AC CHARACTERISTICS AND OPERATING CONDITION(Vcc = 3.3V ± 0.3V, T A = 0° to 70°C; Notes: 5, 6, 7, 8)PARAMETERSYM.-7(PC133, CL2)-75(PC133, CL3)-8H (PC100)UNITMIN.MAX.MIN.MAX.MIN.MAX.Ref/Active to Ref/Active Command Periodt RC 57 65 68 Active to precharge Command Periodt RAS 42 10000045 10000048 100000nS Active to Read/Write Command Delay Timet RCD 15 20 20 Read/Write(a) toRead/Write(b)Command Period t CCD 1 1 1 Cycle Precharge to Active Command Periodt RP 15 20 20 Active(a) to Active(b) Command Periodt RRD 15 15 20 Write Recovery Time CL* = 2 t WR 7.5 10 10CL* = 3 7 7.5 8 CLK Cycle Time CL* = 2 t CK7.5 1000 10 1000 10 1000CL* = 3710007.5100081000CLK High Level width t CH 2.5 2.5 3 CLK Low Level widtht CL2.52.53Access Time from CLKCL* = 2 t AC5.4 6 6CL* = 35.4 5.4 6 nS Output Data Hold Timet OH 3 3 3 Output Data High Impedance Time t HZ 3 7 3 7.5 3 8 Output Data Low Impedance Time t LZ 0 0 0 Power Down Mode Entry Time t SB 0 7 0 7.5 0 8 Transition Time of CLK (Rise and Fall) t T 0.5 10 0.5 10 0.5 10 Data-in Set-up Time t DS 1.5 1.5 2 Data-in Hold Time t DH 0.8 0.8 1 Address Set-up Time t AS 1.5 1.5 2 Address Hold Time t AH 0.8 0.8 1 CKE Set-up Time t CKS 1.5 1.5 2 CKE Hold Time t CKH 0.8 0.8 1 Command Set-up Time t CMS 1.5 1.5 2 Command Hold Time t CMH 0.8 0.8 1 Refresh Timet REF 64 64 64 mS Mode register Set Cycle Timet RSC141516nS*CL = CAS LatencyW981216BHPublication Release Date: October 2000- 7 - Revision A1DC CHARACTERISTICS(V CC = 3.3V ± 0.3V, T A = 0°− 70°C)PARAMETERSYMBOL MIN. MAX. UNIT NOTESInput Leakage Current(0V ≤ V IN ≤ V CC , all other pins not under test = 0V) I I(L)-55µAOutput Leakage Current(Output disable , 0V ≤ V OUT ≤ V CCQ ) I O(L)-55µALVTTL Output ″H ″ Level Voltage (I OUT = -2 mA )V OH2.4-VLVTTL Output ″L ″ Level Voltage (I OUT = 2 mA )V OL-0.4VW981216BH- 8 -Notes:1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.2. All voltages are referenced to V SS3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of t CK and t RC .4. These parameters depend on the output loading conditions. Specified values are obtained with output open.5. Power up sequence is further described in the "Functional Description" section.6. AC Testing ConditionsOutput Reference Level 1.4V/1.4V Output Load See diagram belowInput Signal Levels2.4V/0.4V Transition Time (Rise and Fall) of Input Signal2 nS Input Reference Level1.4V7. Transition times are measured between V IH and V IL .8. t HZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.W981216BHPublication Release Date: October 2000- 9 - Revision A1OPERATION MODEFully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. Table 1 Truth Table (Note (1), (2))Notes:(1) v = valid x = Don't care L = Low Level H = High Level (2) CKEn signal is input level when commands are provided.CKEn-1 signal is the input level one clock cycle before the command is issued. (3) These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation.(5) Power Down Mode can not be entered in the burst cycle.When this command asserts in the burst cycle, device state is clock suspend mode.W981216BH- 10 -FUNCTIONAL DESCRIPTIONPower Up and InitializationThe default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs.During power up, all Vcc and VccQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed V C C +0.3V on any of the input pins or Vcc supplies. After power up, an initial pause of 200 µS is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation.Programming Mode RegisterAfter initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS, CAS, CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to t RSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.Bank Activate CommandThe Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (t RCD ). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t RC ). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t RRD ). The maximum time that each bank can be held active is specified as t RAS (max).Read and Write Access ModesAfter a bank has been activated , a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of t RCD delay. WE pin voltage level defines whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address.Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle.W981216BHPublication Release Date: October 2000- 11 - Revision A1Burst Read CommandThe Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequential mode.Burst Write CommandThe Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored.Read Interrupted by a ReadA Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command the is satisfied.Read Interrupted by a WriteTo interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed.Write Interrupted by a WriteA burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.Write Interrupted by a ReadA Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored.Burst Stop CommandA Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burstW981216BH- 12 -read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored.Addressing Sequence of Sequential ModeA column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2.Table 2 Address Sequence of Sequential ModeAddressing Sequence of Interleave ModeA column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3.Table 3 Address Sequence of Interleave ModeW981216BHPublication Release Date: October 2000- 13 - Revision A1Auto-Precharge CommandIf A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS latency.A Read or Write Command with auto-precharge can not be interrupted before the entire burst operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (t RP ) has been satisfied. Issue of Auto-Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock delay from the last burst write cycle. This delay is referred to as Write t W R . The bank undergoing auto-precharge can not be reactivated until t W R and t RP are satisfied. This is referred to as t DAL , Data-in to Active delay (t DAL = t W R + t RP ). When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy t RAS (min).Precharge CommandThe Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (t RP ).Self Refresh CommandThe Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the t AC cycle time plus the Self Refresh exit time.If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode.Power Down ModeThe Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (t REF ) of the device.W981216BH- 14 -The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on t CK . The input buffers need to be enabled with CKE held high for a period equal to t CKS (min) + t CK (min).No Operation CommandThe No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.Deselect CommandThe Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't cares.Clock Suspend ModeDuring normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited.W981216BHPublication Release Date: October 2000- 15 - Revision A1TIMING WAVEFORMSCommand Input TimingW981216BH- 16 -Timing Waveforms, continuedRead TimingW981216BHPublication Release Date: October 2000- 17 - Revision A1Timing Waveforms, continuedControl Timing of Input / Output DataW981216BH- 18 -Timing Waveforms, continuedMode Register Set CycleW981216BHPublication Release Date: October 2000- 19 - Revision A1OPERATING TIMING EXAMPLEInterleaved Bank Read (Burst Length = 4, CAS Latency = 3)t RCt RASt RPt RASt RCD t RCDt RRDRAaRBdW981216BH- 20 -Operating Timing Example, continedInterleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)(CLK = 100 MHz)t RCt RASt RPt RPt RCDt RRD t RRDW981216BHPublication Release Date: October 2000- 21 - Revision A1Operating Timing Example, continedInterleaved Bank Read (Burst Length = 8, CAS Latency = 3)t RRDW981216BH- 22 -Operating Timing Example, continedInterleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge)W981216BHPublication Release Date: October 2000- 23 - Revision A1Operating Timing Example, continedInterleaved Bank Write (Burst Length = 8)RRDW981216BH- 24 -Operating Timing Example, continedInterleaved Bank Write (Burst Length = 8, Autoprecharge)W981216BHPublication Release Date: October 2000- 25 - Revision A1Operating Timing Example, continedPage Mode Read (Burst Length = 4, CAS Latency = 3)W981216BH- 26 -Operating Timing Example, continedPage Mode Read / Write (Burst Length = 8, CAS Latency = 3)W981216BHPublication Release Date: October 2000- 27 - Revision A1Operating Timing Example, continedAuto Precharge Read (Burst Length = 4, CAS Latency = 3)(CLK = 100 MHz)CLKDQCKEDQMA0-A9,A11A10BS1WECASRASCSBS0t RCt RCDW981216BH- 28 -Operating Timing Example, continedAuto Precharge Write (Burst Length = 4)t RCt RP t RPW981216BHPublication Release Date: October 2000- 29 - Revision A1Operating Timing Example, continedAuto Refresh Cycle(CLK = 100 MHz)All Banks Prechage Auto RefreshAuto Refresh (Arbitrary Cycle)t RC t RCW981216BH- 30 -Operating Timing Example, continedSelf Refresh Cyclet SBW981216BHPublication Release Date: October 2000- 31 - Revision A1Operating Timing Example, continedBurst Read and Single Write (Burst Length = 4, CAS Latency = 3)t RCDW981216BH- 32 -Operating Timing Example, continedPowerDown Modet SBNOPW981216BHPublication Release Date: October 2000- 33 - Revision A1Operating Timing Example, continedAutoprecharge Timing (Read Cycle)APAPActActQ0Q6Q7t RPW981216BH- 34 -Operating Timing Example, continedAutoprecharge Timing (Write Cycle)D1D3D7(1) CAS Latency=2When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS (min).represents the Write with Auto precharge command.represents the start of internal precharging.represents the Bank Activate command.Note )W981216BHPublication Release Date: October 2000- 35 - Revision A1Operating Timing Example, continedTiming Chart of Read to Write CycleTiming Chart of Write to Read CycleW981216BH- 36 -Operating Timing Example, continedTiming Chart of Burst Stop Cycle (Burst Stop Command)Timing Chart of Burst Stop Cycle (Precharge Command)PRCGW981216BHPublication Release Date: October 2000- 37 - Revision A1Operating Timing Example, continedCKE/DQM Input Timing (Write Cycle)W981216BH- 38 -Operating Timing Example, continedCKE/DQM Input Timing (Read Cycle)W981216BHPublication Release Date: October 2000- 39 - Revision A1Operating Timing Example, continedSelf Refresh/Power Down Mode Exit TimingW981216BH- 40 -PACKAGE DIMENSION54L TSOP (II)-400 milW981216BHPublication Release Date: October 2000- 41 - Revision A1No. 4, Creation Rd. III,/11F, No. 115, Sec. 3, MinUnit 9Winbond Memory Lab.TEL: 408HeadquartersScience -Based Industrial Park,Hsinchu, TaiwanTEL: 886-3-5770066FAX: 886-3-5796096Voice & Fax -on -demand: 886-2-27197006Taipei Office-Sheng East Rd.,Taipei, TaiwanTEL: 886-2-27190505FAX: 886-2-27197502 Winbond Electronics (H.K.) Ltd.-15, 22F, Millennium City, No. 378 Kwun Tong Rd; Kowloon, Hong Kong TEL: 852-********FAX: 852-********Winbond Electronics North America Corp.Winbond Microelectronics Corp.Winbond Systems Lab.2727 N. First Street, San Jose,CA 95134, U.S.A.-9436666FAX: 408-5441798Note: All data and specifications are subject to change withou t notice.。