NJU8754中文资料

合集下载

低抖动的串行／解串器芯片组

ＡＴ一（Ｐ２ＡＷＧ屏蔽电缆）的数据６Ｒ３１Ｃ接１，能够支持高达１０／的通成的器件中包含了３个Ｉ２７１０ＫｂｓＣ的功能（时钟Ｃ信速率。０和数据恢复、串行器和解串器）可显著传输范围延长至２ｍ以上，也可支持多，
记录仪
闪存和基于ＰＬ
可用于不同的工业、科学和医疗（Ｓ时，仍然能够提供极佳的抖动容差特ＩＭ）
基于Ｆ—ＲＡＭ的事件数据记录仪频段：３５１ＭＨｚ３ＭＨｚ６ＭＨｚ、４４、８８和性，以支持前向纠错。另外，上行速率（ＤＥＲ）Ｆ４Ｍ６是集成式的事件监控解１２决方案，能够连续监控状态的变化，将
ＭｉｒｃｉＴｅｈｏｏｙｃｏｈｐｃｎｌｇ
消费产品，超越了红外线通信方式的许设备制造商的成本和功耗。该器件适合
多限制。
ＰＭＡ７０１５
用于ＶｅｉｏｉＳ等ＦＴＨ装置中的ｒｚｎＦＯＴ
光网络终端。
ＭＡＸ３８８６采用专有的ＣＤＲ技术，
９１ＭＨＺ５。
可以配置为与下行速率相等（对称工作方
或非只需少量组件，ＭＡ７５可实现式）下行频率的因数（对称工作方Ｐ就１０
。数据存储在ＦＲＡＭ中并向系统提出有家居自动化系统、安防和报警系统、音式） —
可激活事件的时间戳，并作为系统的时
钟和日历。

电路图集

D
VDD IN COM MUTE STBY
VSS OUTP VDDO OUTN VSS
10 9 8 7 6 C19 C22 104
L8 L9
22UH 22UH C23 105
SP2 8ohms SPEAKER
U3 NJU8754 SSOP10 A5V C25 104 10UF/16V 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
10K
9 1N4148 11 7 6 5 1.5K
TL494 4 3 2 1
5.6K
VCC 20K 15K 910 B
B
150k 1/2w
2 330K/1/2W 4.7uF 50V
1
4
EI19 7 8 1N4148 1N4753 36v
100K 2
1N4148
FR105
NPN 2sc2625
2.4K
1
2
3
4
5
6
VDD5V USB1 1 2 3 4 L2 C1 101 C2 101 L1 C4 104 R1 22 R2 22 R3 10K R4 10K
USBDM C17 224 LOR C18 104 BUZZ USBDP
R13 4K7 1 2 3 4 5 R15 4K7 C21
VDD5V
R14 4K7
将半桥式变换器电路中的两个电解电容换成另外两只高反压功率晶体管，并配以图所示。 VTl、 VT2、 VT3、 VT4组成4个桥臂。高频变压器T连接在它们中间。相对替导通，将直流输入电压变换成高频方波交流电压。其工作过程与推挽式功率转线圈得到的电压即为电源电压。它是半桥电路输出电压的一倍，而每个晶体管耐流达到半桥电路的水平，即电流增大一倍的话，则输出功率就可以增大 4倍。全桥极驱动电路，使控制驱动电路成本增大并复杂化。

湖大微机原理及其应用第6章

控制字的格式如图6.4所示
D7 D6 D计0 数器
D5
D4
读/写格式
D3
D2
工作方式
D1 数制
图6.4 8253控制字格式注：图中×可以是0，也可以是1，一般取0
0 —二进制 1 —二― 十进制（BCD）
000 方式0 001 方式1
10 方式2 11 方式3
100 方式4 101 方式5 00 计数器锁存命令 10 只读/写高8位 01 只读/写低8位 11 首先写低8位
定时范围不易由程序来改变和控制，使用不甚
方便，而且定时精度也不高。
3.可编程的定时器
采用软、硬件相结合的方法，用可编程定时计数器芯片（如Intel 8253），构成一个方便灵活的定时计数电路；
这种电路不仅定时值和定时范围可用程序确定和改变，而且具有多种工作方式，可以输出多种控制信号；
由微处理器的时钟信号提供时间基准，故计时也精确稳定。
④ A1A0: 端口选择信号, 当A1A0=00，01，10时表示分别选中计数器0，1，2 ；当A1A0=11时选中控制寄存器。
（3）控制寄存器
• 接收从CPU来的控制字； • 并由控制字的D7、D6位的编码决定该控制字写
入哪个计数器的控制寄存器； • 控制寄存器只能写入，不能读出。
（4）计数器
8253具有较好的通用性和使用灵活性，几乎适合于任何一种微处理器组成的系统。
2. 8253的内部结构
图6.1 8253的内部结构示意图
（1）数据总线缓冲器
8位、双向、三态的缓冲器，可直接挂在数据总线上。 CPU通过数据总线D0~D7传送如下信息：
① 向控制寄存器写入控制字； ② 向某计数器写入计数初值； ③ CPU读取某个计数器的当前计数值。

2N5484中文资料

**L2 **L3
6 turns, (approx. — depends upon circuit layout) AWG #24 enameled copper wire, close wound on 7/32″ ceramic coil form. Tuning provided by an aluminum slug. 1 turn, AWG #16 enameled copper wire, 3/8″ I.D. (AIR CORE). 1/2 turn, AWG #16 enameled copper wire, 1/4″ I.D. (AIR CORE).
POWER GAIN
24 f = 100 MHz
20 PG , POWER GAIN (dB)
16
12
400 MHz Tchannel = 25°C VDS = 15 Vdc VGS = 0 V 0 2.0 4.0 6.0 8.0 10 ID, DRAIN CURRENT (mA) 12 14
8.0 4.0
Figure 2. 100 MHz and 400 MHz Neutralized Test Circuit
NOISE FIGURE
(Tchannel = 25°C)
10 ID = 5.0 mA 8.0 NF, NOISE FIGURE (dB) NF, NOISE FIGURE (dB) 5.5 6.5 VDS = 15 V VGS = 0 V
1 2 3
CASE 29–04, STYLE 5 TO–92 (TO–226AA)
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

8753E8753ES8753D说明书

HP8753E 射频网络分析仪★频率范围：30kHz~3或6GHz★带有固态转换的集成化S参数测试装置★达110dB的动态范围★快的测量速度和数据传递速率★大屏幕LCD显示器加上供外部监视器用的VGA输出★同时显示所有4个S参数★将仪器状态和数据存储/调用到内置软盘驱动器★可选用的时域测量和扫描谐波测量HP 8753E射频网络分析仪为满足研制实验室或生产制造的测试需求，在速度、性能和方便使用上提供了无与伦比的结合。

8753E以其覆盖3或6GHz频率范围的集成化S参数测试装置、达110dB的动态范围以及频率扫描和功率扫描，为表征有源或无源网络、元器件和子系统的线性和非线性特性提供了圆满的解决方案。

所使用的新型微处理器使测量和数据传递速率比以往的型号快达7倍之多。

网络分析仪的特点是有2个独立的测量通道，可同时测量和显示所有4个S参数。

可以选择用幅度、相位、群延迟、史密斯圆图、极坐标、驻波比或时域格式来显示反射和传输参数的任意组合。

便于使用的专用功能键能迅速访问各个测量功能。

可以利用达4个刻度格子在高分辩率的LCD彩色显示器上以重叠或分离屏面的形式来观察测量结果。

为了驱动更大的外部监视器，以便于观察，增加了与VGA兼容的输出。

较好的通用性和性能一个集成化的合成源提供了达10mW的输出功率(用选件011可达100mW)，1Hz的频率分辩率和线性频率，对数频率，列表频率，CW和功率扫描功能。

三个调谐接收机可以在6GHz(带有选件006频率扩展)处105dB或3GHz(标准)110dB的宽动态范围内进行独立的功率测量或同时比值测量。

集成化的测试装置可以在不使用倍频器的情况下，测量达6GHz装置的传输和反射特性。

为了在非同轴系统中进行方便而精确的测量，特提供了TRL*/LRM*1校准。

利用内置适配器移去校准技术，还能实现对非插入式器件的高精度测量。

高稳定度的频率基准(选件1D5)提高了对高Q器件，如表面声波(SAW)器件、晶体谐振器或介质谐振滤波器的频率测量精度。

LC875G24A中文资料

LC875G32A LC875G24A LC875G16A LC875G08AOverviewThe SANYO LC875G32A/24A/16A/08A are 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 100ns, integrates on a single chip a number of hardware features such as 32K/24K/16K/8K-byte ROM, 1024-byte RAM, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block transmission/receptioncapabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), a 12-bit/8-bit 12-channel AD converter, two 12-bit PWM channels, a system clock frequency divider, and a 22-source 10-vector interrupt feature.FeaturesROM• 32768 × 8-bits (LC875G32A) • 24576 × 8-bits (LC875G24A) • 16384 × 8-bits (LC875G16A) • 8192 × 8-bits (LC875G08A)RAM• 1024 × 9-bits (LC875G32A/24A/16A/08A)Minimum Bus Cycle • 100ns (10MHz)Note : The bus cycle time here refers to the ROM read speed.Minimum Instruction Cycle Time • 300ns (10MHz)CMOS ICROM 32K/24K/16K/8K byte, RAM 1024 byte on-chip8-bit 1-chip MicrocontrollerPorts• Normal withstand voltage I/O portsPorts whose I/O direction can be designated in 1-bit units 30 (P1n,P2n,P30 to P36,P70 to P73,PWM0,PWM1,XT2) Ports whose I/O direction can be designated in 4-bit units 8 (P0n)• Normal withstand voltage input port 1 (XT1)• Dedicated oscillator ports 2 (CF1, CF2)• Reset pins 1 (RES)• Power pins 6 (V SS1 to 3, V DD1 to 3)Timers• Timer 0 : 16-bit timer/counter with a capture register.Mode 0 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2-channelsMode 1 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register)Mode 2 : 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)Mode 3 : 16-bit counter (with a 16-bit capture register)• Timer 1 : 16-bit timer/counter that supports PWM/toggle outputsMode 0 : 8-bit timer with an 8-bit prescaler (with toggle outputs) + with an 8-bit prescaler 8-bit timer/counter (with toggle outputs)Mode 1 : 8-bit PWM with an 8-bit prescaler × 2-channelsMode 2 : 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)(toggle outputs also possible from the lower-order 8-bits)Mode 3 : 16-bit timer with an 8-bit prescaler (with toggle outputs)(the lower-order 8-bits can be used as PWM.)• Timer 4 : 8-bit timer with a 6-bit prescaler• Timer 5 : 8-bit timer with a 6-bit prescaler• Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs)• Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs)• Base timer1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaleroutput.2) Interrupts programmable in 5 different time-schemesHigh-speed Clock Counter1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).2) Can generate output real time.SIO• SIO 0 : 8-bit synchronous serial interface1) LSB first/MSB first mode selectable2) Built-in 8-bit baudrate generator (maximum transfer clock cycle4/3 tCYC)3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units, suspension and resumptionof data transmission possible in 1 byte units)• SIO 1 : 8-bit asynchronous/synchronous serial interfaceMode 0 : Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)Mode 1 : Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)Mode 2 : Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)Mode 3 : Bus mode 2 (start detect, 8 data bits, stop detect)UART• Full duplex• 7/8/9 bit data bits selectable• 1stop bit (2-bit in continuous data transmission)• Built-in baudrate generatorAD Converter : 12-bits/8-bits×12-channels• 12-bits/8-bits AD converter selectable• Automatic reference voltage generation controllablePWM : Multifrequency 12-bit PWM×2-channelsRemote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)• Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)Watchdog Timer• External RC watchdog timer• Interrupt and reset signals selectableInterrupts• 22 sources, 10 vector addresses1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests ofthe level equal to or lower than the current interrupt are not accepted.2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest leveltakes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence.SourceNo. VectorAddress Level Interrupt1 00003H X or L INT02 0000BH X or L INT13 00013H H or L INT2/T0L/INT44 0001BH H or L INT3/INT5/base timer5 00023H H or L T0H6 0002BH H or L T1L/T1H7 00033H H or L SIO0/UART1 receive8 0003BH H or L SIO1/UART1 transmit9 00043H H or L ADC/T6/T710 0004BH H or L Port 0/T4/T5/PWM0, PWM1• Priority Level : X > H > L• Of interrupts of the same level, the one with the smallest vector address takes precedence.Subroutine Stack Levels : 512 levels (the stack is allocated in RAM.)High-speed Multiplication/Division Instructions• 16-bits×8-bits (5 tCYC execution time)• 24-bits×16-bits (12 tCYC execution time)• 16-bits÷8-bits (8 tCYC execution time)• 24-bits÷16-bits (12 tCYC execution time)Oscillation Circuits• RC oscillation circuit (internal) : For system clock• CF oscillation circuit : For system clock, with internal Rf• Crystal oscillation circuit : For low-speed system clock, with internal Rf• Frequency variable RC oscillation circuit (internal) : For system clockSystem Clock Divider Function• Can run on low current.• The minimum instruction cycle selectable from 300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, and 76.8µs (at a main clock rate of 10MHz).Standby Function• HALT mode : Halts instruction execution while allowing the peripheral circuits to continue operation.1) Oscillation is not halted automatically.2) Canceled by a system reset or occurrence of an interrupt.• HOLD mode : Suspends instruction execution and the operation of the peripheral circuits.1) The CF, RC, and crystal oscillators automatically stop operation.2) There are three ways of resetting the HOLD mode.(1) Setting the reset pin to the lower level.(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level.(3) Having an interrupt source established at port 0.• X'tal HOLD mode : Suspends instruction execution and the operation of the peripheral circuits except the base timer.1) The CF and RC oscillators automatically stop operation.2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.3) There are four ways of resetting the X'tal HOLD mode.(1) Setting the reset pin to the low level.(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level.(3) Having an interrupt source established at port.(4) Having an interrupt source established in the base timer circuit.Package Form• SQFP48 : Lead-free type• QIP48E : Lead-free typeDevelopment Tools• Evaluation chip : LC87EV690• Emulator : EVA62S+ECB876600D+SUB875G00+POD48QFPICE-B877300+SUB875G00+POD48QFP• Onchip debugger : TCB87 TypeA+LC87F5G32ATypeB+LC87F5G32ATCB87Flash ROM Version• LC87F5G32APackage DimensionsPackage Dimensionsunit : mm unit : mmPin AssignmentSANYO: SQFP48 "Lead-free Type" SANYO: QIP48E "Lead-free Type"Top viewP 73/I N T 3/T 0I N R E S X T 1/A N 10X T 2/A N 11V S S 1C F 1C F 2V D D 1P 10/S O 0P 11/S I 0/S B 0P 12/S C K 0P 13/S O 1P 27/I N T 5/T 1I N P 26/I N T 5/T 1I N P 25/I N T 5/T 1I N P 24/I N T 5/T 1I N P 23/I N T 4/T 1I N P 22/I N T 4/T 1I N P 21/U R X /I N T 4/T 1I N P 20/U T X /I N T 4/T 1I N P 07/T 7O /A N 7 P 06/T 6O /A N 6 P 05/C K O /A N 5 P 04/A N 41 2 3 4 5 6 7 8 9 10 11 12363534333231302928272625P36P35V DD 3V SS 3P34P33P32P31P30P70/INT0/T0LCP/AN8P71/INT1/T0HCP/AN9P72/INT2/T0IN242322212019181716151413P03/AN3 P02/AN2 P01/AN1 P00/AN0 V SS 2 V DD 2 PWM0 PWM1P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB137 38 39 40 41 42 43 44 45 46 47 48LC875G32A/LC875G24A/ LC875G16A/ LC875G08ASQFP/QIP NAME1 P73/INT3/T0IN 25 P04/AN4P05/CKO/AN52 RES 26P06/T6O/AN63 XT1/AN10 274 XT2/AN11 28P07/T7O/AN7P20/UTX/INT4/T1IN1 29P21/URX/INT4/T1IN6 CF1 30P22/INT4/T1IN7 CF2 31P23/INT4/T1IN1 32P24/INT5/T1IN9 P10/SO0 3310 P11/SI0/SB0 34 P25/INT5/T1IN11 P12/SCK0 35 P26/INT5/T1INP27/INT5/T1IN12 P13/SO1 3613 P14/SI1/SB1 37 P3614 P15/SCK1 38 P3515 P16/T1PWML 39 V DD316 P17/T1PWMH/BUZ 40 V SS317 PWM1 41 P3418 PWM0 42 P33P322 432 44P3121 P00/AN0 45 P30P70/INT0/T0LCP/AN822 P01/AN1 4623 P02/AN2 47P71/INT1/T0HCP/AN924 P03/AN3 48 P72/INT2/T0INSystem Block DiagramPin DescriptionPin Name I/O DescriptionOptionV SS 1 V SS 2 V SS 3 -- Power supply pinNoV DD 1 V DD 2 V DD 3 -+ Power supply pinNoPort 0 P00 to P07I/O• 8-bit I/O port• I/O specifiable in 4-bit units• Pull-up resistors can be turned on and off in 4-bit units • HOLD reset input • Port 0 interrupt input • Shared pinsP05 : System clock output P06 : Timer 6 toggle output P07 : Timer 7 toggle outputAD converter input port : AN0 (P00) to AN7 (P07)YesPort 1 P10 to P17I/O• 8-bit I/O port• I/O specifiable in 1-bit units• Pull-up resistors can be turned on and off in 1-bit units • Pin functionsP10 : SIO0 data output P11 : SIO0 data input/bus I/O P12 : SIO0 clock I/O P13 : SIO1 data output P14 : SIO1 data input/bus I/O P15 : SIO1 clock I/O P16 : Timer 1PWML outputP17 : Timer 1PWMH output/beeper outputYes Port 2 • 8-bit I/O port• I/O specifiable in 1-bit units• Pull-up resistors can be turned on and off in 1-bit units • Pin functions P20 : UART transmit P21 : UART receiveP20 to P23 : INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/timer 0H capture inputP24 to P27 : INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/timer 0H capture inputInterrupt acknowledge type Rising FallingRising &Falling H level L levelINT4 INT5 enable enableenable enableenable enabledisable disabledisable disableP20 to P27I/OYes Continued on next page.Port Output TypesThe table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode.Port Name Option Selected inUnits ofOption Type Output Type Pull-up Resistor1 CMOS Programmable (Note 1)P00 to P07 1-bit2 Nch-opendrain No1 CMOS Programmable P10 to P17 1-bit2 Nch-opendrain Programmable1 CMOS Programmable P20 to P27 1-bit2 Nch-opendrain Programmable1 CMOSProgrammableP30 to P36 1-bit2 Nch-opendrain ProgrammableP70 -NoNch-opendrain Programmable P71 to P73 - No CMOS ProgrammablePWM0, PWM1 - No CMOSNoXT1 - No Output for 32.768kHz crystal oscillator(Input only)NoXT2 - No Input for 32.768kHz crystal oscillator(Nch-open drain when in general-purposeoutput mode)NoNote 1 : Programmable pull-up resistor of Port 0 is specified in nibble units (P00 to P03, P04 to P07).Note : To reduce V DD signal noise and to increase the duration of the backup battery supply, V SS1, V SS2, and V SS3 should connect to each other and they should also be grounded.Example 1 : During backup in hold mode, port output ‘H’ level is supplied from the back-up capacitor.Example 2 : During backup in hold mode, output is not held high and its value in unsettled.LSIAbsolute Maximum Ratings at Ta = 25°C, V SS 1 = V SS 2 = V SS 3 = 0VSpecificationParameter Symbol Pin/Remarks ConditionsV DD [V] min typ max unitMaximum supply voltage V DD maxV DD 1, V DD 2,V DD 3 V DD 1=V DD 2=V DD 3-0.3 +6.5Input voltage VI XT1, CF1 -0.3 V DD +0.3Input/output voltageVIO Ports 0, 1, 2, Port 3, 7, PWM0, PWM1, XT2-0.3 V DD +0.3VIOPH(1) Ports 0, 1, 2, 3CMOS output select Per 1 applicable pin-10 IOPH(2) PWM0, PWM1 CMOS output select Per 1 applicable pin -20 Peak output currentIOPH(3)Ports P71 to P73 Per 1 applicable pin -5 IOMH(1) Ports 0, 1, 2, 3CMOS output select Per 1 applicable pin -7.5 IOMH(2) PWM0, PWM1 CMOS output select Per 1 applicable pin -15 Mean output current (Note 1-1)IOMH(3)Ports P71 to P73 Per 1 applicable pin -3 ΣIOAH(1) Ports P71 to P73 Total of all applicable pins -10 ΣIOAH(2)Port 0 Total of all applicable pins -25 ΣIOAH(3) Port 1,PWM0, PWM1Total of all applicable pins-25 ΣIOAH(4) Ports 0, 1 PWM0, PWM1 Total of all applicable pins-45 ΣIOAH(5) Ports 2, P35, P36 Total of all applicable pins -25 ΣIOAH(6) Ports P30 to P34 Total of all applicable pins -25 H i g h l e v e l o u t p u t c u r r e n tTotal output currentΣIOAH(7)Ports 2, 3 Total of all applicable pins -45IOPL(1)Ports P02 to P07 Ports 1, 2, 3 PWM0, PWM1 Per 1 applicable pin20IOPL(2) Ports P00, P01 Per 1 applicable pin 30Peak output currentIOPL(3)Port 7, XT2 Per 1 applicable pin 10IOML(1) Ports P02 to P07 Ports 1, 2, 3 PWM0, PWM1 Per 1 applicable pin15IOML(2) Ports P00, P01 Per 1 applicable pin 20Mean output current (Note 1-1)IOML(3)Port 7, XT2 Per 1 applicable pin 7.5ΣIOAL(1) Port 7, XT2 Total of all applicable pins 15ΣIOAL(2) Port 0 Total of all applicable pins 45ΣIOAL(3)Port 1, PWM0, PWM1 Total of all applicable pins45ΣIOAL(4) Ports 0, 1 PWM0, PWM1 Total of all applicable pins80ΣIOAL(5) Ports 2, P35, P36 Total of all applicable pins 45ΣIOAL(6)Ports P30 to P34Total of all applicable pins45L o w l e v e l o u t p u t c u r r e n tTotal output currentΣIOAL(7)Ports 2, 3 Total of all applicable pins60mASQFP48 190Power dissipationPd maxQIP48ETa= -30 to +70°C390mWOperating ambient temperature Topr-30 +70Storage ambient temperatureTstg-55 +125°CNote 1-1 : The mean output current is a mean value measured over 100ms.a division ratio of 1/2.Note 2-2 : See Tables 1 and 2 for the oscillation constants.Serial Input/Output Characteristics at Ta = -30°C to +70°C, V SS 1 = V SS 2 = V SS 3 = 0V1. SIO0 Serial I/O Characteristics (Note 4-1-1)Specification Parameter Symbol Pin/Remarks ConditionsV DD [V] min typ max unitFrequency tSCK(1) 2 Low level pulse width tSCKL(1)1 tSCKH(1) See Fig. 6.1I n p u t c l o c kHigh level pulse widthtSCKHA(1)SCK0(P12) • Continuous datatransmission/reception mode • See Fig. 6. • (Note 4-1-2)2.5 to 5.54Frequency tSCK(2) 4/3 tCYCLow level pulse width tSCKL(2)1/2tSCKH(2)• CMOS output selected • See Fig. 6.1/2tSCKS e r i a l c l o c kO u t p u t c l o c kHigh level pulse widthtSCKHA(2)SCK0(P12) • Continuous datatransmission/reception mode • CMOS output selected • See Fig. 6.2.5 to 5.5tSCKH(2) +2tCYCtSCKH(2)+(10/3)tCYCtCYCData setup timetsDI(1)2.5 to 5.50.03S e r i a l i n p u tData hold time thDI(1) SB0(P11), SI0(P11)• Must be specified with respect to rising edge of SIOCLK. • See Fig. 6.2.5 to 5.50.03tdD0(1)• Continuous datatransmission/reception mode • (Note 4-1-3)2.5 to 5.5(1/3)tCYC+0.05I n p u t c l o c ktdD0(2)• Synchronous 8-bit mode • (Note 4-1-3) 2.5 to 5.51tCYC +0.05S e r i a l o u t p u t O u t p u t c l o c kOutput delay timetdD0(3)SO0(P10), SB0(P11)(Note 4-1-3)2.5 to 5.5(1/3)tCYC+0.05µsNote 4-1-1: These specifications are theoretical values. Add margin depending on its use.Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA.Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6.2. SIO1 Serial I/O Characteristics (Note 4-2-1)Specification Parameter Symbol Pin/Remarks ConditionsV DD [V] min typ max unitFrequency tSCK(3) 2 Low level pulse width tSCKL(3)1I n p u t c l o c kHigh level pulse width tSCKH(3) SCK1(P15) See Fig. 6.2.5 to 5.51 Frequency tSCK(4) 2tCYCLow level pulse width tSCKL(4)1/2S e r i a l c l o c kO u t p u t c l o c kHigh level pulse width tSCKH(4) SCK1(P15) • CMOS output selected • See Fig. 6.2.5 to 5.51/2tSCKData setup timetsDI(2)2.5 to 5.50.03S e r i a l i n p u tData hold timethDI(2) SB1(P14), SI1(P14)• Must be specified with respect to rising edge of SIOCLK. • See Fig. 6.2.5 to 5.50.03S e r i a l o u t p u tOutput delay time tdD0(4)SO1(P13), SB1(P14)• Must be specified with respect to falling edge of SIOCLK.• Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig. 6.2.5 to 5.5(1/3)tCYC+0.05µsNote 4-2-1: These specifications are theoretical values. Add margin depending on its use.AD Converter Characteristics at V SS1 = V SS2 = V SS3 = 0V<12-bits AD Converter Mode / Ta= -10°C to +50°C>Specification Parameter Symbol Pin/Remarks ConditionsV DD[V] min typ max unit Resolution N 4.75 to 5.2512 bitAbsolute accuracy ET (Note 6-1) 4.75 to 5.25T.B.D LSB Conversion time TCAD See conversion time calculationformulas.(Note 6-2)4.75 to5.2538.5 90µsAnalog input voltage range VAIN4.75 to5.25V SS V DD V IAINH VAIN=V DD 4.75 to 5.251Analog port inputcurrent IAINL AN0(P00) toAN7(P07)AN8(P70)AN9(P71)AN10(XT1)AN11(XT2)VAIN=V SS 4.75 to 5.25-1µA<8-bits AD Converter Mode / Ta= -30°C to +70°C>Specification Parameter Symbol Pin/Remarks ConditionsV DD[V] min typ max unit Resolution N 3.0 to 5.5 8 bitAbsolute accuracy ET (Note 6-1) 3.0 to 5.5 ±1.5LSB4.5 to5.5 22.5 90Conversion time TCAD See conversion time calculationformulas. (Note 6-2) 3.0 to 5.5 45 90µsAnalog input voltage range VAIN3.0 to 5.5 V SS V DD V IAINH VAIN V DD 3.0 to 5.5 1Analog port inputcurrent IAINL AN0(P00) toAN7(P07)AN8(P70)AN9(P71)AN10(XT1)AN11(XT2)VAIN=V SS 3.0 to 5.5 -1µAConversion time calculation formulas :12-bits AD Converter Mode : TCAD (Conversion time) = ((52/(division ratio))+2) × (1/3) × tCYC8-bits AD Converter Mode : TCAD (Conversion time) = ((32/(division ratio))+2) × (1/3) × tCYCNote 6-1 : The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel.Note 6-2 : The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding tothe analog input value.The conversion time is 2 times the normal-time conversion time when :• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bitconversion mode.Consumption Current Characteristics at Ta = -30°C to +70°C, V SS 1 = V SS 2 = V SS 3 = 0VSpecificationParameter Symbol Pin/Remarks ConditionsV DD [V] min typ max unitIDDOP(1) • FmCF =10MHzceramic oscillation mode• FmX’tal=32.768kHz crystal oscillation mode• System clock set to 10MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio4.5 to5.5712.5IDDOP(2)• CF1=20MHz external clock • FmX’tal=32.768kHz crystal oscillation mode• System clock set to CF1 side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio4.5 to5.5815IDDOP(3)4.5 to5.53.7 6.8IDDOP(4)• FmCF=5MHzceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode• System clock set to 5MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio2.5 to 4.51.9 5.2IDDOP(5)4.5 to5.50.6 1.9IDDOP(6)• FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode• System clock set to internal RCoscillation• Frequency variable RC oscillation stopped • 1/2 frequency division ratio2.5 to 4.50.3 1.4IDDOP(7)4.5 to5.5 1.3 4.2IDDOP(8)• FmCF=0Hz (oscillation stopped)• FmX’tal=32.768kHz crystaloscillation mode• Internal RC oscillation stopped• System clock set to 1MHz with frequency variable RC oscillation• 1/2 frequency division ratio2.5 to 4.50.7 3.2mAIDDOP(9)4.5 to5.52685Normal mode consumption current (Note 7-1)IDDOP(10)V DD 1 =V DD 2 =V DD 3• FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode• System clock set to 32.768kHz side• Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio2.5 to 4.51165µANote 7-1 : The consumption current value includes none of the currents that flow into the output Tr and internal pull-upresistors.Continued on next page.Continued from preceding page.Specification Parameter SymbolPin/Remarks ConditionsV DD [V] min typ max unitIDDHALT(1)• HALT mode • FmCF=10MHzceramic oscillation mode• FmX’tal=32.768kHz crystal oscillation mode • System clock set to 10MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio4.5 to5.52.4 4.9IDDHALT(2)• HALT mode• CF1=20MHz external clock• FmX’tal=32.768kHz crystal oscillation mode • System clock set to CF1 side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio4.5 to5.53.4 7.7IDDHALT(3)4.5 to5.51.5 3.1IDDHALT(4)• HALT mode • FmCF=5MHzceramic oscillation mode• FmX’tal=32.768kHz crystal oscillation mode• System clock set to 5MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio2.5 to 4.50.7 2.2IDDHALT(5)4.5 to5.50.3 1.1IDDHALT(6)• HALT mode• FmCF=0Hz (oscillation stopped)• FmX’tal=32.768kHz crystal oscillation mode• System clock set to internal RC oscillation • Frequency variable RC oscillation stopped • 1/2 frequency division ratio2.5 to 4.50.150.8IDDHALT(7)4.5 to5.51.1 3.6IDDHALT(8)• HALT mode• FmCF=0Hz (oscillation stopped)• FmX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped• System clock set to 1MHz with frequency variable RC oscillation• 1/2 frequency division ratio2.5 to 4.50.6 2.7mAIDDHALT(9)4.5 to5.518 60HALT mode consumption current (Note 7-1)IDDHALT(10)V DD 1 =V DD 2 =V DD 3• HALT mode• FmCF=0Hz (oscillation stopped)• FmX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side• Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio2.5 to 4.5740IDDHOLD(1) 4.5 to 5.5 0.015 17HOLD mode consumption current IDDHOLD(2) V DD 1 HOLD mode• CF1=V DD or open(External clock mode)2.5 to 4.50.0112IDDHOLD(3)4.5 to5.5 16 55Timer HOLD mode consumption currentIDDHOLD(4) V DD 1Timer HOLD mode • CF1=V DD or open (External clock mode)• FmX’tal=32.768kHz crystal oscillation mode2.5 to 4.510 36µANote 7-1 : The consumption current value includes none of the currents that flow into the output Tr and internal pull-upresistors.UART (Full duplex) Operating Conditions at Ta = -30°C to +70°C, V SS 1 = V SS 2 = V SS 3 = 0VSpecification Parameter Symbol Pin/Remarks ConditionsV DD [V] min typ max unit Transfer rateUBRP20, P212.5 to 5.516/38192/3tCYCData length : 7, 8, and 9 bits (LSB first)Stop bits : 1-bit (2-bit in continuous data transmission)Parity bits : NoneExample of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H)Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H)Start bitStop bitStop bitStart bitCharacteristics of a Sample Main System Clock Oscillation CircuitGiven below are the characteristics of a sample main system clock oscillation circuit that are measured using aSANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation.Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic OscillatorCircuit ConstantOscillation StabilizationTimeNominal FrequencyVendor NameOscillator NameC1 [pF]C2 [pF] Rf [Ω] Rd1[Ω] Operating Voltage Range [V] typ [ms] max [ms] RemarksCSTCE10M0G52-R0 (10)(10)Open6804.5 to5.5V0.1 0.5 10MHz MURATACSTCE10M0G52-B0 (10)(10) Open 680 4.5 to 5.5V 0.1 0.5 Internal C1, C2(SMD type) CSTCR5M00G53-R0 (15)(15) Open 2.2k 2.5 to 5.5V 0.2 0.6 5MHz MURATACSTCR5M00G53-B0 (15)(15) Open2.2k2.5 to 5.5V0.20.6Internal C1, C2(SMD type) The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after V DDgoes above the operating voltage lower limit (see Figure 4).It is recommended to insert feedback resister (Rf:1M Ω) when power supply voltage is used around 2.5V.Characteristics of a Sample Subsystem Clock Oscillator CircuitGiven below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation.Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal OscillatorCircuit ConstantOscillation StabilizationTimeNominal FrequencyVendor NameOscillator NameC3 [pF]C4 [pF]Rf [Ω]Rd2 [Ω]Operating Voltage Range [V]typ [s] max [s] Remarks32.768kHz SEIKO EPSONMC-3061818 Open 510k 2.5 to 5.51.13.0Applicable CL value=12.5pF The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 4).Note : The components that are involved in oscillation should be placed as close to the IC and to one another as possiblebecause they are vulnerable to the influences of the circuit pattern.Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit Figure 3 AC Timing Measurement Point0.5V DD。

Si875x数据手册说明书

Si8751/52 Data SheetIsolated FET Driver with Pin Control or Diode Emulator InputsThe Si875x enables new pathways to the creation of custom Solid State Relay (SSR) configurations. The Si875x integrates robust isolation technology with an SSR FET driver. A floating secondary side dc power supply is unnecessary as the product generates its own self-contained gate drive output voltage. When combined with a customer-selected external FET, a complete Solid State Relay is formed, allowing customers to optimize their system for cost, PCB area, power, On-Resistance, and thermal performance.Customers have a choice of digital input control (Si8751) or diode emulation control(Si8752) to best suit their application. The Si875x integrates versatile outputs that support driving AC or DC load configurations.The Si875x eliminates the need for bulky mechanical relays which can be difficult to assem-ble onto PCBs and add switching noise to the system.Traditional SSRs integrate optocoupler-style LED inputs, which limit the operating tempera-ture range of the solution. The Si875x experiences no such limitation and can support full industrial and automotive temperature ranges with increased stability and longer life.The Si875x drives FET gates with a nominal 10 V using as little as 1 mA input current. Increasing the input current to 10 mA enables turn-on times as fast as 94 μs. Input side voltages on the Si8751 are flexible from 2.25 V to 5.5 V supporting seamless connectionto low-power controllers. The Si875x devices provide an Active Miller Clamp to prevent the unintended turn-on of the external FET when a high dV/dt is present on the FET’s drain.The Si875x is qualified to the AEC-Q100 standard, making it suitable for automotive applica-tions. Further, its 2.5 KVrms isolation rating forms the basis for full certification to UL, CSA, VDE, and CQC.Applications include mechanical relay, photo switch, or SSR replacement in motor control, valve control, HVAC relay, automotive, charging, battery monitoring, ac mains line switching, and more.The Si8751 and Si8752 come in ROHS-compliant SOIC-8 packaging, providing a compact, industry-standard footprint and generous margin to creepage and clearance requirements.KEY FEATURES•Drives user-selected external FETs •Choice of digital input control (Si8751) or diode emulation control (Si8752)•Internally generated secondary side power supply•10 V output with 1 mA input current •As fast as 82 μs turn-on time and 46 us turn-off time•Active Miller Clamp to prevent unintended turn-on and reduce inductive chatter•Supports AC or DC load switching •2.5 KVrms isolation rating•UL, CSA, VDE, and CQC certifications •AEC-Q100 qualified•Industrial –40 to 105 °C or Automotive –40 to 125 °C temperature ranges •ROHS-compliant SOIC-8 PackageAPPLICATIONS•Motor Controls•Valve Controls•HVAC Relays•HEV/EV Automotive Charging •Battery Monitoring•AC Mains Line Switching1. Ordering GuideTable 1.1. Si8751/2 Ordering Guide2. System OverviewFigure 2.1. Si8751 Block DiagramFigure 2.2. Si8752 Block DiagramThe operation of an Si875x channel is analogous to that of an optocoupler and gate driver, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si875x channel is shown in the figure below.A BFigure 2.3. Simplified Channel DiagramA channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to outputB via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See figure below for more details.Input SignalModulation SignalOutput SignalFigure 2.4. Modulation Scheme2.1 Device BehaviorThe following are truth tables for the Si875x family.Table 2.1. Si8751 Truth TableTable 2.2. Si8752 Truth Table2.2 Power Supply Connections (Si8751 Only)The Si8751 requires a 0.1 µF bypass capacitor between VDD and GND. The capacitor should be placed as close as possible to the package. To enhance the robustness of a design, the user may also include a 1 µf capacitor for bulk decoupling as well as a resistor (50–300 Ω) in series with the input if the system is excessively noisy.2.3 TT Pin Description (Si8751 Only)The Si8751 provides a pin to control how much current is consumed by the supply when the input pin is logic high. The more current consumed by the input supply, the faster the output can turn on the external FET. This allows the application designer to optimize the tradeoff between power consumption and switching time.Typically, this pin is connected to the supply ground through a resistor. The greater the value of the resistor, the less current is consumed by the input supply. Values can range from 0 Ω (shorted to ground) to open (TT not connected).In addition to a resistor, a capacitor, typically 0.1 µf, can be placed in parallel to the resistor. This allows the device to draw more current to switch the external FET on quickly yet draw less supply current in the steady state. Total power over time is reduced while maintaining fast switching of the FET.MCAP1GATESOURCEMCAP2Figure 2.5. Si8751 TT Example Figure 2.6. Drive Current vs. Time Using TT with Capacitor2.4 LED Emulator Input (Si8752 Only)Figure 2.8. Diode Emulator Model and I-V CurveThe Si8752 uses input current to achieve the development of power across the isolation barrier. Therefore, the more current provided to the input, the more power is developed on the isolated side of the device. This translates into a faster turn on time of the external FET.This benefit is limited to an input current of about 15 mA. Beyond that, increasing the input current has little effect on the switching time of the external FET.2.5 Output DescriptionThe output of the Si875x device develops a positive voltage on the GATE pin with respect to the SOURCE pin. This voltage is used to turn on a typical field effect transistor (FET). Because power is transmitted across the isolation barrier, no isolated supply is required. This can be used to drive a FET configured as a switch for a dc load. It can also be used to drive a pair of FETs configured as a switch for an ac load. See 3. Applications.2.6 Miller Clamp2.6.1 Miller Clamp DescriptionThe Si875x devices provide a clamping device to prevent unintended turn on of the external FET when a high dV/dt is present on the FET’s drain. To use this feature, a capacitor is connected between the drain(s) of the FET(s) and one of the MCAPx inputs. A sudden, positive slope on this pin will cause the clamp device within the Si875x to activate and provide a low impedance path between the gate and source pins. This will prevent the FET from being unintentionally turned on.The Si875x device provides two miller clamp input pins. This allows for both FET’s to be protected from unintended turn on when the device is used in an AC switch configuration. In this case each drain is connected to an MCAPx input through a capacitor.Connection to a MCAPx pin, and use of the Miller Clamp feature, is optional. The device will function as expected if these pins are left unconnected.2.6.2 Sizing Miller Clamp CapacitorsThe recommended value of the capacitor used to connect the drain of the external FET to the Si875x device is typically 10 pf. If the application has a very large dV/dt and the clamp is not adequately keeping the external FET off, then this capacitor value can be increased up to 100 pf. The voltage rating of the capacitor should be greater than or equal to the peak voltage expected at the drain of the FET. The relationship of the capacitor and the dV/dt is governed by the equation: C = I MC/(dV/dt); where: I MC is the Miller Clamp input current (6mA max, as specified in Electrical Tables), and dV/dt is the expected slew rate.3. ApplicationsThe following examples illustrate typical circuit configurations using the Si8751/52.3.1 DC SSR ExampleThe Si875x device can be used to control a dc load as shown in the following figure:INVDDTTGNDFigure 3.1. Driving an FET for DC Load Including Miller Clamp CapacitorIn this configuration, the Si8751 charges the gate of the external FET; turning it on. This switches on power, supplied by VDC, to the load. The output side circuitry is identical if using the Si8752.3.2 AC SSR ExampleThe Si875x can be used to control power to an ac load using the following circuit:INTTGNDFigure 3.2. Driving FETs for AC Load SwitchingIn this configuration, both FET’s are turned on by the charge delivered by the Si8751. This allows ac current to flow to the load. When the Si875x is turned off, charge is drained form the gates of both FET’s and the ac current is turned off. The output side circuitry is identical if using the Si8752.Si8751/52 Data Sheet • Applications4. Electrical SpecificationsTable 4.1. Electrical Specifications•Automotive: VDD=2.25 to 5.5V; GND=0V; T A=-40 to +125ºC; typical specs at 25ºC; T J=-40 to +150ºC •Industrial: VDD=2.25 to 5.5V; GND=0V; T A=-40 to +105ºC; typical specs at 25ºC; T J=-40 to +150ºC4.1 Test CircuitsThe following figure depicts a common-mode transient immunity test circuit:IsolatedSupplyFigure 4.1. Common-Mode Transient Immunity Test Circuit4.2 Regulatory InformationTable 4.2. Regulatory Information1,2CSAThe Si875x is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract Number 232873. 60950-1: Up to 125 V RMS reinforced insulation working voltage; up to 600 V RMS basic insulation working voltage.VDEThe Si875x is certified according to VDE 0884-10. For more details, see Certificate 40018443.VDE 0884-10: Up to 630 V peak for basic insulation working voltage.ULThe Si875x is certified under UL1577 component recognition program. For more details, see File E257455.Rated up to 2500 V RMS isolation voltage for basic protection.CQCThe Si875x is certified under GB4943.1-2011. For more details, see Certificate CQC17001177960.Rated up to 125 V RMS reinforced insulation working voltage; up to 600 V RMS basic insulation working voltage.1.Regulatory Certifications apply to2.5 kV RMS rated devices which are production tested to3.0 kV RMS for 1 sec.2.For more information, see 1. Ordering Guide.Table 4.3. Insulation and Safety-Related SpecificationsTable 4.4. IEC 60664-1 RatingsTable 4.5. VDE 0884 Insulation Characteristics1Table 4.6. IEC Safety Limiting Values1Table 4.7. Thermal CharacteristicsFigure 4.2. Thermal Derating Curve for Safety Limiting Current (Si8751)Figure 4.3. Thermal Derating Curve for Safety Limiting Current (Si8752)Table 4.8. Absolute Maximum Ratings14.3 Typical Operating CharacteristicsFigure 4.4. Si8751 Typical Gate Voltage vs. Temperatureand TT Figure 4.5. Si8752 Typical Gate Voltage vs. Temperatureand Anode CurrentFigure 4.6. Si8751 Typical Turn-On Time vs. Temperature and TT with 100 pF Load (50% of Output)Figure 4.7. Si8752 Typical Turn-On Time vs. Temperature and Anode Current with 100 pF Load (50% of Output)Figure 4.8. Si8751 Typical Turn-On Time vs. Temperature and TT with 100 pF Load (90% of Output)Figure 4.9. Si8752 Typical Turn-On Time vs. Temperature and Anode Current with 100 pF Load (90% of Output)Figure 4.10. Si8751 Typical Turn-On Time vs. Capacitanceand TT (50% of Output)Figure 4.11. Si8752 Typical Turn-On Time vs. Capacitance and Anode Current (50% of Output)Figure 4.12. Si8751 Typical Turn-On Time vs. Capacitanceand TT (90% of Output)Figure 4.13. Si8752 Typical Turn-On Time vs. Capacitance and Anode Current (90% of Output)5. Pin Descriptions5.1 Si8751 Pin Descriptions12345678SOURCEMCAP2MCAP1GATEGND TT VDD Si8751IN Figure 5.1. Pin Assignments Si8751Table 5.1. Si8751 Pin Descriptions5.2 Si8752 Pin Descriptions12345678GATEMCAP2MCAP1SOURCECATHODE ANODE NC Si8752NC Figure 5.2. Pin Assignments Si8752Table 5.2. Si8752 Pin Descriptions6. Package Outlines6.1 Package Outline: 8-Pin Narrow Body SOICThe figure below illustrates the package details for the Si875x in an 8-pin narrow-body SOIC package. The table below lists the values for the dimensions shown in the illustration.Figure 6.1. 8-Pin Narrow Body SOIC PackageTable 6.1. 8-Pin Narrow Body SOIC Package Diagram Dimensions7. Land Patterns7.1 Land Pattern: 8-Pin Narrow Body SOICThe figure below illustrates the recommended land pattern details for the Si875x in an 8-pin narrow-body SOIC. The table below lists the values for the dimensions shown in the illustration.Figure 7.1. 8-Pin Narrow Body SOIC Land PatternTable 7.1. 8-Pin Narrow Body SOIC Land Pattern Dimensions8. Top Markings8.1 8-Pin Narrow Body SOICTable 8.1. Top Marking ExplanationLine 1 Marking:Customer Part Number Si875 = ISOdriver product seriesX: 1 = Digital input, 2 = LED emulator inputA: ReservedV: B = 2.5 kV isolation ratingLine 2 Marking:TTTTTT = Mfg code Manufacturing Code from Assembly Purchase Order form.Line 3 Marking:YY = YearWW = Work week Assigned by the Assembly House. Corresponds to the year and workweek of the mold date.9. Revision HistoryRevision A, July 2022•Added Agile data sheet revision in footerRevision 1.0, December 2017•Significant edits with production electrical specifications and load switching diagram.Revision 0.5, September 2016•Significant edits with production electrical specifications.Revision 0.1, May 2016•Initial revision.Table of Contents1. Ordering Guide (2)2. System Overview (3)2.1 Device Behavior (4)2.2 Power Supply Connections (Si8751 Only) (5)2.3 TT Pin Description (Si8751 Only) (5)2.4 LED Emulator Input (Si8752 Only) (5)2.5 Output Description (6)2.6 Miller Clamp (6)2.6.1 Miller Clamp Description (6)2.6.2 Sizing Miller Clamp Capacitors (6)3. Applications (7)3.1 DC SSR Example (7)3.2 AC SSR Example (7)4. Electrical Specifications (8)4.1 Test Circuits (10)4.2 Regulatory Information (10)4.3 Typical Operating Characteristics (16)5. Pin Descriptions (19)5.1 Si8751 Pin Descriptions (19)5.2 Si8752 Pin Descriptions (20)6. Package Outlines (21)6.1 Package Outline: 8-Pin Narrow Body SOIC (21)7. Land Patterns (23)7.1 Land Pattern: 8-Pin Narrow Body SOIC (23)8. Top Markings (24)8.1 8-Pin Narrow Body SOIC (24)9. Revision History (25)Copyright © 2022 Skyworks Solutions, Inc. All Rights Reserved.Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by thecustomer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks’ Terms and Conditions of Sale.THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED,STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSL Y DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESUL T FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale.Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of design defects, errors, or operation of products outside of published parameters or design specifications. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any equipment resulting from the use of Skyworks products outside of Skyworks’ published specifications or parameters.Skyworks, the Skyworks symbol, Sky5®, SkyOne®, SkyBlue™, Skyworks Green™, ClockBuilder®, DSPLL®, ISOmodem®, ProSLIC®, and SiPHY® are trademarks or registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for identification purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at , are incorporated by reference.SkyworksSolutions,Inc.|Nasdaq:SWKS|*********************|Portfolio Quality/qualitySupport & Resources/support。

微电子VSC8584-10数据手册：四口10 100 1000BASE-T PHY 同步以太网PHY

VSC8584-10 Datasheet Quad-Port 10/100/1000BASE-T PHY with Synchronous Ethernet, VeriTime™, Intellisec™, and QSGMII/SGMIIMACMicrosemi HeadquartersOne Enterprise, Aliso Viejo,CA 92656 USAWithin the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996Email: *************************** ©2019 Microsemi, a wholly owned subsidiary of Microchip Technology Inc. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.About MicrosemiMicrosemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Learn more at .Contents1Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.1Revision 4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2Revision 4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3Revision 4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.5Revision2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.6Revision2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32.1Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1.1Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1.2Advanced Carrier Ethernet Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1.3Wide Range of Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1.4Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1.5IEEE1588v2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1.6MACsec Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.2Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73.1Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.1.1QSGMII/SGMII MAC-to-1000BASE-X Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.1.2QSGMII/SGMII MAC-to-100BASE-FX Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.1.3QSGMII/SGMII MAC-to-AMS and 1000BASE-X Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . 93.1.4QSGMII/SGMII MAC-to-AMS and 100BASE-FX Media SerDes . . . . . . . . . . . . . . . . . . . . . . . 103.1.5QSGMII/SGMII MAC-to-AMS and Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.1.6QSGMII/SGMII MAC-to-Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.1.7QSGMII/SGMII MAC-to-Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.1.81000BASE-X MAC-to-Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.2SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.2.11000BASE-X MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.2.2SGMII MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.2.3QSGMII MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.3SerDes Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.3.1QSGMII/SGMII to 1000BASE-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.3.2QSGMII/SGMII to 100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.3.3QSGMII to SGMII Protocol Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.3.4Unidirectional Transport for Fiber Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.4PHY Addressing and Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.4.1PHY Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.4.2SerDes Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.5Cat5 Twisted Pair Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.5.1Voltage Mode Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.5.2Cat5 Autonegotiation and Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.5.3Automatic Crossover and Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.5.4Manual MDI/MDIX Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.5.5Link Speed Downshift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.5.6Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.5.7Ring Resiliency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.6MACsec Block Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.6.1MACsec Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.6.2MACsec Target Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.6.3Formats, Transforms, and Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243.6.4MACsec Integration in PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.6.5MACsec Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.6.6Debug Fault Code in FCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463.6.7Capture FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.6.8Flow Control Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493.6.9Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.7Automatic Media Sense Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.8Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573.8.1Configuring the Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573.8.2Single-Ended REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573.8.3Differential REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.9IEEE1588 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.10Ethernet Inline Powered Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.11IEEE 802.3af PoE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.12ActiPHY Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603.12.1Low Power State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.12.2Link Partner Wake-Up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.12.3Normal Operating State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.13IEEE1588 Block Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.13.1IEEE1588 Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623.13.2IEEE1588 One-Step E2E TC in Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643.13.3IEEE1588 TC and BC in Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643.13.4Enhancing IEEE1588 Accuracy for CE Switches and MACs . . . . . . . . . . . . . . . . . . . . . . . . . 653.13.5MACsec Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653.13.6Supporting One-Step Boundary Clock/Ordinary Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653.13.7Supporting Two- Step Boundary/Ordinary Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673.13.8Supporting One-Step End-to-End Transparent Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693.13.9Supporting One-Step Peer-to-Peer Transparent Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723.13.10Supporting Two-Step Transparent Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763.13.11Calculating OAM Delay Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783.13.12Supporting Y.1731 One-Way Delay Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783.13.13Supporting Y.1731 Two-Way Delay Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803.13.14Device Synchronization for IEEE1588 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823.13.15Time Stamp Update Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833.13.16Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863.13.17Time Stamp Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073.13.18Time Stamp FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083.13.19Serial Time Stamp Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093.13.20Rewriter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103.13.21Local Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113.13.22Serial Time of Day . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133.13.23Programmable Offset for LTC Load Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153.13.24Adjustment of LTC counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153.13.25Pulse per Second Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163.13.26Accuracy and Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173.13.27Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173.13.28IEEE1588 Register Access using SMI (MDC/MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183.13.291588_DIFF_INPUT_CLK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 3.14Daisy-Chained SPI Time Stamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 3.15SPI I/O Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 3.16Media Recovered Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203.16.1Clock Selection Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203.16.2Clock Output Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 3.17Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213.17.1SMI Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213.17.2SMI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223.18LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223.18.1LED Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233.18.2Extended LED Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243.18.3LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253.18.4Basic Serial LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253.18.5Enhanced Serial LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263.18.6LED Port Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263.19Fast Link Failure Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263.20Integrated Two-Wire Serial Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273.20.1Read/Write Access Using the Two-Wire Serial MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273.21GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283.22Testing Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293.22.1Ethernet Packet Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293.22.2CRC Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293.22.3Far-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303.22.4Near-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303.22.5Connector Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313.22.6SerDes Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313.22.7VeriPHY Cable Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343.22.8JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353.22.9JTAG Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353.22.10Boundary Scan Register Cell Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373.23100BASE-FX Far-End Fault Indication (FEFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373.23.1100BASE-FX Halt Code Transmission and Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373.24Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383.24.1Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1394.1Register and Bit Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394.2IEEE802.3 and Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404.2.1Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414.2.2Mode Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424.2.3Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434.2.4Autonegotiation Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434.2.5Link Partner Autonegotiation Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444.2.6Autonegotiation Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444.2.7Transmit Autonegotiation Next Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454.2.8Autonegotiation Link Partner Next Page Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454.2.91000BASE-T Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454.2.101000BASE-T Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1464.2.11MMD Access Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474.2.12MMD Address or Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474.2.131000BASE-T Status Extension 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474.2.14100BASE-TX/FX Status Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474.2.151000BASE-T Status Extension 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484.2.16Bypass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494.2.17Error Counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504.2.18Error Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504.2.19Error Counter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504.2.20Extended Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504.2.21Extended PHY Control Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1514.2.22Extended PHY Control Set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524.2.23Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1534.2.24Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544.2.25Device Auxiliary Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544.2.26LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1554.2.27LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564.3Extended Page 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1574.3.1SerDes Media Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1584.3.2Cu Media CRC Good Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1594.3.3Extended Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1594.3.4ActiPHY Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604.3.5PoE and Miscellaneous Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614.3.6Ethernet Packet Generator Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614.3.7Ethernet Packet Generator Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.4Extended Page 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624.4.1Cu PMD Transmit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634.4.2EEE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654.4.3Extended Chip ID, Address 18E2 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664.4.4Entropy Data, Address 19E2 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664.4.5Extended Interrupt Mask, Address 28E2 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664.4.6Extended Interrupt Status, Address 29E2 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674.4.7Ring Resiliency Control (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 4.5Extended Page 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1684.5.1MAC SerDes PCS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1694.5.2MAC SerDes PCS Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704.5.3MAC SerDes Clause 37 Advertised Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714.5.4MAC SerDes Clause 37 Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714.5.5MAC SerDes Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714.5.6Media/MAC SerDes Transmit Good Packet Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714.5.7Media/MAC SerDes Transmit CRC Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724.5.8Media SerDes PCS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724.5.9Media SerDes PCS Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734.5.10Media SerDes Clause 37 Advertised Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744.5.11Media SerDes Clause 37 Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744.5.12Media SerDes Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744.5.13Media/MAC SerDes Receive CRC Good Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1754.5.14Media/MAC SerDes Receive CRC Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 4.6Extended Page 4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1764.6.1CSR Access Controls and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1764.6.21588_PPS_0/1 Mux Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1774.6.3SPI Daisy-Chain Controls and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 4.7General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1784.7.1Reserved General Purpose Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794.7.2LED/SIGDET/GPIO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794.7.3GPIO Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804.7.4GPIO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1814.7.5GPIO Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1824.7.6GPIO Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1824.7.7Microprocessor Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1834.7.8MAC Configuration and Fast Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1844.7.9Two-Wire Serial MUX Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1844.7.10Two-Wire Serial MUX Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854.7.11Two-Wire Serial MUX Data Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854.7.12Recovered Clock 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854.7.13Recovered Clock 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1864.7.14Enhanced LED Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1874.7.15Global Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 4.8Clause 45 Registers to Support Energy Efficient Ethernet and 802.3bf . . . . . . . . . . . . . . . . . . . . . . . 1894.8.1PMA/PMD Status 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1904.8.2PCS Status 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1904.8.3EEE Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1904.8.4EEE Wake Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1904.8.5EEE Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191。

NJU8758 D级功率放大器特性介

NJU8758 D 级功率放大器特性介
NJU8758 模拟信号输入、无滤波器的D 级功率放大器，可工作于从1.8V 到5.5V 宽广的范围。

由于输出电路是BTL 构成，故无需耦合电容器，并可得到1.5 W 输出?并且，由于无需输出LC 滤波器，可消减外接组件。

此外，在输出部内置有短路保护电路，所以当输出端之间的短路及输出端和GND 间的短路时可保护IC。

因为D 级动作可获得极高的功效，该产品最适用于安防器械等的小型民生设备、手机设备、便携式音响设备、笔记本电脑等。

包装外形图(效果图)
端子配置
方块示意图。

基于USB的晶片分选系统的设计

图1 系统构成
稳定工作。
系统原理及构成本系统的主要工作原理是，通过
螺旋送料器和直线送料器的间歇式高频定向振动，将同一批次且堆放在一起的石英晶片分离开来，并且排列成一个有序队列，向转运工位输送。采用光纤传感器、高精度分度盘以及必要的搬运机构，将队列中的每一片石英晶片转运至测试工位处。待测晶片到达测试工位后，系统启动扫频测试模块对被测晶片实施扫描测试，并实时采集测试结果。扫描测试结束后，将采集到的测试结果通过USB接口发送给计算机。计算机对测试结果进行
引言在石英晶体器件的生产过程中，
通过Байду номын сангаас石英晶片的频率响应特性进行严格的测试和分选，可以起到从源头控制产品的质量和生产工艺，提高产品产能的关键作用。目前已无法通过人工分选的方式满足对晶体器件质量和需求量的不断提升的要求，只有采用大量的自动分选设备才能完成分选任务。本文提出的分选系统通过自主研发的USB设备和上位机应用程序的互相配合，通过并发控制，使外部动作机构产生高效的协同动作，极大地提高设备工作效率和分选质量，同时还有效减少了设备维护的工作量，保证了设备在24小时不停机状态下连续
率点，当所有频率点都测试完成后，由单片机将所有测试数据，通过 USB接口发送给上位机分析处理。其程序流程如图2所示。其中，控制AD9852发出每一个频率点的控制字根据公式 FTW = Freq × 248 SYSCLK [2]计算得出。该固件程序采用C语言，并在Keil μVision集成环境中开发。为了加快项目研制进度，同时也为将来在软硬件的升级上提供方便，在固件程序开发中引入了TI公司针对Cortex M 系列单片机提供的外设驱动开发库 driverlib-cm3.lib和usblib-cm3.lib，这两个库对单片机片上外设控制寄存器底层和USB接口的应用进行了封装，在程序中只要调用相应的封装函数即可，提高了代码的可维护性。

ADD8754资料

ADD8754
FUNCTIONAL BLOCK DIAGRAM
COMP SS VIN_1 VIN_2
ADD8754
FB
FREQ
STEP-UP SWITCHING REGULATOR
LX
SHDN
UNDER VOLTAGE LOCKOUT AND THERMAL PROTECTION
VDD_2 OUT
LOGIC VOLTAGE REGULATOR
VCOM AMPLIFIER
LDO_OUT ADJ
POS NEG
05110-001
GATE PULSE MODULATION
VGH VGH_M VDD_1 CE RE VFLK VDPM
Figure 1.
350 mA. Three selectable output voltages are available: 2.5 V, 2.85 V, and 3.3 V.
The internal voltage regulator operates with an input voltage range of 3 V to 5.5 V and delivers a load current of up to
LCD Panel Power, VCOM,
and Gate Modulation
REVISION HISTORY
4/05—Revision 0: Initial Version
Current-Mode, Step-Up Switching Regulator Operation..... 12 VCOM Amplifier ........................................................................... 16 Gate Pulse Modulator Circuit................................................... 16 Power-Up Sequence ................................................................... 17 Shutdown..................................................................................... 17 UVLO........................................................................................... 17 Power Dissipation....................................................................... 18 Layout Guidelines....................................................................... 19 Typical Application Circuits ......................................................... 20 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25

HA4875E-10资料

HA4850 HD4850
HA4875 HD4875
HA4890 HD4890
Operating Voltage (47-63 Hz) [Vrms]
Max. Load Current 3 [Arms]
Min. Load Current, [mArms] Transient Overvoltage [Vpk] Max. Surge Current, (16.6ms) [Apk] Max. On-State Voltage Drop @ Rated Current [Vpk] Thermal Resistance Junction to Case (RθJC ) [°C/W] Maximum I 2 t for Fusing, (8.3 msec.) [A 2 sec] Max. Off-State Leakage Current @ Rated Voltage [mArms]
元器件交易网
Series HA, HD 12-90Amp • 480 Vac - AC OUTPUT
GENERAL SPECIFICATIONS Dielectric Strength 50/60Hz Input/Output/Base Insulation Resistance (Min.) @ 500 Vdc Max. Capacitance Input/Output Ambient Operating Temperature Range Ambient Storage Temperature Range
HA4825 HD4825
Featuring state-of-the-art Surface Mount Technology, these SPST-NO relays deliver proven reliability in the most demanding applications. Output consists of an SCR AC switch and is available in zero-cross, random turn-on (phase controllable) and versions with either AC or DC input (coil) control. Manufactured in Crydom’s ISO 9001 Certified facility for optimum product performance and reliability.

sp8714中文资料_数据手册_IC数据表

March 2006The SP8714 is a switchable divide by 32/33, 64/65programmable divider which is guaranteed to operate up to 2100MHz. It will operate from a supply of 2.7V to 5.25V and requires typically 6.8mA (including the output current). It also features a power down facility for battery economy.The RF inputs are internally biased and should be capacitively coupled to the signal source. The output is designed to interface with CMOS synthesisers.FEATURES I Operation to 2100MHz I Very Low PowerI Single Supply Operation 2.7V to 5.25V I Power Down Facility for Battery Economy I Latched Modulus Control Input I Push Pull Output DriveIESD Protection on All Pins †APPLICATIONS I Cellular Telephones I Cordless Telephones†ESD precautions must be observedFig. 1 Pin connections - top viewMP81 82 73 64 5RF INPUT POWER DOWN MODULUS CONTROL V EESP8714RF INPUT V RATIO SELECTOUTPUTCCFig. 2 Block diagramOrdering InformationIndustrial Temperature Range Miniature Plastic SOIC PackageSP8714/IG/MPAS 8 Pin SOP/SOIC Tubes SP8714/IG/MPAC 8 Pin SOP/SOIC Tape & Reel SP8714/IG/MPB Q 8 Pin SOP/SOIC* Tape & Reel SP8714/IG/MPB P 8 Pin SOP/SOIC* Tubes*Pb Free Matte Tin1Zarlink Semiconductor Inc.Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved.2SP8714ELECTRICAL CHARACTERISTICSGuaranteed over the following conditions (unless otherwise stated):V CC =+2.7V to +5.25V (with respect to V EE ), Output load (pin 4) = 10pF, T amb = -40°C to +85°C (note 2)CharacteristicUnitsConditionsSupply current (note 3) 6.88.5mA Power down input low Supply current (note 3)850µA Power down input highPower down high V CC -0.5V CC V Power down low 0V CC -2.0V Modulus control high (note 4)0.6V CCV CC V Divide by 32 or 64Modulus control low (note 4)00.4V CC V Divide by 33 or 65Ratio select high (note 4, 9)0.6V CCV CC V Divide by 32 or 33Ratio select low(note 4, 9)0.4V CCVDivide by 64 or 65Max. sinewave input frequency 2100MHz See Figure 5Min. sinewave input frequency 200MHzSee Figure 5Min. RF input voltage 50mV RMS RF input 200MHz to2100MHz. See Figure 5Max. RF input voltage 200mV RMS RF input 200MHz to2100MHz. See Figure 5Output level (pin 4)500600mV p-p Modulus set-up time, t s (notes 5,6,8)10nsRF input = 1GHz Modulus hold time, t h (notes 6,8)1ns RF input = 1GHz Power down time, t pd(notes 7,8)10µs See Figure 9Power down recovery time, t pu (notes 7,8)8µsSee Figure 9NOTES2. All electrical testing is performed at +85°C.3. Typical values are measured at +25°C and V CC = +5V.4. Modulus Control and Ratio Select are high impedance inputs which can be driven directly by standard CMOS outputs.5. Modulus control is latched at the end of the previous cycle.6. See Figure 4.7. See Figure8.8. These parameters are not tested but are guaranteed by design.9. The ratio select pin is not intended to be switched dynamically.ValueMin.Typ.Max.ABSOLUTE MAXIMUM RATINGSSupply voltage (V EE =0V)(note 1)-0.5V to 7V Control and RF inputs,RF output (V EE =0V)(note 1)-0.5V to V CC +0.5V RF input current (note 1)10mA Operating temperature -40°C to +85°C Storage temperature range -55°C to +150°C Maximum junction temperature +150°C NOTE 1. Duration <2 minutes.https://2SP8714OPERATING NOTESThe RF inputs are biased internally and are normally coupled to the signal source with suitable capaitors.The output stage has a novel design and is intended to drive a CMOS synthesiser input. External pull-down resistors or circuits are not required. The SP8714 is not suitable for driving TTL or similar devices.The device will operate down to DC frequencies for non-sinusoidal signals provided that the input slew rate is better than 100V/µs.POWER DOWN (pin 7) is connected internally to a pull-up resistor. If the battery economy facility is not used, pin 7 should be connected to V EE .Fig. 3 Typical input characteristicsRatio Modulus Division Select Control Ratio(Pin 3)(Pin 6)L L 65L H 64H L 33HH321000800600400200500 1000 1500 2000 2500 3000* Tested as specified in table of Electrical CharacteristicsFREQUENCY (MHz)R F I N P U T V O L T A G E (m V R MS )Table 1 Truth tableFig. 4 Modulus control timing diagram4SP8714Fig. 6 Typical S11 parameter for pin 1. V CC = +5.0VFig. 5 Toggle frequency test circuitj0.2j0.5j1j2-j0.2-j0.5-j2-j1f10.20.512f2SP8714INPUT FREQUENCY (MHz)Fig. 7 Typical input impedance v. frequency46SP8714Table.2 Coefficients for Fig.7FREQ-MHZ 130.000177.200224.400271.600318.800366.000413.200460.400507.600554.800602.000649.200596.400743.600790.800838.000885.200332.400979.6001026.801074.001121.201168.401215.601262.801310.001357.201404.401451.601498.801546.001593.201640.401687.601734.801782.001829.201876.401923.601970.802018.002065.202112.402159.602206.802254.002301.202348.402395.602442.802490.00jx (Ω) -733.538-583.339-482.377-411.502-346.620-304.804-269.674-245.161-224.572-203.241-186.545-174.839-160.468-149.642-143.144-132.750-124.495-118.100-109.552-103.110-98.149-99.907-99.639-95.033-89.249-82.581-77.212-71.976-70.250-61.898-53.403-44.704-41.522-43.255-44.879-67.801-86.964-87.052-80.484-73.570-67.291-60.620-54.716-49.220-43.340-37.163-30.805-24.040-17.165-8.172-4.368R (Ω)255.068153.330 88.649 71.050 39.526 38.779 23.809 27.545 22.227 17.767 14.607 13.075 12.583 10.213 11.269 10.509 10.172 10.841 12.260 14.508 19.260 23.285 18.956 14.377 12.711 12.598 14.565 19.164 15.001 15.864 18.993 26.822 39.830 47.875 63.267 74.259 58.878 42.53032.30227.33324.89423.36923.57723.02323.32524.62326.34028.63231.16134.21939.808https://6SP8714Fig. 9 Power-down time test circuitCC V 0.05I CTIME0.95I CCC V Fig. 8 Power up and power down。

8753E8753ES8753D说明书

8753E8753ES8753D说明书HP8753E 射频⽹络分析仪★频率范围：30kHz~3或6GHz★带有固态转换的集成化S参数测试装置★达110dB的动态范围★快的测量速度和数据传递速率★⼤屏幕LCD显⽰器加上供外部监视器⽤的VGA输出★同时显⽰所有4个S参数★将仪器状态和数据存储/调⽤到内置软盘驱动器★可选⽤的时域测量和扫描谐波测量HP 8753E射频⽹络分析仪为满⾜研制实验室或⽣产制造的测试需求，在速度、性能和⽅便使⽤上提供了⽆与伦⽐的结合。

8753E以其覆盖3或6GHz频率范围的集成化S参数测试装置、达110dB的动态范围以及频率扫描和功率扫描，为表征有源或⽆源⽹络、元器件和⼦系统的线性和⾮线性特性提供了圆满的解决⽅案。

所使⽤的新型微处理器使测量和数据传递速率⽐以往的型号快达7倍之多。

⽹络分析仪的特点是有2个独⽴的测量通道，可同时测量和显⽰所有4个S参数。

可以选择⽤幅度、相位、群延迟、史密斯圆图、极坐标、驻波⽐或时域格式来显⽰反射和传输参数的任意组合。

便于使⽤的专⽤功能键能迅速访问各个测量功能。

可以利⽤达4个刻度格⼦在⾼分辩率的LCD彩⾊显⽰器上以重叠或分离屏⾯的形式来观察测量结果。

为了驱动更⼤的外部监视器，以便于观察，增加了与VGA兼容的输出。

较好的通⽤性和性能⼀个集成化的合成源提供了达10mW的输出功率(⽤选件011可达100mW)，1Hz的频率分辩率和线性频率，对数频率，列表频率，CW和功率扫描功能。

三个调谐接收机可以在6GHz(带有选件006频率扩展)处105dB或3GHz(标准)110dB的宽动态范围内进⾏独⽴的功率测量或同时⽐值测量。

集成化的测试装置可以在不使⽤倍频器的情况下，测量达6GHz装置的传输和反射特性。

为了在⾮同轴系统中进⾏⽅便⽽精确的测量，特提供了TRL*/LRM*1校准。

利⽤内置适配器移去校准技术，还能实现对⾮插⼊式器件的⾼精度测量。

⾼稳定度的频率基准(选件1D5)提⾼了对⾼Q器件，如表⾯声波(SAW)器件、晶体谐振器或介质谐振滤波器的频率测量精度。