IC制造流程简介

(a) (b)
Reaction
(d)
(c)
(b) Adsorbed onto the wafer surface (c) Deposition reaction happens (d) Byproducts diffuse through the interface boundary layer (e) Reagents & byproducts pass away
CMP System Schematic
Slurry
Down Force
Carrier Carrier Film Wafer
Interconnects
Wafer Carrier Carrier Film
c
Composite Pad Table
Polishing Pad
Polishing table wafer p
Major Parameters In CMP
SiO2 CMP:
• Down Force • Rotating Speed (p) • Type of The Pad
Metal and Si CMP:
• pH Measurement
* The lower the force-speed ratio the better the planarity
(a) O2 Solid dopant source furnace Heater (b)
Carrier gas
Carrier gas Quartz tube Solid dopant source O2 Valve Liquid dopant source
(c)
Gas dopant source
Diffusion Precess -2
• Precise and stable electric power supplier
• Temperature control
• Concentration control
• The measurement of the ion current (Farady Cup)
Physical Vapor Deposition
Etch to match resist pattern
Strip resist
Wafer
Resist removed
Introduction to Doping
Doping: To get the extrinsic semiconductor by adding donors or acceptors, which may
Si Substrate
Positive Resist
Negative Resist
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Etching Intro - 2
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Positive Resist
Negative Resist
Ion Implanter
Mass Analysis
Accelerator
Scanner
Electron Shower
Farady Cap Extractor
Ion Source
Dopant Source
Doping Parameters
Parameters
• Doping elements selection
The Outline
Wafer Start Wafer Cleaning
CMP
Oxidation PVD, CVD
Photolithography
Annealing
Implantation
Etch (Dry or Wet)
製程
The Introduction to The Manufacturing Process of VLSI
The growth temperature is around 400 0C to 750 0C. Better step coverage ability.
(3) Plasma Enhanced CVD (PECVD)
The growth temperature is under 400 0C. In the case of the Al deposition and non-thermal process.
Seed Melt
Noncontaminating Liner
Growing Crystal
Graphite Crucible
Crystal to Wafe
(a) As-grown crystal
(b) Grind crystal to remove undulations and saw to remove portions in resistive range
A manufacturing process that can uniformly implants the ions into the wafer in the specified depth and consistence by selecting and accelerating ions.
Quartz tube Heater Wafer
Quartz boats
Gas out Gas out
Profiling Tc (In the tube)
Dopants and gas in
Gas in
Introduction to Ion Implantation
1. The definition:
Metal Target
DC
Gas In Wafer
Plate Collimator To The Vacuum Pump
Chemical Vapor Deposition
Main Stream
(e)
Vacuum System
Interface Boundary Layer
(a) Reagents diffuse through the interface boundary layer
Slurry
Particle
(0.1 ~ 2.0 um)
• Silica (Colloidal) • Alumina (Dispersed)
Liquor
(Contains some oxidant and organic reagents in the case of metal CMP)
• KOH • NH4OH
Factors
• The selection of the ion resource • The design of the mass analyzer
• Scanning uniformity control
• Scanning system • Vacuum control • Precise wafer position control
cause the impurity energy level. The action that adding particular impurities into the semiconductor is called “doping” and the impurity that added is called the “dopant”.
(c) Saw into slices (with orienting flats ground before sawing)
(d) Round edges of slice by grinding
(e) Polish slice
微影(Photolithography)
原理： 在晶片表面上覆上一層感光材料，來自光源的 平行光透過光罩的圖形，使得晶片表面的感光 材料進行選擇性的感光。
ANDY
晶圓(Wafer)
晶棒成長 切片(Slicing) 研磨(Lapping)
清洗(Cleaning)
拋光(Polishing)
檢查(Inspection)
The Czochralski Method - 1
(a) Seed being lowered down to melt (b) Seed dipped in melt freezing on seed just beginning (b) Partially grown crystal
Wafer surface
Heat Source
Solutions to Deposition
(1) Thermal Oxidation
The growth temperature is above 900 0C. High quality SiO2.
(2) Low Pressure CVD (LPCVD)
Light source
Mask Wafer
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Resist Wafer Oxide
Photolithography Process - 2
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Develop resist
Wafer
Developed resist showing pattern
Etch oxide
Wafer
Wafer Cleaning
Purpose:
To remove the remains and impurities
Methods:
• Brush Cleaning • Spray Cleaning • Ultrasonic Cleaning
Etching Intro - 1
PhotoMask Photo resist SiO2
相关定义
集成电路是指把特定电路所需的各种电 子元件及线路缩小并制作在大小仅及 2CM平方或更小的面积上的一种电子产 品。
相关定义
集成电路主要种类有两种：逻辑LOGIC 及记忆体MEMORY。前者主要执行逻辑 的运算如电脑的微处理器后者则如只读 器READ ONLY 及随机处理器RANDOM ACCESS MEMORY等。集成电路的生产主 要分三个阶段：硅镜片WAFER的制造， 集成电路的制造及集成电路的包装 PACKAGE
2. The purpose:
To change the resistance value of the semiconductor by implanting the dopant.
3. Energy range (8 years ago)
(1) General process：10 KeV - 180 KeV (>0.35m) (<100KeV for 0.18 m now) (2) Advanced process：10 KeV - 3 MeV (<0.5m) (3) R&D process：0.2 KeV - 5 KeV
感光材料：
正片－經過顯影(DeLeabharlann Baiduelopment)，材料所獲得 的圖案與光罩上相同稱為正片。 負片－如果彼此成互補的關係稱負片
Photolithography Process - 1
Apply resist after priming (spinner) Resist Wafer Condenser lens Resist Wafer Oxide Mask Contact Print to expose resist or Projection print to expose resist Projection lens
IC制造流程简介 ANDY
相关定义
半导体是指导电能力介于导体和非导体之间的 材料，其指四价硅中添加三价或五价化学元素 而形成的电子元件，它有方向性可以用来制造 逻辑线路使电路具有处理资讯的功能。 半导体的传导率可由搀杂物的浓度来控制：搀 杂物的浓度越高，半导体的电阻系数就越底。 P型半导体中的多数载体是电洞。硼是P型的掺 杂物。 N型半导体的多数载体是电子。磷，砷，锑是N 型的搀杂物。
Doping methods: 1.Diffusion 2.Ion Implantation
Diffusion Process -1
Pre-deposition: To put the impurities on the wafer surface. Generally used dopant resource furnace design:
Drive-in: To implant the dopant into the wafer by the thermal process Horizontal Type
Wafer Quartz tube 3-Zone heating element Reaction room
Vertical Type