ADP5065ACBZ-1-R7;中文规格书,Datasheet资料
ADP-101-G1 通用多功能保护测控装置技术和使用说明书
装置初始操作密码是 001。
序号 1
版本号 V1.00
文档修改摘要 第一版
修改日期 2012-11-05
目录
1 概述 .........................................................................................................................................1 1.1 应用范围 ..........................................................................................................................1 1.2 保护配置和功能 ..............................................................................................................1 1.2.1 保护配置 ...................................................................................................................1 1.2.2 测控功能 ...................................................................................................................1 1.2.3 保护信息功能 ...........................................................................................................1 1.3 性能特征 ..........................................................................................................................2
ATSTK520;中文规格书,Datasheet资料
STK520 .............................................................................................. User GuideSTK520 User Guide 3Table of ContentsSection 1Introduction............................................................................................1-2Section 2Using the STK520 Top Module.............................................................2-42.1Connecting the STK520 to the STK500 Starter Kit..................................2-42.1.1Placing an AT90PWM3 on the STK520.............................................2-42.1.2Placing an AT90PWM2 on the STK520.............................................2-52.2Programming the AVR..............................................................................2-72.2.1In-System Programming....................................................................2-72.2.2High-voltage Programming................................................................2-82.3JTAGICE mkII Connector.........................................................................2-92.4STK520 Jumpers, Leds & Test Points....................................................2-112.5DALI Interface.........................................................................................2-122.6Potentiometer.........................................................................................2-13Section 3Troubleshooting Guide........................................................................3-14Section 4Technical Specifications......................................................................4-16Section 5Technical Support ...............................................................................5-17Section 6Complete Schematics .........................................................................6-20IntroductionSection 1IntroductionThe STK520 board is a top module designed to add AT90PWM family support to theSTK500 development board from Atmel Corporation.The STK520 includes connectors and hardware allowing full utilization of the new fea-tures of the AT90PWM, while the Zero Insertion Force (ZIF) socket allows easy to use ofSO24 & SO32 packages for prototyping.This user guide acts as a general getting started guide as well as a complete technicalreference for advanced users.Notice that in this guide, the word AVR is used to refer to the target component(AT90PWM2, AT90PWM3...)Figure 1-1. STK520 Top Module for STK500Introduction1.1Features STK520 is a New Member of the Successful STK500 Starter Kit Family.Supports the AT90PWM2 & AT90PWM3.DALI Hardware Interface.Supported by AVR Studio® 4.Zero Insertion Force Socket for SO24 & SO32 Packages.High Voltage Parallell Programming.Serial Programming.DALI Peripherals can be Disconnected from the Device.6 Pin Connector for On-chip Debugging using JTAG MKII Emulator.Potentiometer for the Demo Application.Quick Reference to all Switches and Jumpers in the Silk-Screen of the PCB.Using the STK520 Top Module Section 2Using the STK520 Top Module2.1Connecting the STK520 to theSTK500 Starter Kit Connect the STK520 to the STK500 expansion header 0 and 1. It is important that the top module is connected in the correct orientation as shown in Figure 2-1. The EXPAND0 written on the STK520 top module should match the EXPAND0 written beside the expansion header on the STK500 board.Figure 2-1. Connecting STK520 to the STK500 BoardNote:Connecting the STK520 with wrong orientation may damage the board.2.1.1Placing anAT90PWM3 on theSTK520The STK520 contains both a ZIF socket for a SO32 package. Care should be taken so that the device is mounted with the correct orientation. Figure 2-2 shows the location of pin1 for the ZIF socket.Using the STK520 Top ModuleFigure 2-2. Pin1 on ZIF SocketCaution: Do not mount an AT90PWM3 on the STK520 at the same time as an AVR ismounted on the STK500 board or at the same time as an AT90PWM2 is mounted on theSTK520 board. None of the devices might work as intended.2.1.2Placing anAT90PWM2 on theSTK520The STK520 contains both a ZIF socket for a SO24 package. Care should be taken so that the device is mounted with the correct orientation. Figure 2-2 shows the location of pin1 for the ZIF socket.Figure 2-3. Pin1 on ZIF SocketPIN1PIN1Using the STK520 Top Module Caution: Do not mount an AT90PWM2 on the STK520 at the same time as an AVR is mounted on the STK500 board or at the same time as an AT90PWM3 is mounted on the STK520 board. None of the devices might work as intended.Using the STK520 Top Module2.2Programming theAVR The AVR (AT90PWM2, AT90PWM3...) can be programmed using both SPI and High-voltage Parallel Programming. This section will explain how to connect the programming cables to successfully use one of these two modes. The AVR Studio STK500 software is used in the same way as for other AVR partsNote:The AT90PWM3 also support Self Programming, See AVR109 application note for more information on this topic.2.2.1In-SystemProgramming Figure 2-4. In-System ProgrammingTo program the AT90PWM3 using ISP Programming mode, connect the 6-wire cable between the ISP6PIN connector on the STK500 board and the ISP connector on the STK520 board as shown in Figure 2-4. The device can be programmed using the Serial Programming mode in the AVR Studio4 STK500 software.Note:See STK500 User Guide for information on how to use the STK500 front-end software for ISP Programming.Using the STK520 Top Module2.2.2High-voltageProgramming Figure 2-5. High-voltage (Parallel) ProgrammingTo program the AVR using High-voltage (Parallel) Programming, connect the PROGC-TRL to PORTD and PROGDATA to PORTB on the STK500 as shown in Figure 2-5. Make sure that the TOSC-switch is placed in the XTAL position.As described in the STK500 User Guide (jumper settings), mount the BSEL2 jumper in order to High-voltage Program the ATmega devices. This setting also applies to High-voltage Programming of the AVR.The device can now be programmed using the High-voltage Programming mode in AVR Studio STK500 software.Note:See the STK500 User Guide for information on how to use the STK500 front-end software in High-voltage Programming mode.Note:For the High-voltage Programming mode to function correctly, the target voltage must be higher than 4.5V.Using the STK520 Top Module2.3JTAGICE mkIIConnector See the following document :“JTAGICE mkII Quick Start Guide” which purpose is “Connecting to a target board with the AVR JTAGICE mkII”.This note explains which signals are required for ISP and which signals are required for debugWIRE.Figure 2-6 shows how to connect the JTAGICE mkII probe on the STK520 board. Figure 2-6. Connecting JTAG ICE to the STK520The ISP connector is used for the AT90PWM3 built-in debugWire interface. The pin out of the connector is shown in Table 2-1 and is compliant with the pin out of the JTAG ICE available from Atmel. Connecting a JTAG ICE to this connector allows On-chip Debug-ging of the AT90PWM3.More information about the JTAG ICE and On-chip Debugging can be found in the AVR JTAG ICE User Guide, which is available at the Atmel web site, .分销商库存信息: ATMELATSTK520。
ADL5606ACPZ-R7;中文规格书,Datasheet资料
ADL5606
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3
The ADL5606 is fabricated on a GaAs HBT process and is packaged in a compact 4 mm × 4 mm, 16-lead LFCSP that uses an exposed paddle for excellent thermal impedance. The ADL5606 operates from −40°C to +85°C. A fully populated evaluation board tuned to 2140 MHz is also available.
SN6505B隔离式电源说明书
10 µF1ZHCA801A–February 2018–Revised March 2019隔离式电源，低噪声电路：5V 、100mA Analog Engineer's Circuit:DataConvertersZHCA801A–February 2018–Revised March 2019隔离式电源，低噪声电路：5V 、100mAReed Kaczmarek电源AVDD Vee Vdd 5.0V6.5V5.0V设计说明此设计展示了采用变压器驱动器和低压降稳压器(LDO)的隔离式电源。
此设计旨在与数字隔离式SAR ADC 结合使用（如数字隔离式ADS8689设计中所示）。
工业应用需要隔离接口的情况下，便是此设计与SAR ADC 结合后的主要应用场合。
根据输出电流要求和输出电压噪声要求不同，可以选择不同的变压器驱动器和LDO 。
该电源的设计和测试均基于采用ADS8689的PCB ，本文档稍后会显示ADS8689的性能以证明该电源的有效性。
该电路实现方案适用于如下一些应用：模拟输入模块、心电图(ECG)、脉动式血氧计和临床患者监护仪。
2ZHCA801A–February 2018–Revised March 2019隔离式电源，低噪声电路：5V 、100mA 规格规格目标值测得值LDO 输出电流<100mA 每通道16mA LDO 输出电压噪声<1mV RMS不适用ADS8689信噪比(SNR)92dB 92.4dB ADS8689总谐波失真(THD)–112dB111.3dB设计注意事项1.确定变压器次级侧所需的电源电流。
此信息将用于组件选择。
2.选择变压器和变压器驱动器对于设计正确的隔离式电源非常重要。
3.SN6505B 上的CLK 引脚可连接到外部时钟或悬空以便使用内部420kHz 时钟。
组件选择1.根据所需的输出电流选择变压器驱动器。
•SN6505将提供高达1A 的输出电流。
FGA25N120FTD;中文规格书,Datasheet资料
@ TC = 25oC @ TC = 100oC
Diode continuous Forward current Maximum Power Dissipation Maximum Power Dissipation Operating Junction Temperature
@ TC = 100oC @ TC = 25oC @ TC = 100oC
Symbol
Parameter
Test Conditions
VFM
Diode Forward Voltage
IF = 25A
TC = 25oC TC = 125oC
trr
Diode Reverse Recovery Time
TC = 25oC TC = 125oC
Irr
Diode Reverse Recovery Time
©2009 Fairchild Semiconductor Corporation
1
FGA25N120FTD Rev. A1
G
E
Ratings
1200 ± 25 50 25 75 25 313 125 -55 to +150 -55 to +150 300
Units
V V A A A A W W oC oC
Applications
• Induction heating and Microvewave oven • Soft switching applications
February 2009
tm
General Description
Using advanced field stop trench technology, Fairchild’s 1200V trench IGBTs offer superior conduction and switching performances, and easy parallel operation with exceptional avalanche ruggedness. This device is designed for soft switching applications.
AD8253ARMZ-R7,AD8253ARMZ-R7,AD8253ARMZ-R7,AD8253ARMZ-RL,AD8253ARMZ, 规格书,Datasheet 资料
10 MHz, 20 V/μs, G = 1, 10, 100, 1000 i CMOSProgrammable Gain Instrumentation AmplifierAD8253 Rev. AInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, M A 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.FEATURESSmall package: 10-lead MSOPProgrammable gains: 1, 10, 100, 1000Digital or pin-programmable gain settingWide supply: ±5 V to ±15 VExcellent dc performanceHigh CMRR: 100 dB (minimum), G = 100Low gain drift: 10 ppm/°C (maximum)Low offset drift: 1.2 μV/°C (maximum), G = 1000 Excellent ac performanceFast settling time: 780 ns to 0.001% (maximum)High slew rate: 20 V/μs (minimum)Low distortion: −110 dB THD at 1 kHz,10 V swingHigh CMRR over frequency: 100 dB to 20 kHz (minimum) Low noise: 10 nV/√Hz, G = 1000 (maximum)Low power: 4 mAAPPLICATIONSData acquisitionBiomedical analysisTest and measurementGENERAL DESCRIPTIONThe AD8253 is an instrumentation amplifier with digitally programmable gains that has gigaohm (GΩ) input impedance, low output noise, and low distortion, making it suitable for interfacing with sensors and driving high sample rate analog-to-digital converters (ADCs).It has a high bandwidth of 10 MHz, low THD of −110 dB, and fast settling time of 780 ns (maximum) to 0.001%. Offset drift and gain drift are guaranteed to 1.2 μV/°C and 10 ppm/°C, respectively, for G = 1000. In addition to its wide input common voltage range, it boasts a high common-mode rejection of 100 dB at G = 1000 from dc to 20 kHz. The combination of precision dc performance coupled with high speed capabilities makes the AD8253 an excellent candidate for data acquisition. Furthermore, this monolithic solution simplifies design and manufacturing and boosts performance of instrumentation by maintaining a tight match of internal resistors and amplifiers.The AD8253 user interface consists of a parallel port that allows users to set the gain in one of two different ways (see Figure 1 for the functional block diagram). A 2-bit word sent via a bus can be latched using the WR input. An alternative is to use transparent gain mode, where the state of logic levels at the gain port determines the gain.FUNCTIONAL BLOCK DIAGRAMS S+IN6983-1Figure 1.8070605040302010–10–201k10k100k1M10M100MFREQUENCY (Hz)GAIN(dB)6983-23Figure 2. Gain vs. FrequencyTable 1. Instrumentation Amplifiers by CategoryGeneralPurposeZeroDriftMilGradeLowPowerHigh SpeedPGAAD82201AD82311AD620AD6271AD8250AD8221AD85531AD621AD6231AD8251AD8222AD85551AD524AD82231AD8253AD82241AD85561AD526AD8228AD85571AD6241 Rail-to-rail output.The AD8253 is available in a 10-lead MSOP package and is specified over the −40°C to +85°C temperature range, making it an excellent solution for applications where size and packing density are important considerations.AD8253Rev. A | Page 2 of 24TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Diagram ........................................................................... 5 Absolute Maximum Ratings ............................................................ 6 Maximum Power Dissipation ..................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 16 Gain Selection ............................................................................. 16 Power Supply Regulation and Bypassing ................................ 18 Input Bias Current Return Path ............................................... 18 Input Protection ......................................................................... 18 Reference Terminal .................................................................... 19 Common-Mode Input Voltage Range ..................................... 19 Layout .......................................................................................... 19 RF Interference ........................................................................... 19 Driving an Analog-to-Digital Converter ................................ 20 Applications Information .............................................................. 21 Differential Output .................................................................... 21 Setting Gains with a Microcontroller ...................................... 21 Data Acquisition ......................................................................... 22 Outline Dimensions ....................................................................... 23 Ordering Guide .. (23)REVISION HISTORY8/08—Rev. 0 to Rev. AChanges to Ordering Guide (23)7/08—Revision 0: Initial VersionAD8253SPECIFICATIONS+V S = +15 V, −V S = −15 V, V REF = 0 V @ T A = 25°C, G = 1, R L = 2 kΩ, unless otherwise noted.Table 2.Parameter Conditions Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR)CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 VG = 1 80 100 dBG = 10 96 120 dBG = 100 100 120 dBG = 1000 100 120 dB CMRR to 20 kHz1+IN = −IN = −10 V to +10 VG = 1 80 dBG = 10 96 dBG = 100 100 dBG = 1000 100 dB NOISEVoltage Noise, 1 kHz, RTIG = 1 45 nV/√HzG = 10 12 nV/√HzG = 100 11 nV/√HzG = 1000 10 nV/√Hz0.1 Hz to 10 Hz, RTIG = 1 2.5 μV p-pG = 10 1 μV p-pG = 100 0.5 μV p-pG = 1000 0.5 μV p-p Current Noise, 1 kHz 5 pA/√Hz Current Noise, 0.1 Hz to 10 Hz 60 pA p-p VOLTAGE OFFSETOffset RTI V OS G = 1, 10, 100, 1000 ±150 + 900/G μV Over Temperature T = −40°C to +85°C ±210 + 900/G μV Average TC T = −40°C to +85°C ±1.2 + 5/G μV/°C Offset Referred to the Input vs. Supply (PSR) V S = ±5 V to ±15 V ±5 + 25/G μV/V INPUT CURRENTInput Bias Current 5 50 nA Over Temperature2T = −40°C to +85°C 40 60 nA Average TC T = −40°C to +85°C 400 pA/°C Input Offset Current 5 40 nA Over Temperature T = −40°C to +85°C 40 nA Average TC T = −40°C to +85°C 160 pA/°C DYNAMIC RESPONSESmall-Signal −3 dB BandwidthG = 1 10 MHzG = 10 4 MHzG = 100 550 kHzG = 1000 60 kHz Settling Time 0.01% ΔOUT = 10 V stepG = 1 700 nsG = 10 680 nsG = 100 1.5 μsG = 1000 14 μsRev. A | Page 3 of 24AD8253Rev. A | Page 4 of 24AD8253Rev. A | Page 5 of 24Parameter Conditions Min Typ Max UnitPOWER SUPPLY Operating Range±5 ±15 V Quiescent Current, +I S 4.6 5.3 mA Quiescent Current, −I S 4.5 5.3mA Over Temperature T = −40°C to +85°C 6 mA TEMPERATURE RANGE Specified Performance−40 +85 °C1 See Figure 20 for CMRR vs. frequency for more information on typical performance over frequency.2Input bias current over temperature: minimum at hot and maximum at cold. 3See Figure 30 for input voltage limit vs. supply voltage and temperature. 4See Figure 32, Figure 33, and Figure 34 for output voltage swing vs. supply voltage and temperature for various loads. 5Add time for the output to slew and settle to calculate the total time for a gain change.TIMING DIAGRAMA0, A1WR06983-003Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)AD8253Rev. A | Page 6 of 24ABSOLUTE MAXIMUM RATINGSTable 3.Parameter RatingSupply Voltage ±17 VPower Dissipation See Figure 4Output Short-Circuit CurrentIndefinite 1 Common-Mode Input Voltage ±V S Differential Input Voltage ±V S Digital Logic Inputs±V SStorage Temperature Range –65°C to +125°C Operating Temperature Range 2–40°C to +85°C Lead Temperature (Soldering 10 sec) 300°C Junction Temperature140°C θJA (4-Layer JEDEC Standard Board) 112°C/W Package Glass Transition Temperature140°C1 Assumes the load is referenced to midsupply.2Temperature for specified performance is −40°C to +85°C. For performance to +125°C, see the Typical Performance Characteristics section.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.MAXIMUM POWER DISSIPATIONThe maximum safe power dissipation in the AD8253 package is limited by the associated rise in junction temperature (T J ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 140°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8253. Exceeding a junction temperature of 140°C for an extended period can result in changes in silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (θJA ), the ambient temperature (T A ), and the total power dissipated in the package (P D ) determine the junction temperature of the die. The junction temperature is calculated as()JA D A J θP T T ×+=The power dissipated in the package (P D ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V S ) times the quiescent current (I S ). Assuming the load (R L ) is referenced tomidsupply, the total drive power is V S /2 × I OUT , some of which isdissipated in the package and some of which is dissipated in theload (V OUT × I OUT ). The difference between the total drive power and the load power is the drive power dissipated in the package.P D = Quiescent Power + (Total Drive Power − Load Power )()L 2OUT L OUTS S S D R V –R V2V I V P ⎟⎟⎠⎞⎜⎜⎝⎛×+×= In single-supply operation with R L referenced to −V S , the worstcase is V OUT = V S /2.Airflow increases heat dissipation, effectively reducing θJA . In addition, more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the θJA .Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature on a 4-layer JEDEC standard board.2.001.751.501.251.000.750.500.250–40–20120100806040200M A X I M U M P O W E R D I S S I P A T I O N (W )AMBIENT TEMPERATURE (°C)06983-004Figure 4. Maximum Power Dissipation vs. Ambient TemperatureESD CAUTIONAD8253Rev. A | Page 7 of 24PIN CONFIGURATION AND FUNCTION DESCRIPTIONS–IN DGND –V S A0A1+INREF+V S OUT WRAD8253TOP VIEW(Not to Scale)1234510987606983-005Figure 5. 10-Lead MSOP (RM-10) Pin ConfigurationAD8253Rev. A | Page 8 of 24TYPICAL PERFORMANCE CHARACTERISTICST A @ 25°C, +V S = +15 V , −V S = −15 V , R L = 10 kΩ, unless otherwise noted.CMRR (µV/V)21006983-006N U M B E R O F U N I T S180150120906030–60–40–20020INPUT OFFSET CURRENT (nA)240120180601502109030604020006983-009N U M B E R O F U N I T S–60–20–40Figure 6. Typical Distribution of CMRR, G = 1 Figure 9. Typical Distribution of Input Offset CurrentINPUT OFFSET VOLTAGE, V OSI , RTI (µV)180120150200100006983-007N U M B E R O F U N I T S–200–10006983-0101100kFREQUENCY (Hz)N O I S E (n V /√H z )101001k10k8070605040302010Figure 10. Voltage Spectral Density Noise vs. FrequencyFigure 7. Typical Distribution of Offset Voltage, V OSI 06983-011INPUT BIAS CURRENT (nA)30020025015010050906030006983-008N U M B E R O F U N I T S–90–30–60Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1Figure 8. Typical Distribution of Input Bias CurrentAD8253Rev. A | Page 9 of 2406983-012Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1000 06983-01318011FREQUENCY (Hz)N O I S E (p A /√H z )00k 101001k 10k 161412108642Figure 13. Current Noise Spectral Density vs. Frequency 06983-014Figure 14. 0.1 Hz to 10 Hz Current Noise 201816141210864200.010.1110WARM-UP TIME (Minutes)C H A N G E I N I N P U T O F F S E T V O L T A G E (µV )06983-015Figure 15. Change in Input Offset Voltage vs. Warm-Up Time, G = 10001401201008040600101M06983-016FREQUENCY (Hz)P S R R (d B )1001k 10k 100k 20Figure 16. Positive PSRR vs. Frequency, RTI1401201008040600101M06983-017FREQUENCY (Hz)P S R R (d B )1001k 10k 100k 20Figure 17. Negative PSRR vs. Frequency, RTIAD8253Rev. A | Page 10 of 2420100–10–20–30–40–50–6012.0I B +10.59.07.56.04.53.01.50–15–10–5051015COMMON-MODE VOLTAGE (V)I N P U T B I A S C U R R E N T (n A )I N P U T O F F S E T C U R R E N T (n A )06983-018I B –I OSFigure 18. Input Bias Current and Offset Current vs. Common-Mode Voltage 302520151050–10–5–60–40–20020406080100120140TEMPERATURE (°C)I N P U T B I A S C U R R E N T A N D O F F S E T C U R R E N T (n A )06983-019I B +I B –I OS Figure 19. Input Bias Current and Offset Current vs. Temperature 012010080604020106983-020FREQUENCY (Hz)C M R R (d B )1001k 10k 100k 1MFigure 20. CMRR vs. Frequency120100806040201006983-021FREQUENCY (Hz)C M R R (d B)1001k 10k 100k 1MFigure 21. CMRR vs. Frequency, 1 kΩ Source Imbalance–15–5013006983-022TEMPERATURE (°C)C M R R (µV /V )10155–5–10–30–101030507090110Figure 22. CMRR vs. Temperature, G = 180706050403020100–10–201k10k100k 1M 10M 100MFREQUENCY (Hz)G A I N (d B )006983-023Figure 23. Gain vs. Frequency40302010–10–300–20–40–10–8–6–4–2024681006983-024N O N L I N E A R I T Y (10p p m /D I V )OUTPUT VOLTAGE (V)Figure 24. Gain Nonlinearity, G = 1, R L = 10 kΩ, 2 kΩ, 600 Ω 40302010–10–300–20–40–10–8–6–4–2024681006983-025N O N L I N E A R I T Y (10p p m /D I V )OUTPUT VOLTAGE (V)Figure 25. Gain Nonlinearity, G = 10, R L = 10 kΩ, 2 kΩ, 600 Ω 80604020–20–600–40–80–10–8–6–4–2024681006983-026N O N L I N E A R I T Y (10p p m /D I V )OUTPUT VOLTAGE (V)Figure 26. Gain Nonlinearity, G = 100, R L = 10 kΩ, 2 kΩ, 600 Ω400300200100–100–3000–200–400–10–8–6–4–2024681006983-027N O N L I N E A R I T Y (10 p p m /D I V )OUTPUT VOLTAGE (V)Figure 27. Gain Nonlinearity, G = 1000, R L = 10 kΩ, 2 kΩ, 600 Ω16–1606983-028OUTPUT VOLTAGE (V)I N P U T C O M M O N -M O D E V O L T A G E (V )1284–4–8–12–12–8–44812Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 116–16–161606983-029OUTPUT VOLTAGE (V)I N P U T C O M M O N -M O D E V O L T A G E (V )1284–4–8–12–12–8–44812Figure 29. Input Common-Mode Voltage Range vs. Output Voltage, G = 1000+V S –V S4106983-030SUPPLY VOLTAGE (±V S )I N P U T V O L T A G E (V )R E F E R R E D T O S U P P L Y V O L T A G E S6–1–2+2+168101214Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, V REF = 0 V, R L = 10 kΩ–1––100m–10–1–100µ–10µ10DIFFERENTIAL INPUT VOLTAGE (V)C U R R E N T (m A )06983-0311001101001Figure 31. Fault Current Draw vs. Input Voltage, G = 1000, R L = 10 kΩ +V S –V S4106983-032SUPPLY VOLTAGE (±V S )OU T P U T V O L T A G E S W I N G (V )R E F E R R E D T O S U P P L Y V O L T A G E S668101214–0.2–0.4–0.6–0.8–1.0–1.2+1.0+1.2+0.8+0.6+0.4+0.2Figure 32. Output Voltage Swing vs. Supply Voltage, G = 1000, R L = 2 kΩ +V S –V S4106983-033SUPPLY VOLTAGE (±V S )O U T P U T V O L T A G E S W I N G (V )R E F E R R E D T O S U P P L Y V O L T A G E S668101214–0.2–0.4–0.6–0.8–1.0+1.0+0.8+0.6+0.4+0.2Figure 33. Output Voltage Swing vs. Supply Voltage, G =1000, R L = 10 kΩ15–1510010k06983-034LOAD RESISTANCE (Ω)1k105–5–10O U T P U T V O L T A G E S W I N G (V )Figure 34. Output Voltage Swing vs. Load Resistance+V S –V S4106983-035OUTPUT CURRENT (mA)668101214–0.4–0.8–1.2–1.6–2.0+2.0+1.6+1.2+0.8+0.4O U T P U T V O L T A G E S W I N G (V )R E F E R R E D T O S U P P L Y V O L T A G E SFigure 35. Output Voltage Swing vs. Output Current06983-036Figure 36. Small-Signal Pulse Response for Various Capacitive Loads, G = 1069TIME (µs)Figure 37. Large-Signal Pulse Response and Settling Time, G = 1, R L= 10 kΩ06983-038TIME (µs)Figure 38. Large-Signal Pulse Response and Settling Time,G = 10, R L= 10 kΩ06983-039TIME (µs)Figure 39. Large-Signal Pulse Response and Settling Time,G = 100, R L= 10 kΩ06983-040TIME (µs)Figure 40. Large-Signal Pulse Response and Settling Time,G = 1000, R L= 10 kΩ06983-041Figure 41. Small-Signal Response,G = 1, R L = 2 kΩ, C L = 10006983-042Figure 42. Small-Signal Response, G = 10, R L = 2 kΩ, C L = 100 pF06983-043Figure 43. Small-Signal Response, G = 100, R L = 2 kΩ, C L = 100 pF06983-044Figure 44. Small-Signal Response, G = 1000, R L = 2 kΩ, C L = 100 pF 06983-045120014000STEP SIZE (V)T I M E (n s )10008006004002004681012141618Figure 45. Settling Time vs. Step Size, G = 1, R L = 10 kΩ06983-04612001400STEP SIZE (V)T I M E (n s )10008006004002004681012141618Figure 46. Settling Time vs. Step Size, G = 10, R L = 10 kΩ06983-04722STEP SIZE (V)T I M E (n s )10008006001800160014004002004681012141618Figure 47. Settling Time vs. Step Size, G = 100, R L = 10 kΩ06983-048STEP SIZE (V)T I M E (µs )1086181614424681012141618Figure 48. Settling Time vs. Step Size, G = 1000, R L = 10 kΩ0–10–20–30–40–50–60–70–80–90–120–110–100101M06983-049FREQUENCY (Hz)T H D + N (d B )1001k 10k 100k Figure 49. Total Harmonic Distortion vs. Frequency,10 Hz to 22 kHz Band-Pass Filter, 2 kΩ Load0–10–20–30–40–50–60–70–80–90–120–110–100101M06983-050FREQUENCY (Hz)T H D + N (d B )1001k 10k 100k Figure 50. Total Harmonic Distortion vs. Frequency, 10 Hz to 500 kHz Band-Pass Filter, 2 kΩ LoadTHEORY OF OPERATIONREFOUTSS 06983-061Figure 51. Simplified SchematicTransparent Gain ModeThe AD8253 is a monolithic instrumentation amplifier based on the classic 3-op-amp topology, as shown in Figure 51. It is fabricated on the Analog Devices, Inc., proprietary i CMOS® process that provides precision linear performance and a robust digital interface. A parallel interface allows users to digitally program gains of 1, 10, 100, and 1000. Gain control is achieved by switching resistors in an internal precision resistor array (as shown in Figure 51).The easiest way to set the gain is to program it directly via a logic high or logic low voltage applied to A0 and A1. Figure 52 shows an example of this gain setting method, referred to through-out the data sheet as transparent gain mode. Tie WR to the negative supply to engage transparent gain mode. In this mode, any change in voltage applied to A0 and A1 from logic low to logic high, or vice versa, immediately results in a gain change. is the truth table for transparent gain mode, and shows the AD8253 configured in transparent gain mode.Table 5Figure 52All internal amplifiers employ distortion cancellation circuitry and achieve high linearity and ultralow THD. Laser-trimmed resistors allow for a maximum gain error of less than 0.03% for G = 1 and a minimum CMRR of 100 dB for G = 1000. A pinout optimized for high CMRR over frequency enables the AD8253 to offer a guaranteed minimum CMRR over frequency of 80 dB at 20 kHz (G = 1). The balanced input reduces the parasitics that in the past had adversely affected CMRR performance.NOTE:1. IN TRANSPARENT GAIN MODE, WR IS TIED TO −V S .THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE SET TO LOGIC HIGH, RESULTING IN A GAIN OF 1000.06983-051GAIN SELECTIONThis section describes how to configure the AD8253 for basic operation. Logic low and logic high voltage limits are listed in the Specifications section. Typically, logic low is 0 V and logic high is 5 V; both voltages are measured with respect to DGND. Refer to the specifications table (Table 2) for the permissible voltage range of DGND. The gain of the AD8253 can be set using two methods: transparent gain mode and latched gain mode. Regardless of the mode, pull-up or pull-down resistors should be used to provide a well-defined voltage at the A0 and A1 pins.Figure 52. Transparent Gain Mode, A0 and A1 = High, G = 1000Latched Gain ModeSome applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation amplifiers on the same PCB. In such cases, devices can share a data bus. The gain of the AD8253 can be set using WR as a latch, allowing other devices to share A0 and A1. shows a schematic using this method, known as latched gain mode. The AD8253 is in this mode when Figure 53WR is held at logic high or logic low, typically 5 V and 0 V , respectively. The voltages on A0 and A1 are read on the downward edge of the WR signal as it transitions from logic high to logic low. This latches in the logic levels on A0 and A1, resulting in a gain change. See the truth table listing in for more on these gain changes.Table 6NOTE:FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0AND A1 ARE READ AND LATCHED IN, RESULTING IN AGAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 1000.06983-052Figure 53. Latched Gain Mode, G = 10001X = don’t care.On power-up, the AD8253 defaults to a gain of 1 when inlatched gain mode. In contrast, if the AD8253 is configured in transparent gain mode, it starts at the gain indicated by the voltage levels on A0 and A1 on power-up.Timing for Latched Gain ModeIn latched gain mode, logic levels at A0 and A1 must be held for a minimum setup time, t SU , before the downward edge of WR latches in the gain. Similarly, they must be held for a minimum hold time, t HD , after the downward edge of WR to ensure that the gain is latched in correctly. After t HD , A0 and A1 may change logic levels, but the gain does not change until the next downward edge of WR . The minimum duration that WR can be held high is t -HIGH , and t -LOW is the minimum duration that WR can be held low. Digital timing specifications are listed in The time required for a gain change is dominated by the settling time of the amplifier. A timing diagram is shown in . Table 2.Figure 54When sharing a data bus with other devices, logic levels applied to those devices can potentially feed through to the output of the AD8253. Feedthrough can be minimized by decreasing the edge rate of the logic signals. Furthermore, careful layout of the PCB also reduces coupling between the digital and analog portions of the board.A0, A106983-053Figure 54. Timing Diagram for Latched Gain ModePOWER SUPPLY REGULATION AND BYPASSINGThe AD8253 has high PSRR. However, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect per-formance. As in all linear circuits, bypass capacitors must be used to decouple the amplifier.Place a 0.1 μF capacitor close to each supply pin. A 10 μF tantalum capacitor can be used farther away from the part (see Figure 55) and, in most cases, it can be shared by other precision integrated circuits.06983-054Figure 55. Supply Decoupling, REF, and Output Referred to GroundINPUT BIAS CURRENT RETURN PATHThe AD8253 input bias current must have a return path to its local analog ground. When the source, such as a thermocouple, cannot provide a return current path, one should be created (see Figure 56).THERMOCOUPLE+V –V SCAPACITIVELY COUPLED +V SREFCC–V SAD8253TRANSFORMER+V SREF–V SAD8253INCORRECTCAPACITIVELY COUPLEDf HIGH-PASS THERMOCOUPLE+V TRANSFORMER–V SCORRECT06983-055Figure 56. Creating an I BIAS PathINPUT PROTECTIONAll terminals of the AD8253 are protected against ESD. An external resistor should be used in series with each of the inputs to limit current for voltages greater than 0.5 V beyond either supply rail. In such a case, the AD8253 safely handles a continuous 6 mA current at room temperature. For applications where the AD8253 encounters extreme overload voltages, external series resistors and low leakage diode clamps such as BAV199Ls, FJH1100s, or SP720s should be used.REFERENCE TERMINALThe reference terminal, REF, is at one end of a 10 kΩ resistor (see Figure 51). The instrumentation amplifier output is referenced to the voltage on the REF terminal; this is useful when the output signal needs to be offset to voltages other than its local analog ground. For example, a voltage source can be tied to the REF pin to level shift the output so that the AD8253 can interface with a single-supply ADC. The allowable reference voltage range is a function of the gain, common-mode input, and supply voltages. The REF pin should not exceed either +V S or −V S by more than 0.5 V .For best performance, especially in cases where the output is not measured with respect to the REF terminal, source imped-ance to the REF terminal should be kept low because parasiticresistance can adversely affect CMRR and gain accuracy.INCORRECTCORRECT06983-056Figure 57. Driving the Reference PinCOMMON-MODE INPUT VOLTAGE RANGEThe 3-op-amp architecture of the AD8253 applies gain and then removes the common-mode voltage. Therefore, internal nodes in the AD8253 experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure 28 and Figure 29 show the allowable common-mode input voltage ranges for various output voltages, supply voltages, and gains.LAYOUTGroundingIn mixed-signal circuits, low level analog signals need to be isolated from the noisy digital environment. Designing with the AD8253 is no exception. Its supply voltages are referenced to an analog ground. Its digital circuit is referenced to a digital ground. Although it is convenient to tie both grounds to a single ground plane, the current traveling through the ground wires and PC board can cause an error. Therefore, use separate analog and digital ground planes. Only at one point, star ground, should analog and digital ground meet.The output voltage of the AD8253 develops with respect to the potential on the reference terminal. Take care to tie REF to the appropriate local analog ground or to connect it to a voltage that is referenced to the local analog ground.Coupling NoiseTo prevent coupling noise onto the AD8253, follow these guidelines: • Do not run digital lines under the device.• Run the analog ground plane under the AD8253.•Shield fast-switching signals with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths.• Avoid crossover of digital and analog signals.• Connect digital and analog ground at one point only (typically under the ADC).•Power supply lines should use large traces to ensure a low impedance path. Decoupling is necessary; follow the guidelines listed in the Power Supply Regulation and Bypassing section.Common-Mode RejectionThe AD8253 has high CMRR over frequency, giving it greater immunity to disturbances, such as line noise and its associated harmonics, in contrast to typical in amps whose CMRR falls off around 200 Hz. They often need common-mode filters at the inputs to compensate for this shortcoming. The AD8253 is able to reject CMRR over a greater frequency range, reducing the need for input common-mode filtering.Careful board layout maximizes system performance. T o maintain high CMRR over frequency, lay out the input traces symmetrically. Ensure that the traces maintain resistive and capacitive balance; this holds for additional PCB metal layers under the input pins and traces. Source resistance and capacitance should be placed as close to the inputs as possible. Should a trace cross the inputs (from another layer), it should be routed perpendicular to the input traces.RF INTERFERENCERF rectification is often a problem when amplifiers are used in applications where there are strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 58. The filter limits the input signal bandwidth according to the following relationship:)C C (R 1FilterFreq C D DIFF +=2π2CCM RC 1FilterFreq π2=where C D ≥ 10 C C .。
ADP150_cn中文PDF
移动电话 数码相机和音频设备 便携式和电池供电设备 后置DC-DC调节 便携式医疗设备 RF、PLL、VCO和时钟电源
概述
ADP150是一款超低噪声(9 μV)、低压差线性调节器，采用 2.2 V至5.5 V电源供电，最大输出电流为150 mA。驱动150 mA 负载时压差仅为105 mV，这种低压差特性不仅可提高效率， 而且能使器件在很宽的输入电压范围内工作。
特性
超低噪声：9 μV rms，与VOUT无关 无需额外噪声旁路电容 1 μF陶瓷输入和输出电容下稳定工作 最大输出电流：150 mA 输入电压范围：2.2 V至5.5 V 低静态电流
IGND = 10 μA(空载) 低关断电流：< 1 μA 低压差：105 mV(150 mA负载) 初始输出电压精度：±1% 多达14种固定输出电压选项：1.8 V至3.3 V PSRR性能：70 dB (10 kHz) 限流和热过载保护 逻辑控制使能 5引脚TSOT封装 4引脚0.8 mm × 0.8 mm、0.4 mm间距WLCSP封装
VOUT = 1.8V
A
COUT
1µF
EN
GND B
图2. 4引脚WLCSP封装，固定输出电压1.8 V
08343-002
实现了超低噪声与低静态功耗的最佳组合，使便式应用 的电池使用时间可达到最长。
ADP150经过专门设计，在1 μF ± 30%小陶瓷输入和输出电 容便可稳定工作，适合高性能、空间受限应用的要求。它 可提供1.8 V至3.3 V范围内的14种固定输出电压选项。
ON
OFF
1 VIN VOUT 5 2 GND
VOUT = 1.8V
COUT 1µF
3 EN
NC 4
uPD71055GB-10中文资料
Document No. A18501EJ3V0DS00 (3rd edition)Date Published March 2008 NS Printed in Japan © NEC Electronics Corporation 2007Disclaimer• This product is not functionally equivalent to any similar non-NEC Electronics product. NEC Electronics shall assume no responsibility for any loss or damage incurred by customers or third parties resulting from the replacement of products similarto, but other than, the μPD71055GB-10-3B4.• NEC Electronics shall assume no responsibility for any loss or damage incurred by customers or third parties resulting from the use of this product outside the conditions described in the absolute maximum ratings, recommended operation range, andquality grades.COMPARISON OF μPD65881GB-P03 AND μPD71055Feature ThisProduct μPD71055 ReferencePart number (mark) μPD65881GB-P03-3BS-A(658N55) μPD71055GB-10-3B4(standard NEC Electronics mark)−Package type Only 44-pin QFP QFP, DIP, QFJ −Package shape (comparison of 44-pin QFP) The body size and package width are the same, but the pin lengthsand pin bending method are different.4. PACKAGEDRAWINGFunction of pin 1 IC (connection with external pinprohibited)NC 1. PIN LAYOUTLead-free support Yes No ORDERINGINFORMATIONRecommended soldering conditions IR60-207-3, partial heating IR35-00-3, VP15-00-3,WS60-00-1, partial heating5. RECOMMENDEDSOLDERING CONDITIONSAbsolute maximum ratingsPower supply voltage −0.5 to +6.0 (V) −0.5 to +7.0 (V) Input voltage −0.5 to +6.0 (V) −0.5 to V DD+0.3 (V) Output voltage −0.5 to +6.0 (V) −0.5 to V DD+0.3 (V)Recommended operating range T A=−40 to +85°C, V DD = 5 V±10%This product does not guarantee operation at less than 4.5 V.DC characteristics Partially differentAC characteristics This product has the following restrictions on load capacitance.D7 to D0: 150 pF or lessP07 to P00, P17 to P10, P27 to P20: 40 pF or less 2. ELECTRICAL SPECIFICATIONSORDERING INFORMATIONPartNumber PackageμPD65881GB-P03-3BS-A 44-pin plastic QFP (10 x 10 mm)Remark Products with -A at the end of the part number are lead-free products.QUALITY GRADES"Standard"This product is intended to be used for applications such as computers, office equipment, communications equipment, test and measurement equipment, and home electronic appliances. It therefore cannot be used for the following applications.Applications requiring special or specific grades, such as transportation equipment (automobiles, trains, ships, etc.), traffic control systems, medical equipment, aircraft equipment, and aerospace equipment.Remark For details of quality grades, refer to Quality Grades on NEC Semiconductor Devices (document number: C11531E).Data Sheet A18501EJ3V0DS2Data Sheet A18501EJ3V0DS3BLOCK DIAGRAM (μPD71055)D 7 -D 07 -D 017 -P 1027 -P 24 (P 23)23 (P 22) -P 20CSRESETA1A0RD WR1. PIN LAYOUTFor a description of pin functions, refer to the μPD71055 Data Sheet (document number: IC-1921).Note This pin is connected to GND or V DD in the chip. To enhance the power supply to handle noise, this pin can be connected to the power supply pin of the board to improve the noise resistance performance.4Data Sheet A18501EJ3V0DS2. ELECTRICAL SPECIFICATIONSThis section describes only the differences with the μPD71055.For electrical specifications other than those below, refer to the μPD71055 Data Sheet (document number: IC-1921).Absolute Maximum RatingsParameter Symbol Conditions Ratings Unit Power supply voltage V DD−0.5 to +6.0 V Input voltage V I−0.5 to +6.0 V Output voltage V O−0.5 to +6.0 V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. In other words, the absolute maximum ratings are values at which the product maybegin to suffer degradation. Therefore the product must be used under conditions that ensure thatthe absolute maximum ratings are not exceeded.Recommended Operating RangeThis is the same as the μPD71055. This product does not guarantee operation at less than 4.5 V.DC Characteristics (V DD = 5 V±10%, T A = −40 to +85°C)This Product μPD71055Parameter SymbolCondition Min. Typ. Max. Condition Min. Typ. Max.UnitInput voltage, high V IH 2.29 V DD 2.2 V DD+0.3 VInput voltage, low V IL 0.00 0.77 −0.5 0.8 VI OH =0 mA V DD−0.1Output voltage, high V OHI OH =3.0 mA V DD−0.4I OH =−400 μA0.7×V DD VOutput voltage, low V OL I OL =3 mA 0.4I OL =2.5 mA0.4VOutput current, low I OL 3.0 2.5 mAAC CharacteristicsThese are similar to the μPD71055 characteristics, except for the following restrictions on load capacitance. Operation outside the range of these restrictions is not guaranteed.D7 to D0: 150 pF or lessP07 to P00, P17 to P10, P27 to P20: 40 pF or lessData Sheet A18501EJ3V0DS 53. CAUTIONS WHEN CONSIDERING ADOPTION OF THIS PRODUCTWhen considering the adoption of this product, note the following points.(1) Functional check using product samplesBefore adopting this product, make sure to request product samples from NEC Electronics to check the functions. Product samples are available free of charge.When mounting this product onto different multiple printed circuit boards, extensively check the functions by changing the supply voltage to be supplied to the printed circuit boards as well as the temperature conditions for all printed circuit boards.The standard number of product samples is five. When requesting product samples, provide the following information to your NEC Electronics sales representative.Your company name, your name, product application, the period of starting adoption, the number of products to be adopted(2) Submitting the Approval SheetWhen normal operation has been confirmed and the adoption has been decided, complete a copy of the Approval Sheet (Appendix of this document) and submit it to NEC Electronics.(3) Shipment inspectionShipment inspection is performed for this product using the μPD71055GB-10-3B4 shipment test pattern. The DC characteristics satisfy the gate array shipment inspection.(4) Order amountOrders from a minimum of 100 units, and in units of 100 are accepted.(5) Package, packing formThe dimensions are partially different from the μPD71055GB-10-3B4. Refer to the package drawing and confirm that the product can actually be mounted. Dry pack tray packing is used for packing.(6) PriceContact your local NEC Electronics sales representative for pricing information.(7) Obtaining the μPD71055 Data Sheet NoteThe μPD71055 (original product) Data Sheet is available from the NEC Electronics Web site(/) at/nesdis/image/IC-1921B.pdfNote Please make this data sheet a standalone document. Do not refer customers to the data sheet for an obsolete device.6Data Sheet A18501EJ3V0DSData Sheet A18501EJ3V0DS74. PACKAGE DRAWING44-PIN PLASTIC QFP (10x10)ITEM MILLIMETERS A B D G 13.2±0.210.0±0.20.8 (T.P.)1.0J 13.2±0.2K S44GB-80-3BS-2C 10.0±0.2I 0.161.6±0.2L 0.8±0.2F 1.0N P Q S0.102.7±0.10.125±0.0753.0 MAX.M 0.17+0.06−0.05H 0.37+0.08−0.07R 3°+7°−3°NOTEEach lead centerline is located within 0.16 mm ofits true position (T.P.) at maximum material condition.detail of lead end5. RECOMMENDED SOLDERING CONDITIONSThese products should be soldered and mounted under the following recommended conditions.For soldering methods and conditions other than those recommended below, please contact an NEC Electronicssales representative.For technical information, see the following website.Semiconductor Device Mount Manual (/pkg/en/mount/index.html)Soldering MethodSoldering ConditonsRecommended Condition SymbolInfrared reflowPackage peak temperature: 260°CTime: 60 seconds max. (at 220°C or higher)Count: 3 times or lessExposure limit: 7 days Note(after that, prebake at 125°C for 20 to 72 hours)IR60-207-3Partial heatingPin temperature: 350°C max. Time: 3 seconds max. (per pin row)−Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.Caution Do not use different soldering methods together (except for partial heating).APPENDIX APPROVAL SHEETCopy this page and complete and confirm the required items.If you accept the conditions, sign and submit this sheet to NEC Electronics.8Data Sheet A18501EJ3V0DSData Sheet A18501EJ3V0DS 9The information in this document is current as of March, 2008. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features.NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific".The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application.The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application.(Note)••••••M8E 02. 11-1(1)(2)"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes itsmajority-owned subsidiaries."NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (asdefined above).Computers, office equipment, communications equipment, test and measurement equipment, audioand visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots.Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disastersystems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support).Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, lifesupport systems and medical equipment for life support, etc."Standard":"Special":"Specific":。
at89c1051中文资料
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AQZ105D;AQZ107D;AQZ207D;AQZ204D;AQZ202D;中文规格书,Datasheet资料
TYPES1. DC type* Load voltage and current of DC type: DC2. AC/DC type* Load voltage and current of AC/DC type: Peak AC/DCOutput rating*PackagePart No.Packing quantityLoad voltage Load currentInner cartonOuter cartonDC only 60 V 3.6 A SIL4-pin AQZ102D25 pcs.500 pcs.100 V2.3 A AQZ105D 200 V 1.1 A AQZ107D 400 V 0.6 AAQZ104DOutput rating*PackagePart No.Packing quantityLoad voltage Load currentInner cartonOuter cartonAC/DCdual use60 V 2.7 A SIL4-pin AQZ202D 25 pcs.500 pcs.100 V 1.8 A AQZ205D 200 V 0.9 A AQZ207D 400 V0.45 AAQZ204Dmm inchRoHS compliantFEATURES1. A voltage-sensitive power PhotoMOSConventional power PhotoMOS are connected externally to an input limiting resistor in order to obtain the appropriate LED current. Adding an internal constant-current element renders the input limiting resistor unnecessary, making it possible for the PhotoMOS to be voltage-driven.2. Wide range of input voltagesAllows a wide range of input voltages from 4 to 30 V DC. The PhotoMOS can be used in 5 V , 12 V or 24 V DC systems.3. Both AC/DC dual types and DC-only types availableThe AC/DC dual type is capable of bi-directional control, and unlikeconventional SSRs, does not have to be used differently depending on the load. The DC-only type is well suited for control of DC solenoids and DC motors.4. High capacitySupports the various types of loadcontrol, from very small loads to a max. 2.7 A for the AC/DC dual type, max. 3.6 A for the DC-only type.5. High sensitivity and low on-resistanceMax. 3.6 A load can be controlled with the min. input voltage of 4 V DC. The on-resistance is also low at typ. 0.033 Ω (AQZ102D).6. Slim SIL4-pin package(W) 3.5 × (D) 21.0 × (H) 12.5 mm (W) .138 × (D) .827 × (H) .492 inch The compact size of the 4-pin SIL package allows high density mounting.Height includes standoff1 Form A Voltage-sensitive (AQZ10❍D, 20❍D)RATING1. DC type1) Absolute maximum ratings (Ambient temperature: 25°C 77°F )2) Electrical characteristics (Ambient temperature: 25°C 77°F )2. AC/DC type1) Absolute maximum ratings (Ambient temperature: 25°C 77°F )ItemSymbol AQZ102DAQZ105DAQZ107DAQZ104DRemarksInput Input voltageV IN 30 V Input reverse voltageV RIN 5 V Power dissipation P in 300 mWOutputLoad voltage (DC)V L 60 V 100 V 200 V 400 V Continuous load current (DC)I L 3.6 A 2.3 A 1.1 A 0.6 A Peak load current I peak 9.0 A6.0 A3.0 A1.5 A100 ms (1 shot), V L = DCPower dissipationP out 1.35 W T otal power dissipation P T 1.35 W I/O isolation voltage V iso2,500 V ACT emperature limitsOperating T opr –40°C to +85°C –40°F to +185°F (4 V q V IN q 6 V)–40°C to +75°C –40°F to +167°F (6 V < V IN q 15 V)–40°C to +60°C –40°F to +140°F (15 V < V IN q 30 V)Non-condensing at low temperaturesStorageT stg–40°C to +100°C –40°F to +212°FItemSymbol AQZ102DAQZ105DAQZ107DAQZ104DRemarksInputOperate voltageT ypical V Fon 1.4 V I L = 100 mA V L = 10 V Maximum 4 V T urn off voltage Minimum V Foff 0.8 V I L = 100 mA V L = 10 V T ypical 1.3 V Input current T ypical I IN 6.5 mAV IN = 5 V OutputOn resistanceT ypical R on 0.033 Ω0.090 Ω0.33 Ω 1.23 ΩV IN = 5 V I L = Max.Within 1 s on time Maximum 0.09 Ω0.17 Ω0.55 Ω1.6 ΩOff state leakage current Maximum I Leak 10 µAV IN = 0 V V L = Max.T ransfercharacteristicsT urn on time*T ypical T on3.3 ms2.2 ms1.5 ms1.2 msV IN = 5 V I L = 100 mA V L = 10 V Maximum 10.0 msT urn off time*T ypical T off 0.2 ms0.1 msV IN = 5 V I L = 100 mA V L = 10 V Maximum 3.0 ms I/O capacitanceT ypical C iso 0.8 pF f = 1 MHz V B = 0 VMaximum 1.5 pF Initial I/O isolation resistance Minimum R iso 1,000 M Ω500 V DC Maximum operating speedMaximum —0.5 cpsV IN = 5 VDuty factor = 50%I L ×V L = 200 (VA)Vibration resistance Minimum —10 to 55 Hz at double amplitude of 3 mm2 hours for3 axes Shock resistanceMinimum—4,900 m/s 2 {500 G}1 ms3 times for 3 axesItemSymbol AQZ202DAQZ205DAQZ207DAQZ204DRemarksInputInput voltageV IN 30 V Input reverse voltage V RIN 5 V Power dissipationP in 300 mWOutputLoad voltage (peak AC)V L 60 V 100 V 200 V 400 V Continuous load currentI L 2.7 A 1.8 A 0.9 A 0.45 A Peak AC, DCPeak load current I peak 9.0 A6.0 A3.0 A1.5 A100 ms (1 shot), V L = DCPower dissipationP out 1.6 W T otal power dissipation P T 1.6 W I/O isolation voltage V iso 2,500 V ACT emperature limitsOperating T opr –40°C to +85°C –40°F to +185°F (4 V q V IN q 6 V)–40°C to +75°C –40°F to +167°F (6 V < V IN q 15 V)–40°C to +60°C –40°F to +140°F (15 V < V IN q 30 V)Non-condensing at low temperaturesStorageT stg–40°C to +100°C –40°F to +212°F1 Form A Voltage-sensitive (AQZ10❍D, 20❍D)■ For Dimensions.■ For Schematic and Wiring Diagrams.■ For Cautions for Use.■ These products are not designed for automotive use.If you are considering to use these products for automotive applications, please contact your local Panasonic Corporation technical representative.For more information.REFERENCE DATA1. Load current vs. ambient temperature characteristicsAllowable ambient temperature:–40°C to +85°C–40°F to +185°F;V IN : Input voltage; I L (derate):Load current (derate); I L : Absolute maximum ratings of continuous load current2.-(1) Load current vs. ambient temperaturecharacteristics in adjacent mountingInput voltage: 4V q V IN q 6V;I L (derate): Load current (derate); I L : Absolute maximum ratings of continuous load current; : Adjacent mounting pitch2.-(2) Load current vs. ambient temperature characteristics in adjacent mountingInput voltage: 6V < V IN q 15V;I L (derate): Load current (derate); I L : Absolute maximum ratings of continuous load current; : Adjacent mounting pitchAmbient temperature, °CAmbient temperature, °CI L (d e r a t e ) × 100, %I LAmbient temperature, °CI L (d e r a t e ) × 100, %I L1 Form A Voltage-sensitive (AQZ10❍D, 20❍D)2.-(3) Load current vs. ambient temperature characteristics in adjacent mountingInput voltage: 15V<V IN q 30V;I L (derate): Load current (derate); I L : Absolute maximum ratings of continuous load current; : Adjacent mounting pitch3.-(1) On resistance vs. ambient temperature characteristics (DC type)Input voltage: 5 V;Continuous load current:3.6 A (DC) (AQZ102D)2.3 A (DC) (AQZ105D)3.-(2) On resistance vs. ambient temperature characteristics (DC type)Input voltage: 5 V;Continuous load current:1.1 A (DC) (AQZ107D)0.6 A (DC) (AQZ104D)Ambient temperature, °CI L (d e r a t e ) × 100, %I LAmbient temperature, °CO n r e s i s t a n c e , ΩAmbient temperature, °CO n r e s i s t a n c e ,Ω3.-(3) On resistance vs. ambient temperature characteristics (AC/DC type)Input voltage: 5 V;Continuous load current:2.7 A (DC) (AQZ202D)1.8 A (DC) (AQZ205D)3.-(4) On resistance vs. ambient temperature characteristics (AC/DC type)Input voltage: 5 V;Continuous load current:0.9 A (DC) (AQZ207D)0.45 A (DC) (AQZ204D)4.-(1) T urn on time vs. ambient temperature characteristics (DC type)Input voltage: 5 V; Load voltage: 10 V (DC);Continuous load current: 100 mA (DC)Ambient temperature, °CO n r e s i s t a n c e , ΩO n r e s is t a n c e , ΩAmbient temperature, °C461028Ambient temperature, °CT u r n o n t i m e , m s4.-(2) T urn on time vs. ambient temperature characteristics (AC/DC type)Input voltage: 5 V;Load voltage: 10 V (DC);Continuous load current: 100 mA (DC)5.-(1) T urn off time vs. ambient temperature characteristics (DC type)Input voltage: 5 V; Load voltage: 10 V (DC);Continuous load current: 100 mA (DC)5.-(2) T urn off time vs. ambient temperature characteristics (AC/DC type)Input voltage: 5 V; Load voltage: 10 V (DC);Continuous load current: 100 mA (DC)Ambient temperature, °CTu r n o n t i m e , m sAmbient temperature, °CT u rn o f f t i m e , m sAmbient temperature, °CT u r n o f f t i m e , m s6. Operate voltage vs. ambient temperature characteristicsLoad voltage: 10 V (DC);Continuous load current: 100 mA (DC)7. T urn off voltage vs. ambient temperature characteristicsLoad voltage: 10 V (DC);Continuous load current: 100 mA (DC)8. Input current vs. ambient temperature characteristicsInput voltage: 5 V2.03.0–405.00–20204060801.04.085Ambient temperature, °CO p e r a t e v o l t a g e , V02.03.0–405.00–20204060801.04.085Ambient temperature, °CT u r n o f f v o l t a g e , m s46–40100–20204060802885Ambient temperature, °CI n p u t c u r r e n t , m A1 Form A Voltage-sensitive (AQZ10❍D, 20❍D)ACCESSORY (mm inch )9.-(1) Current vs. voltage characteristics of output at MOS portion (DC type)Ambient temperature: 25°C 77°F9.-(2) Current vs. voltage characteristics of output at MOS portion (AC/DC type)Ambient temperature: 25°C 77°F10. Input current vs. input voltage characteristicsAmbient temperature: 25°C 77°F461005101520282530Input voltage, VI n p u t c u r r e n t , m A11.-(1) Off state leakage current vs. load voltage characteristicsAmbient temperature: 25°C 77°F11.-(2) Off state leakage current vs. load voltage characteristicsAmbient temperature: 25°C 77°F12. Maximum operating speed vs. load voltage × load current characteristicsInput voltage: 5V; Ambient temperature: 25°C 77°F10–310–610–910Load voltage, VO f f s t a t e l e a k a g e c u r r e n t , A10–310–610–910Load voltage, VO f f s t a t e l e a k ag e c u r r e n t , AMaximum voltage, V ×Load current, AM a x i m u m o p e r a t i n g s p e e d , c p s13.-(1) Output capacitance vs. applied voltage characteristics (DC type)Frequency: 1 MHz; Ambient temperature: 25°C 77°F13.-(2) Output capacitance vs. applied voltage characteristics (AC/DC type)Frequency: 1 MHz; Ambient temperature: 25°C 77°FApplied voltage, VO u t p u t c a p a c i t a n ce , p FApplied voltage, VO u t p u t c a p a c i t a n c e , p F SocketPA1a-PSPA1a-PS-HPC board pattern (BOTTOM VIEW)Standard typeSelf clinching typeT olerance: ±0.1 ±.004分销商库存信息:PANASONICAQZ105D AQZ107D AQZ207D AQZ204D AQZ202D AQZ205D。
MEMORY存储芯片ADM3485EARZ-REEL7中文规格书
Logic Inputs Input Low Voltage Input High Voltage Logic Input Current
ADM3485E
RO
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03338-001
Figure 1.
should be enabled at any time, the output of a disabled or powered-down driver is tristated to avoid overloading the bus. The receiver has a fail-safe feature that ensures a logic high output when the inputs are floating. Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit. The part is fully specified over the industrial temperature range and is available in an 8-lead narrow SOIC package.
ADM3485E
SPECIFICATIONS
19245;中文规格书,Datasheet资料
Made in theUnited States of AmericaDescriptionDesco’s Low Resistance Tester is designed to measures resistance of grounding paths of banana jacks and other equipment. Selectable Test Ranges: <1 OHM, <2 OHMs, and <20 OHMs allow the operator to test grounding Figure 1. Desco 19245 Low Resistance TesterANSI/ESD S6.1 – GroundingThe resistance of the conductor from the groundable point ground of any ESD technical element (e.g. worksurface, floor, chair, wrist strap, etc.) to the common point ground or common connection point shall not be greater than 1 ohm. Where a resistor is used in the grounding conductor, the total Figure 2. Low Resistance Tester features and componentsA. Selectable Test Ranges: Select the appropriate range for required test <1 OHM, <2 OHMs, and <20 OHMs.B. Test Button: Press and hold button to activate the tester.BCD EGFE. Low Battery LED: LED illuminates when the battery needs to be replaced.F. 6 Foot Coiled Cord: Insulation black color PVCG. Banana Plug: Industrial Standard .175 “(4.4 mm) Banana Plug, fits banana jack ≥ .157”.OperationUSING THE TESTER 1. Select test range.2. Connect coil cord banana plug end to known ground. Use adaptors where needed. Note: The Desco Low Resistance Tester may be used with an outlet polarity checker, such as Desco’s 19219, to determine a knownground.3. Connect or touch tester end to banana jack or other equipment that is being tested for resistance to ground.4. Press and hold test button.5. An audio and visual indication will activate for Pass result6. No audio or visual indication will indicate a Fail resultFigure 3. Testing banana jacks with 19245 tester.Example of Test Range Uses<1 OHM Range- ESD Technical element Grounding Conductors: Banana Jacks, Grounding Blocks, Mat Ground Cords ANSI/ESD S6.1 Grounding, sections 6.4 Technical Elements, 6.4.1, 6.4.2 and 6.4.3 - New AC Powered Hand ToolsESD Handbook ESD TR20.20 section 5.5.2.2 Electrical Hand Tools<2 OHM- Soldering IronsESD Handbook ESD TR20.20 section 5.5.2.2 Electrical Hand Tools- Other AC Powered Hand ToolsESD Handbook ESD TR20.20 section 5.5.2.2 Electrical Hand Tools<20 OHM- Soldering iron verificationESD Handbook ESD TR20.20 section 5.5.2.2 Electrical Hand Tools- Auxiliary grounds (ground rods) ANSI/ESD S20.20** ANSI/ESD S20.20 requires <25 ohms from the Auxiliary Ground to the Equipment Grounding Conductor. Desco’s Low Resistance Tester only tests to <20 ohms. In cases of a no pass result with the Low Resistance Tester when testing an Auxiliary Ground, an Ohm meter should used to determine the actual resistance from the Auxiliary Ground to the Equipment Grounding ConductorFigure 4. Testing soldering iron with 19245 tester.Figure 6. Testing auxiliary ground with 19245 tester.Remove the 2 screws located at the back of the tester.Remove and turn over the circuit board.4. Locate and replace the battery (3 Volt; Model CR2032).5. Re-assemble the tester.First, place battery under prongsNext, press here to snap battery in place分销商库存信息: DESCO19245。
atc中文手册
当所有64 字节接收完毕主器件发送停止信号内部编程周期开始此时所有接收到的数据在单
个写周期内写入CAT24WC256
应答查询
可以利用内部写周期时禁止数据输入这一特性一旦主器件发送停止位指示主器件操作结束时
CAT24WC256 启动内部写周期应答查询立即启动包括发送一个起始信号和进行写操作的从器件地址
数据的擦写在内部擦写过程中CAT24WC256 不再应答主器件的任何请求
页写
在页写模式下单个写周期内CAT24WC256 最多可以写入64 个字节数据页写操作的启动和字节
写一样不同在于传送了一字节数据后主器件允许继续发送63 个字节每发送一个字节后
CAT24WC256 将响应一个应答位且内部低6 位地址加1 高位地址保持不变如果主器件在发送停止
如果CAT24WC256 正在进行内部写操作将不会发送应答信号如果CAT24WC256 已经完成了内部写
操作将发送一个应答信号主器件可以继续对CAT24WC256 进行下一次读写操作
写保护
写保护操作特性可使用户避免由于不当操作而造成对存储区域内部数据的改写当WP 管脚接高时
整个寄存器区全部被保护起来而变为只可读取CAT24WC256 可以接收从器件地址和字节地址但是装
主器件通过发送一个起始信号启动发送过程然后发送它所要寻址的从器件的地址8 位从器件地
址的高5 位固定为10100 见图5 接下来的2 位A1 A0 为器件的地址位最多可以连接4 个器件
到同一总线上这些位必须与硬连线输入脚A1 A0 相对应从器件地址的最低位作为读写控制位1
表示对从器件进行读操作0 表示对从器件进行写操作在主器件发送起始信号和从器件地址字节后
ORH-YG35A（IF=20mA） 2.0x1.25x0.8mm（0805）标准包装的阿尔加韦伯
PLCC LED Series DatasheetORH-YG35A(IF=20mA)1.Features:⏹Chip material:AlGaInP/GaAs.⏹Emitted Color:Super Yellow Green.⏹Lens Appearance:Water Clear.⏹Mono-color type.⏹ 2.0x1.25x0.8mm(0805)standard package.⏹Suitable for all SMT assembly methods.⏹Compatible with infrared and vapor phase reflow solder process.⏹Compatible with automatic placement equipment.⏹This product doesn’t contain restriction substance,comply ROHS standard.2.Applications:⏹Automotive:Dashboards,stop lamps,turn signals.⏹Backlighting:LCDs,Key pads advertising.⏹Status indicators:Comsumer&industrial electronics.⏹General use.ORH-YG35A 3.Package Dimensions:4.Absolute Maximum Ratings(Ta=25℃)Parameter Symbol Rating Unit Power Dissipation Pd120mW Forward Current I F30mA Peak Forward Current＊1I FP100mA Operating Temperature Topr-25℃~80℃-Storage Temperature Tstg-30℃~85℃-Soldering Temperature Tsol260℃-＊1Condition for I FP is pulse of1/10duty and0.1msec width.5.Electrical and optical characteristics(Ta=25℃)Parameter Symbol Condition Min.Typ.Max.Unit Forward Voltage Vf I F=20mA 1.8- 2.4V Luminous Intensity Iv I F=20mA1840-mcd Peak Wave Lengthλp I F=20mA-570-nm Dominant Wave Lengthλd I F=20mA566-578nm Spectral Line Half-widthΔλI F=20mA-30-nm Veiwing Angle2θ1/2I F=20mA-120-degORH -YG35A6.Typical Electro-Optical Characteristics CurvesFig.5 Relative luminous intensity vs. forward currentR e l a t i v e l u m i n o u s i n t e n s i t y (@20m A )0.51.01.52.0F o r w a r d c u r r e n t (m A )20103040Forward voltage(V)Fig.3 Forward current vs. forward voltageFig.1 Relative intensity vs. wavelengthR e l a t i v e r a d i a n t i n t e n s i t y500.5Wavelength (nm)R e l a t i v e L u m i n o u s i n t e n s i t yAmbient temperature Ta( C)A(N o r m a l i z e d @20m A )0.51.002.02.51.5vs. ambient temperatureAmbient temperature Ta( C)F o r w a r d c u r r e n t (m A )3.0103040206050Fig.2 Forward current derating curveFig.4 Relative luminous intensity vs.ambient temperatureForward current (mA)R E L A T I V E R A D I A N T I N T E N S I T YRADIATION DIAGRAM0.90.70.890807060501.0020104030ORH-YG35A 7.Judgment criteria of failure for the reliabilityMeasuring items Symbol Measuring conditions Judgement criteria for failure Forward voltage V F(V)I F=20mA Over Ux1.2Reverse current I R(uA)V R=5V Over Ux2Luminous intensity Iv(mcd)I F=20mA Below SX0.5Note:1).U means the upper limit of specified characteristics.S means initial value.2).Measurment shall be taken between2hours and after the test pieces have been returned tonormal ambient conditions after completion of each test.8.Bin LimitsIntensity Bin Limits(At20mA)BIN CODE Min.(mcd)Max.(mcd)L1828M2842N4263P6394Tolerance for each Bin limit is±15%.Color Bin Limits(At20mA)BIN CODE Min.(v)Max.(v)4566569556957265725757575578Tolerance for each Bin limit is±1nm.ORH -YG35AV F Bin Limits (At 20mA)BIN CODEMin.(v)Max.(v)B 1.8 2.0C 2.0 2.2D2.22.4Tolerance for each Bin limit is ±0.05V.9.BIN ：x x xV F BI N CO D E Co l o r BI N CO D E In t e n s i t y BI N CO D E10.Tapping and packaging specifications(Units:mm)FIXING TAPE0.3TRAILERLEADER2.26±0.171.0±1±±USER DIRECTION OF FEEDC A T H OD E4.0A N O D E5.3±0.05START1.420.38.0±NOTE: 4000 pcs PER REEL3.52.0±0.054.00.1±0.11.5±0.11.750.1±0.1END±0.05±13.00.5ORH-YG35A 11.Package Method:(unit:mm)12.Package and Label of Products:(1)Package:Products are packed in one bag of3000pcs(one taping reel)and a label is attached oneach bag.(2)Label:ORIENT LOGOPart No.QuantityBINSealing Datex xx xx xxYear Month DayManufacture LocationORH-YG35A 13.Reliability TestClassification Test Item Reference Standard Test Conditions ResultEnduranceTest Operation Life MIL-STD-750:1026MIL-STD-883:1005JIS-C-7021:B-1Connect with a power If=20mATa=Under room temperatureTest time=1,000hrs0/20HighTemperatureHigh HumidityStorageMIL-STD-202:103BJIS-C-7021:B-11Ta=+65℃±5℃RH=90%-95%Test time=240hrs0/20HighTemperatureStorageMIL-STD-883:1008JIS-C-7021:B-10High Ta=+85℃±5℃Test time=1,000hrs0/20LowTemperatureStorageJIS-C-7021:B-12Low Ta=-35℃±5℃Test time=1,000hrs0/20EnvironmentalTest TemperatureCyclingMIL-STD-202:107DMIL-STD-750:1051MIL-STD-883:1010JIS-C-7021:A-4-35℃~+25℃~+85℃~+25℃60min20min60min20minTest Time=5cycle0/20Thermal Shock MIL-STD-202:107DMIL-STD-750:1051MIL-STD-883:1011-35℃±5℃~+85℃±5℃20min20minTest Time=10cycle0/20SolderResistanceMIL-STD-202:201AMIL-STD-750:2031JIS-C-7021:A-1Preheating：140℃-160℃,within2minutes.Operation heating：260℃(Max.),within10seconds.(Max.)0/2014.Soldering:1).Manual Of SolderingThe temperature of the iron tip should not be higher than300℃(572℉)and Soldering within3 seconds per solder-land is to be observed.2).Reflow SolderingPreheating:140℃~160℃±5℃,within2minutes.Operation heating:260℃(Max.)within10seconds.(Max)Gradual Cooling(Avoid quenching).ORH -YG35A3).DIP soldering (Wave Soldering):Preheating :120℃~150℃,within 120~180sec.Operation heating :245℃±5℃within 5sec.260℃(Max)Gradual Cooling (Avoid quenching).15.Handling :Care must be taken not to cause to the epoxy resin portion of ORIENTLEDs while it is exposed to high temperature.Care must be taken not rub the epoxy resin portion of ORIENT LEDs with hard or sharp article such as the sand blast and the metal hook .16.Notes for designing:Care must be taken to provide the current limiting resistor in the circuit so as to drive the ORIENT LEDs within the rated figures.Also,caution should be taken not to overload ORIENT LEDs with instantaneous voltage at the turning ON and OFF of the circuit.When using the pulse drive care must be taken to keep the average current within the rated figures.Also,the circuit should be designed so as be subjected to reverse voltage when turning off the ORIENT LEDs.Temperature TimeOVER 2 MIN.4℃ /SEC. MAX. 4℃ /SEC. MAX.10 SEC. MAX.260℃ MAX.140~160℃TemperatureTime120~180 sec.Preheat 245 ±5℃ within 5 sec.Soldering heat Max. 260 ℃120~150℃ORH-YG35A17.Storage:In order to avoid the absorption of moisture,it is recommended to solder ORIENT LEDs as soon as possible after unpacking the sealed envelope.If the envelope is still packed,to store it in the environment as following:(1)Temperature:5℃-30℃(41℉)Humidity:RH60﹪Max.(2)After this bag is opened,devices that will be applied to infrared reflow,vapor-phase reflow,orequivalent soldering process must be:pleted within24hours.b....Stored at less than30%RH.(3)Devices require baking before mounting,if:(2)a or(2)b is not met.(4)If baking is required,devices must be baked under below conditions:12hours at60℃±3℃.。
ADP090 Electrical Signal Insert Adaptor Technical
ADP090 Electrical Signal Insert Adaptor Technical Reference ManualIADP090.1Technical Reference Manual Larson Davis ADP090 Electrical Signal Insert Adaptor1/2" Microphone EquivalentCopyrightCopyright 2008 by PCB Piezotronics, Inc. This manual is copyrighted, with all rights reserved. The manual may not be copied in whole or in part for any use without prior written consent of PCB Piezotronics, Inc.DisclaimerThe following paragraph does not apply in any state or country where such statements are not agreeable with local law:Even though PCB Piezotronics, Inc. has reviewed its documentation, PCB Piezotronics, Inc. makes no warranty or representation, either expressed or implied, with respect to this instrument and documentation, its quality, performance, merchantability, or fitness for a particular purpose. This documentation is subject to change without notice, and should not be construed as a commitment or representation by PCB Piezotronics, Inc.This publication may contain inaccuracies or typographical errors. PCB Piezotronics, Inc. will periodically update the material for inclusion in new editions. Changes and improvements to the information described in this manual may be made at any time.RecyclingPCB Piezotronics, Inc. is an environmentally friendly organization and encourages our customers to be environmentally conscious. When this product reaches its end of life, please recycle the product through a local recycling center or return the product to:PCB Piezotronics, Inc.Attn: Recycling Coordinator1681 West 820 NorthProvo, Utah, USA 84601-1341where it will be accepted for disposalADP090 Electrical Signal Insert Adaptor 1/2” Microphone EquivalentApplicationThe ADP090 is used in place of a 1/2” microphone for the following:•Electrical signal insert testing of sound level meters and preamplifiers •Noise floor testing of instrumentsDescriptionThe ADP090 contains a 12 pF Capacitor for electrical signal injection from a signal generator into a preamplifier in place of an acoustical signal. It has a female BNC connector on one end for connection to a signal generator and a ½" female microphone thread on the opposite end. This electrical adaptor is used to simulate the electrical characteristics of a microphone with a capacitance near 12 pF. A male BNC with an internal short is included for electrical noise floor testing.Dimensions: 63.5 mm (2.50") long x 12.7 mm (0.5") diameterThread for preamplifier mounting: 11.7 mm-60 UNS (0.4606-60 UNS)Capacitance: 12 pF ±5%Maximum microphone bias: 250 Volts BNC with ShortSignal Insert AdaptorExtra AttenuationThe rugged construction of the ADP090 means the there is a small capacitance at the preamplifier end of the adaptor. This capacitance results from the physical construction of the adaptor and has a value of about 0.3 pF. It will give added attenuation to the signal since it is in parallel (shunt) across the input of the preamplifier.When used with the following PCB microphone preamplifiers, there is an extra attenuation as shown in Table 1.Preamplifier Extra Attenuation (dB)Uncertainty k = 2 (dB) 426A100.210.04426A110.210.04426A120.210.04426A300.210.04426E010.210.04HT426E010.210.04PRM8310.210.04PRM900C0.210.04PRM9020.210.04PRMLxT10.150.04PRMLxT20.050.04Table 1 : ADP090 Extra Attenuation Measured at 1 kHzApplication ExampleExample: Using an ADP090, determine the effects of the 426E01 loading on a microphone with capacitance equal to 12 pF.Step 1Connect the ADP090 to a 426E01 preamplifierStep 2Remove the BNC shortStep 3Connect the output of a signal generator to the female BNC of the ADP090 and set it to generate a 1 kHz sine wave having an output of 0.500 Vrms.Step 4Measure the output signal of the 426E01 and note that it has amplitude of 0.482 Vrms.Step 5Compute the difference between the input signal and the measured output signal in dB. dB = 20*log10(VmeasuredOutput/Vinput) = -0.32 for this example. The negative sign indicates attenuation. The total attenuation would be 0.32 dB.Step 6Find the ADP090 extra attenuation from Table 1 : 'ADP090 Extra Attenuation Measured at 1 kHz' for the 426E01 preamplifier, which is 0.21 dB. Step 7426E01 loading is equal to the measured attenuation minus the losses due to the 0.3 pF capacitance in the ADP090. Thus, the loading is 0.32 - 0.21 dB = 0.11 dB.Other MicrophonesFor microphones with other capacitance values, use the PCB adaptors indicated in Table 2.Microphone Capacitance (pF)Appropriate Adaptor6.8ADP00218ADP00547ADP006Table 2 : Alternative AdaptorsT otal Customer Satisfaction Guaranteed 3425Walden A venue,Depe w NY USA14043 Phone:716-926-8243T oll Free:888-258-3222 FA X:716-926-8215。
ADP5065：兼容USB功率电能快速电池充电管理方案
•容错输入电压-0.5V~+20V（USBVBUS）
•电池和充电器输出之间的隔离FET
•电池热敏电阻输入，当电池温度超过限值时自动关闭充电器
•符合JEITA锂离子电池充电温度规范
•SYS_EN_OK标志，暂缓系统开通（直到电池要求的最低水
ADP5065：兼容USB功率电能快速电池充电管理方
案
ADI公司的ADP5065是一款内嵌互联直流电压充电输出端与电池端
的FET器件，通过FET可以实现电池隔离，当系统驱动电能来自于废电池或
没有电池时，系统会立即切换到USB供电模式。ADP5065的输入电压范围
为4V~5.5V，最大输入电压高达20V，不用担心USB总线断开或连接过程中
•手机
平）
•由最小电池电压和/或最小电池充电的要求水平启动系统
•EOC编程，C/20，C/10和选择特定的电流水平
表1ADP5065设计方案材料清单
图2ADP5065方框图
ADP5065应用
•数码相机
•数码摄像机
•单节锂离子电池的便携式设备
•PDA、音频、GPS设备
的峰值。ADP5065充电器兼容USB2.0、USB3.0和USB电池充电规范1.1。
ADP5065采用一个非常小的封装，20引脚WLCSP封装（0.5mm间距）。
ADP5065主要特性
•3MHz开关模式充电器
图1ADP5065设计原理图
CM6400A;中文规格书,Datasheet资料
CM6400AEMI Filters with ESD Protection for Data Line ApplicationsProduct DescriptionThe CM6400A is a 24−bump EMI filter with ESD protection device for data line application in a 0.4 mm pitch, 5 x 5 CSP form factor. It is fully compliant with IEC 61000−4−2 Level 4. The CM6400A is RoHS II compliant.Features•24−Bump, 1.96 mm X 1.96 mm Footprint Chip Scale Package •These Devices are Pb −Free and are RoHS CompliantMARKING DIAGRAMDevice Package Shipping †ORDERING INFORMATIONCSP −24(Pb −Free)5000/T ape & ReelCM6400A64P3= CM6400A YYWW = Date CodeXXXX = Last four digits of lot#WLCSP24CASE 567CK†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.ELECTRICAL SCHEMATIC64P3YYWWXXXXRGND1 of 10 Filter Channels+LPACKAGE / PINOUT DIAGRAMSBottom View (Bumps Up View)Top View(Bumps Down View)A BC D EOrientation MarkingA1 Corner IndicatorTable 1. PIN DESCRIPTIONSA5 = Line 1A4 = Line 2A3 = GNDA2 = Line 1A1 = Line 2B5 = Line 3B4 = Line 4B2 = Line 3B1 = Line 4C5 = Line 5C4 = Line 6C3 = GND C2 = Line 5C1 = Line 6D5 = Line 7D4 = Line 8D3 = GND D2 = Line 7D1 = Line 8E5 = Line 9E4 = Line 10E3 = GND E2 = Line 9E1 = Line 10ELECTRICAL SPECIFICATIONS AND CONDITIONSTable 2. PARAMETERS AND OPERATING CONDITIONSParameterRating Units Storage Temperature Range –55 to +150°C Operating Temperature Range –40 to +85°C Power Dissipation at 70°C per Channel60mWTable 3. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)Symbol ParameterConditionsMin Typ Max Units R Resistance 100125150W L Inductance(Note 2)35nH CCapacitance per ChannelAt 1 MHz, V IN = 0 V (Notes 2 and 3)192429pF At 1 MHz, V IN = 2.5 V15pF Att(5)Passband Attenuation at 5 MHz −7dB F C Cut −off Frequency Z SOURCE = 50 W , Z LOAD = 50 W 250MHz V BR Breakdown VoltageI R = ±1 mA ±6±7.8±10V I LEAK Leakage Current per ChannelV IN = 3.0 V 10100nA V ESDESD Peak Discharge Voltage Protection at All Pins:a) Contact Discharge per IEC 61000−4−2 standardb) Air Discharge per IEC 61000−4−2 standard(Notes 2, 3 and 4)±15±15kV1.All parameters specified at T A = 25°C unless otherwise noted.2.These parameters guaranteed by design.3.These parameters guaranteed by characterization.4.Standard IEC 61000−4−2 (C Discharge = 150 pF, R Discharge = 330 W ).RF CHARACTERISTICSFigure 1. Typical Insertion Loss (Bias = 0 V, T A = 255C, 50 W Environment)PACKAGE DIMENSIONSWLCSP24, 1.96x1.96CASE 567CK −01ISSUE ONOTES:1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.2.CONTROLLING DIMENSION: MILLIMETERS.3.COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS.2X DIM A MIN MAX0.57MILLIMETERS A1D 1.96 BSC E b 0.240.29e0.40 BSC0.630.170.241.96 BSC DIMENSIONS: MILLIMETERS*For additional information on our Pb −Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*BOTTOM VIEWA20.40 REF RECOMMENDEDON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION分销商库存信息: ONSEMICM6400A。
CS5165A资料
CS5165A5−Bit Synchronous CPU Buck ControllerThe CS5165A synchronous 5−bit NFET buck controller is optimized to manage the power of the next generation Pentium II processors. It’s V2t control architecture delivers the fastest transient response (100 ns), and best overall voltage regulation in the industry today. It’s feature rich design gives end users the maximum flexibility to implement the best price/performance solutions for their end products.The CS5165A has been carefully crafted to maximize performance and protect the processor during operation. It has a 5−bit DAC on board that holds a ±1.0% tolerance over temperature. Its on board programmable Soft−Start insures a control startup, and the FET nonoverlap circuitry ensures that both FETs do not conduct simultaneously.The on board oscillator can be programmed up to 1.0 MHz to give the designer maximum flexibility in choosing external components and setting systems costs.The CS5165A protects the processor during potentially catastrophic events like overvoltage (OVP) and short circuit. The OVP feature is part of the V2 architecture and does not require any additional components. During short circuit, the controller pulses the MOSFETs in a “hiccup” mode (3.0% duty cycle) until the fault is removed. With this method, the MOSFETs do not overheat or self destruct.The CS5165A is designed for use in both single processor desktop and multiprocessor workstation and server applications. The CS5165A’s current sharing capability allows the designer to build multiple parallel and redundant power solutions for multiprocessor systems.The CS5165A contains other control and protection features such as Power Good, ENABLE, and adaptive voltage positioning. It is available in a 16 lead SOIC wide body package.Features•V2 Control Topology•Dual N−Channel Design•100 ns Controller Transient Response•Excess of 1.0 MHz Operation•5−Bit DAC with 1.0% Tolerance•Power Good Output With Internal Delay•Enable Input Provides Micropower Shutdown Mode•5.0 V and 12 V Operation•Adaptive V oltage Positioning•Remote Sense Capability•Current Sharing Capability•V CC Monitor•Hiccup Mode Short Circuit Protection•Overvoltage Protection (OVP)•Programmable Soft−Start•150 ns PWM Blanking•65 ns FET Nonoverlap Time•40 ns Gate Rise and Fall Times (3.3 nF Load)•Pb−Free Packages are Available**For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our T ape and Reel Packaging Specifications Brochure, BRD8011/D.Device Package Shipping†ORDERING INFORMATIONCS5165AGDW16SOIC−1647 Units/RailCS5165AGDWR16SOIC−161000/Tape & Reel CS5165AGDWR16G SOIC−16(Pb−Free)1000/Tape & Reel CS5165AGDW16G SOIC−16(Pb−Free)47 Units/RailFigure 1. Application Diagram, 5.0 V to 2.8 V @ 14.2 A for 300 MHz Pentium IIMAXIMUM RATINGSRating Value Unit Operating Junction Temperature, T J0 to 150°C Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1)230 peak°C Storage Temperature Range, T S−65 to +150°C ESD Susceptibility (Human Body Model) 2.0kV Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.1.60 second maximum above 183°C.MAXIMUM RATINGSPin Name Pin Symbol V MAX V MIN I SOURCE I SINKIC Power Input V CC16 V−0.3 V N/A 1.5 A peak, 200 mA DC Soft−Start Capacitor SS 6.0 V−0.3 V200 m A10 m A Compensation Capacitor COMP 6.0 V−0.3 V10 mA 1.0 mAVoltage Feedback Input V FB 6.0 V−0.3 V10 m A10 m AOff−Time Capacitor C OFF 6.0 V−0.3 V 1.0 mA50 mAVoltage ID DAC Inputs V ID0−V ID4 6.0 V−0.3 V 1.0 mA10 m AHigh−Side FET Driver GATE(H)16 V−0.3 V 1.5 A peak, 200 mA DC 1.5 A peak, 200 mA DC Low−Side FET Driver GATE(L)16 V−0.3 V 1.5 A peak, 200 mA DC 1.5 A peak, 200 mA DC Enable Input ENABLE 6.0 V−0.3 V100 m A 1.0 mAPower Good Output PWRGD 6.0 V−0.3 V10 m A30 mAPower Ground PGND0 V0 V 1.5 A peak, 200 mA DC N/ALogic Ground LGND0 V0 V100 mA N/AELECTRICAL CHARACTERISTICS (0°C < T A< +70°C; 0°C < T J < +125°C; 8.0V < V CC < 14V; 2.8 DAC Code:(V ID4=V ID2=V ID1=V ID0 = 1; V ID3= 0);C GATE(H) and C GATE(L)= 3.3nF; C OFF = 330 pF; C SS = 0.1 m F, unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit V CC Supply CurrentOperating 1.0 V < V FB < V DAC (max on−time)No Loads on GATE(H) and GATE(L)−1220mA Sleep Mode ENABLE = 0 V−300600m A V CC MonitorStart Threshold GATE(H) switching 3.75 3.95 4.15V Stop Threshold GATE(H) not switching 3.65 3.87 4.05V Hysteresis Start−Stop−80−mV Error AmplifierV FB Bias Current V FB = 0 V−0.1 1.0m A COMP Source Current COMP = 1.2 V to 3.6 V; V FB = 2.7 V153060m A COMP CLAMP Voltage V FB = 2.7 V, Adjust COMP voltage for Comp current = 50 m A0.85 1.0 1.15V COMP Clamp Current COMP = 0 V0.4 1.0 1.6mA COMP Sink Current V COMP = 1.2 V; V FB = 3.0 V; V SS > 2.5 V180400800m A Open Loop Gain(Note 2)5060−dB Unity Gain Bandwidth(Note 2)0.5 2.0−MHz PSRR @ 1.0 kHz(Note 2)6085−dB GATE(H) and GATE(L)High Voltage at 100 mA Measure V CC − GATE− 1.2 2.0V Low Voltage at 100 mA Measure GATE− 1.0 1.5V Rise Time 1.6 V < GATE < (V CC − 2.5 V)−4080ns Fall Time(V CC − 2.5 V) > GATE > 1.6 V−4080ns GATE(H) to GATE(L)Delay GATE(H) < 2.0 V; GATE(L) > 2.0 V3065100ns GATE(L) to GATE(H)Delay GATE(L) < 2.0 V; GATE(H) > 2.0 V3065100ns GATE pulldown Resistor to PGND, (Note 2)2050115k W Fault ProtectionSS Charge Time V FB = 0 V 1.6 3.3 5.0ms SS Pulse Period V FB = 0 V25100200ms SS Duty Cycle(Charge Time/Period) × 100 1.0 3.3 6.0% SS COMP Clamp Voltage V FB = 2.7 V; V SS = 0 V0.500.95 1.10V V FB Low Comparator Increase V FB till no SS pulsing and normal Off−time0.9 1.0 1.1V PWM ComparatorTransient Response V FB = 1.2 to 5.0 V. 500 ns after GATE(H)(after Blanking time) to GATE(H) = (V CC −1.0 V) to 1.0 V−130180nsMinimum Pulse Width (Blanking Time)Drive V FB. 1.2 to 5.0 V upon GATE(H) rising edge(> V CC − 1.0 V), measure GATE(H) pulse width50150250nsC OFFNormal Off−Time V FB = 2.7 V 1.0 1.6 2.3m s Extended Off−Time V SS = V FB = 0 V 5.08.012.0m s Time−Out TimerTime−Out Time V FB = 2.7 V, Measure GATE(H) Pulse Width103050m s Fault Duty Cycle V FB = 0V305070% Enable InputENABLE Threshold GATE(H) Switching0.8 1.15 1.30V Shutdown delay (Note 3)ENABLE−to−GATE(H) < 2.0 V− 3.0−m s 2.Guaranteed by design, not 100% tested in production.ELECTRICAL CHARACTERISTICS (0°C < T A< +70°C; 0°C < T J < +125°C; 8.0V < V CC < 14V; 2.8 DAC Code:(V ID4=V ID2=V ID1=V ID0 = 1; V ID3= 0);C GATE(H) and C GATE(L)= 3.3nF; C OFF = 330 pF; C SS = 0.1 m F, unless otherwise specified.)TypTest ConditionsMinMax Characteristic Unit Enable InputPullup Current ENABLE = 0 V 3.07.015m A Pullup Voltage No load on ENABLE pin 1.30 1.8 3.0V Input Resistance ENABLE = 5.0 V, R = (5.0 V − V PULLUP)/I ENABLE102050k W Power Good OutputLow to High Delay V FB = (0.8 × V DAC) to V DAC3065110m s High to Low Delay V FB = V DAC to(0.8 × V DAC)3075120m s Output Low Voltage V FB = 2.4 V, I PWRGD = 500 m A−0.20.3V Sink Current Limit V FB = 2.4 V, PWRGD = 1.0 V0.5 4.015.0mA 3.Guaranteed by design, not 100% tested in production.ELECTRICAL CHARACTERISTICS (0°C < T A< +70°C; 0°C < T J < +125°C; 8.0V < V CC < 14V; 2.8 DAC Code:(V ID4=V ID2=V ID1=V ID0 = 1; V ID3= 0);C GATE(H) and C GATE(L)= 3.3nF; C OFF = 330 pF; C SS = 0.1 m F, unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Voltage Identification DACAccuracy (all codes except 11111)Measure V FB = COMP (C OFF = 0 V)−1.0−+1.0%25°C ≤T J≤125°C; V CC = 12 VV ID4V ID3V ID2V ID1V ID010000− 3.505 3.540 3.575V 10001− 3.406 3.440 3.474V 10010− 3.307 3.340 3.373V 10011− 3.208 3.240 3.272V 10100− 3.109 3.140 3.171V 10101− 3.010 3.040 3.070V 10110− 2.911 2.940 2.969V 10111− 2.812 2.840 2.868V 11000− 2.713 2.740 2.767V 11001− 2.614 2.640 2.666V 11010− 2.515 2.540 2.565V 11011− 2.416 2.440 2.464V 11100− 2.317 2.340 2.363V 11101− 2.218 2.240 2.262V 11110− 2.119 2.140 2.161V 00000− 2.069 2.090 2.111V 00001− 2.020 2.040 2.060V 00010− 1.970 1.990 2.010V 00011− 1.921 1.940 1.959V 00100− 1.871 1.890 1.909V 00101− 1.822 1.840 1.858V 00110− 1.772 1.790 1.808V 00111− 1.723 1.740 1.757V 01000− 1.673 1.690 1.707V 01001− 1.624 1.640 1.656V 01010− 1.574 1.590 1.606V 01011− 1.525 1.540 1.555V 01100− 1.475 1.490 1.505VELECTRICAL CHARACTERISTICS (0°C < T A< +70°C; 0°C < T J < +125°C; 8.0V < V CC < 14V; 2.8 DAC Code:(V ID4=V ID2=V ID1=V ID0 = 1; V ID3= 0);C GATE(H) and C GATE(L)= 3.3nF; C OFF = 330 pF; C SS = 0.1 m F, unless otherwise specified.) Characteristic UnitMaxTypMinTest ConditionsVoltage Identification DAC01101− 1.426 1.440 1.455V 01110− 1.376 1.390 1.405V 01111− 1.327 1.340 1.353V 11111− 1.223 1.247 1.273V Input Threshold V ID4, V ID3, V ID2, V ID1, V ID0 1.000 1.250 2.400V Input Pullup Resistance V ID4, V ID3, V ID2, V ID1, V ID02550100k W Input Pullup Voltage 4.85 5.00 5.15VThreshold AccuracyLower Threshold Upper ThresholdMin Typ Max Min Typ Max UnitDAC CODE% of Nominal DAC Output−12−8.5−5.0 5.08.512% V ID4V ID3V ID2V ID1V ID010000 3.115 3.239 3.363 3.717 3.841 3.965V 10001 3.027 3.148 3.268 3.612 3.732 3.853V 10010 2.939 3.056 3.173 3.507 3.624 3.741V 10011 2.851 2.965 3.078 3.402 3.515 3.629V 10100 2.763 2.873 2.983 3.297 3.407 3.517V 10101 2.675 2.782 2.888 3.192 3.298 3.405V 10110 2.587 2.690 2.793 3.087 3.190 3.293V 10111 2.499 2.599 2.698 2.982 3.081 3.181V 11000 2.411 2.507 2.603 2.877 2.973 3.069V 11001 2.323 2.416 2.508 2.772 2.864 2.957V 11010 2.235 2.324 2.413 2.667 2.756 2.845V 11011 2.147 2.233 2.318 2.562 2.647 2.733V 11100 2.059 2.141 2.223 2.457 2.539 2.621V 11101 1.971 2.050 2.128 2.352 2.430 2.509V 11110 1.883 1.958 2.033 2.250 2.322 2.397V 00000 1.839 1.912 1.986 2.195 2.268 2.341V 00001 1.795 1.867 1.938 2.142 2.213 2.285V 00010 1.751 1.821 1.810 2.090 2.159 2.229V 00011 1.707 1.775 1.843 2.037 2.105 2.173V 00100 1.663 1.729 1.796 1.985 2.051 2.117V 00101 1.619 1.684 1.748 1.932 1.996 2.061V 00110 1.575 1.638 1.701 1.880 1.942 2.005V 00111 1.531 1.592 1.653 1.827 1.888 1.949V 01000 1.487 1.546 1.606 1.775 1.834 1.893V 01001 1.443 1.501 1.558 1.722 1.779 1.837V 01010 1.399 1.455 1.511 1.670 1.725 1.781V 01011 1.355 1.409 1.463 1.617 1.671 1.724V 01100 1.311 1.363 1.416 1.565 1.617 1.669V 01101 1.267 1.318 1.368 1.512 1.562 1.613V 01110 1.223 1.272 1.321 1.460 1.508 1.557V 01111 1.179 1.226 1.273 1.407 1.454 1.501V 11111 1.097 1.141 1.185 1.309 1.353 1.397VPACKAGE PIN DESCRIPTIONPACKAGE PIN #SOIC−16PIN SYMBOL FUNCTION1, 2, 3, 4, 6V ID0−V ID4Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V if left open. V ID4 selects the DAC range. When V ID4 is high (logic one), the Error Amp reference range is 2.14 V to 3.45 V with 100 mV increments. When V ID4 is low (logic zero), the Error Amp reference voltage 1.34 V to 2.09 V with 50 mV increments.5SS Soft−Start Pin. A capacitor from this pin to LGND sets the Soft−Start and fault timing.7C OFF Off−Time Capacitor Pin. A capacitor from this pin to LGND sets both the normal and extended off time.8ENABLE Output Enable Input. This pin is internally pulled up to 1.8 V. A logic Low (< 0.8) on this pin disables operation and places the CS5165A into a low current sleep mode.9V CC Input Power Supply Pin.10GATE(H)High Side Switch FET driver pin.11PGND High current ground for the GATE(H) and GATE(L) pins.12GATE(L)Low Side Synchronous FET driver pin.13PWRGD Power Good Output. Open collector output drives low when V FB is out of regulation. Active when ENABLE input is low.14LGND Reference ground. All control circuits are referenced to this pin.15COMP Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error Amp compensation.16V FBError Amp, PWM Comparator, and Low V FB Comparator feedback input.Figure 2. Block DiagramV V V V V CCOFFGATE(H)GATE(L)VTYPICAL PERFORMANCE CHARACTERISTICS200040006000800010000120001400016000020406080100120140160180200Load Capacitance (pF)R i s e t i m e (n s )200040006000800010000120001400016000020406080100120140160180200Load Capacitance (pF)F a l l t i m e (n s )0200040006000800010000120001400016000Load Capacitance (pF)204060100120−0.180−0.08−0.06−0.04−0.0200.020.04Junction Temperature (°C)D A C O u t p u t V o l t a g e D e v i a t i o n (%)Figure 3. GATE(L) Risetime vs. Load Capacitance Figure 4. GATE(H) Risetime vs. Load CapacitanceFigure 5. GATE(H) & GATE(L) Falltime vs. LoadCapacitanceFigure 6. DAC Output Voltage vs. Temperature,DAC Code = 10111, V CC = 12 V2.12.22.32.42.52.62.72.82.93.03.13.23.33.53.4−0.25−0.20−0.15−0.100.051.31.31.41.41.51.51.61.61.71.71.81.81.92.01.92.0Figure 7. Percent Output Error vs. DAC VoltageSetting, V CC = 12 V, T A = 255C, V ID4 = 0DAC Output Voltage Setting (V)Figure 8. Percent Output Error vs. DAC Output Voltage Setting V CC = 12 V, T A = 255C, V ID4 = 1DAC Output Voltage Setting (V)O u t p u t E r r o r (%)O u t p u t E r r o r (%)APPLICATIONS INFORMATIONTHEORY OF OPERATIONV2 Control MethodThe V2 method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the value of the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a rampfrom inductor current.Figure 9. V2 Control DiagramCOMPThe V2 control method is illustrated in Figure 9. The output voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required.A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V2 control scheme to compensate the duty cycle. Since the change in inductor current modifies the ramp signal, as in current mode control, the V2 control scheme has the same advantages in line transient response.A change in load current will have an affect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods.The error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. The main purpose of this ‘slow’ feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered.Line and load regulation are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load.Constant Off TimeTo maximize transient response, the CS5165A uses a constant off time method to control the rate of output pulses. During normal operation, the off time of the high side switch is terminated after a fixed period, set by the C OFF capacitor. To maintain regulation, the V2 control loop varies switch on time. The PWM comparator monitors the output voltage ramp, and terminates the switch on time.Constant off time provides a number of advantages. Switch duty cycle can be adjusted from 0 to 100% on a pulse by pulse basis when responding to transient conditions. Both 0% and 100% duty cycle operation can be maintained for extended periods of time in response to load or line transients. PWM slope compensation to avoid sub−harmonic oscillations at high duty cycles is avoided.Switch on time is limited by an internal 30 m s (typical) timer, minimizing stress to the power components. Programmable OutputThe CS5165A is designed to provide two methods for programming the output voltage of the power supply. A 5−bit on board digital to analog converter (DAC) is used to program the output voltage within two different ranges. The first range is 2.14 V to 3.54 V in 100 mV steps, the second is 1.34 V to 2.09 V in 50 mV steps, depending on the digital input code. If all five bits are left open, the CS5165A enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the V FB pin, as in traditional controllers. The CS5165A is specifically designed to meet or exceed Intel’s Pentium II specifications.StartupUntil the voltage on the V CC supply pin exceeds the 3.95 V monitor threshold, the Soft−Start and GA TE pins are held low. The FAULT latch is reset (no Fault condition). The output of the error amplifier (COMP) is pulled up to 1.0 V by the comparator clamp. When the V CC pin exceeds the monitor threshold, the GA TE(H) output is activated, and the Soft−Startcapacitor begins charging. The GA TE(H) output will remain on, enabling the NFET switch, until terminated by either the PWM comparator, or the maximum on time timer.If the maximum on time is exceeded before the regulator output voltage achieves the 1.0 V level, the pulse is terminated.The GA TE(H) pin drives low, and the GA TE(L) pin drives high for the duration of the extended off time. This time is set by the time out timer and is approximately equal to the maximum on time, resulting in a 50% duty cycle. The GA TE(L) pin will then drive low, the GA TE(H) pin will drive high, and the cycle repeats.When regulator output voltage achieves the 1.0 V level present at the COMP pin, regulation has been achieved and normal off time will ensue. The PWM comparator terminates the switch on time, with off time set by the C OFF capacitor. The V 2 control loop will adjust switch duty cycle as required to ensure the regulator output voltage tracks the output of the error amplifier.The Soft−Start and COMP capacitors will charge to their final levels, providing a controlled turn on of the regulator output. Regulator turn on time is determined by the COMP capacitor charging to its final value. Its voltage is limited by the Soft−Start COMP clamp and the voltage on the Soft−Start pin.Power Supply SequencingThe CS5165A offers inherent protection from undefined startup conditions, regardless of the 12 V and 5.0 V supply power up sequencing. The turn on slew rates of the 12 V and 5.0 V power supplies can be varied over wide ranges without affecting the output voltage or causing detrimental effects to the buck regulator.Figure 10. Demonstration Board Startup in Response to Increasing 12 V and 5.0 V Input Voltages. Extended Off Time is Followed by Normal Off Time Operation when Output Voltage AchievesRegulation to the Error Amplifier Output.M 250 m sTrace 3− 12 V Input (V CC ) (5.0 V/div.)Trace 1− Regulator Output Voltage (1.0 V/div.)Trace 4− 5.0 V Input (1.0 V/div.)Trace 2− Inductor Switching Node (2.0 V/div.)Figure 11. Demonstration Board Startup WaveformsTrace 2− COMP PIn (error amplifier output) (1.0 V/div.)Trace 1− Soft−Start Pin (2.0 V/div.)Trace 4− Regulator Output Voltage (1.0 V/div.)Figure 12. Demonstration Board Enable StartupWaveforms M 10.0 m sTrace 1− Regulator Output Voltage (1.0 V/div.)Trace 2− Inductor Switching Node (5.0V/div.)Normal OperationDuring normal operation, switch off time is constant and set by the C OFF capacitor. Switch on time is adjusted by the V 2 control loop to maintain regulation. This results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. Output voltage ripple will be determined by inductor ripple current working and the ESR of the output capacitors (see Figures 13 and 14).Figure 13. Normal Operation Showing Output Inductor Ripple Current and Output Voltage Ripple, 0.5 A Load,V OUT = +2.84 V (DAC = 10111)Trace 1− GATE(H) (10 V/div.)Trace 2− Inductor Switching Node (5.0 V/div.)Trace 3− Output Inductor Ripple Current (2.0 A/div.)Trace 4− V OUT ripple (20 mV/div.)Trace 1− GATE(H) (10 V/div.)Trace 2− Inductor Switching Node (5.0 V/div.)Trace 3− Output Inductor Ripple Current (2.0 A/div.)Trace 4− V OUT ripple (20 mV/div.)Figure 14. Normal Operation Showing Output InductorRipple Current and Output Voltage Ripple, I LOAD = 14 A, V OUT= +2.84 V (DAC = 10111)Transient ResponseThe CS5165A V 2 control loop’s 100 ns reaction time provides unprecedented transient response to changes in input voltage or output current. Pulse by pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current.Overall load transient response is further improved through a feature called “Adaptive V oltage Positioning”. This technique pre−positions the output capacitors voltage to reduce total output voltage excursions during changes in load.Holding tolerance to 1.0% allows the error amplifiers reference voltage to be targeted +40 mV high without compromising DC accuracy. A “Droop Resistor”,implemented through a PC board trace, connects the Error Amps feedback pin (V FB ) to the output capacitors and loadand carries the output current. With no load, there is no DC drop across this resistor, producing an output voltage tracking the Error amps, including the +40 mV offset. When the full load current is delivered, an 80 mV drop is developed across this resistor. This results in output voltage being offset −40 mV low.The result of Adaptive V oltage Positioning is that additional margin is provided for a load transient before reaching the output voltage specification limits. When load current suddenly increases from its minimum level, the output capacitor is pre−positioned +40 mV . Conversely, when load current suddenly decreases from its maximum level, the output capacitor is pre−positioned −40 mV (see Figures 15,16, and 17). For best Transient Response, a combination of a number of high frequency and bulk output capacitors are usually used.If the Maximum On−Time is exceeded while responding to a sudden increase in Load current, a normal off−time occurs to prevent saturation of the output inductor.Figure 15. Output Voltage Transient Response to a 14 A Load Pulse, V OUT = +2.84 V (DAC = 10111)Trace 4− V OUT (100 mV/div.)Trace 3− Load Current (5.0A/10 mV/div.)Figure 16. Output Voltage Transient Response to a 14 A Load Step, V OUT = +2.84 V (DAC = 10111)Trace 1− GATE(H) (10 V/div.)Trace 2− Inductor Switching Node (5.0 V/div.)Trace 3− Load Current (5.0 A/div)Trace 4− V OUT(100 mV/div.)Figure 17. Output Voltage Transient Response to a 14A Load Turn−Off, V OUT = +2.84 V (DAC = 10111)Trace 1− GATE(H) (10 V/div.)Trace 2− Inductor Switching Node (5.0 V/div.)Trace 3− Load Current (5.0 A/div)Trace 4− V OUT (100 mV/div.)PROTECTION AND MONITORING FEATURESShort Circuit ProtectionA lossless hiccup mode short circuit protection feature is provided, requiring only the Soft−Start capacitor to implement.If a short circuit condition occurs the V FB low comparator sets the FAULT latch. This causes the top FET to shut off,disconnecting the regulator from it’s input voltage. The Soft−Start capacitor is then slowly discharged by a 2.0 m A current source until it reaches it’s lower 0.7 V threshold. The regulator will then attempt to restart normally, operating in it’s extended off time mode with a 50% duty cycle, while the Soft−Start capacitor is charged with a 60 m A charge current.If the short circuit condition persists, the regulator output will not achieve the 1.0 V low V FB comparator threshold before the Soft−Start capacitor is charged to it’s upper 2.5 V threshold. If this happens the cycle will repeat itself until the short is removed. The Soft−Start charge/discharge current ratio sets the duty cycle for the pulses (2.0 m A/60 m A = 3.3%),while actual duty cycle is half that due to the extended off time mode (1.65%).This protection feature results in less stress to the regulator components, input power supply, and PC board traces than occurs with constant current limit protection (see Figures 18and 19).If the short circuit condition is removed, output voltage will rise above the 1.0 V level, preventing the FAULT latch from being set, allowing normal operation to resume.Figure 18. Demonstration Board Hiccup Mode Short Circuit Protection. Gate Pulses are Delivered While the Soft−Start Capacitor Charges, and Cease DuringDischargeM 25.0 msTrace 3− Soft−Start Timing Capacitor (1.0 V/div.)Trace 4− 5.0 V Supply Voltage (2.0 V/div.)Trace 2− Inductor Switching Node (2.0 V/div.)Figure 19. Demonstration Board Startup withRegulator Output Shorted To Ground M 50.0 m sTrace 4− 5.0 V from PC Power Supply (2.0 V/div.)Trace 2− Inductor Switching Node (2.0V/div.)Overvoltage ProtectionOvervoltage protection (OVP) is provided as result of the normal operation of the V 2 control topology and requires no additional external components. The control loop responds to an overvoltage condition within 100 ns, causing the top MOSFET to shut off, disconnecting the regulator from it’s input voltage. The bottom MOSFET is then activated, resulting in a “crowbar” action to clamp the output voltage and prevent damage to the load (see Figures 20 and 21 ). The regulator willremain in this state until the overvoltage condition ceases or the input voltage is pulled low. The bottom FET and board trace must be properly designed to implement the OVP function.If a dedicated OVP output is required, it can be implemented using the circuit in Figure 22. In this figure the OVP signal will go high (overvoltage condition), if the output voltage (V CORE )exceeds 20% of the voltage set by the particular DAC code and provided that PWRGD is low. It is also required that the overvoltage condition be present for at least the PWRGD delay time for the OVP signal to be activated. The resistor values shown in Figure 22 are for V DAC = +2.8 V (DAC = 10111).The V OVP (overvoltage trip−point) can be set using the following equation:V OVP +V BEQ3ǒ1)R2R1ǓFigure 20. OVP Response to an Input−to−Output Short Circuit by Immediately Providing 0% Duty Cycle, Crow−Barring the Input Voltage to GroundM 10.0 m sTrace 1− Regulator Output Voltage (1.0 V/div.)Trace 2− Inductor Switching Node 5.0 V/div.)Trace 4− 5.0 V from PC Power Supply (5.0 V/div.)Figure 21. OVP Response to an Input−to−Output ShortCircuit by Pulling the Input Voltage to GroundM 5.00 msTrace 1− Regulator Output Voltage (1.0 V/div.)Trace 4− 5.0 V from PC Power Supply (2.0 V/div.)Figure 22. Circuit To Implement A Dedicated OVPOutput Using The CS5165A Output Enable CircuitThe Enable pin (pin 8) is used to enable or disable the regulator output voltage, and is consistent with TTL DC specifications. It is internally pulled−up. If pulled low (below 0.8 V), the output voltage is disabled. At the same time the Power Good and Soft−Start pins are pulled low, so that when normal operation resumes power−up of the CS5165A goes through the Soft−Start sequence. Upon pulling the Enable pin low, the internal IC bias is completely shut off, resulting in total shutdown of the Controller IC.Power Good CircuitThe Power Good pin (pin 13) is an open−collector signal consistent with TTL DC specifications. It is externally pulled−up, and is pulled low (below 0.3 V) when the regulator output voltage typically exceeds ± 8.5% of the nominal output voltage. Maximum output voltage deviation before Power Good is pulled low is ± 12%.Figure 23. PWRGD Signal Becomes Logic High as V OUT Enters −8.5% of Lower PWRGD Threshold,V OUT = +2.84 V (DAC = 10111)Trace 4− V OUT (1.0 V/div.)Trace 2− PWRGD (2.0 V/div.)。
AD5066ARUZ资料
Preliminary Technical Data
Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
AD5066
FEATURES
Low power Quad 16 bit DAC, ± 1LSB INL Individual reference pins 2.7 V to 5.5 V power supply Unbuffered voltage output capable of driving 60KΩ Fast Settling time of 4 us typically Power-on reset to zero scale or mid-scale Per channel power-down 3 power-down functions Low glitch on power up Hardware LDAC with LDAC override function CLR Function to programmable code Small 16 lead TSSOP
PRODUCT HIGHLIGHTS
1. Quad channel available in 16-lead TSSOP package. 2. Individual voltage reference pins 3. 16 bit accurate, 1 LSB INL. 4. Low glitch on power-up. 5. High speed serial interface with clock speeds up to 50 MHz. 6. Three power-down modes available to the user. 7. Reset to known output voltage (zero scale).
ADP5065:兼容USB功率电能快速电池冲电管理方案
ADP5065：兼容USB功率电能快速电池冲电管理方案
佚名
【期刊名称】《世界电子元器件》
【年(卷),期】2013(000)007
【摘要】ADI公司的ADP5065是一款内嵌互联直流电压充电输出端与电池端的FET器件，通过FET可以实现电池隔离，当系统驱动电能来自于废电池或没有电
池时，系统会立即切换到USB供电模式。
ADP5065的输入电压范围为4V-5．5V，最大输入电压高达20V，不用担心USB总线断开或连接过程中的峰值。
【总页数】2页(P17-18)
【正文语种】中文
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3.差异化备电设备和电池共用管理器在5G基站备电方案中的应用研究 [J], 刘宇
刚
4.与两节碱性电池和USB兼容的低损耗PowerPath TM控制器 [J],
5.ADI公司的单芯片电能表IC采用先进的电池管理技术降低功耗——ADE7100
和ADE7500系列采用了先进的电池管理、高集成度，而且容易连接LCD，适合
于高级功能、低成本的单芯片电能计量解决方案 [J],
因版权原因，仅展示原文概要，查看原文内容请购买。
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Fast Charge Battery Manager with PowerPath and USB Compatibility Data Sheet ADP5065Rev. BInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.FEATURES3 MHz switch mode charger1.25 A charge current from dedicated chargerUp to 680 mA charging current from 500 mA USB host Operating input voltage from 4.0 V up to 5.5 VTolerant input voltage −0.5 V to +20 V (USB VBUS)Dead battery isolation FET between battery andcharger outputBattery thermistor input with automatic charger shutdown for when battery temperature exceeds limitsCompliant with the JEITA Li-Ion battery charging temperature specificationSYS_EN_OK flag to hold off system turn-on until battery is at minimum required level for guaranteed system startup due to minimum battery voltage and/or minimum battery charge level requirementsEOC programming with C/20, C/10 and specific current level selectionAPPLICATIONSDigital still camerasDigital video camerasSingle cell Li-Ion portable equipmentPDA, audio, GPS devicesMobile phones FUNCTIONAL BLOCK DIAGRAM937-1Figure 1.GENERAL DESCRIPTIONThe ADP5065 charger is fully compliant with the USB 2.0, USB 3.0, and USB Battery Charging Specification 1.1 and enables charging via the mini USB VBUS pin from a wall charger, car charger, or USB host port.The ADP5065 operates from a 4 V to 5.5 V input voltage range but is tolerant of voltages of up to 20 V. This alleviates the concerns about the USB bus spiking during disconnect or connect scenarios.The ADP5065 also features an internal FET between the dc-to-dc charger output and the battery. This permits battery isolation and, hence, system powering under a dead battery or no battery scenario, which allows for immediate system function on connection to a USB power supply. Based on the type of USB source, which is detected by an external USB detection chip, the ADP5065 can be set to apply the correct current limit for optimal charging and USB compliance.The ADP5065 comes in a very small and low profile 20-lead WLCSP (0.5 mm pitch spacing) package.The overall solution requires only five small, low profile external components consisting of four ceramic capacitors (one of which is the battery filter capacitor), one multilayer inductor. In addition to these components, there is one optional dead battery situation default setting resistor. This configuration enables a very small PCB area to provide an integrated and performance enhancing solution to USB battery charging and power rail provision.ADP5065Data SheetRev. B | Page 2 of 40TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Recommended Input and Output Capacitance ........................ 5 I 2C-Compatible Interface Timing Specifications ..................... 6 Absolute Maximum Ratings ....................................................... 7 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ............................................. 9 Temperature Characteristics ..................................................... 11 Typical Waveforms ..................................................................... 13 Theory of Operation ...................................................................... 15 Introduction ................................................................................ 15 Charger Modes............................................................................ 17 Thermal Management ............................................................... 19 Battery Isolation FET ................................................................. 19 Battery Detection ....................................................................... 20 Battery Pack Temperature Sensing .......................................... 22 External Resistor for V_WEAK_SET ...................................... 23 I 2C Interface ................................................................................ 24 Charger Operational Flowchart ............................................... 25 I 2C Register Map ......................................................................... 26 Register Bit Descriptions ........................................................... 27 Applications Information .............................................................. 33 External Components ................................................................ 33 PCB Layout Guidelines .................................................................. 35 Power Dissipation and Thermal Considerations ....................... 37 Charger Power Dissipation ....................................................... 37 Junction Temperature ................................................................ 38 Factory-Programmable Options .................................................. 39 Packaging and Ordering Information ......................................... 40 Outline Dimensions ................................................................... 40 Ordering Guide .. (40)REVISION HISTORY4/12—Rev.A to Rev. BChanges to Features Section and General Description Section ........ 1 Changes to Table 1 ............................................................................ 3 Changes to VIN1, VIN2 to PGND1, PGND2 Parameter, Table 4 ... 7 Changes to Introduction Section .. (15)11/11—Rev. 0 to Rev. AChanges to Figure 10 ...................................................................... 10 Changes to Figure 17 and Figure 18 ............................................. 11 Changes to Figure 41 . (36)10/11—Revision 0: Initial VersionData SheetADP5065Rev. B | Page 3 of 40SPECIFICATIONS−40°C < T J < 125°C, V IN = 5.0 V , V ISO_S > 3.0 V , V HOT < V THR < V COLD , V BAT_SNS = 3.6 V , C VIN = 2.2 µF, C DCDC = 22 µF, C BAT = 22 µF, C CFILT = 4.7 µF, L OUT = 1 µH, all registers are at default values, unless otherwise noted. Table 1.ParameterSymbol Min Typ Max Unit Test Conditions/Comments GENERAL PARAMETERSUndervoltage Lockout V UVLO 2.25 2.35 2.45 V Falling threshold, higher of V CFILT and V BAT_SNS50 100 150 mV Hysteresis, higher of V CFILT and V BAT_SNS rising Total Input Current I VIN 86 92 100 mA Nominal USB initialized current level 1 150 mA USB super speed300 mA USB enumerated current level (specification for China)460 475 500 mA USB enumerated current level 900 mA Dedicated charger input1500 mA Dedicated wall charger Current ConsumptionVINxI QVIN 15 mA No battery, no ISO_Sx load, switching 3 MHz Battery, StandbyI QISO_B 0.22 2 µA T J = −40°C to +85°CSWxPin Leakage Current −I OUT 2 µA V VIN = 0 V, T J = −40°C to +85°C CHARGING PARAMETERSFast Charge Current, CC Mode (Battery Voltage > V TRK_DEAD ) I CHG 1250 mA V CFILT > V BAT_SNS + V CCDROP 1, 2Fast Charge Current Accuracy I CHG(TOL) −7 +5 % T j = 25°C, I CHG = 550 mA to 1250 mA−8+8%I CHG = 550 mA to 1150 mA, fast charge current accuracy is guaranteed at temperatures from T j = 0°C to isothermal regulation limit (typically T j = 115°C)−17 +8 % I CHG = 1250 mA, T j = 0°C to isothermal regulation limit (typically T j = 115°C) Trickle Charge Current 1, 2 I TRK_DEAD 16 2025mAWeak Charge Current I CHG_WEAK I CHG + 20 mA When V TRK_DEAD < V BAT_SNS < V WEAK 1, 3 Dead BatteryTrickle to Weak Charge Threshold V TRK_DEAD 2.4 2.5 2.6 V On BAT_SNS 1 Trickle to Weak Charge Threshold Hysteresis ΔV TRK_DEAD 90 mVWeak BatteryWeak to Fast Charge Threshold V WEAK 2.9 3.0 3.1 V On BAT_SNS 1, 3 Weak Battery Threshold Hysteresis ΔV WEAK90mVBattery Termination VoltageV TRM 4.158 4.200 4.242 V On BAT_SNS, T J = 0°C to 115°C 1Battery Termination Voltage Accuracy−0.3+0.3 % On BAT_SNS, T J = 25°C, I END = 52.5 mA 1 Battery Overvoltage Threshold V BATOV V CFILT − 0.15 V Relative to CFILT voltage, BAT_SNS rising Charge Complete CurrentI END 52.5 mA V BAT_SNS = V TRM 1Charge Complete Current Threshold Accuracy −25 +25 % I END = 72.5 mA or 92.5 mA, T J = 0°C to 115°C −35 +35 % I END = 52.5 mA, T J = 0°C to 115°C−55 +55 % I END = 32.5 mA, T J = 0°C to 115°C Recharge Voltage DifferentialV RCH 260 mV Relative to V TRM , BAT_SNS falling 1 Battery Node Short Threshold Voltage 1 V BAT_SHR 2.3 2.4 2.5 V CHARGER DC-to-DC CONVERTERSwitching Frequency f SWCHG 2.8 3 3.2 MHz Maximum Duty Cycle D MAX93% Peak Inductor Current I L(PK) 1500 1750 2000 mARegulated System Voltage V ISO_STRK 3.21 3.3 3.39 V V BAT_SNS < V TRK_DEAD , trickle charging mode Load Regulation 5 mV/A DC-to-DC PowerPMOS On Resistance R DS(ON)P 220 285 mΩ NMOS On ResistanceR DS(ON)N160210mΩADP5065Data SheetRev. B | Page 4 of 40ParameterSymbol Min Typ Max Unit Test Conditions/Comments BATTERY ISOLATION FETBump to Bump Resistance Between ISO_Bx and ISO_Sx Bumps R DSONISO 76 115 mΩ Includes bump resistances and battery isolation PMOS on resistance; on battery supplement mode, V IN = 0 V, V ISO_B = 3.6 V, I ISO_B = 500 mA Regulated System VoltageV ISO_SFC 3.15 3.3 3.45 V V TRK_DEAD < V BAT_SNS , fast charging CC mode Battery Supplementary Threshold V THISO 0 5 10 mV V ISO_S[1:2] < V ISO_B[1:2], V SYS rising HIGH VOLTAGE BLOCKING FET VINx InputHigh Voltage Blocking FET On ResistanceR DSONHV 340 455 mΩ I IN = 500 mA Current, Suspend Mode I SUSPEND 1.3 2.5 mA EN_CHG = low Input VoltageGood ThresholdRising V VIN_OK_RISE 3.78 3.9 4.0 V FallingV VIN_OK_FALL 3.6 3.67 V Overvoltage ThresholdV VIN_OV 5.35 5.42 5.5 V Overvoltage Threshold Hysteresis 75 mV VINx Transition TimingMinimum Rise Time for VINx from 5 V to 20 Vt VIN_RISE 10 µs Minimum Fall Time for VINx from 4 V to 0 Vt VIN_FALL 10 µsTHERMAL CONTROLIsothermal Charging Temperature T LIM 115 °C Thermal Early Warning Temperature T SDL 130 °CThermal Shutdown Temperature T SD 140 °C T J rising110 °C T J falling THERMISTOR CONTROL Thermistor Current10,000 NTC I NTC_10k 400 μA 100,000 NTCI NTC_100k 40 μA Thermistor Capacitance C NTC 100 pFCold Temperature Threshold T NTC_COLD 0 °C No battery charging occurs Resistance ThresholdsCool to Cold Resistance R COLD_FALL 24,050 27,300 30,600 Ω Cold to Cool Resistance R COLD_RISE 23,100 26,200 29,400 ΩHot Temperature Threshold T NTC_HOT 60 °C No battery charging occurs Resistance ThresholdsHot to Typical Resistance R HOT_FALL 2990 3310 3640 Ω Typical to Hot ResistanceR HOT_RISE 2730 3030 3330 Ω JEITA SPECIFICATION 4JEITA Cold Temperature T JEITA_COLD 0 °C No battery charging occurs Resistance ThresholdsCool to Cold Resistance R COLD_FALL 24,050 27,300 30,600 Ω Cold to Cool Resistance R COLD_RISE 23,100 26,200 29,400 ΩJEITA Cool Temperature T JEITA_COOL 10 °C Battery charging occurs at 50% of programmed level Resistance ThresholdsTypical to Cool Resistance R TYP_FALL 15,200 17,800 20,400 Ω Cool to Typical Resistance R TYP_RISE 14,500 17,000 19,500 ΩJEITA Typical Temperature T JEITA_TYP °C Normal battery charging occurs at default/programmed levels Resistance ThresholdsWarm to Typical Resistance R WARM_FALL 4710 5400 6100 Ω Typical to Warm Resistance R WARM_RISE 4320 4950 5590 ΩJEITA Warm Temperature T JEITA_WARM 45 °C Battery termination voltage (V TRM ) is reduced by 100 mV Resistance ThresholdsHot to Warm Resistance R HOT_FALL 2990 3310 3640 Ω Warm to Hot Resistance R HOT_RISE 2730 3030 3330 ΩJEITA Hot TemperatureT JEITA_HOT60°CNo battery charging occursData SheetADP5065Rev. B | Page 5 of 40ParameterSymbol Min Typ Max Unit Test Conditions/Comments BATTERY DETECTION Sink Current I SINK 13 20 34 mA Source Current I SOURCE 7 10 13 mA Battery Threshold Low V BATL 1.8 1.9 2.0 V HighV BATH 3.4 VNo Battery Threshold V NOBAT 3.3 V V TRM ≥ 3.7 V, valid after charge complete (see Figure 38)3.0 V V TRM < 3.7 V, valid after charge complete (see Figure 38) Battery Detection Timer t BATOK 333 ms TIMERSStart Charging Delay Timer t START 1 sec Trickle Charge Timer t TRK 60 min Fast Charge Timert CHG 600 minCharge Complete Timer t END 7.5 min V BAT_SNS = V TRM , I CHG < I ENDDeglitch Timer t DG 31 ms Applies to V TRK , V RCH , I END , V DEAD , V VIN_OK Watchdog Timer 1 t WD 32 sec Safety Timert SAFE 36 40 44 min Battery Node Short Timer 1 t BAT_SHR 30 sec LOGIC INPUTSMaximum Voltage on Digital Inputs V DIN_MAX 5.5 VMaximum Logic Low Input Voltage V IL 0.5 V Applies to SCL, SDA, TRK_EXT, IIN_EXT Minimum Logic High Input Voltage V IH 1.2 V Applies to SCL, SDA, TRK_EXT, IIN_EXT Pull-Down Resistance215350610kΩApplies to TRK_EXT, IIN_EXT1These values are programmable via I 2C. Values are given with default register values. 2The output current during charging can be limited by I BUS or by the isothermal charging mode. 3Programmable via external resistor programming, if required. 4JEITA can be enabled or disabled in I 2C.RECOMMENDED INPUT AND OUTPUT CAPACITANCETable 2.Parameter Min Typ Max Unit Test Conditions/Comments CAPACITANCEVINx Capacitance1.0 µF Effective capacitance CFILT Pin Total External Capacitance2.0 4.7 5.0 μF Effective capacitance ISO_Sx Pin Total Capacitance 10 50 µF Effective capacitance ISO_Bx Pin Total Capacitance10µFEffective capacitanceADP5065Data SheetRev. B | Page 6 of 40I 2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONSTable 3.Parameter 1Symbol Min Typ Max Unit I 2C-COMPATIBLE INTERFACE 2 Capacitive Load, Each Bus Line C S 400 pF SCL Clock Frequency f SCL 400 kHz SCL High Time t HIGH 0.6 µs SCL Low Time t LOW 1.3 µs Data Setup Time t SUDAT 100 ns Data Hold Timet HDDAT 0 0.9 µs Setup Time for Repeated Start t SUSTA 0.6 µs Hold Time for Start/Repeated Startt HDSTA 0.6 µs Bus Free Time Between a Stop and a Start Condition t BUF 1.3 µs Setup Time for Stop Condition t SUSTO 0.6µs Rise Time of SCL/SDA t R 20 300 ns Fall Time of SCL/SDAt F 20 300 ns Pulse Width of Suppressed Spiket SP 0 50 ns1 Guaranteed by design.2A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. See Figure 2, the I 2C timing diagram.Timing DiagramS = START CONDITIONSr = REPEATED START CONDITION P = STOP CONDITION09370-002Figure 2. I 2C Timing DiagramData SheetADP5065Rev. B | Page 7 of 40ABSOLUTE MAXIMUM RATINGSTable 4.ParameterRatingVIN1, VIN2 to PGND1, PGND2 −0.5 V to +20 V All Other Pins to AGND−0.3 V to +6 V Continuous Drain Current, Battery Supple-mentary Mode, from ISO_Bx to ISO_SxT J ≤ 85°C 2.2 A T J = 125°C1.1 AStorage Temperature Range−65°C to +150°C Operating Junction Temperature Range −40°C to +125°C Soldering ConditionsJEDEC J-STD-020Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.This is a stress rating only;functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied.Exposure to absolute maximum rating conditions for extended periods may affect device reliability.THERMAL RESISTANCEθJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal ResistancePackage Type θJA θJC θJB Unit 20-Lead WLCSP 146.8 0.7 9.2 °C/W15 × 4 array, 0.5 mm pitch (2.75 mm × 2.08 mm); based on a JEDEC, 2S2P,4-layer board with 0 m/sec airflow.Maximum Power DissipationThe maximum safe power dissipation in the ADP5065 package is limited by the associated rise in junction temperature (T J ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the para-metric performance of the ADP5065. Exceeding a junction temperature of 175°C for an extended period of time can result in changes in the silicon devices that potentially cause failure.ESD CAUTIONADP5065Data SheetRev. B | Page 8 of 40PIN CONFIGURATION AND FUNCTION DESCRIPTIONSTOP VIEW(BALL SIDE DOWN)Not to Scale09370-003Figure 3. Pin ConfigurationTable 6. Pin Function DescriptionsPin No. Mnemonic Type 1 DescriptionD3, E3 SW1, SW2 I/O DC-to-DC Converter Inductor Connection. These pins are high current outputs when in charging mode. D1, E1 VIN1, VIN2 I/O Power Connection to USB VBUS. These pins are high current inputs when in charging mode. D4, E4 PGND1, PGND2 G Charger Power Ground. These pins are high current inputs when in charging mode.C2 AGND G Analog Ground.E2 CFILTI/O 4.7 μF Filter Capacitor Connection. This pin is a high current input/output when in charging mode. C3, C4 ISO_S1, ISO_S2 I/O Charger Supply Side Input to Internal Isolation FET/Battery Current Regulation FET. B3, B4 ISO_B1, ISO_B2 I/O Battery Supply Side Input to Internal Isolation FET/Battery Current Regulation FET.A2 SCL I I 2C-Compatible Interface Serial Clock. B1 SDA I/O I 2C-Compatible Interface Serial Data.A4 IIN_EXT I Set Input Current Limit. This pin sets the input current limit directly. When IIN_EXT = low or high-Z, the input limit is 100 mA. When IIN_EXT = high, the input limit is 500 mA.B2 TRK_EXT I Enable Trickle Charge Function. When TRK_EXT = low or high-Z, the trickle charge is enabled. When TRK_EXT = high, the trickle charge is disabled.A3 THRI Battery Pack Thermistor Connection. If not used, connect a dummy 10 kΩ resistor from THR to GND. C1 BAT_SNS I Battery Voltage Sense Pin.D2 SYS_ON_OK O Battery Okay Open-Drain Output Flag. Active low. This pin enables the system when the battery reaches V WEAK .A1V_WEAK_SETI/OExternal Resistor Setting Pin for V_WEAK threshold. The use of this pin is optional. When not in use, connect to GND.1I is input, O is output, I/O is input/output, and G is ground.Data SheetADP5065Rev. B | Page 9 of 40TYPICAL PERFORMANCE CHARACTERISTICS10001020304050607090802.52.93.3 3.74.1 4.5E F F I C I E N C Y (%)BATTERY VOLTAGE (V)09370-004Figure 4. Battery Charger Efficiency vs. Battery Voltage, V IN = 5.0 V0.0010.010.11S Y S T E M V O L T A G E (V )SYSTEM OUTPUT CURRENT (A)3.253.263.273.283.293.303.313.323.333.343.3509370-005Figure 5. System Voltage Regulation vs. Output Current, V IN = 5.0 V70001002003004005006002.73.0 3.3 3.6 3.94.2B A T T E R Y C H A R G E C U R R E NT (m A )BATTERY VOLTAGE (V)09370-006Figure 6. USB Compliant Charge Current vs. Battery Voltage,V IN = 5.0 V, ILIM = 500 mA 0.010.11SYSTEM OUTPUT CURRENT (A)1000102030405060709080E F F I C I EN C Y (%)09370-007Figure 7. System Voltage Efficiency vs. Output Current, V IN = 5.0 V2.73.0 3.3 3.6 3.94.2BATTERY VOLTAGE (V)4.52.52.72.93.13.33.53.73.94.34.1S Y S T E M V O L T A G E (V)09370-008Figure 8. System Voltage vs. Battery Voltage, V IN = 5.0 V, ILIM = 100 mA2.73.0 3.3 3.6 3.94.2BATTERY VOLTAGE (V)140020406080100120B A T T E R Y C H A R GE C U R R E N T (m A )09370-009Figure 9. USB Limited Battery Charge Current vs. Battery Voltage,V IN = 5.0 V, ILIM = 100 mAADP5065Data SheetRev. B | Page 10 of 402.73.0 3.3 3.6 3.94.2BATTERY VOLTAGE (V)100707580859095R O N R E S I S TA N C E (m Ω)09370-010Figure 10. Battery Isolation FET Resistance vs. Battery Voltage, V IN = 5.0 V,Load Current = 1.0 A123456VIN VOLTAGE (V)1.61.41.21.00.80.60.40.20V I N C U R R E NT (m A )09370-011Figure 11. VINx Current vs. VINx Voltage, Suspend Mode (EN_CHG = 0)50100150CHARGE TIME (Minutes)4.44.24.03.83.63.43.23.00.70.60.50.40.30.200.1B A T T E R Y V O L T A G E (V )C U R R E N T (A)09370-012Figure 12. Charge Profile, V IN = 5.0 V, ILIM = 500 mA,Battery Capacity = 1320 mAh分销商库存信息: ANALOG-DEVICES ADP5065ACBZ-1-R7。