EEVHD1A331P中文资料

合集下载

HDSP-3351中文资料

Features• Low Power Consumption • Industry Standard Size• Industry Standard Pinout • Choice of Character Size7.6 mm (0.30 in), 10 mm (0.40 in), 10.9 mm (0.43 in), 14.2 mm (0.56 in), 20 mm (0.80 in)• Choice of ColorsAlGaAs Red, High Efficiency Red (HER), Yellow, Green• Excellent Appearance Evenly Lighted Segments±50° Viewing Angle• Design FlexibilityCommon Anode or Common CathodeSingle and Dual DigitLeft and Right Hand Decimal Points±1. Overflow Character• Categorized for Luminous IntensityYellow and Green Categorized for ColorUse of Like Categories Yields a Uniform Display• Excellent for Long Digit String Multiplexing DescriptionThese low current seven segment displays are designed for applica-tions requiring low power consumption. They are tested and selected for their excellent low current characteristics to ensure that the segments are matched at low currents. Drive currents as low as 1 mA per segment are available.Pin for pin equivalent displays are also available in a standard current or high light ambient design. The standard current displays are available in all colors and are ideal for most applica-tions. The high light ambient displays are ideal for sunlight ambients or long string lengths. For additional information see the 7.6 mm Micro Bright Seven Segment Displays, 10 mm Seven Segment Displays, 7.6 mm/10.9 mm Seven Segment Displays, 14.2 mm Seven Segment Displays, 20 mm Seven Segment Displays, or High Light Ambient Seven Segment Displays data sheets.Low Current Seven SegmentDisplays Technical Data HDSP-335x SeriesHDSP-555x SeriesHDSP-751x SeriesHDSP-A10x Series HDSP-A80x Series HDSP-A90x Series HDSP-E10x Series HDSP-F10x Series HDSP-G10x Series HDSP-H10x Series HDSP-K12x, K70x Series HDSP-N10x SeriesHDSP-N40x SeriesDevicesAlGaAs HER Yellow Green Package HDSP-HDSP-HDSP-HDSP-Description Drawing A1017511A801A9017.6 mm Common Anode Right Hand Decimal A A1037513A803A9037.6 mm Common Cathode Right Hand Decimal B A1077517A807A9077.6 mm Common Anode ±1. Overflow C A1087518A808A9087.6 mm Common Cathode ±1. Overflow D F10110 mm Common Anode Right Hand Decimal E F10310 mm Common Cathode Right Hand Decimal F F10710 mm Common Anode ±1. Overflow G F10810 mm Common Cathode ±1. Overflow H G10110 mm Two Digit Common Anode Right Hand Decimal X G10310 mm Two Digit Common Cathode Right Hand Decimal Y E100335010.9 mm Common Anode Left Hand Decimal I E101335110.9 mm Common Anode Right Hand Decimal J E103335310.9 mm Common Cathode Right Hand Decimal K E106335610.9 mm Universal ±1. Overflow[1]L H101555114.2 mm Common Anode Right Hand Decimal M H103555314.2 mm Common Cathode Right Hand Decimal N H107555714.2 mm Common Anode ±1. Overflow O H108555814.2 mm Common Cathode ±1. Overflow P K121K70114.2 mm Two Digit Common Anode Right Hand Decimal R K123K70314.2 mm Two Digit Common Cathode Right Hand Decimal S N10020 mm Common Anode Left Hand Decimal Q N101N40120 mm Common Anode Right Hand Decimal T N103N40320 mm Common Cathode Right Hand Decimal U N10520 mm Common Cathode Left Hand Decimal V N106N40620 mm Universal ±1. Overflow[1]W Note:1. Universal pinout brings the anode and cathode of each segment’s LED out to separate pins. See internal diagrams L or W.Part Numbering System5082-x xx x-x x x xxHDSP-x xx x-x x x xxMechanical Options[1]00: No mechanical optionColor Bin Options[1,2]0: No color bin limitationMaximum Intensity Bin[1,2]0: No maximum intensity bin limitationMinimum Intensity Bin[1,2]0: No minimum intensity bin limitationDevice Configuration/Color[1]G: GreenDevice Specific Configuration[1]Refer to respective datasheetPackage[1]Refer to Respective datasheetNotes:1. For codes not listed in the figure above, please refer to the respective datasheet or contact your nearest Agilent representative fordetails.2. Bin options refer to shippable bins for a part-number. Color and Intensity Bins are typically restricted to 1 bin per tube (excep-tions may apply). Please refer to respective datasheet for specific bin limit information.Package DimensionsPackage Dimensions (cont.)Package Dimensions (cont.)*The Side View of package indicates Country of Origin.Package Dimensions (cont.)Package Dimensions (cont.)Package Dimensions (cont.)Internal Circuit DiagramInternal Circuit Diagram (cont.)Absolute Maximum RatingsAlGaAs Red - HDSP-HERA10X/E10X/H10X HDSP-751X/Yellow GreenK12X/N10X/N40X335X/555X/HDSP-A80X HDSP-A90X Description F10X, G10X Series K70X Series Series Series Units Average Power per Segment or DP375264mW Peak Forward Current per 45mA Segment or DPDC Forward Current per15[1]15[2]mA Segment or DPOperating Temperature Range-20 to +100-40 to +100°C Storage Temperature Range -55 to +100°C Reverse Voltage per Segment 3.0V or DPWave Soldering Temperature for 3Seconds (1.60 mm [0.063 in.] below 250°C seating body)Notes:1. Derate above 91°C at 0.53 mA/°C.2. Derate HER/Yellow above 80°C at 0.38 mA/°C and Green above 71°C at 0.31 mA/°C.Electrical/Optical Characteristics at T A = 25°CAlGaAs RedDeviceSeriesHDSP-Parameter Symbol Min.Typ.Max.Units Test Conditions315600I F = 1 mA A10x3600I F = 5 mA330650I F = 1 mAF10x, G10x3900I F = 5 mA390650I F = 1 mA E10x Luminous Intensity/Segment[1,2]I Vµcd(Digit Average)3900I F = 5 mA400700I F = 1 mAH10x, K12x4200I F = 5 mA270590I F = 1 mAN10x, N40x3500I F = 5 mA1.6I F = 1 mAForward Voltage/Segment or DP V F 1.7V I F = 5 mA1.82.2I F = 20 mA PkAll Devices Peak WavelengthλPEAK645nmDominant Wavelength[3]λd637nmReverse Voltage/Segment or DP[4]V R 3.015V I R = 100 µATemperature Coefficient of∆V F/°C-2 mV mV/°CV F/Segment or DPA10x255F10x, G10x320E10x340Thermal Resistance LED RθJ-PIN°C/W/SegH10x, K12x Junction-to-Pin400N10x, N40x430High Efficiency RedDeviceSeriesHDSP-Parameter Symbol Min.Typ.Max.Units Test Conditions160270I F = 2 mA 751x1050I F = 5 mA200300I F = 2 mA Luminous Intensity/Segment[1,2]I V mcd(Digit Average)1200I F = 5 mA335x, 555x,K70x270370I F = 2 mA1480I F = 5 mA1.6I F = 2 mAForward Voltage/Segment or DP V F 1.7V I F = 5 mA2.1 2.5I F = 20 mA Pk All Devices Peak WavelengthλPEAK635nmDominant Wavelength[3]λd626nmReverse Voltage/Segment or DP[4]V R 3.030V I R = 100 µATemperature Coefficient of∆V F/°C-2mV/°CV F/Segment or DP751x200335x Thermal Resistance LED RθJ-PIN280°C/WJunction-to-Pin555x, K70x345YellowDeviceSeriesHDSP-Parameter Symbol Min.Typ.Max.Units Test Conditions Luminous Intensity/Segment[1,2]250420I F = 4 mA(Digit Average)I V mcd1300I F = 10 mA1.7I F = 4 mAForward Voltage/Segment or DP V F 1.8V I F = 5 mA A80x2.1 2.5I F = 20 mA PkPeak WavelengthλPEAK583nmDominant Wavelength[3,5]λd581.5585592.5nmReverse Voltage/Segment or DP[4]V R 3.030V I R = 100 µATemperature Coefficient of∆V F/°C-2mV/°CV F/Segment or DPThermal Resistance LED RθJ-PIN200°C/WJunction-to-PinGreenDeviceSeriesHDSP-Parameter Symbol Min.Typ.Max.Units Test Conditions Luminous Intensity/Segment[1,2]250475I F = 4 mA(Digit Average)I V mcd1500I F = 10 mA1.9I F = 4 mAForward Voltage/Segment or DP V F 2.0V I F = 10 mA A90x2.1 2.5I F = 20 mA PkPeak WavelengthλPEAK566nmDominant Wavelength[3,5]λd571577nmReverse Voltage/Segment or DP[4]V R 3.030V I R = 100 µATemperature Coefficient of∆V F/°C-2mV/°CV F/Segment or DPThermal Resistance LED RθJ-PIN200°C/WJunction-to-PinNotes:1. Device case temperature is 25°C prior to the intensity measurement.2. The digits are categorized for luminous intensity. The intensity category is designated by a letter on the side of the package.3. The dominant wavelength, λd, is derived from the CIE chromaticity diagram and is the single wavelength which defines the color of thedevice.4. Typical specification for reference only. Do not exceed absolute maximum ratings.5. The yellow (HDSP-A800) and Green (HDSP-A900) displays are categorized for dominant wavelength. The category is designated by anumber adjacent to the luminous intensity category letter.AlGaAs RedIntensity Bin Limits (mcd)AlGaAs RedHDSP-A10xIV Bin Category Min.Max.E0.3150.520F0.4280.759G0.621 1.16H0.945 1.71I 1.40 2.56J 2.10 3.84K 3.14 5.75L 4.708.55HDSP-E10x/F10x/G10xIV Bin Category Min.Max.D0.3910.650E0.5320.923F0.755 1.39G 1.13 2.08H 1.70 3.14HDSP-H10x/K12xIV Bin Category Min.Max.C0.4150.690D0.5650.990E0.810 1.50F 1.20 2.20G 1.80 3.30H 2.73 5.00I 4.097.50HDSP-N10xIV Bin Category Min.Max.A0.2700.400B0.3250.500C0.4150.690D0.5650.990E0.810 1.50F 1.20 2.20G 1.80 3.30H 2.73 5.00I 4.097.50Intensity Bin Limits (mcd), continued HERHDSP-751xIV Bin Category Min.Max.B0.1600.240C0.2000.300D0.2500.385E0.3150.520F0.4280.759G0.621 1.16HDSP-751xIV Bin Category Min.Max.B0.2400.366C0.3000.477D0.3910.650E0.5320.923F0.755 1.39G 1.13 2.08H 1.70 3.14HDSP-555x/K70xIV Bin Category Min.Max.A0.2700.400B0.3250.500C0.4150.690D0.5650.990E0.810 1.50F 1.20 2.20G 1.80 3.30H 2.73 5.00I 4.097.50Intensity Bin Limits (mcd), continued YellowHDSP-A80xIV Bin Category Min.Max.D0.2500.385E0.3150.520F0.4250.760G0.625 1.14H0.940 1.70I 1.40 2.56J 2.10 3.84K 3.14 5.76L 4.718.64M7.0713.00N10.6019.40O15.9029.20P23.9043.80Q35.8065.60GreenHDSP-A90xIV Bin Category Min.Max.E0.3150.520F0.4250.760G0.625 1.14H0.940 1.70I 1.40 2.56J 2.10 3.84K 3.14 5.76L 4.718.64M7.0713.00N10.6019.40O15.9029.20P23.9043.80Q35.8065.60Electrical/OpticalFor more information on electrical/optical characteristics, please see Application Note 1005.Contrast Enhancement For information on contrast enhancement, please see Application Note 1015.Soldering/Cleaning Cleaning agents from the ketone family (acetone, methyl ethyl ketone, etc.) and from the chorinated hydrocarbon family (methylene chloride, trichloro-ethylene, carbon tetrachloride, etc.) are not recommended for cleaning LED parts. All of these various solvents attack or dissolve the encapsulating epoxies used to form the package of plastic LED parts.For information on soldering LEDs, please refer to Application Note 1027.Note:All categories are established for classification of products. Productsmay not be available in all categories. Please contact your localAgilent representatives for further clarification/information.Color Categories/semiconductorsFor product information and a complete list ofdistributors, please go to our web site.For technical assistance call:Americas/Canada: +1 (800) 235-0312 or(916) 788 6763Europe: +49 (0) 6441 92460China: 10800 650 0017Hong Kong: (+65) 6271 2451India, Australia, New Zealand: (+65) 6271 2394Japan: (+81 3) 3335-8152(Domestic/International), or0120-61-1280(Domestic Only)Korea: (+65) 6271 2194Malaysia, Singapore: (+65) 6271 2054Taiwan: (+65) 6271 2654Data subject to change.Copyright © 2005 Agilent Technologies, Inc.Obsoletes 5988-8412ENJanuary 19, 20055989-0080EN。

单片机内的Flash与EEPROM作用及区别

单片机运行‎时的数据都‎存在于RA‎M（随机存‎储器）中，‎在掉电后R‎A M 中的‎数据是无‎法保留的，‎那么怎样使‎数据在掉电‎后不丢失呢‎？这就需要‎使用EEP‎R OM或‎F LASH‎R OM 等‎存储器来‎实现。

在传‎统的单片机‎系统中，一‎般是在片外‎扩展存储器‎，单片机与‎存储器之间‎通过II‎C或SP‎I等接口‎来进行数据‎通信。

这样‎不光会增加‎开发成本，‎同时在程序‎开发上也要‎花更多的‎心思。

在S‎T C 单片‎机中内置了‎E EPRO‎M（其实是‎采用IAP‎技术读写‎内部FLA‎S H 来‎实现EEP‎R OM），‎这样就节省‎了片外资源‎，使用起来‎也更加方便‎。

下面就详‎细介绍ST‎C单片‎机内置EE‎P ROM ‎及其使用方‎法。

‎f lash‎是用来放程‎序的，可以‎称之为程序‎存储器，可‎以擦出写入‎但是基本都‎是整个扇区‎进行的.‎一般来说‎单片机里的‎f lash‎都用于存放‎运行代码，‎在运行过程‎中不能改；‎EEP‎R OM是用‎来保存用户‎数据，运行‎过程中可以‎改变，比如‎一个时钟的‎闹铃时间初‎始化设定为‎12：00‎，后来在运‎行中改为6‎：00，这‎是保存在E‎E PROM‎里，不怕掉‎电，就算重‎新上电也不‎需要重新调‎整到6：0‎0下面‎是网上详细‎的说法，感‎觉不错：‎F LASH‎和EEP‎R OM的最‎大区别是F‎L ASH按‎扇区操作，‎E EPRO‎M则按字节‎操作，二者‎寻址方法不‎同，存储单‎元的结构也‎不同，FL‎A SH的电‎路结构较简‎单，同样容‎量占芯片面‎积较小，成‎本自然比E‎E PROM‎低，因而适‎合用作程序‎存储器，E‎E PROM‎则更多的用‎作非易失的‎数据存储器‎。

当然用F‎L ASH做‎数据存储器‎也行，但操‎作比EEP‎R OM麻烦‎的多，所以‎更“人性化‎”的MCU‎设计会集成‎F LASH‎和EEPR‎O M两种非‎易失性存储‎器，而廉价‎型设计往往‎只有 FL‎A SH，早‎期可电擦写‎型MCU则‎都是EEP‎R M结构，‎现在已基本‎上停产了。

XP143 Specification-Chinese

种类 Side
Side
Side
Side
Side
Side
121212121212
供料平台
MFU-X10E 固定
○○○
○○○
○○○
废料带切刀
○○○
○○○Leabharlann 废料带BOX○○○
○○○
LCD触摸屏
○○○
○○○
○○○
对应AA模式
△
吸嘴自动更换器
△
△
△
△
△
△
对应BGA，CSP
△
△
△
真空支撑销
△
△
△
△
△
△
软件版本更新
IEC规格※4，UL规格，CE标记
※1．电源：可以选择200,210,220,230,380,400,415,460,480V （变压器组的插座切换方式）为了避开杂讯、电压波动、高频失真等的影响，避免与其他机器共用，推荐使用专用的电源。
※2．气源应该在大气压露点:－17℃ 以下、微粉尘:粒径5μm以下、油的最高浓度:5mg/m3以下。 ※3．湿度是保持不结露。此外，本公司推介的环境条件是，温度15℃～30℃以及湿度50%～70%。 ※4．IP22：对应IEC规格（对于人体、固体杂物以及水的浸入的保护）
-3-
XP143-020505RS
1. 概要
1.2.4 丰富的吸嘴配置
１）小芯片专用的吸嘴配置例在吸嘴尺寸φ0.37～φ2.5mm的配置上，可以吸取12个4532尺寸以内的元件进行贴装。
φ0 .7 φ1 .0 φ1 .3 φ1 .8 φ2 .5
２）贴装小芯片／中型元件的吸嘴配置例
吸取８个4532以内的元件贴装，贴装小芯片后，吸取4个超过4532 □10mm以内的元件进行贴装。

MB2411E1W01;MB2411E1W03;MB2411E1G01;MB2411S1W01;MB2411E1W03-FA;中文规格书,Datasheet资料

A
Rated 3A @ 125V AC & 0.4VA max @ 28V
Power Level (silver): 3A @ 125V AC Logic Level (gold): 0.4VA maximum @ 28V AC/DC maximum (Applicable Range 0.1mA ~ 0.1A @ 20mV ~ 28V)
Logic/Power Level: Combines silver & gold ratings (gold over silver) Note: Find additional explanation of dual rating & operating range in Supplement section.
To g g l e s
Rockers
Keylocks Programmable Illuminated PB Pushbuttons
Rotaries
Series MB2400
Snap-Action Pushbuttons
General Specifications
Electrical Capacity (Resistive Load)
Slides
Ta c t i l e s
Tilt
To u c h
Supplement Accessories Indicators
C96 /
w w
To g g l e s
Rockers
Keylocks Programmable Illuminated PB Pushbuttons
TYPICAL SWITCH ORDERING EXAMPLE
MB24 11 E1 W 01 F A

ATMEGA324P中文资料

(PCINT13/MOSI) PB5 (PCINT14/MISO) PB6
(PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1
(PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2
PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVCC PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20)
PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVCC PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20) PC3 (TMS/PCINT19) PC2 (TCK/PCINT18) PC1 (SDA/PCINT17) PC0 (SCL/PCINT16) PD7 (OC2A/PCINT31)
Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program True Read-While-Write Operation – 512B/1K/2K Bytes EEPROM Endurance: 100,000 Write/Erase Cycles – 1/2/4K Bytes Internal SRAM – Programming Lock for Software Security • JTAG (IEEE std. 1149.1 Compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface • Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Six PWM Channels – 8-channel, 10-bit ADC Differential mode with selectable gain at 1x, 10x or 200x – Byte-oriented Two-wire Serial Interface – Two Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change • Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby • I/O and Packages – 32 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF • Operating Voltages – 1.8 - 5.5V for ATmega164P/324P/644PV – 2.7 - 5.5V for ATmega164P/324P/644P • Speed Grades – ATmega164P/324P/644PV: 0 - 4MHz @ 1.8 - 5.5V, 0 - 10MHz @ 2.7 - 5.5V – ATmega164P/324P/644P: 0 - 10MHz @ 2.7 - 5.5V, 0 - 20MHz @ 4.5 - 5.5V • Power Consumption at 1 MHz, 1.8V, 25°C for ATmega164P/324P/644P – Active: 338/398/TBD µA – Power-down Mode:0.035 /0.027/TBD µA – Power-save Mode:0.5 /0.5/TBD µA (Including 32 kHz RTC)

M38B51EEXXXFP资料

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself.Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.Renesas Technology Corp.Customer Support Dept.April 1, 2003To all our customers元器件交易网DESCRIPTIONThe 38B5 group is the 8-bit microcomputer based on the 740 familycore technology.The 38B5 group has six 8-bit timers, a 16-bit timer, a fluorescent display automatic display circuit, 12-channel 10-bit A-D converter, a serial I/O with automatic transfer function, which are available for controlling musical instruments and household appliances.The 38B5 group has variations of internal memory size and packag-ing. For details, refer to the section on part numbering.For details on availability of microcomputers in the 38B5 group, refer to the section on group expansion.MITSUBISHI MICROCOMPUTERS38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTERFEATURES•Basic machine-language instructions .......................................71•The minimum instruction execution time ..........................0.48 µs (at 4.19 MHz oscillation frequency)•Memory sizeROM.............................................24K to 60K bytes RAM ............................................512 to 2048 bytes•Programmable input/output ports .............................................55•High-breakdown-voltage output ports.......................................36•Software pull-up resistors ......(Ports P5, P61 to P65, P7, P84 to P87, P9)•Interrupts..................................................21 sources, 16 vectors •Timers ...........................................................8-bit ! 6, 16-bit ! 1•Serial I/O1 (Clock-synchronized)....................................8-bit ! 1......................(max. 256-byte automatic transfer function)•Serial I/O2 (UART or Clock-synchronized).....................8-bit ! 1•PWM .............................................................................14-bit ! 18-bit ! 1 (also functions as timer 6)•A-D converter..............................................10-bit ! 12 channels •Fluorescent display function ........................Total 40 control pins •Interrupt interval determination function .....................................1•Watchdog timer.............................................................20-bit ! 1•Buzzer output.............................................................................1•2 Clock generating circuitMain clock (X IN –X OUT ).........................Internal feedback resistor Sub-clock (X CIN –X COUT ).........Without internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator )•Power source voltageIn high-speed mode ...................................................4.0 to 5.5 V (at 4.19 MHz oscillation frequency and high-speed selected)In middle-speed mode ...............................................2.7 to 5.5 V (at 4.19 MHz oscillation frequency and middle-speed selected)In low-speed mode ....................................................2.7 to 5.5 V (at 32 kHz oscillation frequency and low-speed selected)•Power dissipationIn high-speed mode ..........................................................35 mW (at 4.19 MHz oscillation frequency)In low-speed mode ............................................................60 µW (at 32 kHz oscillation frequency, at 3 V power source voltage)•Operating temperature range ...................................–20 to 85 °CAPPLICATIONMusical instruments, VCR, household appliances, etc.PR E L I M I N A R Y N o t i c e: T h i s i s no t a f i n a l s p e c i f i c a t i o n .So m e p a r am e t r i c l i m i t s a r e s u b j e c t t oc h a n g e .元器件交易网38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER2PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .FUNCTIONAL BLOCK38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER3PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .PIN DESCRIPTIONTable 1 Pin Description (1)Pin Name FunctionV CC , V SS Power source • Apply voltage of 4.0–5.5 V to V CC , and 0 V to V SS .V EE Pull-down • Apply voltage supplied to pull-down resistors of ports P0, P1, and P3.power sourceV REF Reference • Reference voltage input pin for A-D converter.voltage AV SSAnalog power • Analog power source input pin for A-D converter.source • Connect to V SS .______RESET Reset input • Reset input pin for active “L.”X INClock input• Input and output pins for the main clock generating circuit.• Feedback resistor is built in between X IN pin and X OUT pin.• Connect a ceramic resonator or quartz-crystal oscillator between the X IN and X OUT pins to set the oscillation frequency.• When an external clock is used, connect the clock source to the X IN pin and leave the X OUT pin open.• The clock is used as the oscillating source of system clock.P00/FLD 8–I/O port P0• 8-bit I/O port.• FLD automatic display P07/FLD 15• I/O direction register allows each pin to be individually programmed as either pinsinput or output.• At reset, this port is set to input mode.• A pull-down resistor is built in between port P0 and the V EE pin.• CMOS compatible input level.• High-breakdown-voltage P-channel open-drain output structure.• At reset, this port is set to V EE level.P10/FLD 16–Output port P1• 8-bit output port.• FLD automatic display P17/FLD 23• A pull-down resistor is built in between port P1 and the V EE pin.pins• High-breakdown-voltage P-channel open-drain output structure.• At reset, this port is set to V EE level.P20/B UZ02/I/O port P2• 8-bit I/O port with the same function as port P0.• FLD automatic display FLD 0–• Low-voltage input level.pinsP27/FLD 7• High-breakdown-voltage P-channel open-drain output structure.• Buzzer output pin (P20)P30/FLD 24–Output port P3• 8-bit output port.• FLD automatic display P37/FLD 31• A pull-down resistor is built in between port P3 and the V EE pin.pins• High-breakdown-voltage P-channel open-drain output structure.• At reset, this port is set to V EE level.P40/INT 0,I/O port P4• 7-bit I/O port with the same function as port P0.• Interrupt input pinsP41/INT 1,• CMOS compatible input level.P42/INT 3• N-channel open-drain output structure.P43/B UZ01• Buzzer output pin P44/PWM 1• PWM output pin (Timer output pin)P45/T 1OUT ,• Timer output pinP46/T 3OUT P47/INT 2Input port P4• 1-bit input port.• Interrupt input pin• CMOS compatible input level.Function except a port functionX OUT Clock output38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER4PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .Table 2 Pin Description (2)Function except a port function Pin Name FunctionP50/S IN1,I/O port P5• 8-bit CMOS I/O port with the same function as port P0.• Serial I/O1 function pinsP51/S OUT1,• CMOS compatible input level.P52/S CLK11,• CMOS 3-state output structure.P53/S CLK12P54/R X D,• Serial I/O2 function pinsP55/T X D,P56/S CLK21,________P57/S RDY2/S CLK22P60/CNTR 1I/O port P6• 1-bit I/O port with the same function as port P0.• Timer input pin• CMOS compatible input level.• N-channel open-drain output structure.P61/CNTR 0/• 5-bit CMOS I/O port with the same function as port P0.• Timer I/O pinCNTR 2• CMOS compatible input level.________P62/S RDY1/• CMOS 3-state output structure.• Serial I/O1 function pin AN 8• A-D conversion input pin P63/AN 9• A-D conversion input pin P64/INT 4/• Serial I/O1 function pin S BUSY1/AN 10,• A-D conversion input pin P65/S STB1/• Interrupt input pin (P64)AN 11P70/AN 0–I/O port P7• 8-bit CMOS I/O port with the same function as port P0.• A-D conversion input pinP77/AN 7• CMOS compatible input level.• CMOS 3-state output structure.P80/FLD 32–I/O port P8• 4-bit I/O port with the same function as port P0.• FLD automatic display pins P83/FLD 35• Low-voltage input level.• High-breakdown-voltage P-channel open-drain output structure.P84/FLD 36• 4-bit CMOS I/O port with the same function as port P0.P85/RTP 0/• Low-voltage input level.• FLD automatic display pins FLD 37,P86/RTP 1/FLD 38P87/PWM 0/• FLD automatic display pins FLD 39• 14-bit PWM output P90/X CIN ,I/O port P9• 2-bit CMOS I/O port with the same function as port P0.• I/O pins for sub-clock generatingP91/X COUT• CMOS compatible input level. circuit (connect a ceramic resona-• CMOS 3-state output structure.tor or a quarts-crystal oscillator)38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER5PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .PART NUMBERINGFig. 3 Part Numbering38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER6PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .GROUP EXPANSIONMitsubishi plans to expand the 38B5 group as follows:Memory TypeSupport for Mask ROM, One Time PROM and EPROM versions.Memory SizeROM/PROM size ..................................................24K to 60K bytes RAM size ...........................................................1024 to 2048 bytesPackage80P6N-A .....................................0.8 mm-pitch plastic molded QFP 80D0........................0.8 mm-pitch ceramic LCC (EPROM version)Currently supported products are listed below.Table 3 List of Supported Products(P) ROM size (bytes)Product RAM size (bytes)Package RemarksROM size for User ( )As of Jan. 1998M38B57MC-XXXFP49152(49022)102480P6N-AMask ROM version38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER7PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)The 38B5 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instruc-tions or the 740 Family Software Manual for details on the instruction set.Machine-resident 740 Family instructions are as follows:•The FST and SLW instructions cannot be used.•The MUL, DIV, WIT and STP instructions can be used.Fig. 5 Structure of CPU Mode Register[CPU Mode Register] CPUMThe CPU mode register contains the stack page selection bit and internal system clock control bits. The CPU mode register is allo-cated at address 003B 16.38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER8PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .MemorySpecial function register (SFR) areaThe special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.RAMRAM is used for data storage and for stack area of subroutine calls and interrupts.ROMThe first 128 bytes and the last 2 bytes of ROM are reserved for device testing, and the other areas are user areas for storing pro-grams.Interrupt vector areaThe interrupt vector area contains reset and interrupt vectors.Zero pageThe 256 bytes from addresses 000016 to 00FF 16 are called the zero page area. The internal RAM and the special function registers (SFR)are allocated to this area.The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.Special pageThe 256 bytes from addresses FF0016 to FFFF 16 are called the spe-cial page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.Fig. 6 Memory Map Diagram38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER9PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .Fig. 7 Memory Map of Special Function Register (SFR)I/O Ports[Direction Registers] PiD Array The 38B5 group has 55 programmable I/O pins arranged in eightindividual I/O ports (P0, P2, P40–P46, and P5–P9). The I/O portshave direction registers which determine the input/output direction ofeach individual pin. Each bit in a direction register corresponds toone pin, and each pin can be set to be input port or output port. When“0” is written to the bit corresponding to a pin, that pin becomes aninput pin. When “1” is written to that pin, that pin becomes an outputpin. If data is read from a pin set to output, the value of the portoutput latch is read, not the value of the pin itself. Pins set to input(the bit corresponding to that pin must be set to “0”) are floating andthe value of that pin can be read. If a pin set to input is written to, onlythe port output latch is written to and the pin remains floating.[High-Breakdown-Voltage Output Ports]The 38B5 group microprocessors have 5 ports with high-breakdown-voltage pins (ports P0–P3and P80–P83). The high-breakdown-volt-age ports have P-channel open-drain output with Vcc- 45 V of break-down voltage. Each pin in ports P0, P1, and P3 has an internal pull-down resistor connected to V EE. At reset, the P-channel output tran-sistor of each port latch is turned off, so that it goes to V EE level (“L”)by the pull-down resistor.Writing “1” (weak drivability) to bit 7 of the FLDC mode register (ad-dress 0EF416) shows the rising transition of the output transistors forreducing transient noise. At reset, bit 7 of the FLDC mode register isset to “0” (strong drivability).[Pull-up Control Register] PULLPorts P5, P61–P65, P7, P84–P87 and P9 have built-in programmablepull-up resistors. The pull-up resistors are valid only in the case thatthe each control bit is set to “1” and the corresponding port directionregisters are set to input mode.Fig. 8 Structure of Pull-up Control Registers (PULL1 and PULL2)SINGLE-CHIP 8-BIT CMOS MICROCOMPUTERTable 4 List of I/O Port Functions (1)Pin Name Input/Output I/O Format Non-Port Function Related SFRs Ref.No. P00/FLD8–Port P0Input/output,CMOS compatible input level FLD automatic display function FLDC mode register(1)P07/FLD15individual bits High-breakdown voltage P-Port P0FLD/port switch registerchannel open-drain outputwith pull-down resistorP10/FLD16–Port P1Output High-breakdown voltage P-FLDC mode register(2)P17/FLD23channel open-drain outputwith pull-down resistorP20/B UZ02/Port P2Input/output,Low-voltage input level Buzzer output (P20)FLDC mode register(3) FLD0individual bits High-breakdown voltage P-Port P2FLD/port switch registerP21/FLD1–channel open-drain output Buzzer output control register(1)P27/FLD7P30/FLD24–Port P3Output High-breakdown voltage P-FLDC mode register(2)P37/FLD31channel open-drain outputwith pull-down resistorP40/INT0,Port P4Input/output,CMOS compatible input level External interrupt input Interrupt edge selection register(4)P41/INT1,individual bits N-channel open-drain outputP42/INT3P43/B UZ01Buzzer output Buzzer output control register(5)P44/PWM1PWM output Timer 56 mode register(6)P45/T1OUT Timer output Timer 12 mode register(7)P46/T3OUT Timer output Timer 34 mode register(7)P47/INT2Input CMOS compatible input level External interrput input I nterrupt edge selection register(8)Interrupt interval determinationcontrol registerP50/SIN1Port P5Input/output,CMOS compatible input level Serial I/O1 function I/O Serial I/O1 control register 1, 2(9)P51/S OUT1,individual bits CMOS 3-state output(10)P52/S CLK11,P53/S CLK12P54/R X D,Serial I/O2 function I/O Serial I/O2 control register(9)P55/T X D,UART control register(10)P56/S CLK21________P57/S RDY2/(11)S CLK22P60/CNTR1Port P6CMOS compatible input level External count I/O Interrupt edge selection register(4)N-channel open-drain outputP61/CNTR0/CMOS compatible input level(12) CNTR2CMOS 3-state output________P62/S RDY1/Serial I/O1 function I/O Serial I/O1 control register 1, 2(13) AN8A-D conversion input A-D control registerP63/AN9A-D conversion input A-D control register(14)P64/INT4/Serial I/O1 function I/O Serial I/O1 control register 1, 2(15)S BUSY1/AN10A-D conversion input A-D control registerExternal interrupt input Interrupt edge selection registerP65/S STB1/Serial I/O1 function I/O Serial I/O1 control register 1, 2(16) AN11A-D conversion input A-D control registerP70/AN0–Port P7A-D conversion input A-D control register(14)P77/AN7Table 5 List of I/O Port Functions (2)Pin Name Input/Output I/O Format Non-Port Function Related SFRs Ref.No. P80/FLD32–Port P8Input/output,Low-voltage input level FLD automatic display function FLDC mode register(1)P83/FLD35individual bits High-breakdown voltage P-Port P8FLD/port switch registerchannel open-drain outputP84/FLD36Low-voltage input level(17) P85/RTP0/CMOS 3-state output FLD automatic display function FLDC mode register(18) FLD37,Real time port output Port P8FLD/port switch registerP86/RTP1/Timer X mode register 2FLD38P87/PWM0/FLD automatic display function FLDC mode register(19) FLD39PWM output Port P8FLD/port switch registerPWM control registerP90/X CIN Port P9CMOS compatible input level Sub-clock generating circuit I/O CPU mode register(20) P91/X COUT CMOS 3-state output(21) Notes 1 : How to use double-function ports as function I/O ports, refer to the applicable sections.2 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction.When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.SINGLE-CHIP 8-BIT CMOS MICROCOMPUTERSINGLE-CHIP 8-BIT CMOS MICROCOMPUTERInterruptsInterrupts occur by twenty one sources: five external, fifteen internal, and one software.(1) Interrupt ControlEach interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0.” Interrupt enable bits can be set or cleared by software. Inter-rupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occurs at the same time the interrupt with highest priority is accepted first.(2) Interrupt OperationUpon acceptance of an interrupt the following operations are auto-matically performed:1. The contents of the program counter and processor statusregister are automatically pushed onto the stack.2. The interrupt disable flag is set and the correspondinginterrupt request bit is cleared.3. The interrupt jump destination address is read from the vectortable into the program counter.s Notes on UseWhen the active edge of an external interrupt (INT0–INT4) is set or when switching interrupt sources in the same vector address, the corresponding interrupt request bit may also be set. Therefore, please take following sequence:(1) Disable the external interrupt which is selected.(2) Change the active edge in interrupt edge selection register(3) Clear the set interrupt request bit to “0.”(4) Enable the external interrupt which is selected.SINGLE-CHIP 8-BIT CMOS MICROCOMPUTERTable 6 Interrupt Vector Addresses and PriorityVector Addresses (Note 1)Interrupt RequestInterrupt Source Priority RemarksHigh Low Generating ConditionsReset (Note 2)1FFFD16FFFC16At reset Non-maskableINT02FFFB16FFFA16At detection of either rising or falling edge of External interruptINT0 input(active edge selectable)INT13FFF916FFF816At detection of either rising or falling edge of External interruptINT1 input(active edge selectable)INT24FFF716FFF616At detection of either rising or falling edge of External interruptINT2 input(active edge selectable)Remort control/At 8-bit counter overflow Valid when interrupt interval counter overflow determination is operatingSerial I/O15FFF516FFF416At completion of data transfer Valid when serial I/O1 ordinarymode is selectedSerial I/O1 auto-At completion of the last data transfer Valid when serial I/O1 automatic matic transfer transfer mode is selectedTimer X6FFF316FFF216At timer X underflowTimer 17FFF116FFF016At timer 1 underflowTimer 28FFEF16FFEE16At timer 2 underflow STP release timer underflowTimer 39FFED16FFEC16At timer 3 underflowTimer 410FFEB16FFEA16At timer 4 underflowTimer 511FFE916FFE816At timer 5 underflowTimer 612FFE716FFE616At timer 6 underflowSerial I/O2 receive13FFE516FFE416At completion of serial I/O2 data receiveINT314FFE316FFE216At detection of either rising or falling edge of External interruptINT3 input(active edge selectable)Serial I/O2 transmit At completion of data transmitINT415FFE116FFE016At detection of either rising or falling edge of External interruptINT4 input(active edge selectable)Valid when INT4 interrupt is selectedA-D conversion At completion of A-D conversion Valid when A-D conversion is selected FLD blanking16FFDF16FFDE16At falling edge of the last timing immediately Valid when FLD blankingbefore blanking period starts interrupt is selectedFLD digit At rising edge of each digit Valid when FLD digit interrupt is selected BRK instruction17FFDD16FFDC16At BRK instruction execution Non-maskable software interrupt Notes 1 : Vector addresses contain interrupt jump destination addresses.2 : Reset function in the same way as an interrupt with the highest priority.SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timers Array 8-Bit TimerThe 38B5 group has six built-in timers : Timer 1, Timer 2, Timer 3,Timer 4, Timer 5, and Timer 6.Each timer has the 8-bit timer latch. All timers are down-counters.When the timer reaches “0016,” an underflow occurs with the nextcount pulse. Then the contents of the timer latch is reloaded into thetimer and the timer continues down-counting. When a timerunderflows, the interrupt request bit corresponding to that timer isset to “1.”The count can be stopped by setting the stop bit of each timer to “1.”The internal system clock can be set to either the high-speed modeor low-speed mode with the CPU mode register. At the same time,timer internal count source is switched to either f(X IN) or f(X CIN).q Timer 1, Timer 2The count sources of timer 1 and timer 2 can be selected by settingthe timer 12 mode register. A rectangular waveform of timer 1underflow signal divided by 2 is output from the P45/T1OUT pin. Thewaveform polarity changes each time timer 1 overflows. The activeedge of the external clock CNTR0 can be switched with the bit 6 ofthe interrupt edge selection register.At reset or when executing the STP instruction, all bits of the timer 12mode register are cleared to “0,” timer 1 is set to “FF16,” and timer 2is set to “0116.”q Timer 3, Timer 4The count sources of timer 3 and timer 4 can be selected by settingthe timer 34 mode register. A rectangular waveform of timer 3underflow signal divided by 2 is output from the P46/T3OUT pin. Thewaveform polarity changes each time timer 3 overflows. The activeedge of the external clock CNTR1 can be switched with the bit 7 ofthe interrupt edge selection register.q Timer 5, Timer 6The count sources of timer 5 and timer 6 can be selected by settingthe timer 56 mode register. A rectangular waveform of timer 6underflow signal divided by 2 is output from the P44/PWM1 pin. Thewaveform polarity changes each time timer 6 overflows.q Timer 6 PWM1 ModeTimer 6 can output a rectangular waveform with “H” duty cycle n/(n+m) from the P44/PWM1 pin by setting the timer 56 mode register(refer to Figure 16). The n is the value set in timer 6 latch (address002516) and m is the value in the timer 6 PWM register (address002716). If n is “0,” the PWM output is “L,” if m is “0,” the PWM outputis “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occurat the rising edge of the PWM output.38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER20PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .38B5 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTER21PR E L I M I N A R Y N o t i c e : T h i s i s n o t a f i n a l s p e c i f i c a t i o n .S om e p a r a m e t r i c l i mi t s a r e s u b j e c tt o c h a n g e .116-Bit TimerTimer X is a 16-bit timer that can be selected in one of four modes by the Timer X mode register 1, 2 and can be controlled the timer X write and the real time port by setting the timer X mode registers. Read and write operation on 16-bit timer must be performed for both high- and low-order bytes. When reading a 16-bit timer, read from the high-order byte first. When writing to 16-bit timer, write to the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during write operation, or when writing during read operation.q Timer XTimer X is a down-counter. When the timer reaches “000016,” an underflow occurs with the next count pulse. Then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. When a timer underflows, the interrupt request bit corre-sponding to that timer is set to “1.”(1) Timer modeA count source can be selected by setting the Timer X count source selection bits (bits 1 and 2) of the Timer X mode register 1.(2) Pulse output modeEach time the timer underflows, a signal output from the CNTR2 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR2 pin to output.(3) Event counter modeThe timer counts signals input through the CNTR2 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR2 pin to input.(4) Pulse width measurement modeA count source can be selected by setting the Timer X count source selection bits (bits 1 and 2) of the Timer X mode register 1. When CNTR2 active edge switch bit is “0,” the timer counts while the input signal of the CNTR2 pin is at “H.” When it is “1,” the timer counts while the input signal of the CNTR2 pin is at “L.” When using a timer in this mode, set the port shared with the CNTR2 pin to input.s Note•Timer X Write ControlIf the timer X write control bit is “0,” when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time.If the timer X write control bit is “1,” when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows.When the value is written in latch only, unexpected value may be set in the high-order counter if the writing in high-order latch and the underflow of timer X are performed at the same timing.•Real Time Port ControlWhile the real time port function is valid, data for the real time port are output from ports P85 and P86 each time the timer X underflows. (However, if the real time port control bit is changed from “0” to “1,”data are output without the timer X.) When the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X.Before using this function, set the corresponding port direction regis-ters to output mode.22。

艾威图w系列伺服说明书

FG 43
19
机壳地
位置控制的标准接线
1
电机 4 芯插头
光电编码器 15 芯插头
编码器信号输出编码器 Z 信号集电极开路输出编码器信号地
PDF 文件使用 "pdfFactory Pro" 试用版本创建 w–w１w.０fi–
驱动器的连接
速度控制接线图
三相AC220V（≥1.0KW）单相AC220V（<1.0KW）
功率零速转矩额定转速额定电流
（Kw）（Nm）（Rpm）（A）
0.4
2
3000
4
0.75
2
3000
4
0.6
2
3000
4
1.2
4
3000
5
1.5
5
3000
6
1.2
6
2000
6
1.8
6
3000
8
0.6
4
2500
4
1.0
4
2500
4
1.3
5
2500
5
1.5
6
2500
6
1.6
7.7
2000
6
2.4
7.7
3000
9
1.5
10
1500
6
2.6
10
2500
10
2.3
15
1500
10
PDF 文件使用 "pdfFactory Pro" 试用版本创建 ww–w７.f–
驱动器的使用
使用环境防护
伺服驱动器自身结构无防护，因此必须安装在防护良好的电柜内，并防接触腐蚀性、易燃性气体，防止导电物体、金属粉尘、油雾及液体进入内部。

EP1-3G1S中文资料

DESCRIPTIONThe NEC TOKIN EP2 / EP1 series are PC-board mount type automotive relays suitable for various motorcontrols and other applications that require a high level of quality and performance.EP2 series is a twin-relay and divided into two types for different usage.One is an H-bridge type designed for forward and reverse control of the motors, and the other, a separatetype containing two separated relays in one package.EP1 series is a 1 Form c relay equivalent to EP2 series in performance.FEATURESFor motor reversible control and solenoid controlApprox. 50% less relay space than conventional relayHigh performance and productivity by unique structureFlux tight housingAPPLICATIONSPower windowAntenna lifterAuto-seat positioningElectrical door lockPassive seat belt controlKeyless/Remote entry systemSliding roof controlThe information in this document is subject to change without notice.Date Published August 2002 MPrinted in Japan© NEC TOKIN Corporation 2002EP2 / EP1 SERIES2SCHEMATIC (BOTTOM VIEW)EP2 SERIESEP1 SERIESDIMENSIONS mm (inch)EP2 SERIESEP2/EP1 SERIES3EP1 SERIESPCB PAD LAYOUT mm (inch) (BOTTOM VIEW)EP2 SERIESEP1 SERIESEP2 / EP1 SERIES4SPECIFICATIONSat 25°C (77°F )Items EP2 EP1Contact Form1 Form c ×2 (H bridge type and separatetype)1 Form c Contact Material Silver oxide complex alloy(special type available) Contact Resistance 50 m Ω max. (measured at 7 A) initial Contact Switching Voltage 16 Vdc max. Contact Switching Current 25 A max. (at 16 Vdc) Contact Carrying Current 20 A max. (1 hour max.),25 A max. (2 minutes max.) at 12 Vdc25 A max. (1 hour max.),30 A max. (2 minutes max.) at 12 VdcOperate Time Approx. 5 ms (at 12 Vdc) initialRelease TimeApprox. 2 ms (at 12 Vdc) initial. without diode Normal Operate Power 0.48 W / 0.64 W (at 12 Vdc) Insulation Resistance 100 M Ω min. (at 500 Vdc) initial Breakdown Voltage 500 Vdc min. (for 1 minute) initialShock Resistance 98 m / s 2[10 G] min. (misoperating), 980 m / s 2[100 G] min. (destructive failure)Vibration Resistance10 to 300 Hz, 43 m/s 2[ 4.4 G] min. (misoperating)10 to 500 Hz, 43 m/s 2, [ 4.4 G] 200 hours (destructive failure) Ambient Temperature –40 °C to +85 °C (–40 °F to +185 °F)Coil Temperature50 °C / W (122 °F/W)(contact carrying current 0 A)Mechanical1 × 106operationsLife ExpectancyElectrical100 x 103operations (at 14 Vdc. Motor Load 20 A / 3 A) WeightApprox. 15 gn (0.53oz) Approx. 8 gr (0.28 oz)COIL RATINGEP2 SERIESat 25°C (77°F ) Part Number H Bridge Type Separate Type Nominal Voltage (Vdc) Coil Resistance (Ω±10%)Nominal Current (mA) Must Operate Voltage (Vdc max.)Must Release Voltage (Vdc min.)Nominal Operate Power (W) EP2-3L1 EP2-3L2 EP2-3L3 EP2-4L3 EP2-4L4 EP2-4L5EP2-3L1T EP2-3L2T EP2-3L3T EP2-4L3T EP2-4L4T EP2-4L5T12 12 12 12 12 12225 225 225 300 300 30053.5 53.5 53.5 40.0 40.0 40.06.57.0 7.5 7.58.0 8.50.9 0.9 0.9 0.9 0.9 0.90.64 0.64 0.64 0.48 0.48 0.48EP1 SERIESPart NumberRegularTypeHigh Carrying Current Type Nominal Voltage (Vdc) Coil Resistance (Ω±10%)Nominal Current (mA) Must Operate Voltage (Vdc max.)Must Release Voltage (Vdc min.)Nominal Operate Power (W) EP1-3L1EP1-3L2EP1-3L3EP1-4L3EP1-4L4EP1-4L5EP1-B3G1 EP1-B3G2 EP1-B3G3 EP1-B4G3 EP1-B4G4 EP1-B4G5 12 12 12 12 12 12225 225 225 300 300 30053.3 53.3 53.3 40.0 40.0 40.06.57.0 7.5 7.58.0 8.50.9 0.9 0.9 0.9 0.9 0.90.64 0.64 0.64 0.48 0.48 0.48EP2/EP1 SERIES5NUMBERING SYSTEMTYPICAL APPLICATION (H Bridge Type)MOTOR Tr1Tr2 STOP off off FORWARD on off REVERSE off onIt is necessary to take more than 100 ms intervals for on / off timing between driving Tr1 and Tr2. If the interval is less than 100 ms, an excessive current happen to flow to the relay contacts.EP2 / EP1 SERIES6TECHNICAL DATACoil Temperature Rise (EP2-3L1)Operate Time (EP2-3L1) Release time (EP2-3L1)EP2/EP1 SERIES7EP2 / EP1 SERIESPrinted on recycled paper。

Lorex MPX HDSe

2. Se connecter avec le nom d’utilisateur du système (par défaut : admin) et le mot de passe (par défaut : 000000).
3.
2. Clic Droit: • En mode visionnement en direct :
Contrôle des caméras PTZ (non incluses) Ajuste les réglages de la couleur et de l’image de la caméra Voir les informations du système Démarrer/arrêter le mode séquence Esactiver l’alarme sonore
6: EN MARCHE
Bip
Si le système émet un signal sonore au démarrage, le câble Ethernet n’est peut-être pas branché, ou le système n’est peut-être pas connecté à Internet. Pour arrêter le signal sonore : 1. Brancher un câble Ethernet du système au routeur et redémarrer le système. OU 2. Cliquer avec le bouton droit et cliquer sur Disable Beep.
Cliquer sur et sélectionner SETTING
4. Cliquer sur GENERAL et sélectionner l’onglet Date&Time.

2SA1011P中文资料

Symbol
VCBO VCEO VEBO
IC ICP PC Tj
Tstg
Tc=25°C
Electrical Characteristics at Ta=25°C
Conditions
Current Emitter Cutoff Current DC Current Gain Gain-Bandwidth Product Output Capacitance Base-to-Emitter Voltage Collector-to-Emitter Saturation Voltage Collector-to-Base Breakdown Voltage Collector-to-Emitter Breakdown Voltage Emitter-to-Base Breakdown Voltage
* : The 2SA1011P/2SC2344P are classified by 300mA hFE as follows :
Rank
D
E
hFE
60 to 120
100 to 200
Ratings
Unit
(--)180
V
(--)160
V
(--)6
V
(--)1.5
A
(--)3
A
30
W
150
°C
--55 to +150
--5mA
--4mA
--3mA --2mA
--1mA
IB=0mA
--10
--20
--30
--40
--50
Collector to Emitter Voltage, VCE -- V IT02132

331P说明书

࢒ 3 ᐺ ; ‫߈ܠ‬ਜ਼݄੓
打电话 .................................................................................................................................................... 2.2 免提拨号 ................................................................................................................................................ 2.2 电话簿拨号 ........................................................................................................................................... 2.2
ii
目录
Rhine_UK.book Page iii Wednesday, August 28, 2002 1:57 PM
࢒ 2 ᐺ ; ࿸ᒙਜ਼আ፝
功能 ........................................................................................................................................................ 1.2 熟悉您的新机器 ................................................................................................................................... 1.3

CDRH64BNP-331MC中文资料

1．外形1-1．寸法図(mm)＊公差のない寸法は参考値とする。

1-2．捺印表示例 O-3．推奨ランド図(mm)2．コイル仕様2-1．端子接続図(裏面図)電極（端子）間の隙間はシルク処理をして御使用下さい。

捺印位置不定製造密番頭部直捺印100電極側電極側compliance Cd:Max.0.01wt%others:Max.0.1wt%RoHS12-2.電気的特性Ⅰ(リール梱包の場合)NO. 品名表示インダクタンス［以内］※1D.C.R.(Ω)[以下](at 20℃)※2定格電流(Ａ)※3スミダコード0102 CDRH64BNP-1ØØMCCDRH64BNP-12ØMC10012010μH ± 20%12μH ± 20%0.12 (88m)0.13 (97m)1.351.204745-01454745-01460304 CDRH64BNP-15ØMCCDRH64BNP-18ØMC15018015μH ± 20%18μH ± 20%0.18 (0.13)0.24 (0.18)1.101.004745-01474745-01480506 CDRH64BNP-22ØMCCDRH64BNP-27ØMC22027022μH ± 20%27μH ± 20%0.27 (0.20)0.30 (0.22)0.910.824745-01494745-01500708 CDRH64BNP-33ØMCCDRH64BNP-39ØMC33039033μH ± 20%39μH ± 20%0.33 (0.25)0.37 (0.27)0.750.694745-01514745-01520910 CDRH64BNP-47ØMCCDRH64BNP-56ØMC47056047μH ± 20%56μH ± 20%0.52 (0.38)0.56 (0.41)0.620.584745-01544745-01551112 CDRH64BNP-68ØMCCDRH64BNP-82ØMC68082068μH ± 20%82μH ± 20%0.63 (0.47)0.71 (0.53)0.520.474745-01564745-01571314 CDRH64BNP-1Ø1MCCDRH64BNP-121MC101121100μH ± 20%120μH ± 20%1.03 (0.76)1.15 (0.85)0.430.394745-01584745-01591516 CDRH64BNP-151MCCDRH64BNP-181MC151181150μH ± 20%180μH ± 20%1.68 (1.29)1.87 (1.44)0.350.324745-01604745-01611718 CDRH64BNP-221MCCDRH64BNP-271MC221271220μH ± 20%270μH ± 20%2.08 (1.60)2.37 (1.82)0.290.264745-01624745-01631920 CDRH64BNP-331MCCDRH64BNP-391MC331391330μH ± 20%390μH ± 20%2.67 (2.05)2.94 (2.26)0.230.224745-01654745-01662122 CDRH64BNP-471MCCDRH64BNP-561MC471561470μH ± 20%560μH ± 20%3.93 (3.02)5.43 (4.18)0.200.184745-01674745-01682324 CDRH64BNP-681MCCDRH64BNP-821MC681821680μH ± 20%820μH ± 20%7.32 (5.63)8.24 (6.34)0.170.154745-01694745-017025 CDRH64BNP-1Ø2MC 102 1 mH ± 20% 9.26 (7.13) 0.14 4745-0171※1: 測定周波数Ｌ at 1 kHz※2: ( )内は、標準値とする。

P3ec 系列软件应用参考手册

第 1 页共 1 页
P3e/c 系列软件应用参考手册（水电篇）
目录
4.1 工程项目管理类型 -------------------------------------------------------------------------------------- 78 4.2 P3e/c 在水电工程建设领域的应用模式和作用 ---------------------------------------------------- 79 第五章水电建设项目 P3e/c 应用案例 ------------------------------------------------------------------------ 84
P3e/c 系列软件应用参考手册（水电篇）
目录
目
录
Hale Waihona Puke 前言 ------------------------------------------------------------------------------------------------------------------3 第一章 P3e/c 软件介绍 -------------------------------------------------------------------------------------------5 1.1 概述 ----------------------------------------------------------------------------------------------------------5 1.2 P3e/c 功能介绍 ---------------------------------------------------------------------------------------------6 1.2.1 P3e/c 组成及各组件使用对象-------------------------------------------------------------------6 1.2.2 P3e/c 主要功能特点 -------------------------------------------------------------------------------8 第二章 P3e/c 关键概念的理解和运用 ----------------------------------------------------------------------- 11 2.1 P3e/c 中体现的项目管理组织方式 ------------------------------------------------------------------- 12 2.1.1 工程项目管理组织结构形式 ------------------------------------------------------------------ 12 2.1.2 P3e/c 软件实现矩阵式项目管理组织方式的原理 ---------------------------------------- 14 2.1.3 权限传递中 OBS、用户及 EPS/WBS 之间的关系--------------------------------------- 17 2.2 建立合理的工作分解结构 --------------------------------------------------------------------------- 19 2.2.1 为什么要使用工作分解结构 ----------------------------------------------------------------- 19 2.2.2 工作分解结构的作用 -------------------------------------------------------------------------- 19 2.2.3 怎么应用工作分解结构 ----------------------------------------------------------------------- 20 2.2.4 常用的工作分解结构分解方法 --------------------------------------------------------------- 21 2.2.5 工作分解结构分解时应注意的问题： ----------------------------------------------------- 22 2.2.6 工作分解结构的重要规则-百分之百规则 -------------------------------------------------- 23 2.3 多级网络计划的应用 --------------------------------------------------------------------------------- 24 2.3.1 多级网络计划概述 ----------------------------------------------------------------------------- 24 2.3.2 多级网络的应用模式 -------------------------------------------------------------------------- 25 2.3.3 P3e/c 软件中多级网络的实现----------------------------------------------------------------- 26 2.4 P3e/c 中赢得值原理的运用 -------------------------------------------------------------------------- 38 2.4.1 关于赢得值 --------------------------------------------------------------------------------------- 38 2.4.2 赢得值各参数释义 ------------------------------------------------------------------------------ 39 2.4.3 运用赢得值方法进行项目投资控制 --------------------------------------------------------- 48 2.4.4 运用赢得值方法进行项目成本控制 --------------------------------------------------------- 59 2.4.5 总结 ------------------------------------------------------------------------------------------------ 64 第三章水电工程建设项目管理信息化的总体构架 ------------------------------------------------------- 66 3.1 水电工程建设项目的特点分析 ----------------------------------------------------------------------- 66 3.2 水电建设工程项目管理信息化的模式（P3e/c+PIP） ------------------------------------------- 70 3.3 水电建设工程项目管理信息化的基本框架 ------------------------------------------------------- 72 3.3.1 P3e/c 项目管理软件 ----------------------------------------------------------------------------- 72 3.3.2 项目管理信息平台（PIP） ------------------------------------------------------------------- 72 3.4 水电建设工程项目管理信息化的实施建议 ------------------------------------------------------- 74 3.4.1 进一步理顺和完善适应工程项目管理信息化的工程管理制度和流程（组织件）75 3.4.2 组织各参与单位参加工程项目管理信息化强化研讨班（教育件） ------------------ 76 3.4.3 建立集成的水电建设工程项目管理信息化系统（软件） ----------------------------- 77 3.4.4 购置必要的硬件 -------------------------------------------------------------------------------- 77 第四章 P3e/c 在水电工程建设领域的应用模式 ----------------------------------------------------------- 78

HQxxxx-xxx-3AA中文资料

HQ SeriesSPECIFICATIONS STANDARD*SPECIAL ELECTRICALCenter Frequency (Fc)100 to 1000 Mhz80 to 1400 MHz 3dB Relative Bandwidth (% of FC) 4 to 40 4 to 50 Number of Sections Available 3 to 8 2 to 10 Nominal Impedance50 Ohms50 to 75 Ohms Maximum Insertion Loss See Curve See Curve Maximum VSWR 1.5/1 1.3/1 Attenuation in the Stopband See Graph See GraphMaximum Input Power (Average)(Watts to10,000 ft.)500 x 3dB BW (MHz)(Loss Factor)(Fc MHz)See StandardMaximum Input Power (Peak)(Watts to10,000 ft.)300 x 3dB BW (MHz)Fc (MHz)2,000ENVIRONMENTALShock15 G's25 G's Vibration 5 G's10 G's Humidity90% relative100% relativeINSERTION LOSS:The Maximum Insertion Loss at center frequency is equal to :LF x (N + 0.5) / % 3 dB BW + 0.2 Where:LF= Loss Factor, N= Number of Sections% 3dB BW:3dB BW (MHz) x 100divided byCenter Frequency (MHz) Example:A 3 section HQ with a center frequency of 400 MHz and a 3dB BW of 40 MHz would have,1.5 x 3.5 / 10 = 5.25 / 10 = 0.525 0.525 + 0.2 = 0.8 dBConnectors Available on HQ Series:Lark Code Type C DIM.Inches & MMLarkCodeType C DIM.Inches & MMA SMA JACK.800 & 20.3G N JACK 1.625 & 41.3B SMA PLUG.855 & 22.5H N PLUG 1.585 & 40.3C TNC JACK 1.350 & 34.3L SOLDER MPINAXIAL.625 & 15.9D TNC PLUG 1.280 & 32.5*M SOLDER PINRADIAL.625 & 15.9E BNC JACK 1.350 & 34.3S SPECIALF BNC PLUG 1.280 & 32.5*Not recommended for use with this series.LENGTH:The approximate length of a Lark HQ series filter can be determined by the formula:( 0.5 N + 2 / %BW ) x LC = LWhere N is the number of sections used, % BW is:3dB BW (MHz) x 100divided byCENTER FREQUENCY (MHz)LC is the length constant at the specified center frequency, L is the dimension between theconnectors; C1 and C2 are the connector lengths as shown above. All of the length information given here is approximate. Exact length specifications must be quoted by the factory. If a special length is needed,please submit all of your requirements - both electrical and mechanical. This will enable Lark Engineering to quote the optimum design for your application.Example:A 3 section HQ with a center frequency of 400 MHz a 3dB BW of 40 MHz and SMA jack input and output connectors would be:(1.5 + 0.2) x 1.38 = 2.35 + C1 + C2In most cases, the L dimension is rounded to the nearest 1/4 inch which in this instance would be 2.25inches and the O.A.L. is:2.25 + .800 + .800 =3.85 inches.To convert inches to millimeters multiply x 25.40.Lark Engineering HQ SERIES元器件交易网STOPBAND ATTENUATIONThe graph on the following pages defines the normal specification limits on attenuation Lark bandpass filter series HP, HQ, SF, and SM. The minimum level of attenuation in dB is shown as a "number of 3dB bandwidths from center frequency".Since the frequency characteristics vary for differing bandwidths, it is necessary to establishspecifications for each bandwidth of filter. The different graphs represent various 3dB percentage bandwidths. Intermediate values should be interpolated. The 3dB percentage bandwidth is defined asfollows:STOPATT5.HTM元器件交易网As the 3dB bandwidth is exactly 10% of the center frequency, the answer can be read directly from the 10% graph. Using the 5 section curve at the point -1.5 (255 MHz) we find the minimum level of attenuation is 36dB. At +1.6 (348 MHz) the minimum level of attenuation is 48dB.For special requirements, please contact our Application Engineering Department.STOPBAND ATTENUATIONSTOPBAND ATTENUATIONSTOPATT5.HTM元器件交易网STOPBAND ATTENUATIONSTOPBAND ATTENUATIONSTOPBAND ATTENUATION。

Lenovo ThinkAgile HX3321 Certified Node for SAP HA

Lenovo ThinkAgile HX3321 Certified Node forSAP HANA (Xeon SP Gen 1)Product Guide (withdrawn product)Lenovo ThinkAgile HX Certified Nodes for SAP HANA are designed to help you simplify IT infrastructure, reduce costs, and accelerate time to value. These hyperconverged appliances from Lenovo combine industry-leading hyperconvergence software from Nutanix with Lenovo enterprise platforms that feature the Intel Xeon Processor Scalable Family.The ThinkAgile HX Certified Nodes for SAP HANA deliver fully validated and integrated Lenovo hardware and firmware, certified and preloaded with Nutanix software. Nutanix brings the benefits of web-scale technologies to enterprise applications through enterprise storage, data protection, infrastructure resilience, management and analytics, and security.The ThinkAgile HX3321 Certified Node for SAP HANA is a 1U rack-mount system that supports two processors, up to 3 TB of 2666 MHz TruDDR4 memory, 10x or 12x SFF hot-swap drive bays with an extensive choice of SAS/SATA SSDs and HDDs, and flexible network connectivity options with 1/10 GbE RJ-45, 10 GbE SFP+, and 10/25 GbE SFP28 ports.The ThinkAgile HX3321 Certified Node for SAP HANA is certified by SAP for deploying SAP HANA solutions on hyperconverged infrastructure (HCI) in production environments.The ThinkAgile HX3321 Certified Node for SAP HANA is shown in the following figure.Figure 1. Lenovo ThinkAgile HX3321 Certified Node for SAP HANADid you know?The ThinkAgile HX Certified Nodes for SAP HANA are built on industry-leading Lenovo ThinkSystem servers that feature enterprise-class reliability, management, and security.The ThinkAgile HX Certified Nodes for SAP HANA deliver fully validated and integrated hardware and firmware that is certified with Nutanix software.Click here to check for updatesFigure 2. ThinkAgile HX3321 Certified Node for SAP HANA front viewFigure 3. ThinkAgile HX3321 Certified Node for SAP HANA 10-drive bay rear viewThe following figure shows the rear view of the ThinkAgile HX3321 Certified Node for SAP HANA with 12 drive bays.Figure 4. ThinkAgile HX3321 Certified Node for SAP HANA 12-drive bay rear viewThe rear of the ThinkAgile HX3321 Certified Node for SAP HANA includes the following components: Three (models with 10 drive bays) or one (models with 12 drive bays) PCIe expansion slotsTwo SFF SAS/SATA hot-swap rear drive bays (models with 12 drive bays)One LOM card slotOne 1 GbE port for XClarity ControllerOne VGA portTwo USB 3.0 portsTwo hot-swap power suppliesTable 4. Memory selection optionsDescription Part number Featurecode Quantity2666 MHz RDIMMsThinkSystem 8GB TruDDR4 2666 MHz (1Rx8 1.2V) RDIMM 7X77A01301AUU1-12+12------ThinkSystem 16GB TruDDR4 2666 MHz (2Rx8 1.2V) RDIMM 7X77A01303AUNC 12-12+12----ThinkSystem 32GB TruDDR4 2666 MHz (2Rx4 1.2V) RDIMM 7X77A01304AUND --1224---2666 MHz LRDIMMsThinkSystem 64GB TruDDR4 2666 MHz (4Rx4 1.2V) LRDIMM 7X77A01305AUNE ----1224--2666 MHz 3DS RDIMMsThinkSystem 64GB TruDDR4 2666MHz (4Rx4, 1.2V) 3DS RDIMM4ZC7A08716AUW5------12+12-ThinkSystem 128GB TruDDR4 2666 MHz (8Rx4 1.2V) 3DS RDIMM 7X77A01307AUNF-----1224192 G B288 G B384 G B576 G B768 G B1.5 T B2.25 T B 3 T B3m Cat6 Green Cable 00WE139AVG010m Cat6 Green Cable 90Y3718A1MT 25m Cat6 Green Cable90Y3727A1MWDescriptionPart number Feature code The following table lists transceivers and cables for the 10 GbE SFP+ ports.Table 11. Transceivers and cables for 10 GbE SFP+ portsDescriptionPart numberFeature code10 GbE SFP+ SR transceivers for 10 GbE SFP+ ports Lenovo 10GBASE-SR SFP+ Transceiver 46C34475053Lenovo 10GBASE-LR SFP+ Transceiver 00FE331B0RJOptical cables for 10 GbE SFP+ SR transceivers Lenovo 0.5m LC-LC OM3 MMF Cable 00MN499ASR5Lenovo 1m LC-LC OM3 MMF Cable 00MN502ASR6Lenovo 3m LC-LC OM3 MMF Cable 00MN505ASR7Lenovo 5m LC-LC OM3 MMF Cable 00MN508ASR8Lenovo 10m LC-LC OM3 MMF Cable 00MN511ASR9Lenovo 15m LC-LC OM3 MMF Cable 00MN514ASRA Lenovo 25m LC-LC OM3 MMF Cable00MN517ASRB Passive SFP+ DAC cables for 10 GbE SFP+ ports Lenovo 0.5m Passive SFP+ DAC Cable 00D6288A3RG Lenovo 1m Passive SFP+ DAC Cable 90Y9427A1PH Lenovo 1.5m Passive SFP+ DAC Cable 00AY764A51N Lenovo 2m Passive SFP+ DAC Cable 00AY765A51P Lenovo 3m Passive SFP+ DAC Cable 90Y9430A1PJ Lenovo 5m Passive SFP+ DAC Cable 90Y9433A1PK Lenovo 7m Passive SFP+ DAC Cable00D6151A3RHActive SFP+ DAC cables for 10 GbE SFP+ ports Lenovo 1m Active DAC SFP+ Cable 00VX111AT2R Lenovo 3m Active DAC SFP+ Cable 00VX114AT2S Lenovo 5m Active DAC SFP+ Cable00VX117AT2TSFP+ active optical cables for 10 GbE SFP+ ports Lenovo 1m SFP+ to SFP+ Active Optical Cable 00YL634ATYX Lenovo 3m SFP+ to SFP+ Active Optical Cable 00YL637ATYY Lenovo 5m SFP+ to SFP+ Active Optical Cable 00YL640ATYZ Lenovo 7m SFP+ to SFP+ Active Optical Cable 00YL643ATZ0Lenovo 15m SFP+ to SFP+ Active Optical Cable 00YL646ATZ1Lenovo 20m SFP+ to SFP+ Active Optical Cable00YL649ATZ2The following table lists transceivers and cables for the 25 GbE SFP28 ports. Table 12. Transceivers and cables for 25 GbE SFP28 portsDescription Part number Feature code25 GbE SFP28 SR transceivers for 25 GbE SFP28 portsLenovo 25GBASE-SR SFP28 Transceiver7G17A03537AV1B Optical cables for 25 GbE SFP28 SR transceiversLenovo 0.5m LC-LC OM3 MMF Cable00MN499ASR5 Lenovo 1m LC-LC OM3 MMF Cable00MN502ASR6 Lenovo 3m LC-LC OM3 MMF Cable00MN505ASR7 Lenovo 5m LC-LC OM3 MMF Cable00MN508ASR8 Lenovo 10m LC-LC OM3 MMF Cable00MN511ASR9 Lenovo 15m LC-LC OM3 MMF Cable00MN514ASRA Lenovo 25m LC-LC OM3 MMF Cable00MN517ASRB Passive copper cables for 25 GbE SFP28 portsLenovo 1m Passive 25G SFP28 DAC Cable7Z57A03557AV1W Lenovo 3m Passive 25G SFP28 DAC Cable7Z57A03558AV1X Lenovo 5m Passive 25G SFP28 DAC Cable7Z57A03559AV1Y Active optical cables for 25 GbE SFP28 portsLenovo 3m 25G SFP28 Active Optical Cable7Z57A03541AV1F Lenovo 5m 25G SFP28 Active Optical Cable7Z57A03542AV1G Lenovo 10m 25G SFP28 Active Optical Cable7Z57A03543AV1H Lenovo 15m 25G SFP28 Active Optical Cable7Z57A03544AV1J Lenovo 20m 25G SFP28 Active Optical Cable7Z57A03545AV1KPower supplies and cablesThe ThinkAgile HX3321 Certified Nodes for SAP HANA ship with two power supplies. The following table lists the power supply options that are available for selection.Table 13. Power supply selection optionsDescription Featurecode QuantityThinkSystem 750W (230/115V) Platinum Hot-Swap Power Supply AVWA2 ThinkSystem 750W (230V) Titanium Hot-Swap Power Supply AVW92 ThinkSystem 1100W (230V/115V) Platinum Hot-Swap Power Supply AVWB2Israel 2.8m, 10A/250V, C13 to SI 32 Line Cord 39Y79206218Israel 4.3m, 10A/250V, C13 to SI 32 Line Cord 81Y23816579Italy 2.8m, 10A/250V, C13 to CEI 23-16 Line Cord 39Y79216217Italy 4.3m, 10A/250V, C13 to CEI 23-16 Line Cord 81Y23806493Japan 2.8m, 12A/125V, C13 to JIS C-8303 Line cord 46M2593A1RE Japan 2.8m, 12A/250V, C13 to JIS C-8303 Line Cord 4L67A083575472Japan 4.3m, 12A/125V, C13 to JIS C-8303 Line Cord 39Y79266335Japan 4.3m, 12A/250V, C13 to JIS C-8303 Line Cord 4L67A083626495Korea 2.8m, 12A/250V, C13 to KS C8305 Line Cord 39Y79256219Korea 4.3m, 12A/250V, C13 to KS C8305 Line Cord 81Y23856494South Africa 2.8m, 10A/250V, C13 to SABS 164 Line Cord 39Y79226214South Africa 4.3m, 10A/250V, C13 to SABS 164 Line Cord 81Y23796576Switzerland 2.8m, 10A/250V, C13 to SEV 1011-S24507 Line Cord 39Y79196216Switzerland 4.3m, 10A/250V, C13 to SEV 1011-S24507 Line Cord 81Y23906578Taiwan 2.8m, 10A/125V, C13 to CNS 10917-3 Line Cord 23R71586386Taiwan 2.8m, 10A/250V, C13 to CNS 10917-3 Line Cord 81Y23756317Taiwan 2.8m, 15A/125V, C13 to CNS 10917-3 Line Cord 81Y23746402Taiwan 4.3m, 10A/125V, C13 to CNS 10917-3 Line Cord 4L67A08363AX8BTaiwan 4.3m, 10A/250V, C13 to CNS 10917-3 Line Cord 81Y23896531Taiwan 4.3m, 15A/125V, C13 to CNS 10917-3 Line Cord 81Y23886530United Kingdom 2.8m, 10A/250V, C13 to BS 1363/A Line Cord 39Y79236215United Kingdom 4.3m, 10A/250V, C13 to BS 1363/A Line Cord 81Y23776577United States 2.8m, 10A/125V, C13 to NEMA 5-15P Line Cord 90Y30166313United States 2.8m, 10A/250V, C13 to NEMA 6-15P Line Cord 46M2592A1RF United States 2.8m, 13A/125V, C13 to NEMA 5-15P Line Cord 00WH5456401United States 4.3m, 10A/125V, C13 to NEMA 5-15P Line Cord 4L67A083596370United States 4.3m, 10A/250V, C13 to NEMA 6-15P Line Cord 4L67A083616373United States 4.3m, 13A/125V, C13 to NEMA 5-15P Line Cord4L67A08360AX8ADescriptionPart number Feature code Configuration note: If the 1100 W AC power supplies in the certified node are connected to a low-voltage power source (100 - 125 V), the only supported power cables are those that are rated above 10 A; cables that are rated at 10 A are not supported.Rack installationRack installationThe ThinkAgile HX3321 Certified Nodes for SAP HANA ship with a rail kit. The following table lists the rail kit options that are available for selection.Table 15. Rack kit selection optionsDescription FeaturecodeQuantity(min / max)4-post rail kitsThinkSystem Tool-less Slide Rail AXCA0 / 1 ThinkSystem Tool-less Slide Rail Kit with 1U CMA AXCB0 / 1 Lockable front bezelThinkSystem 1U Security Bezel AUWR0 / 1Configuration note: One of the rail kits is required for selection.The following table summarizes the rail kit features and specifications.Table 16. Rail kit features and specifications summaryFeature Tool-less Slide RailWithout CMA With 1U CMACMA Not included IncludedRail length730 mm (28.74 in.)807 mm (31.8 in.)Rail type Full-out slide (ball bearing)Tool-less installation YesIn-rack maintenance Yes1U PDU support Yes0U PDU support Limited*Rack type IBM and Lenovo 4-post, IEC standard-compliant Mounting holes Square or roundMounting flange thickness 2 mm (0.08 in.) – 3.3 mm (0.13 in.)Distance between front and rear mounting flanges^609.6 mm (24 in.) – 863.6 mm (34 in.)* If a 0U PDU is used, the rack cabinet must be at least 1100 mm (43.31 in.) deep if no CMA is used, or at least 1200 mm (47.24 in.) deep if a CMA is used.^ Measured when mounted on the rack, from the front surface of the front mounting flange to the rear most point of the rail.TrademarksLenovo and the Lenovo logo are trademarks or registered trademarks of Lenovo in the United States, other countries, or both. A current list of Lenovo trademarks is available on the Web athttps:///us/en/legal/copytrade/.The following terms are trademarks of Lenovo in the United States, other countries, or both:Lenovo®AnyBay®Lenovo ServicesThinkAgile®ThinkSystem®TruDDR4XClarity®The following terms are trademarks of other companies:Intel® and Xeon® are trademarks of Intel Corporation or its subsidiaries.Linux® is the trademark of Linus Torvalds in the U.S. and other countries.Microsoft®, PowerShell, Windows PowerShell®, and Windows® are trademarks of Microsoft Corporation in the United States, other countries, or both.Other company, product, or service names may be trademarks or service marks of others.。

netgear-ag731f-1.0625gbd-fiber-channel-and-gigabit

350 E. Plumeria DriveSan Jose, CA 95134-1911 USA 1-888-NETGEAR (638-4327) E-mail:**************** RoHS Compliant Small Form Factor Pluggable Transceiver for Gigabit Ethernet and Fiber ChannelAGM731FRoHS Compliant Small Form Factor Pluggable Transceiver for Gigabit Ethernet and Fiber ChannelFEATURESCompliant with SFP Transceiver MSAspecificationCompliant with Specifications for IEEE802.3z/Gigabit EthernetCompliant with the 1.0625GBd Fiber ChannelFC-PI 100-M5-SN-I Rev.13Compliant with Industry Standard RFTElectrical Connector and CageSingle + 3.3V Power Supply and TTL LogicInterfaceEEPROM with Serial ID FunctionalityLaser Class 1 Product which comply with therequirements of IEC 60825-1 and IEC 60825-2Duplex LC Connector interfaceDescriptionThis transceiver is hot pluggable 3.3V Small-Form-Factor transceiver module designed expressly for high-speed communication applications that require rates of up to 1.25Gbit/sec. It is compliant with the Gigabit Ethernet standards, as well as the SFP Multisource Agreement (MSA).It provides with the LC receptacle that is compatible with the industry standard LC connector. The transceiver is also compatible with industry standard RFT connector and cage.The post-amplifier of the transceiver also includes a LOS (Loss Of Signal) circuit that provides a TTL logic-high output when an unusable optical signal level is detected.The transceiver is a Class 1 eye safety product. The optical power levels, under normal operation, are at eye safe level.ApplicationsGigabit EthernetFibre channelSwitch to Switch interfaceSwitched backplane applicationsFile server interfacePerformanceData Link up to 550m in 50/125µm Multi Mode Fiber Data Link up to 275m in 62.5/125µm Multi Mode FiberAbsolute Maximum RatingsParameter Symbol Min. Typ. Max. Unit Note Storage Temperature Ts -40 85 ºCSupply Voltage V CC0 5 V Recommended Operating ConditionsParameter Symbol Min. Typ. Max. Unit Note Case Operating Temperature T C-5 70 ºCSupply Voltage V CC 3.135 3.465 VElectrical Characteristics(V CC=3.135V to 3.465V)Parameter Symbol Min. Typ. Max. Unit Note Total Supply Current I CCT180 300 mATransmitterTransmitter Differential Input Voltage V DT0.5 2.4 V 1 Transmitter Disable Input-High V DISH 2 V CC+0.3 VTransmitter Disable Input-Low V DISL0 0.8 VTransmitter Fault Output-High V TXFH 2 V CC+0.3 V 2 Transmitter Fault Output-Low V TXFL0 0.8 V 2 ReceiverReceiver Differential Output Voltage V DR0.35 0.7 2 V 3LOS Output Voltage-High V LOSH 2 V CC+0.3 V 2LOS Output Voltage-Low V LOSL0 0.8 V 2 Output Data Rise/Fall Time t r / t f400 psec 4Total Jitter (pk-pk) TJ RX220 psecNotes:1. Internally AC coupled and terminated to 100Ohm differential load.2. Pull up to V CC with a 4.7K – 10K Ohm resistor on host Board3. Internally AC coupled, but requires a 100 Ohm differential termination at or internal to Serializer/Deserializer.4. These are 20%~80% valuesOptical Characteristics(V CC=3.135V to 3.465V, Data Rate=1.25 Gb/sec, PRBS=27-1 NRZ, 50/125µm or 62.5/125µm MMF) Parameter Symbol Min. Typ. Max. Unit Note TransmitterOutput Optical Power (Avg.) P O-9.5 -3 dBmOptical Extinction Ratio ER 9 dBCenter Wavelength λC830 850 860 nmSpectral Width (RMS) σ0.85 nmOptical Rise/Fall Time t r /t f260 psec 1 Total Jitter (pk-pk) TJ TX220 psecRelative Intensity Noise RIN -117 dB/HzOutput Eye Complies with the IEEE 802.3z/D2 specification, and is class 1 laser eye safetyReceiverSensitivity (Avg.) P IN-17 dBm 2 Input Optical Wavelength λ850 nmLOS- De-Asserted (Avg.) P D-17 dBmLOS- asserted (Avg.) P A-30 dBmLOS-Hysteresis P D-P A0.5 dBOverload P O-3 dBmNotes:1. These are 20%~80% values2. The sensitivity is provided at a BER of 1×10-10 or better with an input signal consisting of 1250Mb/s,27-1 PRBS.Mask of the eye diagram for the optical transmit signalSFP Transceiver Electrical Pad LayoutPin Function DefinitionsPin Num.Name FunctionPlug Seq. Notes1 VeeT Transmitter Ground1 2TX Fault Transmitter Fault Indication 3 Note 13 TX Disable Transmitter Disable 3Note 2Module disables on high or open4 MOD-DEF2 Module Definition 2 3 Note 3, 2 wire serial ID interface5 MOD-DEF1 Module Definition 1 3 Note 3, 2 wire serial ID interface6 MOD-DEF0 Module Definition 0 3 Note 3, Grounded in Module7 Rate SelectNot Connect 3 Function not available 8 LOS Loss of Signal 3 Note 4 9 VeeR Receiver Ground 1 Note 5 10 VeeR Receiver Ground 1 Note 5 11 VeeR Receiver Ground1 Note 5 12 RD- Inv. Received Data Out3 Note 6 13 RD+ Received Data Out 3 Note 7 14 VeeR Receiver Ground 1 Note5 15 VccR Receiver Power 2 3.3 ± 5%, Note 7 16 VccT Transmitter Power 2 3.3 ± 5%, Note7 17 VeeT Transmitter Ground 1 Note 5 18 TD+ Transmit Data In 3 Note 8 19 TD- Inv. Transmit Data In 3 Note 8 20VeeTTransmitter Ground1 Note 5Plug Seq.: Pin engagement sequence during hot plugging.Notes:1) TX Fault is an open collector/drain output, which should be pulled up with a 4.7K – 10KΩ resistor on the hostboard. Pull up voltage between 2.0V and VccT, R+0.3V. When high, output indicates a laser fault of some kind.Low indicates normal operation. In the low state, the output will be pulled to < 0.8V.2) TX disable is an input that is used to shut down the transmitter optical output. It is pulled up within the modulewith a 4.7 – 10 K Ω resistor. Its states are:Low (0 – 0.8V): Transmitter on(>0.8, < 2.0V): UndefinedHigh (2.0 – 3.465V): Transmitter DisabledOpen: Transmitter Disabled3) Mod-Def 0,1,2. These are the module definition pins. They should be pulled up with a 4.7K – 10KΩresistor on thehost board. The pull-up voltage shall be VccT or VccR (see Section IV for further details). Mod-Def 0 is grounded by the module to indicate that the module is present Mod-Def 1 is the clock line of two wire serial interface for serial ID Mod-Def 2 is the data line of two wire serial interface for serial ID4) LOS (Loss of Signal) is an open collector/drain output, which should be pulled up with a 4.7K – 10KΩ resistor.Pull up voltage between 2.0V and VccT, R+0.3V. When high, this output indicates the received optical power is below the worst-case receiver sensitivity (as defined by the standard in use). Low indicates normal operation. In the low state, the output will be pulled to < 0.8V.5) VeeR and VeeT may be internally connected within the SFP module.6) RD-/+: These are the differential receiver outputs. They are AC coupled 100Ω differential lines which should beterminated with 100Ω (differential) at the user SERDES. The AC coupling is done inside the module and is thus not required on the host board. The voltage swing on these lines will be between 370 and 2000 mV differential (185 – 1000 mV single ended) when properly terminated.7) VccR and VccT are the receiver and transmitter power supplies. They are defined as 3.3V ±5% at the SFPconnector pin. Maximum supply current is 300mA. Recommended host board power supply filtering is shown below. Inductors with DC resistance of less than 1 ohm should be used in order to maintain the required voltage at the SFP input pin with 3.3V supply voltage. When the recommended supply-filtering network is used, hot plugging of the SFP transceiver module will result in an inrush current of no more than 30mA greater than the steady state value. VccR and VccT may be internally connected within the SFP transceiver module.8) TD-/+: These are the differential transmitter inputs. They are AC-coupled, differential lines with 100Ωdifferential termination inside the module. The AC coupling is done inside the module and is thus not required on the host board. The inputs will accept differential swings of 500 – 2400 mV (250 – 1200 mV single-ended), though it is recommended that values between 500 and 1200 mV differential (250 – 600 mV single-ended) be used for best EMI performance.Package Outline Drawing for Metal Housing with Bail de-latchC o m p l i e s w i t h 21 C F R 1040.10a n d 1040.11SFP timing parameters for SFP managementParameter Symbol Min. Max. Unit Unit ConditionsTX_DISABLE Assert time t_off 10 µsecTime from rising edge of TX_DISABLE towhen the optical output falls below 10% ofnominalTX_DISABLE Negate time t_on 1 msecTime from falling edge of TX_DISABLE towhen the modulated optical output risesabove 90% of nominalTime to initialize,including reset of TX_FAULT t_init 300 msecFrom power on or negation of TX_Fault usingTX Disable.TX Fault Assert Time t_fault100 µsec Time from fault to TX fault on.TX_DISABLE to reset t_rest 10 µsecTime TX Disable must be held high to resetTX_FaultLOS Assert Time t_loss_on 100 µsec Time from LOS state to Rx LOS assertLOS Deassert Time t_loss_off 100 µsec Time from non-LOS state to Rx LOS deassert Serial ID Clock Rate f_serial_clock 100 kHzSFP timing parametersPower on initialization of SFP transceiver, TX_DISABLE negated Power on initialization of SFP, TX_DISABLE asserted Initialization during hot plugging of SFP TRANSCEIVER.Example of initialization during hot plugging, TX_DISABLE negated.SFP TX_DISABLE timing during normal operation.Detection of transmitter safety fault conditionSuccessful recovery from transient safety fault conditionUnsuccessful recovery from safety fault conditionTiming of LOS detectionEEPROM Serial ID Memory Contents (2-Wire Address A0h)Address Hex ASCII Address Hex ASCII Address Hex ASCII Address Hex ASCII Address Hex ASCII Address Hex ASCII00 03 25 41 A 50 20 75 SN 100 00 125 0001 04 26 52 R 51 20 76 SN 101 00 126 0002 07 27 20 52 20 77 SN 102 00 127 0003 00 28 20 53 20 78 SN 103 0004 00 29 20 54 20 79 SN 104 0005 00 30 20 55 20 80 SN 105 0006 01 31 20 56 41 81 SN 106 0007 40 32 20 57 20 82 SN 107 0008 40 33 20 58 20 83 SN 108 0009 00 34 20 59 20 84 DC Note 3 109 0010 00 35 20 60 03 85 DC 110 0011 03 36 00 61 52 86 DC 111 0012 0D 37 00 62 00 87 DC 112 0013 00 38 00 63 CS1 Note 1 88 DC 113 0014 00 39 00 64 00 89 DC 114 0015 00 40 41 A 65 1A 90 DC 115 0016 37 41 47 G 66 00 91 DC 116 0017 1B 42 4D M 67 00 92 00 117 0018 00 43 37 7 68 SN Note 2 93 00 118 0019 00 44 33 3 69 SN 94 00 119 0020 4E N 45 31 1 70 SN 95 CS2 Note 4 120 0021 45 E 46 46 F 71 SN 96 00 121 0022 54 T 47 20 72 SN 97 00 122 0023 47 G 48 20 73 SN 98 00 123 0024 45 E 49 20 74 SN 99 00 124 00Notes:1) Byte 63: Check sum of bytes 0-62.2) Byte 68-83 (SN): Serial number.3) Byte 84-91 (DC): Date code.4) Byte 95 (CS2): Check sum of bytes 64-94.5) Byte 128-255 had been set hex. 00.11Rev. 0ARegulatory Compliance FeatureReference Performance Electromagnetic Interference(EMI)FCC CRF 47, Part15 Class B EN 55022 Class B (CISPR 22A) Radio FrequencyElectromagnetic Field EN 61000-4-3 IEC 61000-4-3 Electrostatic Discharge to the Duplex LC Receptacle EN 61000-4-2 IEC 61000-4-2IEC 801.2Electrostatic Discharge to the Electrical PinsMIL-STD-883E Method 3015.7 (1) Satisfied with electricalcharacteristics of productspec.(2) No physical damage Eye Safety US FDA CDRH AEL Class 1EN 60950: 2000EN 60825-1: 1994+A11+A2EN 60825-2: 2000CDRH File # 0321539-00 TUV Certificate No. R50032471 Component Recognition Underwriters Laboratories and Canadian Standards Association JointComponent Recognition for InformationTechnology Equipment IncludingElectrical Business EquipmentUL File # E239394© 2008 NETGEAR, Inc. NETGEAR, the NETGEAR Logo, NETGEAR Digital Entertainer Logo, Connect with Innovation, FrontView, IntelliFi, PowerShift, ProSafe, RAIDar, RAIDiator, X-RAID, RangeMax, ReadyNAS and Smart Wizard are trademarks of NETGEAR, Inc. in the United States and/or other countries. Other brand names mentioned herein are for identification purposes only and may be trademarks of their respective holder(s). Information is subject to change without notice. All rights reserved.D-AGM731F-0。

DOM44S3R272资料

1. PRODUCT OVERVIEWGENERAL DESCRIPTIONThe HFDOM44S3Rxxx series 44Pin Flash Disk Module is a flash technology based with True IDE interface flash memory card. It is constructed with flash disk controller chip and NAND-type (Samsung) flash memory device. The HFDOM44S3R-xxx series operates in both 3.3-Volt and 5.0-Volt power supplies. It comes in capacity of 16, 32, 48, 64, 80, 96, 128, 144, 160, 192, 208, 224, 256, 272,288, 320, 384 and up to 512MByte formatted 44Pin type .By optimizing flash memory management, the life of this HFDOM44S3Rxxx series can be extended to its maximum level. Because the ECC function is included, the correctness of data transfer between the HFDOM44S3Rxxx series and a True IDE compatible interface device can be guaranteed.The HFDOM44S3Rxxx series is fully compatible with applications such as CPU card / board, set top box, industry / military PC / Notebook, security equipment, measuring instrument and embedded systems.FEATURES-ATA / True IDE compatible host interface-ATA command set compatible-Automatic sensing of PC Card ATA or true IDE host interface.-Very high performance, very low power consumption-Automatic error correction-Auto Standby to save power consumption.-Supports power down commands and sleep modes.-Integrated PCMCIA attribute memory of 256 bytes (CIS)-Support for 8 or 16 bit host transfers- 3.3V/5.0V operation voltage-Host Interface bus width : 8/16 bit Access-Flash Interface bus width : 8 bit Access-Capacity : Min. 16MB ~ Max. 512MB-MTBF > 1,000,000 hours.-Minimum 10,000 insertions.-Shock : 2,000 G max.-Vibration : 15 G peak to peak max.PRODUCT SPECIFICATIONSCapacities :16, 32, 48, 64, 80, 96, 128, 144, 160, 192,208, 224, 256, 272,288, 320, 384 and up to 512MB (formatted)System Compatibility :Please refer to the compatibility list of index.Performance :Host Data Transfer Rates : up to 16.6 MB/sec, PIO mode 4; 16.6MB/secOperating Voltage : 3.3V / 5.0V 10%Power consumption : 3.3V ± 5%Read mode <30 mAWrite mode <56 mAStop mode <2 mAEnvironment conditions :Operating temperature 0°C to + 70°CStorage temperature - °C to + °CRelative humidity 8% to 95%, non-condensingELECTRICAL SPECIFICATIONSTable 1.1 Absolute Maximum RatingsSymbol Parameter Rating UnitsV DD Power supply -0.3 to 3.6 VV IN Input voltage -0.3 to V DD+0.3 VV OUT Output voltage -0.3 to V DD+0.3 Vtemperature -55 to 150o CT STG StorageTable 1.2 Recommended Operating ConditionsMax. Units Symbol Parameter Min.3.6 V3.0V DD Powersupply-0.3V DD+0.3VvoltageV IN Inputtemperature 0 70 o CT OPR OperatingTable 1.3 DC CharacteristicsMaxUnitsTypSym. Parameter MinV IL Input low voltage 0.2V DD VV IH Input high voltage 0.2 VV IL Schmitt input low voltage 0.9 VV IH Schmitt input high voltage 2.5 VV OL Output low voltage 0.4 VV OH Output high voltage Vcc – 0.8 VR I Input pull up/down resistance 75 kΩPHYSYCAL SPECIFICATION52.5±0.3mm< View from connector side >< View from Right side >44 pin Type Flash Disk Module DimensionsINSTALLTION GUIDE1) Setting Method①Make sure your computer is turned off before you open the case.②Plug the carefully into the 44pin IDE slot on your computer.Caution: Make sure to align pin1 on host adapter interface connector with pin 1 on your Flash Disk Module. Pin 1 is indicated by a triangle on the Flash Disk Module connector.③The Flash Disk Module is used power connector cable of the computer.Caution: If you need to remove your Flash Disk Module, use both hands to pull it out carefully.④Check all cable connections and then replace your computer cover.2) BIOS setting MethodBefore you format or partition your new drive, you must configure your computer's BIOS so that the computer can recognize your new drive.①Turn your computer on. As your computer start up, watch the screen for a message describing how to run thesystem setup program on the screen (sometimes called BIOS or CMOS setup). This is usually done by pressing a special key, such as Delete, Esc or F1 during startup. See your computer manual for details. Press the appropriate key to run the system setup program.②If your BIOS provides automatic drive detection (an "AUTO" drive type), select this option. ( Werecommend to use Normal / CHS mode to partition your Flash Disk Module to get the maximum formatted capacity. )This allows your computer to configure itself automatically for your new drive.If your BIOS dose not provide “AUTO” drive detection, select "User-defined" drive setting and enter the CHS values from the table. BIOS Settings (see specification) Capacity Cylinders Heads Sectors(unformatted)③Save the settings and exit the System Setup program. ( your computer will automatically reboot ) After youconfigure your computer, you can use the standard DOS commands to partition and format your Flash Disk Module, as described below.3) Formatting MethodTo partition your new Flash Disk Module with Microsoft DOS program :① Insert a bootable DOS diskette into your diskette drive and restart your computer.② Insert a DOS program diskette that contains the FDISK.EXE and programs into your diskette drive. Use the same DOS version that is on your bootable diskette. At the A:\ > prompt, type “FDISK” and press Enter.③ Select “Create DOS partition or logical DOS drive” by pressing 1. Then press Enter.④ Select “Create primary DOS partition” by pressing 1 again. Then press Enter.Create your first drive partition. If you are creating a partition that will be used to boot your computer (drive C),make sure that the partition is marked active.⑤ Create an extended partition and additional logical drives as necessary, until all the space on your new hard drivehas been partitioned.⑥ When the partitioning is complete, FDISK reboots your computer.Caution: Make sure to use the correct drive letters so that you do not format a drive that already contains data.⑦ At the A:\ > prompt, type “format c:/s”, where c is the letter of your first new partition, Repeat the format processfor all the new partitions you have created.⑧ After you format your drive, it is ready to use.2. PIN INFORMATIONPIN ASSIGNMENTS AND PIN TYPETable 2.1 Pin Assignment and Pin typePin PinIDE Signal Pin Type IDE Signal Pin Type1 /RESET I2 GND Ground3 D07 I/O4 D08 I/O5 D06 I/O 6 D09 I/O7 D05 I/O8 D10 I/O9 D04 I/O 10 D11 I/O 11 D03 I/O 12 D12 I/O 13 D02 I/O 14 D13 I/O 15 D01 I/O 16 D14 I/O 17 D00 I/O 18 D15 I/O 19 GND DC 20 NC -- 21 NC -- 22 GND Ground 23 /IOW I 24 GND Ground 25 /IOR I 26 GND Ground 27 IORDY O 28 NC -- 29 NC -- 30 GND Ground 31 IRQ O 32 /IOIS16 O 33 A01 I 34 /PDIAG I/O 35 A00 I 36 A02 I 37 /CS0 I 38 /CS1 I 39 /DASP(LED) I/O 40 GND Ground 41 VCC Power 42 VCC Power 43GND Ground 44NC --Signal DescriptionsTable 2.2 Signal DescriptionsSignal Name Dir.PinDescriptionA[2:0] I 33,35,36 In True IDE Mode only A[2:0] are used to select the one of eight registers inthe Task File, the remaining address lines should be grounded by the host.-PDIAG I/O 34 This input / output is the Pass Diagnostic signal in the Master / Slavehandshake protocol.-DASP I/O 39 In the True IDE Mode, this input/output is the Disk Active/SlavePresent signal in the Master/Slave handshake protocol.-CS0, -CS1I 37,38 CS0 is the chip select for the task file registers while CS2 is used to selectthe Alternate Status Register and the Device Control Register.D[15:00]I/O3,4,5,6,7,8,9,10, 11,12,13, 14,15,16, 17,18 All Task File operations occur in byte mode on the low order bus D00-D07while all data transfers are 16 bit using D00-D15.GND-- 2,19,22,24,26, 30,40,43Ground.-IOR I 25This is an I/O Read strobe generated by the host. -IOWI 23 The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the Storage Card controller registers when the Storage Card isconfigured to use the I/O interface. The clocking will occur on the negative topositive edge of the signal (trailing edge). IRQ O 31In True IDE Mode signal is the active high Interrupt Request to the host. -RESET I 1This input pin is the active low hardware reset from the host. IORDY O 27This output signal may be used as IORDY. -IOIS16 O 32 This output signal is asserted low when this device is expecting a word datatransfer cycle. VCCPower 41,42 PowerBLOCK DIAGRAMFigure 2.1 Block Diagram3. INTERFACE BUS TIMINGACCESS SPCIFICATIONS1 System clock timingSym. Description Min. Typ. Max. Unit Tc Clock cycle time45 50 100 ns Tlpd Clock low pulse duration 0.4Tc 0.6Tc ns Thpd Clock high pulse duration 0.4Tc 0.6Tc ns2 Host Read/Write timingSym. Description Min.Typ.Max. Unit Td HD bus asserted from HIOR# / HOE# 10ns Th (R) HD hold time after HIOR# / HOE# 40 70 ns Ts (W) HD set up time of HIOW# / HWE# 10 ns Th (W) HD hold time of HIOW# / HWE# 5ns3 Flash Read/Write timingSym. Description Min.Typ.Max. Unit Tc (F) Flash Read / Write cycle time 100 ns Ts (FW) FD set up time of FWE# 80 ns Th (FW) FD hold time of FWE# 40 ns Ts (FR) FD set up time of FRD# 10 ns Th (FR) FD hold time of FRD# 5nsREGISTERS1) Data Register (Address – 1F0h[170h];Offset 0,8,9)The Data Register is a 16-bit register, and it is used to transfer data blocks between theCompactFlash Storage Card data buffer and the Host. This register overlaps the Error Register.The table below describes the combinations of data register access and is provided to assist in understanding the overlapped Data Register and Error/Feature Register rather than to attempt to define general PCMCIA word and byte access modes and operations. See the PCMCIA PC Card Standard Release 2.0 for definitions of the Card Accessing Modes for I/O and Memory cycles.Note: Because of the overlapped registers, access to the 1F1h, 171h or offset 1 are not defined for word (-CE2 = 0 and -CE1 = 0) operations. These accesses are treated as accesses to the Word DataRegister. The duplicated registers at offsets 8, 9 and Dh have no restrictions on the operations thatcan be performed by the socket.Data Register AccessDATA Register CE2- CE1- A0 OffsetData Bus Word Data Register 0 0 X 0,8,9 D15-D01 0 0 0,8 D7-D0Even Data RegisterOdd Data Register 1 0 1 9 D7-D0Odd Data Register 0 1 X 8,9 D15-D8Error/Feature Register 1 0 1 1,Dh D7-D0Error/Feature Register 0 1 X 1 D15-D8Error/Feature Register 0 0 X Dh D15-D82) Error Regis t er (Address – 1F1h[171h];Offset 1,0Dh Read Only)This register contains additional information about the source of an error when an error isindicated in bit 0 of the Status register. The bits are defined as follows:D7 D6 D5 D4 D3 D2 D1 D0BBK UNC 0 IDNF 0 ABRT 0 AMNFError RegisterThis register is also accessed on data bits D15-D8 during a write operation to offset 0 with -CE2 low and -CE1 high.Bit 7 (BBK): this bit is set when a Bad Block is detected.Bit 6 (UNC): this bit is set when an Uncorrectable Error is encountered.Bit 5: this bit is 0.Bit 4 (IDNF): the requested sector ID is not valid error or cannot be found.Bit 3: this bit is 0.Bit 2 (Abort) This bit is set if the command has been aborted because of a CompactFlashStorage Card status condition: (Not Ready, Write Fault, etc.) or when an invalid commandhas been issued.Bit 1 This bit is 0.Bit 0 (AMNF) This bit is set in case of a general error happened.3) Feature Register(Address – 1F1h[171h];Offset 1,0Dh Writer Only)This register provides information regarding features of the CompactFlash Storage Card that the host can utilize.This register is also accessed on data bits D15-D8 during a write operation to Offset 0 with -CE2 low and -CE1 high.BIT DESCRIPTION-7 6 5 4 3 2 1 0Command specific4) Sector Count Register(Address – 1F2h[172h];Offset 2)This register contains the numbers of sectors of data requested to be transferred on a read orwrite operation between the host and the CompactFlash Storage Card. If the value in this register is zero, a count of 256 sectors is specified. If the command was successful, this register is zero at command completion. If not successfully completed, the register contains the number of sectors that need to be transferred in order to complete the request.BIT DESCRIPTION-7 6 5 4 3 2 1 0Sector Count5) Sector Number (LBA 7-0) Register(Address–1F3h[173h];Offset 3)This register contains the starting sector number or bits 7-0 of the Logical Block Address (LBA)for any CompactFlash Storage Card data access for the subsequent command.BIT DESCRIPTION - CHS7 6 5 4 3 2 1 0Sector (7: 0)LBA7 6 5 4 3 2 1 0LBA (7 : 0)6) Cylinder Low (LBA 15-8 )Register (Address–1F4h[174h];Offset 4)This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of theLogical Block Address.DIT DESCRIPTION-CHS7 6 5 4 3 2 1 0Cylinder ( 7: 0 )LBA7 6 5 4 3 2 1 0LBA ( 15 : 8 )7) Cylinder High(LBA 23–16)Register(Address–1F5h[175h]; Offset 6)This register contains the high order bits of the starting cylinder address or bits 23-16 of theLogical Block Address.BIT DESCRIPTION-CHS7 6 5 4 3 2 1 0Cylinder ( 15 :8 )LBA7 6 5 4 3 2 1 0LBA ( 23 : 16 )8) Status/Alternate Status Register(Address 1F7h[177h]/3F6h[376h];Offset 7/ Eh)These registers return the CompactFlash Storage Card status when read by the host. Readingthe Status register does clear a pending interrupt, while reading the Alternate Status register does not. The status bits are described as follows:D7 D6 D5 D4 D3 D2 D1 D0 BUSY RDY DWF DSC DRQ CORR 0 ERRStatus & Alternate Status RegisterBit 7 (BUSY): the busy bit is set when the CompactFlash Storage Card has access to thecommand buffer and registers and the host is locked out from accessing the commandregister and buffer. No other bits in this register are valid when this bit is set to a 1.Bit 6 (DRDY): DRDY indicates whether the device is capable of performing CompactFlash Storage Card operations. This bit is cleared at power up and remains cleared until the CompactFlash Storage Card is ready to accept a command.Bit 5 (DWF): This bit, if set, indicates a write fault has occurred.Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready.Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires theinformation to be transferred either to or from the host through the Data register.Bit 2 (CORR): This bit is set when a Correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation.Bit 1 (IDX): This bit is always set to 0.Bit 0 (ERR): This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. It is recommendedthat media access commands (such as Read Sectors and Write Sectors) that end with anerror condition should have the address of the first sector in error in the command blockregisters.9) Device Control Register( Address – 3F6h[376h]; Offset Eh)This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft reset to the card. This register can be written even if the device is BUSY. The bits are defined as follows: D& D6 D5 D4 D3 D2 D1 D0Rst-IEn 0SWX X X X 1Device Control RegisterBit 7: this bit is an X (don’t care).Bit 6: this bit is an X (don’t care).Bit 5: this bit is an X (don’t care).Bit 4: this bit is an X (don’t care).Bit 3: this bit is ignored by the CompactFlash Storage Card.Bit 2 (SW Rst): this bit is set to 1 in order to force the CompactFlash Storage Card to perform an AT Disk controller Soft Reset operation. This does not change the PCMCIA CardConfiguration Registers (4.3.2 to 4.3.5) as a hardware Reset does. The Card remains inReset until this bit is reset to ‘0.’Bit 1 (-IEn): the Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1,The interrupts from the CompactFlash Storage Card are disabled. This bit also controls the Int bit in the Configuration and Status Register. This bit is set to 0 at power on and Reset.Bit 0: this bit is ignored by the CompactFlash Storage Card.10) Card (Drive) Address Register(Address 3F7h[377h]; Offset Fh)This register is provided for compatibility with the AT disk drive interface. It is recommended that this register not be mapped into the host’s I/O space because of potential conflicts on Bit 7. The bits are defined as follows:D7 D6 D5 D4 D3 D2 D1 D0X -WTG -HS3 -HS2 -HS1 -HS0 -nDS1 -nDS0Card (Drive) Address RegisterBit 7: this bit is in High Imoedence.. Implementation Note:Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller operating at the same addresses as the CompactFlash Storage Card. Following are some possible solutions to this problem for the PCMCIA implementation:1) Locate the CompactFlash Storage Card at a non-conflicting address, i.e. Secondaryaddress (377) or in an independently decoded Address Space when a Floppy Disk Controller is located at the Primary addresses.2) Do not install a Floppy and a CompactFlash Storage Card in the system at the same time. 3) Implement a socket adapter, which can be programmed to (conditionally) tri-state D7 of I/0 address 3F7h/377h when a Compact Flash Storage Card is installed and conversely to tri-state D6-D0 of I/O address 3F7h/377h when a floppy controller is installed.4) Do not use the CompactFlash Storage Card’s Drive Address register. This may beaccomplished by either a) If possible, program the host adapter to enable only I/O addresses 1F0h-1F7h, 3F6h (or 170h-177h, 176h) to the CompactFlash Storage Card or b) if provided use an additional Primary / Secondary configuration in the CompactFlash Storage Card which does not respond to accesses to I/O locations 3F7h and 377h. With either of these implementations, the host software must not attempt to use information in the Drive Address Register.Bit 6 (-WTG ): this bit is 0 when a write operation is in progress, otherwise, it is 1. Bit 5 (-HS3): this bit is the negation of bit 3 in the Drive/Head register. Bit 4 (-HS2): this bit is the negation of bit 2 in the Drive/Head register. Bit 3 (-HS1): this bit is the negation of bit 1 in the Drive/Head register. Bit 2 (-HS0): this bit is the negation of bit 0 in the Drive/Head register. Bit 1 (-nDS1): this bit is 0 when drive 1 is active and selected. Bit 0 (-nDS0): this bit is 0 when the drive 0 is active and selected.4. ATA COMMANDCF-ATA Command SetTable summarizes the CF-ATA command set with the paragraphs that follow describing the individual commands and the task file for each. Table:CF-ATA Command Set Class COMMAND Code FR SC SN CY DH LBA 1Check Power ModeE5h or 98h----D-1 Execute Drive Diagnostic 90h - - - - D -2 Format Track 50h - Y - Y Y Y 1 Identify Drive ECh - - - - D - 1 IdleE3h or 97h - Y - - D - 1Idel ImmediateE1h or 95h----D-1 Initialize Drive Parameters 91h - Y - - Y - 1 Read Buffer E4h - - - - D - 1Read Long Sector22h or 23h --YYYY1 Read Multiple C4h - Y Y Y Y Y 1 Read Sector(s) 20h or 21h - Y Y Y Y Y 1Read Verify Sector(s)40h or 41h -YYYYY1 Recalibrate 1Xh - - - - D - 1 Request Sence03h- - - - D -1 Seek 7Xh - - Y Y Y Y 1 Set Features EFh Y - - - D - 1 Set Multiple Mode C6h - Y - - D - 1 Set Sleep Mode E6h or 99h - - - - D - 1 Stand ByE2h or 96h - - - - D - 1Stand By ImmediateE0h or 94h ----D-1 Translate Sector 87h - Y Y Y Y Y 1 Wear Level F5h - - - - Y -2 Write Buffer E8h - - - -- D - 2Write Long Sector32h or 33h --YYYY3 Write Multiple C5h- Y Y Y Y Y 3 WriteMultiple w/o Erase CDh - Y Y Y Y Y 2 Write Sector(s)30h or 31h- Y Y Y Y Y 2Write Sector(s) w/o Erase 38h-YYYYY3 Write Verify 3Ch- Y Y Y Y YDefinitions:--FR = Features Register --SC = Sector Count Register --SN = Sector Number Register --CY = Cylinder Registers--DH = Card/Drive/Head Register--LBA = Logical Block Address Mode Supported (see command descriptions for use).--Y - The register contains a valid parameter for this command. For the Drive/Head Register Ymeans both the CompactFlash Storage Card and head parameters are used; D - only the CompactFlash Storage Card parameter is valid and not the head parameter. Check Power Mode – 98h or E5hBit-> 7 6 5 4 3 2 1 0 Command(7)98h or E5hC/D/H(6) X Drive X Cly High(5) X Cly Low(4) X Sec Num(3) X Sec Cnt(2)XFeature(1) XCheck Power ModeThis command checks the power mode. f the CompactFlash Storage Card is in, going to, or recovering from the sleep mode, the CompactFlash Storage Card sets BSY, sets the Sector Count Register to 00h, clears BSY and generates an interrupt. If the CompactFlash Storage Card is in Idle mode, the CompactFlash Storage Card sets BSY, sets the Sector Count Register to FFh, clears BSY and generates an interrupt.Execute Drive Diagnostic – 90hBit-> 7 6 5 4 3 2 1 0 Command(7) 90hDrive XC/D/H(6) XCyl High(5) XCyl Low(4) XSec Num(3) XSec Cnt(2) XFeature(1) XExecute Drive DiagnosticThis command performs the internal diagnostic tests implemented by the CompactFlash Storage Card.If in PCMCIA configuration this command runs only on the CompactFlash Storage Card which is addressed by the Drive/Head register when the diagnostic command is issued. This is because PCMCIA card interface does not allows for direct inter-drive communication (such as the ATA PDIAG and DASP signals). If in True IDE Mode the Drive bit is ignored and the diagnostic command is executed by both the Master and the Slave with the Master responding with status for both devices.The Diagnostic codes shown in Table 39 are returned in the Error Register at the end of the command.Diagnostic CodesCode ERROR TYPE01h No Error Detected02h Formatter Device Error03h Sector Buffer Error04h ECC Circuitry Error05h Controlling Microprocessor Error8Xh Slave Error in True IDE ModeErase Sector(s) – C0hBit-> 7 6 5 4 3 2 1 0 Command(7) C0h C/D/H(6) 1 LBA 1 Drive Head(LBA27-24)Cyl High(5) Cylinder High (LBA 23-16)Cyl Low(4) Cylinder Low (LBA 15-8)Sec Num(3) Sector Number (LBA 7-0 )Sec Cnt(2) Sector CountFeature(1) XErase SectorThis command is used to pre-erase and condition data sectors in advance of a Write withoutErase or Write Multiple without Erase command. There is no data transfer associated with thiscommand but a Write Fault error status can occur.Format Track -50hBit-> 7 6 5 4 3 2 1 0 Command(7) 50h C/D/H(6) 1 LBA 1 Drive Head(LBA27-24)Cyl High(5) Cylinder High (LBA 23-16)Cyl Low(4) Cylinder Low (LBA 15-8)Sec Num(3) X (LBA 7-0 )Sec Cnt(2) Count (LBA mode only)Feature(1) XFormat TrackThis command writes the desired head and cylinder of the selected drive with a vendor unique data pattern (typically FFh or 00h).To remain host backward compatible, the CompactFlash Storage Card expects a sector buffer of data from the host to follow the command with the same protocol as the Write Sector(s) command although the information in the buffer is not used by the CompactFlash Storage Card.If LBA=1 then the number of sectors to format is taken from the SecCnt register (0=256). The use of this command is not recommended.Identify Drive - EChBit-> 7 6 5 4 3 2 1 0 Command(7) ECh C/D/H(6) X X X Drive XCyl High(5) XCyl Low(4) XSec Num(3) XSec Cnt(2) XFeature(1) XIdentify DriveThe Identify Drive command enables the host to receive parameter information from theCompactFlash Storage Card. This command has the same protocol as the Read Sector(s)command. The parameter words in the buffer have the arrangement and meanings defined inTable . All reserved bits or words are zero. Table 40 is the definition for each field in theIdentify Drive Information.Table: Identify Drive InformationWord Address DefaultValueTotalBytesData Field Type Information0 848Ah 2 Generalconfiguration – signature for the CompactFlash Storage Card1 xxxxh2 Default number of cylinders2 0000h 2 Reserved3 00xxh 2 Default number of heads4 xxxxh 2 Number of unformatted bytes per track5 xxxxh 2 Number of unformatted bytes per sector6 xxxxh 2 Default number of sectors per track7-8 xxxxh 4 Number of sectors per card (Word 7 = MSW , word 8 = LSW)Unique9 xxxxh 2Vendor10-19 aaaa 20 Serial number in ASCII (Right Justified )type20 xxxxh 2 Buffer21 xxxxh 2 Buffer size in 512 byte increments22 0004h 2 # of ECC bytes passed on Read/Write Long Commands23-26 aaaa 8 Firmware revision in ASCII. Big Endian Byte Order in Word27-46 aaaa 40 Model number in ASCII (Left Justified) Big Endian Byte Order in Word47 xxxxh 2 Maximum number of sectors on Read/Write Mutliple command48 0000h 2 Double Word not supported49 xx00h 2 Capabilities50 0000h 2 Reserved51 0x00h 2 PIO data transfer cycle timing mode52 0000h 2 DMA data transfer cycle timing mode53 0001h 2 Translation parameters are valid54 Xxxxh 2 Current numbers of cylinders55 xxxxh 2 Current numbers of heads56 xxxxh 2 Current sectors per track57-58 xxxxh 4 Current capacity in sectors(LBAs)(Word 57 = LSW , Word 58 = MSW)59 010xh 2 Multiple sector setting60-61 xxxxh 4 Total number of sectors addressable in LBA Mode62-127 0000h 138 Reserved128 xxxxh 2 Securitystatus129-159 0000h 64 Vendor unique bytes160 xxxxh 2 Power requirement description161-255 0000h 170 ReservedIdle – 97h or E3hBit-> 7 6 5 4 3 2 1 0 Command(7) 97h or E3hC/D/H(6) X Drive XCyl High(5) XCyl Low(4) XSec Num(3) XSec Cnt(2) Timer Count (5 mess increments)Feature(1) XIdleThis command causes the CompactFlash Storage Card to set BSY, enter the Idle mode, clearBSY and generate an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5 milliseconds and the automatic power down mode is enabled. If the sector count is zero, the automatic power down mode is disabled. Note that this time base (5msec) is different from the ATA specification.Idle Immediate – 95h or E1hBit-> 7 6 5 4 3 2 1 0 Command(7) 95h or E1hC/D/H(6) X Drive XCyl High(5) XCyl Low(4) XSec Num(3) XSec Cnt(2) XFeature(1) XIdle ImmediateThis command causes the CompactFlash Storage Card to set BSY, enter the Idle mode, clearBSY and generate an interrupt.Initialize Drive Parameters – 91hBit-> 7 6 5 4 3 2 1 0 Command(7) 91h C/D/H(6) X 0 X Drive Max Head(no. of heads-1)Cyl High(5) XCyl Low(4) XSec Num(3) XSec Cnt(2) Number of SectorsFeature(1) XInitialize Drive ParametersThis command enables the host to set the number of sectors per track and the number of heads per cylinder. Only the Sector Count and the Card/Drive/Head registers are used by this command.Read Buffer –E4h。

1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。

10(1A)
16(1C)
25(1E)
35(1V)
50(1H)
B B B B C D E F G
63(1J) 100(2A)
B C D F G
E F G
B C D D E F G
B C D E F G G
Байду номын сангаас
E F G
E F F G
Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consulation without fail.
EE61
4.0 5.8 5.0 5.8 6.3 5.8 8.0 6.2
0.65±0.1 0.65±0.1 0.65±0.1 0.65±0.1 0.90±0.2 0.90±0.2
1.0 0.35 -0.20 to +0.15 1.5 0.35 -0.20 to +0.15 1.8 0.35 -0.20 to +0.15 2.2 0.35 -0.20 to +0.15 3.1 0.70 ±0.20 4.6 0.70 ±0.20
EE60
元器件交易网
Aluminum Electrolytic Capacitor/HD
s Standard
Products
Case size Specification
Ripple current (120Hz) (+105°C) (m A ) Impedance (100kHz) (+20°C) ( Ω) Dia. Length Size Code
= 0.01 CV or 3(µA) After 2 minutes application of rated working voltage at +20°C. ( Whichever is greater) I< Please see the attached standard products list
16
47 100 220 4.7 10 22 33 47 100 330 4.7 10 22
25
V . HD
35
33 47 100 220 0.47 1.0 2.2 3.3
50
4.7 10 22 33 47 10
63
22 33 3.3 4.7 10 22
100
The taping dimension are explained on p.42 of our Catalog. Please use it as a reference guide. Endurance: 105°C 5000h
16 2 5
25 2 3
35 2 3
50 2 3
63 2 3
100 2 3
(Impedance ratio at 120 Hz)
Endurance
Shelf Life
Resistance to Soldering Heat
s Marking
After applying rated working voltage for 5000 hours at +105±2°C and then being stabilized at +20°C, capacitors shall meet the following limits. Capacitance change ±30% of initial measured value < 300 % of initial specified value tan δ = < DC leakage current = initial specified value After storage for 1000hours at +105±2 °C with no voltage applied and then being stabilized at +20°C, capacitors shall meet the limits specified in Endurance.(With voltage treatment) Capacitance change ±20% of initial measured value < tan δ = 200 % of initial specified value < DC leakage current = initial specified value After reflow soldering ( Refer to page 20 for recommendable temperature profile.) and then being stabilized at +20°C, capacitor shall meet the following limits. Capacitance change ±10% of initial measured value < initial specified value tan δ = < initial specified value DC leakage current =
Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consulation without fail.
s Dimensions in mm (not to scale) 0.3 max A±0.2 (I) ( ) reference size
Example.16V10µF Marking color : BLACK
φD±0.5
Negative polarity marking
C HD
Series identification
Japan
Category temp. range Rated W.V. Range Nominal Cap. Range Capacitance Tolerance DC Leakage Current tan δ Characteristics at Low Temperature
W.V. (V) 10 Z(-25°C) / Z( +20 ° C) 6 Z(-40 °C)/ Z(+20 °C) 12
W.V. code
V Code V Code s Case Size
Cap.(µF) W.V. 0.47 1.0 2.2 3.3 4.7 10 22 33 47 100 220 330
10 A 50 H
16 C 63 J
25 E 100 2A
35 V
D E F G
8.0 10.2 8.3
10.0 10.2 10.3 12.0
W.V. (V) 10
Cap.
(±20%)
tan δ
(120Hz) (+20°C)
Part No.
Min.Packaging Q'ty Taping
(µF) 100 220 330 10 22
(mm) 8 8 10 4 5 6.3 8 10 4 5 6.3 6.3 8 8 10 4 5 6.3 8 8 10 10 4 4 4 4 5 6.3 8 8 10 8 8 10 8 8 8 10
元器件交易网
Aluminum Electrolytic Capacitor/HD Surface Mount Type Series: HD Type : V
s Features Endurance: 5000h at105°C
s Specifications
Vibration-proof product is available upon request.(φ8 < = ) -40 to +105°C 10 to 100V .DC 0.47 to 330 µ F ±20 % (120Hz/+20°C)
(mm) 6.2 10.2 10.2 5.8 5.8 5.8 10.2 10.2 5.8 5.8 5.8 5.8 6.2 10.2 10.2 5.8 5.8 5.8 6.2 10.2 10.2 10.2 5.8 5.8 5.8 5.8 5.8 5.8 6.2 10.2 10.2 6.2 10.2 10.2 6.2 10.2 10.2 10.2 E F G B C D F G B C D D E F G B C D E F G G B B B B C D E F G E F G E F F G
L ±0.3 Size code B C D L A,B H max. 4.3 5.3 6.6 8.3 5.5 6.5 7.8 9.5 10.0 I 1.8 2.2 2.6 3.4 3.4 3.5 W
w P
(I)
10
Capacitance (µF)
(P)
H
W.V. code
B±0.2
K
Lot number
(pcs) EEVHD1A101P EEVHD1A221P EEVHD1A331P EEVHD1C100R EEVHD1C220R EEVHD1C470P EEVHD1C101P EEVHD1C221P EEVHD1E4R7R EEVHD1E100R EEVHD1E220P EEVHD1E330P EEVHD1E470P EEVHD1E101P EEVHD1E331P EEVHD1V4R7R EEVHD1V100R EEVHD1V220P EEVHD1V330P EEVHD1V470P EEVHD1V101P EEVHD1V221P EEVHD1HR47R EEVHD1H1R0R EEVHD1H2R2R EEVHD1H3R3R EEVHD1H4R7R EEVHD1H100P EEVHD1H220P EEVHD1H330P EEVHD1H470P EEVHD1J100P EEVHD1J220P EEVHD1J330P EEVHD2A3R3P EEVHD2A4R7P EEVHD2A100P EEVHD2A220P 1000 500 500 2000 1000 1000 500 500 2000 1000 1000 1000 1000 500 500 2000 1000 1000 1000 500 500 500 2000 2000 2000 2000 1000 1000 1000 500 500 1000 500 500 1000 500 500 500