FPGA可编程逻辑器件芯片EP2A15F672I8N中文规格书

WROSRLMT and EMAC_DMA_BMMODE.RDOSRLMT bits. Maximum outstanding requests=EMAC_DMA_ BMMODE.WROSRLMT + 1 (or) EMAC_DMA_BMMODE.RDOSRLMT + 1.
•Allowed burst sizes. The allowed burst sizes are 4 (EMAC_DMA_BMMODE.BLEN4), 8 (EMAC_DMA_BMMODE.
BLEN8), 16 (EMAC_DMA_BMMODE.BLEN16) and the SINGLE burst. Only those burst sizes configured by the program (via the EMAC_DMA_BMMODE register) are used for data transfer through the SCB bus.
However, SINGLE burst is available by default, when the EMAC_DMA_BMMODE.UNDEF bit in the is cleared.
Data transfers are restricted to the maximum burst size from this list of programmed burst sizes.•Burst splitting and burst selection. The EMAC-SCB splits the DMA requests into multiple bursts on the SCB system bus. Splitting is based on DMA count and software controllable burst enable bits (shown in the Allowed burst sizes) as well as burst types (INCR and INCR_ALIGNED) which are also controllable through the software. SINGLE burst is enabled when the EMAC_DMA_BMMODE.UNDEF bit is not set. Burst length select priority is in the sequence: UNDEF, 16, 8, and 4.
•INCR burst type
–If the EMAC_DMA_BMMODE.UNDEF bit is set, then the EMAC-SCB always chooses the maximum allowed burst length based on the EMAC_DMA_BMMODE.BLEN16, EMAC_DMA_BMMODE.BLEN8, EMAC_ DMA_BMMODE.BLEN4 bits. In cases where the DMA requests are not multiples of the maximum
allowed burst length, the SCB may also choose a burst-length of any value less than the maximum enabled burst-length (all lesser burst-length enables are redundant). For example, when length bits are enabled and the DMA requests a burst transfer size of 42 beats, then the SCB splits it into three bursts of 16, 16 and 10 beats respectively.
–If EMAC_DMA_BMMODE.UNDEF is not enabled, then the burst length is based on the priority of the enabled bits in the following order EMAC_DMA_BMMODE.BLEN16, EMAC_DMA_BMMODE.BLEN8, EMAC_ DMA_BMMODE.BLEN4. When the DMA requests a burst transfer, the SCB interface splits the
requested bursts into multiple transfers using only the enabled burst lengths. This splitting can occur when the requested burst is not a multiple of the maximum enabled burst. If it cannot choose any of the enabled burst lengths then it selects the burst length as 1.
For example, when EMAC_DMA_BMMODE.BLEN16, EMAC_DMA_BMMODE.BLEN8, EMAC_DMA_BMMODE.BLEN4 are enabled and the DMA requests a burst transfer of 42 beats, then the SCB interface splits it into multiple bursts of size 16, 16, 8, 1 and 1 beats respectively (the sequence is in decreasing burst sizes). •INCR_ALIGNED burst type. When the address-aligned burst-type is enabled (EMAC_DMA_BMMODE.
AAL), then in addition to the burst splitting conditions explained in the INCR Burst type, the SCB inter-face splits the DMA requested bursts such that each burst-size is aligned to the least significant bits of the start address. The SCB interface initially generates smaller bursts so that the remaining transfers can be transferred with the maximum possible (enabled) fixed burst lengths.
For example, in the same setting as explained earlier for EMAC_DMA_BMMODE.UNDEF set (EMAC_DMA_ BMMODE.BLEN16, EMAC_DMA_BMMODE.BLEN8, and EMAC_DMA_BMMODE.BLEN4 are enabled), DMA requests a burst size of 42 beats at the start address of 0x000003A4. The SCB starts the first transfer with
Table 23-6:Core Receive Engine Sub-Blocks (Continued)
CORE Receive Engine sub block Functionality overview
Receive Frame Controller Module–Packs incoming 8-bit input stream to 32-bit data
internally.
–Performs Frame filtering, for uni-cast/multi-cast/
broadcast frames.
–Attaches the calculated IP Checksum input from
Checksum Offload Engine.
–Updates the Receive Status to Bus Interface. Receive Flow Control Module–Detects the receiving Pause frame and pauses the
frame transmission for the delay specified within the
received Pause frame.
–Works in Full Duplex mode.
Receive IP Checksum Offload Engine–Calculates IPv4 header checksums and verify against
the received IPv4 header checksums.
–Identifies a TCP, UDP or ICMP payload in the
received IP datagrams.
Receive Bus Interface Unit Module Interface to the FIFO.
Address Filtering Module Performs Destination Address Filtering based on
Unicast/ Multi-cast/Broadcast frames.
–Provides CRC hash filtering.
EMAC PHY Interface
The EMAC can interface to the PHY via the RMII interface standard. The tables below indicate the RMII pins available in the EMAC in terms of their generic names. Please refer to the data sheet for exact pin names.
Table 23-7:RMII Pins
Sl. No.Generic Signal Name (IEEE Standards)RMII Pin functionality.
1. TXD0RMII transmit data pin D0 (di-bit lower)
2. TXD1RMII transmit data pin D1 (di-bit higher)
3. RXD0RMII receive data pin D0 (di-bit lower)
4. RXD1RMII receive data pin D1 (di-bit higher)
5. RMII CLK RMII common clock (for Tx and Rx), also called
reference clock
6. TXEN RMII transmit enable pin (Tx valid)
7. CRS RMII Carrier Sense / receive data valid
8. MDC Serial management clock driven by EMAC
E THERNET M EDIA A CCESS C ONTROLLER (EMAC)
EMAC F UNCTIONAL D ESCRIPTION
this. With this option available, programs are not always restricted to a contiguous memory loca-
tion in ring mode.
DMA Related Registers
A summary of DMA registers relative to their function is provided in the table below. Please refer to the
“Register Descriptions” sections for complete bit descriptions of each of these registers.
Table 23-10:Summary of DMA Related Registers.
Register Name Description
Bus Mode1Establishes the bus operating modes for the DMA with respect to the
SCB master interface.
Transmit Poll Demand Enables the transmit DMA to check whether or not the current
descriptor is owned by DMA. The transmit poll demand command is
given to wake up the TxDMA if it is in suspend mode. The TxDMA
can go into suspend mode because of an underflow error in a
transmitted frame or because of the unavailability of descriptors owned
by transmit DMA. This command can be issued anytime and the
TxDMA resets this command once it starts re-fetching the current
descriptor from host memory.
Receive Poll Demand Enables the receive DMA to check for new descriptors. This command
is given to wake-up the RxDMA from the SUSPEND state. The
RxDMA can go into SUSPEND state only because of the unavailability
of descriptors owned by it.
Receive Descriptor List Address Points to the start of the receive descriptor list. The descriptor lists
reside in the application memory space and must be word-aligned (32-
bit data bus). The DMA internally converts the descriptor list to a bus
width aligned address by making the corresponding LSBs low. Transmit Descriptor List Address Points to the start of the transmit descriptor list. The descriptor lists
reside in the application memory space and must be word-aligned (for
32-bit data bus). The DMA internally converts it to bus width aligned
address by making the corresponding LSB to low.
DMA Status Contains all the status bits that the DMA reports to the application.
The software driver reads this register during an interrupt service
routine or during polling. Most of the fields in this register cause the
host to be interrupted.
Operation Mode Establishes the transmit and receive operating modes and commands.
The operation mode register should be the last control register to be
written as part of DMA initialization.
Interrupt Enable Enables the interrupts reported by DMA status register. After a
hardware or software reset, all interrupts are disabled.。