MB8501E064AB-60L资料

144-pin, 1 M × 64 BIT Hyper Page Mode SO-DIMM, 3.3 V, 1-bank, 4 KR
s DESCRIPTION
The Fujitsu MB8501E064AB is a fully decoded, CMOS Dynamic Random Access Memory (DRAM) module consisting of four MB81V16165A devices. The MB8501E064AB is optimized for those applications requiring small size package, low power consumption, enhanced performance. The operation and electrical characteristics of the MB8501E064AB are the same as the MB81V16165A which features hyper page mode (EDO) operation. For ease of memory expansion, the MB8501E064AB is offered in an 144-pin Small Outline Dual In-line Memory Module package (SO-DIMM).
s PRODUCT LINE & FEATURES
Parameter
MB8501E064AB
-60-60L-70-70L
RAS Access Time60 ns max.70 ns max. Random Cycle Time104 ns min.124 ns min. Address Access Time30 ns max.35 ns max. CAS Access Time15 ns max.17 ns max. Hyper Page Mode Cycle Time25 ns min.30 ns min.
Power Dissipation (max.)Operating Mode1296 mW1152 mW Standby Mode28.8 mW14.4 mW28.8 mW14.4 mW
•Conformed to 144-pin SO-DIMM JEDEC standard
•Organization:1,048,576 words × 64 bits •Module Size:1.00” (height) × 2.66”
(length) × 0.15” (thick)•Memory: MB81V16165A
(1 M × 16, 4 K ref., 3.3 V), 4 pcs •3.3 V ± 0.3 V Supply Voltage •4,096 Refresh Cycles/65.6 ms
•Hyper Page Operation (EDO)
•Serial Presence Detect (Serial EEPROM)•RAS Only Refresh/CAS-before-RAS Refresh •Package and Ordering Information:
144-pin SO-DIMM, order as
MB8501E064AB-××DG (DG = Gold Pad)
2
MB8501E064AB-60/-70/-60L/-70L
3
MB8501E064AB-60/-70/-60L/-70L
s PIN ASSIGNMENTS
Pin No.MB8501E064AB Pin No.MB8501E064AB Pin No.MB8501E064AB Pin No.MB8501E064AB 1V SS37DQ873OE109A9
2V SS38DQ4074N.C.110N.C.
3DQ039DQ975V SS111A10
4DQ3240DQ4176V SS112N.C.
5DQ141DQ1077N.C.113V CC
6DQ3342DQ4278N.C.114V CC
7DQ243DQ1179N.C.115CAS2
8DQ3444DQ4380N.C.116CAS6
9DQ345V CC81V CC117CAS3
10DQ3546V CC82V CC118CAS7
11V CC47DQ1283DQ16119V SS
12V CC48DQ4484DQ48120V SS
13DQ449DQ1385DQ17121DQ24
14DQ3650DQ4586DQ49122DQ56
15DQ551DQ1487DQ18123DQ25
16DQ3752DQ4688DQ50124DQ57
17DQ653DQ1589DQ19125DQ26
18DQ3854DQ4790DQ51126DQ58
19DQ755V SS91V SS127DQ27
20DQ3956V SS92V SS128DQ59
21V SS57N.C.93DQ20129V CC
22V SS58N.C.94DQ52130V CC
23CAS059N.C.95DQ21131DQ28
24CAS460N.C.96DQ53132DQ60
25CAS161N.C.97DQ22133DQ29
26CAS562N.C.98DQ54134DQ61
27V CC63V CC99DQ23135DQ30
28V CC64V CC100DQ55136DQ62
29A065N.C.101V CC137DQ31
30A366N.C.102V CC138DQ63
31A167WE103A6139V SS
32A468N.C.104A7140V SS
33A269RAS0105A8141SDA
34A570N.C.106A11142SCL
35V SS71N.C.107V SS143V CC
36V SS72N.C.108V SS144V CC
4
MB8501E064AB-60/-70/-60L/-70L
s PIN DESCRIPTIONS
Symbol Function Input/Output Pin Count
A0 to A11Address Input Input12
RAS0Row Address Strobe Input1 CAS0 to CAS7Column Address Strobe Input8 WE Write Enable Input1
OE Output Enable Input1 DQ0 to DQ63Data-input/Data-output Input/Output64 SCL Serial PD Clock Input1
SDA Serial PD I/O Input/Output1
V CC Power Supply—18
V SS Ground—18
N.C.No Connection—19
5
MB8501E064AB-60/-70/-60L/-70L
s SERIAL PRESENCE DETECT (SPD) TABLE
Note:Any write operation must NOT be executed into the addresses of Byte 0 to Byte 127. Some or all data stored into Byte 0 to Byte 127 may be broken.
Byte Function Described Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 0
Number of Bytes Used by Module
Manufacturer
12 Bytes00001100
1T otal SPD Memory Size 256 Bytes00001000 2Memory Type EDO00000010 3Number of Row Addresses12 Addresses00001000 4Number of Column Addresses8 Addresses00001000 5Number of Banks 1 Bank00000001 6Module Data Width (1)64 Bits01000000 7Module Data Width (2)+0 Bits00000000 8Module Interface Levels LVTTL00000001 9RAS Access Time (t RAC)
60ns00111100
70ns01000110 10CAS Access Time (t CAC)
15ns00001111
17ns00010001 11
Module Configuration T ype
(Parity or ECC or None)
None00000000 12
Refresh Rate/
Type
Normal, Self Refresh10000000
Low Power, Self Refresh10000011
13 to 31Reserved for Future Offerings—————————
32 to 63Superset Information—————————
64 to 127Manufacturer’s Information—————————
128 to 255Unused Storage Locations—————————
6
MB8501E064AB-60/-70/-60L/-70L s ABSOLUTE MAXIMUM RATINGS (See WARNING)
WARNING:Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
(Referenced to V SS)
Note: * Undershoots of up to –2.0 volts with a pulse width not exceeding 20 ns are acceptable.
WARNING:Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses , operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
Parameter Symbol Value Unit Supply Voltage V CC–0.5 to +4.6V
Input Voltage V IN–0.5 to +4.6V
Output Voltage V OUT–0.5 to +4.6V
Short Circuit Output Current I OUT–50 to +50mA
Power Dissipation P D4W Storage T emperature T STG–55 to +125°C
Parameter Symbol
Value
Unit
Min.Typ.Max.
Supply Voltage V CC 3.0 3.3 3.6V Ground V SS—00V
Input High Voltage, All Inputs V IH 2.0—V CC + 0.3 V V
Input Low Voltage, All Inputs*V IL–0.3—0.8V Ambient T emperature T A0—+70°C
7
MB8501E064AB-60/-70/-60L/-70L
s CAPACITANCE
(T A = 25°C, f = 1 MHz, V CC = +3.3 V) Parameter Symbol
Value
Unit
Min.Max.
Input Capacitance
A0 to A11C IN1—28pF
RAS0C IN2—23pF
CAS0 to CAS7C IN3—12pF
WE C IN4—24pF
OE C IN5—24pF
SCL C IN6—8pF I/O Capacitance
DQ0 to DQ63C DQ—13pF
SDA C SDA—8pF
8
MB8501E064AB-60/-70/-60L/-70L
s DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)
Notes:*1.Referenced to V SS.
*2.I CC depends on the output load conditions and cycle rate. The specific values are obtained with the output open.
I CC depends on the number of address change as RAS = V IL and CAS = V IH and V IL > -0.3 V.
I CC1, I CC3, I CC4 and I CC5 are specified at one time of address change during RAS = V IL and CAS = V IH.
I CC2 are specified during RAS = V IH and V IL > –0.3 V. I CC6 is measured on condition that all address
signals are fixed steady state.
Parameter Notes Test Condition Symbol Min.
Max.
Unit
-60/-70-60L/-70L
Output High Voltage*1I OH = –2.0 mA V OH 2.4—V Output Low Voltage*1I OL = +2.0 mA V OL—0.4V
Input Leakage Current
CAS0 V ≤ V IN≤ V CC,
3.0 V ≤ V CC ≤ 3.6 V,
V SS = 0 V, all other pins
not under test = 0 V
I I(L)
–1010
µA
Others–3030
Output Leakage Current
0 V ≤ V OUT≤ V CC,
3.0 V ≤ V CC≤ 3.6 V,
Data out disabled
I O(L)–1010µA
Operating Current
(Average power
supply current)
*2
MB8501E064AB
-60/-60L RAS & CAS cycling,
t RC = min.
I CC1
—360
mA
MB8501E064AB
-70/-70L
—320
Standby Current
(Power supply
current)
*2
TTL Level RAS = CAS = V IH
I CC2
—8
mA
CMOS Level RAS = CAS ≥ V CC – 0.2 V—40.6
Refresh Current #1
(Average power
supply current)
*2
MB8501E064AB
-60/-60L CAS = V IH,
RAS = cycling,
t RC = min.
I CC3
—360
mA
MB8501E064AB
-70/-70L
—320
Hyper Page Mode
Current
*2
MB8501E064AB
-60/-60L RAS = V IL,
CAS = cycling,
t HPC = min.
I CC4
—360
mA
MB8501E064AB
-70/-70L
—320
Refresh Current #2
(Average power
supply current)
*2
MB8501E064AB
-60/-60L RAS = cycling,
CAS-before-RAS,
t RC = min.
I CC5
—360
mA
MB8501E064AB
-70/-70L
—320
Battery Backup
Current
(Average power
supply current)
*2
MB8501E064AB
-60/-70
RAS = cycling,
CAS-before-RAS,
t RAS = min. to 300 ns
V IH≥ V CC – 0.2 V,
V IL≤ 0.2 V, t RC = 16 µs
I CC6
—4—mA
MB8501E064AB
-60L/-70L
RAS = cycling,
CAS-before-RAS,
t RAS = min. to 300 ns
V IH≥ V CC – 0.2 V,
V IL≤ 0.2 V, t RC = 32 µs
—— 1.2mA
Refresh Current #3
(Average power supply current)
Self Refresh;I CC9—41mA
4
9
MB8501E064AB-60/-70/-60L/-70L
s AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Notes 1, 2, 3
(Continued) No.Parameter Notes Symbol
MB8501E064AB-60/-60L MB8501E064AB-70/-70L
Unit
Min.Max.Min.Max.
1
Time between
Refresh
-60/-70
t REF
—65.6—65.6ms -60L/-70L—128—128ms 2Random Read/Write Cycle Time t RC104—124—ns 3Read-Modify-Write Cycle Time t RWC138—162—ns 4Access Time from RAS*4, 7t RAC—60—70ns 5Access Time from CAS*5, 7t CAC—15—17ns 6Column Address Access Time*6, 7t AA—30—35ns 7Output Hold Time t OH3—3—ns 8Output Hold Time from CAS t OHC5—5—ns 9Output Buffer T urn On Delay Time t ON0—0—ns 10Output Buffer Turn Off Delay Time*8t OFF—15—17ns 11
Output Buffer T urn Off Delay Time
from RAS
*8t OFR—15—17ns 12
Output Buffer T urn Off Delay Time
from WE
*8t WEZ—15—17ns 13T ransition Time t T150150ns 14RAS Precharge Time t RP40—50—ns 15RAS Pulse Width t RAS6010000070100000ns 16RAS Hold Time t RSH15—17—ns 17CAS to RAS Precharge Time t CRP5—5—ns 18RAS to CAS Delay Time*9, 10t RCD14451453ns 19CAS Pulse Width t CAS10—13—ns 20CAS Hold Time t CSH40—50—ns 21CAS Precharge Time (Normal)*17t CPN10—10—ns 22Row Address Set Up Time t ASR0—0—ns 23Row Address Hold Time t RAH10—10—ns 24Column Address Set Up Time t ASC0—0—ns 25Column Address Hold Time t CAH10—10—ns 26
Column Address Hold Time from
RAS
t AR24—24—ns 27
RAS to Column Address Delay
Time
*11t RAD12301235ns 28Column Address to RAS Lead Time t RAL30—35—ns
10
(Continued)
No.Parameter Notes Symbol MB8501E064AB-60/-60L MB8501E064AB-70/-70L Unit Min.Max.Min.Max.29Column Address to CAS Lead Time t CAL 23—28—ns 30Read Command Set Up Time t RCS
0—0—ns 31Read Command Hold Time Referenced to RAS *12t RRH 0—0—ns 32Read Command Hold Time Referenced to CAS
*12t RCH 0—0—ns 33Write Command Set Up Time *13, 18
t WCS 0—0—ns 34Write Command Hold Time
t WCH 10—10—ns 35Write Command Hold Time from RAS t WCR 24—24—ns 36WE Pulse Width
t WP 10—10—ns 37Write Command to RAS Lead Time t RWL 15—17—ns 38Write Command to CAS Lead Time t CWL 10—13—ns 39DIN Set Up Time t DS 0—0—ns 40DIN Hold Time
t DH 10—10—ns 41Data Hold Time from RAS t DHR 24—24—ns 42RAS to WE Delay Time *18t RWD 77—89—ns 43CAS to WE Delay Time *18t CWD 32—36—ns 44Column Address to WE Delay Time
*18t AWD 47—54—ns 45RAS Precharge Time to CAS Active Time (Refresh Cycles)t RPC 5—5—ns 46CAS Set Up Time (C-B-R Refresh)t CSR 0—0—ns 47CAS Hold Time (C-B-R Refresh)t CHR 10—12—ns 48Access Time from OE
*7t OEA —15—17ns 49Output Buffer Turn Off Delay from OE
*8t OEZ —15—17ns 50OE to RAS Lead Time for Valid Data t OEL 10—10—ns 51OE to CAS Lead Time
t COL 5—5—ns 52OE Hold Time Referenced to WE *14t OEH 5—5—ns 53OE to Data in Delay Time t OED 15—17—ns 54RAS to Data in Delay Time t RDD 15—17—ns 55CAS to Data in Delay Time t CDD 15—17—ns 56DIN to CAS Delay Time *15t DZC 0—0—ns 57
DIN to OE Delay Time
*15t DZO
—
—
ns
(Continued)
No.Parameter Notes Symbol MB8501E064AB-60/-60L MB8501E064AB-70/-70L
Unit Min.Max.Min.Max.
58OE Precharge Time t OEP8—8—ns 59OE Hold Time Referenced to CAS t OECH10—10—ns 60WE Precharge Time t WPZ8—8—ns 61WE to Data in Delay Time t WED15—17—ns 62Hyper Page Mode RAS Pulse Width t RASP—100000—100000ns
63Hyper Page Mode Read/Write
Cycle Time
t HPC25—30—ns
64Hyper Page Mode Read-Modify-
Write Cycle Time
t HPRWC69—79—ns
65Access Time from CAS
Precharge
*7, 16t CPA—35—40ns
66Hyper Page Mode CAS
Precharge Time
t CP10—10—ns
67Hyper Page Mode RAS Hold
Time from CAS Precharge
t RHCP35—40—ns
68Hyper Page Mode CAS
Precharge to WE Delay Time
*18t CPWD52—59—ns
69RAS Pulse Width (Self Refresh)*19t RASS100—100—µs
70RAS Precharge Time (Self
Refresh)
*19t RPS104—124—ns
71CAS Hold Time (Self Refresh)*19t CHS–50—–50—ns
Notes:*1.An initial pause (RAS = CAS = V IH) of 200 µs is required after power-up followed by any eight RAS-only cycles before proper device operation is achieved. If an internal refresh counter is used, a minimum
of eight CAS-before-RAS initialization cycles are required instead of eight RAS cycles.
*2.AC characteristics assume t T = 5 ns.
*3.V IH (min) and V IL (max) are reference levels for measureing the timing of input signals. Transition times are measured between V IH (min) and V IL (max).
*4.Assumes that t RCD≤ t RCD (max), t RAD ≤ t RAD (max). If t RCD and/or t RAD is greater than the maximum recommended value shown in this table, t RAC will be increased by the amount that t RCD and/or t RAD
exceeds the value shown.
*5.If t RCD ≥ t RCD (max), t RAD ≥ t RAD (max), and t ASC ≥ t AA - t CAC - t T, access time is t CAC.
*6.If t RAD≥ t RAD (max) and t ASC ≤ t AA - t CAC - t T, access time is t AA.
*7.Measured with a load equivalent to two TTL loads and 100 pF.
*8.t OFF, t OEZ, t OFR and t WEZ are specified that output buffer change to high-impedance state.
*9.Operation within the t RCD (max) limit ensures that t RAC (max) can be met. t RCD (max) is specified as a reference point only; if t RCD is greater than the specified t RCD (max) limit, access time is controlled
exclusively by t CAC or t AA.
*10.t RCD (min) = t RAH (min)+ 2 t T + t ASC (min).
*11.Operation within the t RAD (max) limit ensures that t RAC (max) can be met. t RAD (max) is specified as a reference point only; if t RAD is greater than the specified t RAD (max) limit, access time is controlled
exclusively by t CAC or t AA.
*12.Either t RRH or t RCH must be satisfied for a read cycle.
*13.t WCS is specified as a reference point only. If t WCS≥ t WCS (min) the data output pin will remain High-Z state through entire cycle.
*14.Assumes that t WCS < t WCS (min).
*15.Either t DZC or t DZO must be satisfied.
*16.t CP A is access time from the selection of a new column address (caused by changing CAS from “L” to “H”). Therefore, if t CP become long, t CP A also become longer than t CP A (max).
*17.Assumes that CAS-before-RAS refresh.
*18.t WCS, t CWD, t RWD, t AWD, and t CPWD are not restrictive operating parameters. They are included in the data sheet as an electrical characteristic only. If t WCS≥ t WCS (min), the cycle is an early write cycle and D OUT
pin will maintain high-impedance state thoughout the entire cycle. If t CWD≥ t CWD (min), t RWD≥ t RWD
(min), t AWD≥ t AWD (min), and t CPWD≥ t CPWD (min), the cycle is a read-modify-write cycle and data from
the selected cell will appear at the D OUT pin. If neither of the above conditions is satisfied, the cycle is
a delayed write cycle and invalid data will appear the D OUT pin, and write operation can be executed
by satisfying t RWL, t CWL, t RAL and t CAL specifications.
*19.Assumes that self refresh.
*Source: See MB81V16165A Data Sheet for details on the electricals.
s SERIAL PRESENCE DETECT (SPD) FUNCTION
1.PIN DESCRIPTIONS
SCL (Serial Clock)
SCL input is used to clock all data input/output of SPD.
SDA (Serial Data)
SDA is a common pin used for all data input/output of SPD. The SDA pull-up resistor is required due to the open-drain output.
SA 0, SA 1, SA 2 (Address)
Address inputs are used to set the least significant three bits of the eight bits slave address. The address inputs must be fixed to select a particular module and the fixed address of each module must be different each other.For this module, any address inputs are not required because all addresses (SA 0, SA 1, SA 2) are driven to V SS on the module.2.SPD OPERATIONS
CLOCK and DATA CONVENTION
Data states on the SDA can change only during SCL = Low. SDA state changes during SCL = High are indicated start and stop conditions. Refer to Fig.2 below.
START CONDITION
All commands are preceded by a start condition, which is a transition of SDA state from High to Low when SCL = High. SPD will not respond to any command until this condition has been met.
STOP CONDITION
All read or write operation must be terminated by a stop condition, which is a transition of SDA state from Low to High when SCL = High. The stop condition is also used to make the SPD into the state of standby power mode after a read sequence.
START
Fig.2 – START AND STOP CONDITIONS
STOP
SCL
SDA
START = High to Low transition of SDA state when SCL is High STOP = Low to High transition of SDA state when SCL is High
ACKNOWLEDGE
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will put the SDA line to Low in order to acknowledge that it received the eight bits of data.
The SPD will respond with an acknowledge when it received the start condition followed by slave address issued by master.
In the read operation, the SPD will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is issued by master, the SPD will continue to transmit data. If anacknowledge is not detected, the SPD will terminated further data transmissions. The master must then issue a stop condition to return the SPD to the standby power mode.
In the write operation, upon receipt of eight bits of data the SPD will respond with an acknowledge, and await the next eight bits of data, again responding with an acknowledge until the stop condition is issued by master.
SLAVE ADDRESS ADDRESSING
Following a start condition, the master must output the eight bits slave address. The most significant four bits of the slave address are device type identifier. For the SPD this is fixed as 1010[B]. Refer to the Fig.3 below.The next three significant bits are used to select a particular device. A system could have up to eight SPD devices–namely up to eight modules– on the bus. The eight addresses for eight SPD devices are defined by the state of the SA0, SA1 and SA2 inputs. For this module, the three bits are fixed as 000[B] because all addresses are driven to V SS on the module. Therefore, no address inputs are required.
The last bit of the slave address defines the operation to be performed. When R/W bit is “1”, a read operation is selected, when R/W bit is “0”, a write operation is selected.
Following the start condition, the SPD monitors the SDA line comparing the slave address being transmitted with its slave address (device type and state of SA 0, SA 1, and SA 2 inputs). Upon a correct compare the SPD outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the SPD will execute a read or write operation.
1010R/W
SA 2SA 1SA 0DEVICE TYPE IDENTIFIER
DEVICE ADDRESS
Fig.3 – SLAVE ADDRESS
3.READ OPERATIONS
CURRENT ADDRESS READ
Internally the SPD contains an address counter that maintains the address of the last data accessed,incremented by one. Therefore, if the last access (either a read or write operation) was to address(n), the next read operation would access data from address(n+1). Upon receipt of the slave address with the R/W bit = “1”,the SPD issues an acknowledge and transmits the eight bits of data during the next eight clock cycles. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge.Refer to Fig.4 for the sequence of address, acknowledge and data transfer.
RANDOM READ
Random Read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit = “1”, the master must first perform a “dummy” write operation on the SPD.The master issues the start condition, and the slave address followed by the word address. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit = “1”. This will be followed by an acknowledge from the SPD and then by the eight bits of data. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig.5 for the sequence of address, acknowledge and data transfer.
A C K
Fig.4 – CURRENT ADDRESS READ
S T O P
DATA
SLAVE ADDRESS
S T A R T
BUS ACTIVITY:MASTER SDA LINE BUS ACTIVITY:SPD
A C K
Fig.5 – RANDOM READ
S T O P
DATA
SLAVE ADDRESS
A C K A C K SLAVE ADDRESS
WORD ADDRESS
S T A R T
S T A R T
BUS ACTIVITY:MASTER SDA LINE BUS ACTIVITY:SPD
SEQUENTIAL READ
Sequential Read can be initiated as either a current address read or random read. The first data are transmitted as with the other read mode, however, the master now responds with an acknowledge, indicating it requires additional data. The SPD continues to output data for each acknowledge received. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Fig.6 for the sequence of address, acknowledge and data transfer.
The data output is sequential, with the data from address (n) followed by the data from address (n+1). The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 255), the counter “rolls over” to address 0 and the SPD continues to output data for each acknowledge received.
4.DC CHARACTERISTICS
Parameter Note Test Condition Symbol Min.Max.Unit Input Leakage Current0 V ≤ V IN≤ V CC S ILI–1010µA Output Leakage Current0 V ≤ V OUT≤ V CC S ILO–1010µA Output Low Voltage*1I OL = 3.0 mA S VOL—0.4V Note:*1.Referenced to V SS.
5.AC CHARACTERISTICS
No.Parameter Symbol Min.Max.Unit 1SCL Clock Frequency f SCL0100KHz
2Noise Suppression Time
Constant at SCL, SDA Inputs
T I—100ns
3SCL Low to SDA Data Out Valid t AA0.3 3.5µs
4Time the Bus must be Free before
a New Transmission can Start
t BUF 4.7—µs
5Start Condition Hold Time t HD:STA 4.0—µs 6Clock Low Period t LOW 4.7—µs 7Clock High Period t HIGH 4.0—µs 8Start Condition Set Up Time t SU:STA 4.7—µs 9Data In Hold Time t HD:DAT0—µs 10Data In Set Up Time t SU:DAT250—ns 11SDA and SCL Rise Time t R—1µs 12SDA and SCL Fall Time t F—300ns 13Stop Condition Set Up Time t SU:STO 4.7—µs 14Data Out Hold Time t DH100—ns 15Write Cycle Time t WR—15
ms
s PACKAGE DIMENSIONS
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