12位串行DA芯片

V OUT A
V OUT B
V OUT C
V OUT D
V REF L
A0A1A2A3
GND
SCL
SDA
LDAC
DAC7573
SLAS398–SEPTEMBER2003 QUAD,12-BIT,LOW-POWER,VOLTAGE OUTPUT,
I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER
FEATURES DESCRIPTION
•Micro power Operation:600µA at5V V DD The DAC7573is a low-power,quad channel,12-bit •Power-On Reset to Zero buffered voltage output DAC.Its on-chip precision out-
put amplifier allows rail-to-rail output swing to be •+2.7V to+5.5V Analog Power Supply
achieved.The DAC7573utilizes an I2C compatible two •12-Bit Monotonic
wire serial interface supporting high-speed interface •I2C™Interface Up to3.4Mbps mode with address support of up to sixteen DAC7573s
for a total of64channels on the bus.
•Data Transmit Capability
•On-Chip Output Buffer Amplifier,Rail-to-Rail The DAC7573requires an external reference voltage Operation to set the output range of the DAC.The DAC7573•Double-Buffered Input Register incorporates a power-on-reset circuit that ensures that
the DAC output powers up at zero volts and remains •Address Support for up to Sixteen DAC7573s
there until a valid write takes place to the device.The •Synchronous Update Support for up to64
DAC7573contains a power-down feature,accessed Channels via the internal control register,that reduces the current
•Operation From-40°C to105°C consumption of the device to200nA at5V.
•Small16Lead TSSOP Package
The low power consumption of this part in normal
operation makes it ideally suited to portable battery APPLICATIONS operated equipment.The power consumption is less
•Process Control than3mW at V DD=5V reducing to1µW in power-down
mode.
•Data Acquisition Systems
The DAC7573is available in a16-lead TSSOP pack-•Closed-Loop Servo Control
age.
•PC Peripherals
•Portable Instrumentation
I2C is a trademark of Philips Corporation.
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.Copyright©2003,Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments
standard warranty.Production processing does not necessarily in-
cludetestingofallparameters.
A3A2A112345678
1615141
1211109V OUT A V OUT B V REF H V DD V REF L GND V OUT C V OUT D
A0IOV DD SDA SCL LDAC
DAC7573
DAC7573
SLAS398–SEPTEMBER 2003
This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE SPECIFICATION PACKAGE ORDERING TRANSPORT MEDIA
DRAWING TEMPERATURE
MARKING NUMBER NUMBER
RANGE DAC757316-TSSOP PW
-40°C TO +105°C
D7573I
DAC7573IPW 90Piece Tube DAC7573IPWR
2000Piece Tape and Reel
PIN DESCRIPTIONS
PW PACKAGE PIN NAME DESCRIPTION (TOPVIEW)
1
V OUT A Analog output voltage from DAC A 2V OUT B Analog output voltage from DAC B 3V REF H Positive reference voltage input 4V DD Analog voltage supply input 5V REF L Negative reference voltage input
Ground reference point for all circuitry on the 6GND
part
7V OUT C Analog output voltage from DAC C 8V OUT D Analog output voltage from DAC D 9LDAC H/W synchronous V OUT update 10SCL Serial clock input 11SDA Serial data input 12IOV DD I/O voltage supply input 13A0Device address select -I 2C 14A1Device address select -I 2C 15A2Device address select -Extended 16
A3
Device address select -Extended
ABSOLUTE MAXIMUM RATINGS (1)
V DD to GND
–0.3V to +6V Digital input voltage to GND –0.3V to V DD +0.3V V OUT to GND
–0.3V to V DD +0.3V Operating temperature range –40°C to +105°C Storage temperature range
–65°C to +150°C
Junction temperature range (T J max)+150°C Power dissipation:
Thermal impedance (ΘJA)161°C/W Thermal impedance (ΘJC)29°C/W Lead temperature,soldering:
Vapor phase (60s)215°C Infrared (15s)
220°C
(1)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.Exposure to absolute maximum conditions for extended periods may affect device reliability.
2
DAC7573 SLAS398–SEPTEMBER2003
ELECTRICAL CHARACTERISTICS
V DD=2.7V to5.5V,R L=2kΩto GND;C L=200pF to GND;all specifications-40°C to+105°C,unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE(1)(2)
Resolution12Bits Relative accuracy±8LSB Differential nonlinearity Specified monotonic by design±1LSB Zero-scale error520mV
Full-scale error-0.15±1.0%of FSR Gain error±1.0%of FSR Zero code error drift±7µV/°C Gain temperature coefficient±3ppm of FSR/°C OUTPUT CHARACTERISTICS(3)
Output voltage range0V REF H V Output voltage settling time(full scale)R L=∞;0pF<C L<200pF810µs
R L=∞;C L=500pF12µs
Slew rate1V/µs
DC crosstalk(channel-to-channel)0.02LSB
AC crosstalk(channel-to-channel)1kHz Sine Wave-100dB Capacitive load stability R L=∞470pF
R L=2kΩ1000pF Digital-to-analog glitch impulse1LSB change around major12nV-s
carry
Digital feedthrough0.3nV-s
DC output impedance1Ω
Short-circuit current V DD=5V50mA
V DD=3V20mA Power-up time Coming out of power-down 2.5µs
mode,V DD=+5V
Coming out of power-down5µs
mode,V DD=+3V
REFERENCE INPUT
V REF H Input range0V DD V
V REF L Input range V REF L<V REF H0GND V DD V Reference input impedance25kΩReference current V REF=V DD=+5V185260µA
V REF=V DD=+3V122200
LOGIC INPUTS(3)
Input current±1µA
V IN_L,Input low voltage0.3xIOV DD V
V IN_H,Input high voltage V DD=3V0.7xIOV DD V
Pin Capacitance3pF POWER REQUIREMENTS
V DD,IOV DD 2.7 5.5V
I DD(normal operation),including reference current Excluding load current
I DD@V DD=+3.6V to+5.5V V IH=IOV DD and V IL=GND600900µA
(1)Linearity tested using a reduced code range of48to4047;output unloaded.
(2)V
REF H=V DD-0.1,V REF L=GND
(3)Specified by design and characterization,not production tested.
3
DAC7573
SLAS398–SEPTEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
V DD =2.7V to 5.5V,R L =2k Ωto GND;C L =200pF to GND;all specifications -40°C to +105°C,unless otherwise specified.
PARAMETER TEST CONDITIONS MIN
TYP MAX UNITS I DD @V DD =+2.7V to +3.6V
V IH =IOV DD and V IL =GND
550
750
µA
I DD (all power-down modes)
I DD @V DD =+3.6V to +5.5V V IH =IOV DD and V IL =GND 0.21µA I DD @V DD =+2.7V to +3.6V
V IH =IOV DD and V IL =GND
0.05
1
µA
POWER EFFICIENCY I OUT /I DD
I LOAD =2mA,V DD =+5V
93%
TEMPERATURE RANGE Specified performance
-40
+105
°C
TIMING CHARACTERISTICS
V DD =2.7V to 5.5V,R L =2k Ωto GND;all specifications -40°C to +105°C,unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS MIN
TYP
MAX UNITS Standard mode
100kHz Fast mode
400kHz f SCL
SCL clock frequency
High-Speed Mode,C B =100pF max 3.4MHz High-speed mode,C B =400pF max
1.7
MHz Standard mode 4.7µs Bus free time between a t BUF
STOP and START condition Fast mode 1.3µs Standard mode
4.0µs Hold time (repeated)START
t HD ;t STA
Fast mode 600ns condition
High-speed mode 160ns Standard mode
4.7µs Fast mode
1.3µs t LOW
LOW period of the SCL clock
High-speed mode,C B =100pF max 160ns High-speed mode,C B =400pF max
320ns Standard mode
4.0µs Fast mode
600ns t HIGH
HIGH period of the SCL clock
High-Speed Mode,C B =100pF max 60ns High-speed mode,C B =400pF max
120ns Standard mode
4.7µs Setup time for a repeated
t SU ;t STA
Fast mode 600ns START condition
High-speed mode 160ns Standard mode
250ns t SU ;t DAT
Data setup time
Fast mode 100ns High-speed mode 10ns Standard mode
0 3.45µs Fast mode
00.9µs t HD ;t DAT
Data hold time
High-speed mode,C B =100pF max 070ns High-speed mode,C B =400pF max
150ns Standard mode
20×0.1C B 1000ns Fast mode
20×0.1C B
300ns t RCL
Rise time of SCL signal
High-speed mode,C B =100pF max 1040ns High-speed mode,C B =400pF max
20
80
ns
4
DAC7573
SLAS398–SEPTEMBER2003 TIMING CHARACTERISTICS(continued)
V DD=2.7V to5.5V,R L=2kΩto GND;all specifications-40°C to+105°C,unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Standard mode20×0.1C B1000ns Rise time of SCL signal after
Fast mode20×0.1C B300ns
a repeated START condition
t RCL1
and after an acknowledge High-speed mode,C
B =100pF max1080ns
BIT
High-speed mode,C B=400pF max20160ns
Standard mode20×0.1C B300ns
Fast mode20×0.1C B300ns
t FCL Fall time of SCL signal
High-speed mode,C B=100pF max1040ns
High-speed mode,C B=400pF max2080ns
Standard mode20×0.1C B1000ns
Fast mode20×0.1C B300ns
t RDA Rise time of SDA signal
High-speed mode,C B=100pF max1080ns
High-speed mode,C B=400pF max20160ns
Standard mode20×0.1C B300ns
Fast mode20×0.1C B300ns
t FDA Fall time of SDA signal
High-speed mode,C B=100pF max1080ns
High-speed mode,C B=400pF max20160ns
Standard mode 4.0µs Setup time for STOP con-
t SU;t STO Fast mode600ns dition
High-speed mode160ns
Capacitive load for SDA and
C B400pF
SCL
Fast mode50ns Pulse width of spike sup-
t SP
pressed High-speed mode10ns
Standard mode
Noise margin at the HIGH
V NH level for each connected de-Fast mode0.2V DD V vice(including hysteresis)High-speed mode
Standard mode
Noise margin at the LOW
V NL level for each connected de-Fast mode0.1V DD V vice(including hysteresis)High-speed mode
5
-8-6-4-202468
L E - L S B -1.0
-0.50.00.51.0
512
1024
1536
2048
2560
3072
3584
D L
E - L S B
Digital Input Code
-8-6-4-202468L E - L S B
-1.0
-0.50.00.51.0
512
1024
1536
2048
2560
3072
3584
D L
E - L S B
Digital Input Code
-8-6-4-202468L E - L S B -1.0
-0.50.00.51.0
512
1024
1536
2048
2560
3072
3584
D L
E - L S B
Digital Input Code
-8-6-4-202468L E - L S B
-1.0
-0.50.00.51.0
512
1024
1536
2048
2560
3072
3584
D L
E - L S B
Digital Input Code
-8-6-4-202468
L E - L S B -1.0
-0.50.00.51.0
512
1024
1536
2048
2560
3072
3584
D L
E - L S B
Digital Input Code
-8-6-4-202468
L E - L S B
-1.0
-0.50.00.51.00
512
1024
15362048256030723584
D L
E - L S B
Digital Input Code
DAC7573
SLAS398–SEPTEMBER 2003
TYPICAL CHARACTERISTICS
At T A =+25°C,unless otherwise noted.
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
LINEARITY ERROR vs DIGITAL INPUT CODE
Figure 1.
Figure 2.
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
LINEARITY ERROR vs DIGITAL INPUT CODE
Figure 3.
Figure 4.
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
Figure 5.
Figure 6.
6
-8-6-4-202468
L E - L S B -1.0
-0.50.00.51.0
512
1024
1536
2048
2560
3072
3584
D L
E - L S B
Digital Input Code
-8-6-4-202468
L E - L S B
-1.0
-0.50.00.51.0
512
1024
1536
2048
2560
3072
3584
D L
E - L S B
Digital Input Code
3
6
9
T A − Free-Air Temperature − °C
Z e r o -S c a l e E r r o r − m V
−20
2
4
−40
−10
20
50
80
T A − Free-Air T emperature − °C
Z e r o -S c a l e E r r o r − m V
−40
−10
20
50
80
T A − Free-Air T emperature − °C
F u l l -S c a l e E r r o r − m V
−2
−1.75
−1.5
−1.25
−1
−40
−10
20
50
80
T A − Free-Air T emperature − °C
F u l l -S c a l e E r r o r − m V
DAC7573
SLAS398–SEPTEMBER 2003
TYPICAL CHARACTERISTICS (continued)
At T A =+25°C,unless otherwise noted.
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
LINEARITY ERROR vs DIGITAL INPUT CODE
Figure 7.
Figure 8.
ZERO-SCALE ERROR ZERO-SCALE ERROR Figure 9.
Figure 10.
FULL-SCALE ERROR
FULL-SCALE ERROR vs TEMPERATURE
Figure 11.
Figure 12.
7
0.000
0.025
0.0500.0750.1000.1250.150
1
2
3
4
5
I SINK - Sink Current - mA
V O U T - O u t p u t V o l t a g e - V
5.30
5.35
5.40
5.45
5.50
1
2
3
4
5
I SOURCE - Source Current - mA
V O U T - O u t p u t
V o l t a g e - V
2.3
2.4
2.5
2.6
2.7
1
2
3
4
5
I SOURCE - Source Current - mA
V O U T - O u t p u t
V o l t a g e - V
Digital Input Code
1002003004005006007008000
512
1024153620482560307235844096
I D D - S u p p l y C u r r e n t - µA
T A - Free-Air Temperature - °C
0100
200
300400500600
700-40
-10
20
50
80
110
I D D - S u p p l y C u r r e n t - µA
V DD - Supply Voltage - V
200
250300350400450
5005506006507002.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
I D D - S u p p l y C u r r e n t - µA
DAC7573
SLAS398–SEPTEMBER 2003
TYPICAL CHARACTERISTICS (continued)
At T A =+25°C,unless otherwise noted.
SINK CURRENT CAPABILITY
SOURCE CURRENT CAPABILITY
AT NEGATIVE RAIL
AT POSITIVE RAIL
Figure 13.
Figure 14.
SOURCE CURRENT CAPABILITY
SUPPLY CURRENT AT POSITIVE RAIL
vs DIGITAL INPUT CODE
Figure 15.Figure 16.
SUPPLY CURRENT SUPPLY CURRENT vs TEMPERATURE
vs SUPPLY VOLTAGE
Figure 17.
Figure 18.
8
I DD - Current Consumption - µA
500
1000
15002000
F r e q u e n c y
V Logic - Logic Input Voltage - V
200
400
600800
100012000
1
2
3
4
5
I D D - S u p p l y C u r r e n t - µA
-1
0123456
Time (2 µs/div)
V O U T - O u t p u t V o l t a g
e - V
I DD - Current Consumption - µA
500
1000
15002000
400420440460480500520540560580600620
F r e q u e n c y
2.40
2.422.442.462.482.502.522.542.56
Time (15 µs/div)
V O U T - O u t p u t V o l t a g e - V (20 m V /d i v )
4.56
4.584.604.624.644.664.684.704.724.74Time (15 µs/div)
V O U T - O u t p u t V o l t a g e - V (20 m V /d i v )
DAC7573
SLAS398–SEPTEMBER 2003
TYPICAL CHARACTERISTICS (continued)
At T A =+25°C,unless otherwise noted.
SUPPLY CURRENT HISTOGRAM
OF CURRENT CONSUMPTION
Figure 19.
Figure 20.
HISTOGRAM
EXITING
POWER-DOWN MODE
Figure 21.
Figure 22.
OUTPUT GLITCH (Mid-Scale)
OUTPUT GLITCH (Worst Case)
Figure 23.
Figure 24.
9
Digital Input Code
048121620
240
512
1024
1536
2048
2560
3072
3584
O u t p u t E r r o r - m V
Digital Input Code
-6
-2261014180
512
1024
1536
2048
2560
3072
3584
O u t p u t E r r o r - m V
12345
Time (25 µs/div)V O U T - O u t p u t V o l t a g e - V
0.0
0.51.01.52.02.53.0Time (25 µs/div)
V O U T - O u t p u t V o l t a g e - V
DAC7573
SLAS398–SEPTEMBER 2003
TYPICAL CHARACTERISTICS (continued)
At T A =+25°C,unless otherwise noted.
ABSOLUTE ERROR †
ABSOLUTE ERROR †
Figure 25.Figure RGE SIGNAL LARGE SIGNAL SETTLING TIME
SETTLING TIME
Figure 27.
Figure 28.
†
Absolute error is the deviation from ideal DAC characteristics.It includes affects of offset,gain,and integral linearity.
10
V OUT V H
V REF L
V
OUT+V REF L)(V REF H*V REF L)
D 4096
(1)
To Output
Amplifier
V REF L
THEORY OF OPERATION
D/A SECTION
The architecture of the DAC7573consists of a string DAC followed by an output buffer amplifier.Figure29 shows a generalized block diagram of the DAC architecture.
Figure29.R-String DAC Architecture
The input coding to the DAC7573is unsigned binary,which gives the ideal output voltage as:
Where D=decimal equivalent of the binary code that is loaded to the DAC register;it can range from0to4095. RESISTOR STRING
The resistor string section is shown in Figure30.It is basically a divide-by-2resistor,followed by a string of resistors,each of value R.The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier.Because the architecture consists of a string of resistors,it is specified monotonic.
Figure30.Typical Resistor String
Output Amplifier
The output buffer is a gain-of-2noninverting amplifier,capable of generating rail-to-rail voltages on its output, which gives an output range of0V to V DD.It is capable of driving a load of2kΩin parallel with1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves.The slew rate is1V/µs with a half-scale settling time of8µs with the output unloaded.
I2C Interface
I2C is a2-wire serial interface developed by Philips Semiconductor(see I2C-Bus Specification,Version2.1, January2000).The bus consists of a data line(SDA)and a clock line(SCL)with pullup structures.When the bus is idle,both SDA and SCL lines are pulled high.All the I2C compatible devices connect to the I2C bus through open drain I/O pins,SDA and SCL.A master device,usually a microcontroller or a digital signal processor, controls the bus.The master is responsible for generating the SCL signal and device addresses.The master also generates specific conditions that indicate the START and STOP of data transfer.A slave device receives and/or transmits data on the bus under control of the master device.
SLAS398–SEPTEMBER2003
THEORY OF OPERATION(continued)
The DAC7573works as a slave and supports the following data transfer modes,as defined in the I2C-Bus Specification:standard mode(100kbps),fast mode(400kbps),and high-speed mode(3.4Mbps).The data transfer protocol for standard and fast modes is exactly the same,therefore they are referred to as F/S-mode in this document.The protocol for high-speed mode is different from the F/S-mode,and it is referred to as H/S-mode.The DAC7573supports7-bit addressing;10-bit addressing and general call address are not supported.
F/S-Mode Protocol
•The master initiates data transfer by generating a start condition.The start condition is when a high-to-low transition occurs on the SDA line while SCL is high,as shown in Figure31.All I2C-compatible devices should recognize a start condition.
•The master then generates the SCL pulses,and transmits the7-bit address and the read/write direction bit R/W on the SDA line.During all transmissions,the master ensures that data is valid.A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse(see Figure32).All devices recognize the address sent by the master and compare it to their internal fixed addresses.Only the slave device with a matching address generates an acknowledge(see Figure33)by pulling the SDA line low during the entire high period of the9th SCL cycle.Upon detecting this acknowledge,the master knows that communication link with a slave has been established.
•The master generates further SCL cycles to either transmit data to the slave(R/W bit1)or receive data from the slave(R/W bit0).In either case,the receiver needs to acknowledge the data sent by the transmitter.So acknowledge signal can either be generated by the master or by the slave,depending on which one is the receiver.9-bit valid data sequences consisting of8-bit data and1-bit acknowledge can continue as long as necessary.
•To signal the end of the data transfer,the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high(see Figure31).This releases the bus and stops the communication link with the addressed slave.All I2C compatible devices must recognize the stop condition.Upon the receipt of a stop condition,all devices know that the bus is released,and they wait for a start condition followed by a matching address.
H/S-Mode Protocol
•When the bus is idle,both SDA and SCL lines are pulled high by the pullup devices.
•The master generates a start condition followed by a valid serial byte containing H/S master code 00001XXX.This transmission is made in F/S-mode at no more than400Kbps.No device is allowed to acknowledge the H/S master code,but all devices must recognize it and switch their internal setting to support3.4Mbps operation.
•The master then generates a repeated start condition(a repeated start condition has the same timing as the start condition).After this repeated start condition,the protocol is the same as F/S-mode,except that
transmission speeds up to3.4Mbps are allowed.A stop condition ends the H/S-mode and switches all the internal settings of the slave devices to support the F/S-mode.Instead of using a stop condition,repeated start conditions should be used to secure the bus in H/S-mode.
Start Condition
SDA Stop Condition
SCL
Condition
THEORY OF OPERATION (continued)
Figure 31.START and STOP Conditions
Figure 32.Bit Transfer on the I 2C Bus
Figure 33.Acknowledge on the I 2C Bus
Recognize START or REPEATED START
Recognize STOP or REPEATED START
Repeated START
Condition
STOP or
Repeated START
Condition
SLAS398–SEPTEMBER 2003
Figure 34.Bus Protocol
DAC7573I 2C Update Sequence
The DAC7573requires a start condition,a valid I 2C address,a control byte,an MSB byte,and an LSB byte for a single update.After the receipt of each byte,DAC7573acknowledges by pulling the SDA line low during the high period of a single clock pulse.A valid I 2C address selects the DAC7573.The control byte sets the operational mode of the selected DAC7573.Once the operational mode is selected by the control byte,DAC7573expects an MSB byte followed by an LSB byte for data update to occur.DAC7573performs an update on the falling edge of the acknowledge signal that follows the LSB byte.
Control byte needs not to be resent until a change in operational mode is required.The bits of the control byte continuously determine the type of update performed.Thus,for the first update,DAC7573requires a start condition,a valid I 2C address,a control byte,an MSB byte and an LSB byte.For all consecutive updates,DAC7573needs an MSB byte and an LSB byte as long as the control command remains the same.
Using the I 2C high-speed mode (f scl =3.4MHz),the clock running at 3.4MHz,each 12-bit DAC update other than the first update can be done within 18clock cycles (MSB byte,acknowledge signal,LSB byte,acknowledge signal),at ing the fast mode (f scl =400kHz),clock running at 400kHz,maximum DAC update rate is limited to 22.22KSPS.Once a stop condition is received DAC7573releases the I 2C bus and awaits a new start condition.Address Byte
MSB LSB 1
1
1
A1
A0
R/W
The address byte is the first byte received following the START condition from the master device.The first five bits (MSBs)of the address are factory preset to 10011.The next two bits of the address are the device select bits A1and A0.The A1,A0address inputs can be connected to V DD or digital GND,or can be actively driven by TTL/CMOS logic levels.The device address is set by the state of these pins during the power-up sequence of the DAC7573.Up to 16devices (DAC7573)can still be connected to the same I 2C-Bus.
Broadcast Address Byte
MSB LSB
10010000
Broadcast addressing is also supported by DAC7573.Broadcast addressing can be used for synchronously updating or powering down multiple DAC7573devices.DAC7573is designed to work with other members of the DAC857x and DAC757x families to support multichannel synchronous ing the broadcast address, DAC7573responds regardless of the states of the address pins.Broadcast is supported only in write mode (Master writes to DAC7573).
Control Byte
MSB LSB
A3A2L1L0X Sel1Sel0PD0
Table1.Control Register Bit Descriptions
Bit Name Bit Number/Description
A3Extended Address Bit The state of these bits must match the state of pins A3and A2in order for a
proper DAC7573data update,except in broadcast update mode.
A2Extended Address Bit
L1Load1(Mode Select)Bit
Are used for selecting the update mode.
L2Load0(Mode Select)Bit
00Store I2C data.The contents of MS-BYTE and LS-BYTE(or power down information)are stored in the
temporary register of a selected channel.This mode does not change the DAC output of the selected
channel.
01Update selected DAC with I2C data.Most commonly utilized mode.The contents of MS-BYTE and
LS-BYTE(or power down information)are stored in the temporary register and in the DAC register of
the selected channel.This mode changes the DAC output of the selected channel with the new data.
104-Channel synchronous update.The contents of MS-BYTE and LS-BYTE(or power down information)
are stored in the temporary register and in the DAC register of the selected channel.Simultaneously,
the other three channels get updated with previously stored data from the temporary register.This
mode updates all four channels together.
11Broadcast update mode.This mode has two functions.In broadcast mode,DAC7573responds
regardless of local address matching,and channel selection becomes irrelevant as all channels update.
This mode is intended to enable up to64channels simultaneous update,if used with the I2C broadcast
address(10010000).
If Sel1=0All four channels are updated with the contents of their temporary register
data.
If Sel1=1All four channels are updated with the MS-BYTE and LS-BYTE data or
powerdown.
Sel1Buff Sel1Bit
Channel Select Bits
Sel0Buff Sel0Bit
00Channel A
01Channel B
10Channel C
11Channel D
PD0Power Down Flag
0Normal operation
1Power-down flag(MSB7and MSB6indicate a power-down operation,as shown in Table2).
SLAS398–SEPTEMBER2003
Table2.Control Byte
C7C6C5C4C3C2C1C0MSB7MSB6MSB5...
Don’t MSB MSB-1MSB-2 A3A2Load1Load0Ch Sel1Ch Sel0PD0
Care(PD1)(PD2)...LSB DESCRIPTION (Address
Select)
(A3and A200X000Data Write to temporary should corre-register A(TRA)with spond to the data
package ad-Write to temporary dress,set via00X010Data register B(TRB)with pins A3and data A2)
Write to temporary 00X100Data register C(TRC)with
data
Write to temporary 00X110Data register D(TRD)with
data
(00,01,10,or11)Write to TRx(selected
by C2&C1 00X1see Table80
w/Powerdown Com-
mand
(00,01,10,or11)Write to TRx(selected 01X0Data by C2&C1and load
DACx w/data
(00,01,10,or11)Power-down DACx 01X1see Table80(selected by C2and
C1)
(00,01,10,or11)Write to TRx(selected 10X0Data by C2&C1w/data and
load all DACs
(00,01,10,or11)Power-down DACx 10X1see Table80(selected by C2and
C1)&load all DACs BROADCAST MODES(CONTROLS UP TO4DEVICES ON A SINGLE SERIAL BUS)
Update all DACs,all X X11X0X X X devices with previously
stored TRx data
Update all DACs,all X X11X1X0Data devices with MSB[7:0]
and LSB[7:0]data
Power-down all DACs, X X11X1X1see Table80
all devices
Most Significant Byte
Most Significant Byte MSB[7:0]consists of eight most significant bits of12-bit unsigned binary D/A conversion data.C0=1,MSB[7],MSB[6]indicate a powerdown operation as shown in Table8.
Least Significant Byte
Least Significant Byte LSB[7:0]consists of the4least significant bits of the12-bit unsigned binary D/A conversion data,followed by4don’t care bits.DAC7573updates at the falling edge of the acknowledge signal that follows the LSB[0]bit.
Default Readback Condition
If the user initiates a readback of a specified channel without first writing data to that specified channel,the default readback is all zeros,since the readback register is initialized to0during the power on reset phase.。