MTC24中文资料
c-24中文说明书
AVID C|24Guide 中文说明书一、简介1、C|24功能控件功能• 24个声道条,每个声道条都有以下控件: • 触敏机动推子 • 多功能旋转编码器和开关• 自动化模式选择器• 专用EQ和Dynamics开关• 专用Insert和Send开关• 专用Input和RecEnable开关• 声道Solo和Mute开关• 声道选择开关• 双排多功能显示器• 全局自动化模式和启动开关• 走带和导航控件• 编辑和功能控件• ProTools窗口和全局控制开关模拟音频功能• 16麦克风/线路/DI前置放大器具有以下功能:• 无级变速输入增益控件• 有开关控制的高通滤波器• 削波指示器• 幻象电源(8个声道分2组,每组都有)• 8x2辅助混音器具有以下功能:• 8 个输入装置都配有独立的增益控件• 立体声混音输出配有主音量控件• C|24 监控器分区输出装置有开关控制• 6声道监控器分区具有以下功能:2 个 (主要的和辅助的)环绕声输出音源2 个外部立体声输入音源配有选择器开关和电平控件的主要监控器输出装置 (5.1、LCRS 或立体声)和辅助监控输出装置(立体声)提示输出的2个声道 配有电平控件和提示监控功能的耳机输出装置 配有内置或外部音源和电平控件的对讲电话 配有外部输入和电平控件的对听机二、启动和关闭 Pro Tools 系统 基于 D-Command 的系统必须按照特定顺序启动和关闭。
按照此顺序打开系统电源:1、 首先打开外置硬盘。
等待 10 至 15 秒,让它们达到所需的转速。
2 、打开 C|243、 如果计划使用 MIDI 设备工作,打开 MIDI 接口和其他MIDI 装置。
4 、打开全部 Pro Tools 音频接口。
5、 打开计算机。
6 、打开监听音箱放大器或有源音箱。
按照此顺序关闭系统:1、 关闭监听音箱放大器或有源音箱。
2 、关闭全部 Pro Tools 音频接口。
3 、关闭计算机。
24C04中文资料
ST24C04, ST25C04 ST24W04, ST25W044 Kbit Serial I 2C Bus EEPROMwith User-Defined Block Write ProtectionFebruary 19991/16AI00851E2E1-E2SDAV CCST24x04ST25x04MODE/WC*SCLV SSPRE Figure 1. Logic Diagram1 MILLION ERASE/WRITE CYCLES with 40 YEARS DATA RETENTION SINGLE SUPPLY VOLTAGE:–3V to 5.5V for ST24x04 versions –2.5V to 5.5V for ST25x04 versionsHARDWARE WRITE CONTROL VERSIONS:ST24W04 and ST25W04PROGRAMMABLE WRITE PROTECTION TWO WIRE SERIAL INTERFACE, FULLY I 2C BUS COMPATIBLEBYTE and MULTIBYTE WRITE (up to 4BYTES)PAGE WRITE (up to 8 BYTES)BYTE, RANDOM and SEQUENTIAL READ MODESSELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH UP PERFORMANCESDESCRIPTIONThis specification covers a range of 4 Kbits I 2C bus EEPROM products, the ST24/25C04 and the ST24/25W04. In the text, products are referred to as ST24/25x04, where "x" is: "C" for Standard version and "W" for hardware Write Control ver-sion.PRE Write Protect Enable E1-E2Chip Enable InputsSDA Serial Data Address Input/Output SCL Serial ClockMODE Multibyte/Page Write Mode (C version)WC Write Control (W version)V CC Supply Voltage V SSGroundTable 1. Signal Names81SO8 (M)150mil Width81PSDIP8 (B)0.25mm FrameNote: WC signal is only available for ST24/25W04 products.The ST24/25x04 are 4 Kbit electrically erasable programmable memories (EEPROM), organized as 2 blocks of 256 x8 bits. They are manufactured in STMicroelectronics’s Hi-Endurance Advanced CMOS technology which guarantees an endur-ance of one million erase/write cycles with a data retention of 40 years.Both Plastic Dual-in-Line and Plastic Small Outline packages are available.The memories are compatible with the I 2C stand-ard, two wire serial interface which uses a bi-direc-tional data bus and serial clock. The memoriescarry a built-in 4 bit, unique device identification code (1010) corresponding to the I 2C bus defini-tion. This is used together with 2 chip enable inputs (E2, E1) so that up to 4 x 4K devices may be attached to the I 2C bus and selected individually.The memories behave as a slave device in the I 2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 7 bits (identification code 1010), plus one read/write bit and terminated by an acknowledge bit.SDAV SSSCL MODE/WC E1PRE V CCE2AI00852EST24x04ST25x0412348765Figure 2A. DIP Pin Connections 1AI01107E2348765SDAV SSSCL MODE/WC E1PRE V CCE2ST24x04ST25x04Figure 2B. SO Pin ConnectionsDESCRIPTION (cont’d)Symbol ParameterValue Unit T A Ambient Operating Temperature –40 to 125 °C T STG Storage Temperature –65 to 150°C T LEAD Lead Temperature, Soldering (SO8 package)(PSDIP8 package)40 sec 10 sec215260°C V IO Input or Output Voltages –0.6 to 6.5 V V CC Supply Voltage–0.3 to 6.5V V ESDElectrostatic Discharge Voltage (Human Body model) (2)4000V Electrostatic Discharge Voltage (Machine model) (3)500VNotes:1.Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute MaximumRating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.-STD-883C, 3015.7 (100pF, 1500 Ω).3.EIAJ IC-121 (Condition C) (200pF, 0 Ω).Table 2. Absolute Maximum Ratings (1)2/16ST24/25C04, ST24/25W04ModeRW bit MODE Bytes Initial SequenceCurrent Address Read ’1’X 1START, Device Select, RW = ’1’Random Address Read ’0’X1START, Device Select, RW = ’0’, Address,’1’reSTART, Device Select, RW = ’1’Sequential Read ’1’X 1 to 512Similar to Current or Random Mode Byte Write ’0’X 1START, Device Select, RW = ’0’Multibyte Write (2)’0’V IH 4START, Device Select, RW = ’0’Page Write’0’V IL8START, Device Select, RW = ’0’Notes:1.X = V IH or V IL2.Multibyte Write not available in ST24/25W04 versions.Table 4. Operating Modes (1)Device CodeChip EnableBlock Select RW Bitb7b6b5b4b3b2b1b0Device Select11E2E1A8RWNote: The MSB b7 is sent first.Table 3. Device Select CodeWhen writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are termi-nated with a STOP condition.Power On Reset: V CC lock out write protect. In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Until the V CC voltage has reached the POR threshold value, the internal reset is active, all operations are disabled and the device will not respond to any command.In the same way, when V CC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable V CC must be applied before applying any logic signal.SIGNAL DESCRIPTIONSSerial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connected from the SCL line to V CC to act as a pull up (see Figure 3).Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory.It is an open drain output that may be wire-OR’edwith other open drain or open collector signals on the bus. A resistor must be connected from the SDA bus line to V CC to act as pull up (see Figure 3).Chip Enable (E1 - E2). These chip enable inputs are used to set the 2 least significant bits (b2, b3)of the 7 bit device select code. These inputs may be driven dynamically or tied to V CC or V SS to establish the device select code.Protect Enable (PRE). The PRE input pin, in ad-dition to the status of the Block Address Pointer bit (b2, location 1FFh as in Figure 7), sets the PRE write protection active.Mode (MODE). The MODE input is available on pin 7 (see also WC feature) and may be driven dynami-cally. It must be at V IL or V IH for the Byte Write mode, V IH for Multibyte Write mode or V IL for Page Write mode. When unconnected, the MODE input is internally read as V IH (Multibyte Write mode). Write Control (WC). An hardware Write Control feature (WC) is offered only for ST24W04 and ST25W04 versions on pin 7. This feature is usefull to protect the contents of the memory from any erroneous erase/write cycle. The Write Control sig-nal is used to enable (WC = V IH ) or disable (WC =V IL ) the internal write protection. When uncon-nected, the WC input is internally read as V IL and the memory area is not write protected.3/16ST24/25C04, ST24/25W04AI01100V CCC BUSSDA R LMASTERR LSCLC BUS10020030040048121620C BUS (pF)R L m a x (k Ω)V CC = 5VFigure 3. Maximum R L Value versus Bus Capacitance (C BUS ) for an I 2C BusThe devices with this Write Control feature no longer support the Multibyte Write mode of opera-tion, however all other write modes are fully sup-ported.Refer to the AN404 Application Note for more de-tailed information about Write Control feature.DEVICE OPERATION I 2C Bus BackgroundThe ST24/25x04 support the I 2C protocol. This protocol defines any device that sends data onto the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master will always initiate a data transfer and will provide the serial clock for syn-chronisation. The ST24/25x04 are always slave devices in all communications.Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the ST24/25x04 con-tinuously monitor the SDA and SCL signals for a START condition and will not respond unless one is given.Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition termi-nates communication between the ST24/25x04and the bus master. A STOP condition at the end of a Read command, after and only after a No Acknowledge, forces the standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle.Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successfull data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data.Data Input. During data input the ST24/25x04sample the SDA bus signal on the rising edge of the clock SCL. Note that for correct device opera-tion the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low.Memory Addressing. To start communication be-tween the bus master and the slave ST24/25x04,the master must initiate a START condition. Follow-ing this, the master sends onto the SDA bus line 8bits (MSB first) corresponding to the device select code (7 bits) and a READ or WRITE bit.SIGNAL DESCRIPTIONS (cont’d)4/16ST24/25C04, ST24/25W04Symbol ParameterTest ConditionMinMax Unit C IN Input Capacitance (SDA)8pF C IN Input Capacitance (other pins)6pF Z WCL WC Input Impedance (ST24/25W04)V IN ≤ 0.3 V CC 520k ΩZ WCH WC Input Impedance (ST24/25W04)V IN ≥ 0.7 V CC500k Ωt LPLow-pass filter input time constant (SDA and SCL)100nsNote: 1. Sampled only, not 100% tested.Table 5. Input Parameters (1) (T A = 25 °C, f = 100 kHz )Symbol ParameterTest Condition MinMax Unit I LI Input Leakage Current 0V ≤ V IN ≤ V CC ±2µA I LO Output Leakage Current 0V ≤ V OUT ≤ V CC SDA in Hi-Z ±2µA I CCSupply Current (ST24 series)V CC = 5V, f C = 100kHz (Rise/Fall time < 10ns)2mA Supply Current (ST25 series)V CC = 2.5V, f C = 100kHz 1mA I CC1Supply Current (Standby)(ST24 series)V IN = V SS or V CC ,V CC = 5V 100µA V IN = V SS or V CC , V CC = 5V, f C = 100kHz 300µA I CC2Supply Current (Standby) (ST25 series)V IN = V SS or V CC , V CC = 2.5V 5µA V IN = V SS or V CC , V CC = 2.5V, f C = 100kHz50µA V IL Input Low Voltage (SCL, SDA)–0.30.3 V CC V V IH Input High Voltage (SCL, SDA)0.7 V CC V CC + 1V V IL Input Low Voltage(E1-E2, PRE, MODE, WC)–0.30.5V V IH Input High Voltage(E1-E2, PRE, MODE, WC)V CC – 0.5V CC + 1V V OLOutput Low Voltage (ST24 series)I OL = 3mA, V CC = 5V 0.4V Output Low Voltage (ST25 series)I OL = 2.1mA, V CC = 2.5V0.4VTable 6. DC Characteristics(T A = 0 to 70°C, –20 to 85°C or –40 to 85°C; V CC = 3V to 5.5V or 2.5V to 5.5V)5/16ST24/25C04, ST24/25W04The 4 most significant bits of the device select codeare the device type identifier, corresponding to the I 2C bus definition. For these memories the 4 bits are fixed as 1010b. The following 2 bits identify the specific memory on the bus. They are matched to the chip enable signals E2, E1. Thus up to 4 x 4K memories can be connected on the same bus giving a memory capacity total of 16 Kbits. After a START condition any memory on the bus will iden-tify the device code and compare the following 2bits to its chip enable inputs E2, E1.The 7th bit sent is the block number (one block =256 bytes). The 8th bit sent is the read or write bit (RW), this bit is set to ’1’ for read and ’0’ for write operations. If a match is found, the corresponding memory will acknowledge the identification on the SDA bus during the 9th bit time.Input Rise and Fall Times ≤ 50nsInput Pulse Voltages0.2V CC to 0.8V CCInput and Output Timing Ref. Voltages 0.3V CC to 0.7V CCAC MEASUREMENT CONDITIONSAI008250.8V CC0.2V CC0.7V CC 0.3V CCFigure 4. AC Testing Input Output WaveformsDEVICE OPERATION (cont’d)Symbol Alt ParameterMinMax Unit t CH1CH2t R Clock Rise Time 1µs t CL1CL2t F Clock Fall Time 300ns t DH1DH2t R Input Rise Time 1µs t DL1DL1t F Input Fall Time300ns t CHDX (1)t SU:STA Clock High to Input Transition 4.7µs t CHCL t HIGH Clock Pulse Width High4µs t DLCL t HD:STA Input Low to Clock Low (START)4µs t CLDX t HD:DAT Clock Low to Input Transition 0µs t CLCH t LOW Clock Pulse Width Low4.7µs t DXCX t SU:DAT Input Transition to Clock Transition 250ns t CHDH t SU:STO Clock High to Input High (STOP) 4.7µs t DHDL t BUF Input High to Input Low (Bus Free) 4.7µs t CLQV (2)t AA Clock Low to Next Data Out Valid 0.3 3.5µs t CLQX t DH Data Out Hold Time 300ns f C f SCL Clock Frequency 100kHz t W (3)t WRWrite Time10msNotes:1.For a reSTART condition, or following a write cycle.2.The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP conditions.3.In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) themaximum programming time is doubled to 20ms.Table 7. AC Characteristics(T A = 0 to 70°C, –20 to 85°C or –40 to 85°C; V CC = 3V to 5.5V or 2.5V to 5.5V)6/16ST24/25C04, ST24/25W04SCL SDA INSCL SDA OUTSCL SDA INtCHCLtDLCLtCHDXSTARTCONDITIONtCLCHtDXCXtCLDXSDAINPUTSDACHANGEtCHDHtDHDLSTOP &BUS FREEDATA VALIDtCLQV tCLQXDATA OUTPUTtCHDHSTOPCONDITIONtCHDXSTARTCONDITIONWRITE CYCLEtWAI00795BFigure 5. AC WaveformsWrite OperationsThe Multibyte Write mode (only available on the ST24/25C04 versions) is selected when the MODE pin is at V IH and the Page Write mode when MODE pin is at V IL. The MODE pin may be driven dynami-cally with CMOS input levels.Following a START condition the master sends a device select code with the RW bit reset to ’0’. The memory acknowledges this and waits for a byte address. The byte address of 8 bits provides ac-cess to one block of 256 bytes of the memory. After receipt of the byte address the device again re-sponds with an acknowledge.For the ST24/25W04 versions, any write command with WC = 1 will not modify the memory content. Byte Write. In the Byte Write mode the master sends one data byte, which is acknowledged by the memory. The master then terminates the transfer by generating a STOP condition. The Write mode is independant of the state of the MODE pin which could be left floating if only this mode was to be used. However it is not a recommended operating mode, as this pin has to be connected to either V IH or V IL, to minimize the stand-by current.7/16ST24/25C04, ST24/25W04SCL SDASCL SDASDASTARTCONDITIONSDAINPUTSDACHANGEAI00792STOPCONDITION 123789MSB ACKSTARTCONDITIONSCL123789MSB ACKSTOPCONDITION Figure 6. I2C Bus ProtocolMultibyte Write. For the Multibyte Write mode, the MODE pin must be at V IH. The Multibyte Write mode can be started from any address in the memory. The master sends from one up to 4 bytes of data, which are each acknowledged by the mem-ory. The transfer is terminated by the master gen-erating a STOP condition. The duration of the write cycle is t W = 10ms maximum except when bytes are accessed on 2 rows (that is have different values for the 6 most significant address bits A7-A2), the programming time is then doubled to a maximum of 20ms. Writing more than 4 bytes in the Multibyte Write mode may modify data bytes in an adjacent row (one row is 8 bytes long). However, the Multibyte Write can properly write up to 8 consecutive bytes as soon as the first address of these 8 bytes is the first address of the row, the 7 following bytes being written in the 7 following bytes of this same row.Page Write. For the Page Write mode, the MODE pin must be at V IL. The Page Write mode allows up to 8 bytes to be written in a single write cycle, provided that they are all located in the same ’row’in the memory: that is the 5 most significant mem-8/16ST24/25C04, ST24/25W04ory address bits (A7-A3) are the same inside one block. The master sends from one up to 8 bytes of data, which are each acknowledged by the mem-ory. After each byte is transfered, the internal byte address counter (3 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter ’roll-over’ which could result in data being overwritten. Note that, for any write mode, the generation by the master of the STOP condition starts the internal memory pro-gram cycle. All inputs are disabled until the comple-tion of this cycle and the memory will not respond to any request.Minimizing System Delays by Polling On ACK.During the internal write cycle, the memory discon-nects itself from the bus in order to copy the data from the internal latches to the memory cells. The maximum value of the write time (t W ) is given in the AC Characteristics table, since the typical time is shorter, the time seen by the system may be re-duced by an ACK polling sequence issued by the master.WRITE Cycle in ProgressAI01099BNext Operation is Addressing the MemorySTART Condition DEVICE SELECT with RW = 0ACK ReturnedYESNOYESNOReSTARTSTOPProceedWRITE OperationProceedRandom Address READ OperationSend Byte AddressFirst byte of instruction with RW = 0 already decoded by ST24xxxFigure 8. Write Cycle Polling using ACKAI00855B1FFhb7b3b2XX100hBlock 1Block 0Protect Flag Enable = 0Disable = 18 byte boundary address Protect Location Figure 7. Memory Protection9/16ST24/25C04, ST24/25W04The sequence is as follows:–Initial condition: a Write is in progress (see Figure 8).–Step 1: the Master issues a START condition followed by a Device Select byte (1st byte of the new instruction).–Step 2: if the memory is busy with the internal write cycle, no ACK will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it will re-spond with an ACK, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction was already sent during Step 1).Write Protection. Data in the upper block of 256bytes of the memory may be write protected. The memory is write protected between a boundary address and the top of memory (address 1FFh)when the PRE input pin is taken high and when the Protect Flag (bit b2 in location 1FFh) is set to ’0’.The boundary address is user defined by writing it in the Block Address Pointer. The Block Address Pointer is an 8 bit EEPROM register located at the address 1FFh. It is composed by 5 MSBs Address Pointer, which defines the bottom boundary ad-dress, and 3 LSBs which must be programmed atDEVICE OPERATION (cont’d)’0’. This Address Pointer can therefore address a boundary in steps of 8 bytes.The sequence to use the Write Protected feature is:–write the data to be protected into the top of the memory, up to, but not including, location 1FFh;–set the protection by writing the correct bottom boundary address in the Address Pointer (5MSBs of location 1FFh) with bit b2 (Protect flag)set to ’0’. Note that for a correct fonctionality of the memory, all the 3 LSBs of the Block Address Pointer must also be programmed at ’0’.The area will now be protected when the PRE input pin is taken High. While the PRE input pin is read at ’0’ by the memory, the location 1FFh can be used as a normal EEPROM byte.Caution: Special attention must be used when using the protect mode together with the Multibyte Write mode (MODE input pin High). If the Multibyte Write starts at the location right below the first byte of the Write Protected area, then the instruction will write over the first 3 bytes of the Write Protected area. The area protected is therefore smaller than the content defined in the location 1FFh, by 3 bytes.This does not apply to the Page Write mode as the address counter ’roll-over’ and thus cannot go above the 8 bytes lower boundary of the protected area.S T O PS T A R TBYTE WRITEDEV SELBYTE ADDR DATA INS T A R TMULTIBYTE ANDPAGE WRITEDEV SEL BYTE ADDR DATA IN 1DATA IN 2AI00793S T O PDATA IN NACKACKACKR/W ACKACKACKR/WACKACKFigure 9. Write Modes Sequence (ST24/25C04)10/16ST24/25C04, ST24/25W04S T O PS T A R TBYTE WRITEDEV SELBYTE ADDR DATA INWCS T A R TPAGE WRITEDEV SELBYTE ADDR DATA IN 1WCDATA IN 2AI01101BPAGE WRITE (cont'd)WC (cont'd)S T O PDATA IN NACKACKACKR/WACKACKACKR/WACKACKFigure 10. Write Modes Sequence with Write Control = 1 (ST24/25W04)Read OperationsRead operations are independent of the state of the MODE pin. On delivery, the memory content is set at all "1’s" (or FFh).Current Address Read. The memory has an inter-nal byte address counter. Each time a byte is read,this counter is incremented. For the Current Ad-dress Read mode, following a START condition,the master sends a memory address with the RW bit set to ’1’. The memory acknowledges this and outputs the byte addressed by the internal byte address counter. This counter is then incremented.The master does NOT acknowledge the byte out-put, but terminates the transfer with a STOP con-dition.Random Address Read. A dummy write is per-formed to load the address into the address counter, see Figure 11. This is followed by another START condition from the master and the byte address is repeated with the RW bit set to ’1’. The memory acknowledges this and outputs the byte addressed. The master have to NOT acknowledge the byte output, but terminates the transfer with a STOP condition.Sequential Read. This mode can be initiated with either a Current Address Read or a Random Ad-dress Read. However, in this case the master DOES acknowledge the data byte output and the memory continues to output the next byte in se-quence. To terminate the stream of bytes, the master must NOT acknowledge the last byte out-11/16put, but MUST generate a STOP condition. The output data is from consecutive byte addresses,with the internal byte address counter automat-ically incremented after each byte output. After a count of the last memory address, the addresscounter will ’roll- over’ and the memory will continue to output data.Acknowledge in Read Mode. In all read modes the ST24/25x04 wait for an acknowledge during the 9th bit time. If the master does not pull the SDA line low during this time, the ST24/25x04 terminate the data transfer and switches to a standby state.S T A R TDEV SEL *BYTE ADDRS T A R TDEV SELDATA OUT 1AI00794CDATA OUT NS T O PS T A R TCURRENT ADDRESS READDEV SELDATA OUTRANDOM ADDRESS READS T O PS T A R TDEV SEL *DATA OUTSEQUENTIAL CURRENT READS T O P DATA OUT NS T A R TDEV SEL *BYTE ADDR SEQUENTIAL RANDOM READS T A R TDEV SEL *DATA OUT 1S T O PACKR/WNO ACKACKR/WACKACK R/WACKACK ACK NO ACKR/WNO ACKACKACKR/WACK ACKR/WACK NO ACKFigure 11. Read Modes SequenceNote:*The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.DEVICE OPERATION (cont’d)12/16ORDERING INFORMATION SCHEMENotes: 3 * Temperature range on special request only.Parts are shipped with the memory content set at all "1’s" (FFh).For a list of available options (Operating Voltage, Range, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.Operating Voltage ST24C04 3V to 5.5V ST24W04 3V to 5.5V ST25C04 2.5V to 5.5V ST25W04 2.5V to 5.5VRangeStandardHardware Write Control StandardHardware Write ControlPackage B PSDIP80.25mm Frame MSO8 150mil WidthTemperature Range 10 to 70 °C 5–20 to 85 °C 6–40 to 85 °C 3 *–40 to 125 °COption TRTape & Reel PackingExample: ST24C04 M 1 TR13/16PSDIP-aA2A1A Le1DE1EN1CeA eBB1BSymbmm inches TypMin Max TypMin Max A 3.90 5.900.1540.232A10.49–0.019–A2 3.30 5.300.1300.209B 0.360.560.0140.022B1 1.15 1.650.0450.065C 0.200.360.0080.014D 9.209.900.3620.390E 7.62––0.300––E1 6.00 6.700.2360.264e1 2.54––0.100––eA 7.80–0.307–eB –10.00–0.394L 3.00 3.800.1180.150N88Drawing is not to scalePSDIP8 - 8 pin Plastic Skinny DIP , 0.25mm lead frame14/16SO-aENCPBe ADCLA1α1Hh x 45˚Symbmm inches TypMin Max TypMin Max A 1.35 1.750.0530.069A10.100.250.0040.010B 0.330.510.0130.020C 0.190.250.0070.010D 4.80 5.000.1890.197E 3.80 4.000.1500.157e 1.27––0.050––H 5.80 6.200.2280.244h 0.250.500.0100.020L 0.400.900.0160.035α0°8°0°8°N 88CP0.100.004Drawing is not to scaleSO8 - 8 lead Plastic Small Outline, 150 mils body width15/16Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronics© 1999 STMicroelectronics - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.16/16。
LMV324DTBR2G资料
9 IN C−
IN B− 6
8 OUT C OUT B 7
TSSOP−14
−A+
+D−
−+ +−
B
C
14 OUT D 13 IN D− 12 IN D+ 11 V− 10 IN C+ 9 IN C− 8 OUT C
(Top View)
2
元器件交易网
GAIN (dB) CMRR (dB)
50
40
30
20
10
Over −40°C to +85°C 0 Same Gain $1.8 dB (Typ)
−10
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 1. Open Loop Frequency Response (RL = 2 kW, TA = 255C, VS = 5 V)
SC−70
Continuous 150
280
°C °C/W
Micro8
238
TSOP−5
333
UDFN8 (1.2 mm x 1.8 mm x 0.5 mm)
350
SOIC−8
212
SOIC−14
156
TSSOP−14
190
Tstg
Storage Temperature
Mounting Temperature (Infrared or Convection −20 sec)
LMV321, LMV358, LMV324
MAXIMUM RATINGS
Symbol
Rating
Value
Unit
74ACT00MTC中文资料
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form. (PC not available in Tape and Reel.)
TC24 用户手册说明书
User manualTable of ContentsGenerally (3)FCC notes (3)Section 15.19 (3)Section 15.21 Statement (3)Section 15.105 (a) Statement (3)IC notes (3)RSS-GEN – User Manual Statements (English/French) (3)RF exposure statement (3)2 / 3GenerallyThe module is not sold separately and is exclusively used for systems of HBC-radiomatic. The module is only used in professional industrial radio applications.For integration in host device integration instructions define requirements for installation, safety instructions written in host manual and labeling requirements.Changes or modifications made to this module not expressly approved by the party responsible for compliance may void the authorization to operate this equipment.FCC notesSection 15.19This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.Section 15.21 StatementChanges or modifications to the unit not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.Section 15.105 (a) StatementThis equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense.IC notesRSS-GEN – User Manual Statements (English/French)Licence exemptThis device complies with Industry Canada’s licence-exempt RSSs. Operation is subject to the following two conditions:1. This device may not cause interference; and2. This device must accept any interference, including interference that may cause undesiredoperation of the device.Le présent appareil est conforme aux CNR d’Industrie Canada applicables aux appareils radio exempts de licence. L’exploitation est autorisée aux deux conditions suivantes:1. l’appareil ne doit pas produire de brouillage;2. l’utilisateur de l’appareil doit accepte r tout brouillage radioélectrique subi, même si le brouillageest susceptible d’en compromettre le fonctionnement.RF exposure statementThis RF module will be integrated with internal and external antennas in different host devices. For each final host device the RF exposure conditions to comply with FCC / ISED requirements will be individually defined and the user instructions of the host device will have appropriate installation or usage instructions. In general, the final host device will be used in such a manner that the potential for human contact including by-standers during normal operation is minimized.3 / 3。
NM24C03中文资料
Connection Diagrams
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
A0 A1 A2 VSS 1 2 NM24C02 3 4 6 5 SCL SDA
元器件交易网
NM24C02/03 – 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
February 2000
NM24C02/03 – 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
DC Electrical Characteristics (2.7V to 5.5V)
Symbol Parameter Test Conditions Min
ICCA ISB Active Power Supply Current Standby Current fSCL = 400 KHz fSCL = 100 KHz VIN = GND or VCC VCC = 2.7V - 5.5V VCC = 2.7V - 5.5V (L) VCC = 2.7V - 4.5V (LZ)
Features
I Extended operating voltage 2.7V – 5.5V I 400 KHz clock frequency (F) at 2.7V - 5.5V I 200µA active current typical 10µA standby current typical 1µA standby current typical (L) 0.1µA standby current typical (LZ) I IIC compatible interface – Provides bi-directional data transfer protocol I Schmitt trigger inputs I Sixteen byte page write mode – Minimizes total write time per byte I Self timed write cycle Typical write cycle time of 6ms I Hardware Write Protect for upper half (NM24C03 only) I Endurance: 1,000,000 data changes I Data retention greater than 40 years I Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP I Available in three temperature ranges - Commercial: 0° to +70°C - Extended (E): -40° to +85C - Automotive (V): -40° to +125°C
FM24C08中文资料
2
FM24C08U/09U Rev. A.3
元器件交易网
FM24C08U/09U – 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Ordering Information FM 24 C XX U F LZ E XXX
NOTE: Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the VCC applied to the device. This will ensure proper operation.
DC Electrical Characteristics (2.7V to 5.5V)
Symbol Parameter Test Conditions Min
ICCA ISB (Note 3) ILI ILO VIL VIH VOL Active Power Supply Current Standby Current fSCL = 400 KHz ("F" version) fSCL = 100 KHz VIN = GND or VCC VCC = 2.7V - 5.5V VCC = 2.7V - 5.5V (L) VCC = 2.7V - 4.5V (LZ)
atc中文手册
A T24C256中文资料2009-11-15 09:43特性与1MHz I2C 总线兼容1.8 到6.0 伏工作电压范围低功耗CMOS 技术写保护功能当WP 为高电平时进入写保护状态64 字节页写缓冲器自定时擦写周期100,000 编程/擦写周期可保存数据100 年8 脚DIP SOIC 封装温度范围商业级工业级和汽车级概述CAT24WC256 是一个256K 位串行CMOS E2PROM 内部含有32768 个字节每字节为8 位CATALYST 公司的先进CMOS 技术实质上减少了器件的功耗CAT24WC256 有一个64 字节页写缓冲器该器件通过I2C 总线接口进行操作管脚描述管脚名称功能A0 A1 地址输入SDA 串行数据/地址SCL 串行时钟WP 写保护Vcc +1.8V 6.0V 电源Vss 地NC 未连接极限参数工作温度工业级-55 +125商业级0 +75贮存温度-65 +150各管脚承受电压-2.0V Vcc+2.0VVcc 管脚承受电压-2.0V +7.0V封装功率损耗Ta=25 1.0W焊接温度(10 秒) 300口输出短路电流100mA功能描述CAT24WC256 支持I2C 总线数据传送协议I2C 总线协议规定任何将数据传送到总线的器件作为发送器任何从总线接收数据的器件为接收器数据传送是由产生串行时钟和所有起始停止信号的主器件控制的CAT24WC256 是作为从器件被操作的主器件和从器件都可以作为发送器或接收器但由主器件控制传送数据发送或接收的模式管脚描述SCL 串行时钟CAT24WC256 串行时钟输入管脚用于产生器件所有数据发送或接收的时钟这是一个输入管脚SDA 串行数据/地址双向串行数据/地址管脚用于器件所有数据的发送或接收SDA 是一个开漏输出管脚可与其它开漏输出或集电极开路输出进行线或wire-ORWP 写保护当WP 脚连接到Vcc 所有内存变成写保护只能读当WP 引脚连接到Vss 或悬空允许器件进行读/写操作A0 A1 器件地址输入这些管脚为硬连线或者不连接对于单总线系统最多可寻址4 个CAT24WC256 器件参阅器件寻址当这些引脚没有连接时其默认值为0I2C 总线协议I2C 总线协议定义如下1 只有在总线空闲时才允许启动数据传送2 在数据传送过程中当时钟线为高电平时数据线必须保持稳定状态不允许有跳变时钟线为高电平时数据线的任何电平变化将被看作总线的起始或停止信号起始信号时钟线保持高电平期间数据线电平从高到低的跳变作为I2C 总线的起始信号停止信号时钟线保持高电平期间数据线电平从低到高的跳变作为I2C 总线的停止信号器件寻址主器件通过发送一个起始信号启动发送过程然后发送它所要寻址的从器件的地址8 位从器件地址的高5 位固定为10100 见图5 接下来的2 位A1 A0 为器件的地址位最多可以连接4 个器件到同一总线上这些位必须与硬连线输入脚A1 A0 相对应从器件地址的最低位作为读写控制位1表示对从器件进行读操作0 表示对从器件进行写操作在主器件发送起始信号和从器件地址字节后CAT24WC256 监视总线并当其地址与发送的从地址相符时响应一个应答信号通过SDA 线CAT24WC256 再根据读写控制位R/W 的状态进行读或写操作应答信号I2C 总线数据传送时每成功地传送一个字节数据后接收器都必须产生一个应答信号应答的器件在第9 个时钟周期时将SDA 线拉低表示其已收到一个8 位数据CAT24WC256 在接收到起始信号和从器件地址之后响应一个应答信号如果器件已选择了写操作则在每接收一个8 位字节之后响应一个应答信号当CAT24WC256 工作于读模式时在发送一个8 位数据后释放SDA 线并监视一个应答信号一旦接收到应答信号CAT24WC256 继续发送数据如主器件没有发送应答信号器件停止传送数据并等待一个停止信号写操作字节写在字节写模式下主器件发送起始信号和从器件地址信息R/W 位置0 给从器件在从器件送回应答信号后主器件发送两个8 位地址字写入CAT24WC256 的地址指针主器件在收到从器件的应答信号后再发送数据到被寻址的存储单元CAT24WC256 再次应答并在主器件产生停止信号后开始内部数据的擦写在内部擦写过程中CAT24WC256 不再应答主器件的任何请求页写在页写模式下单个写周期内CAT24WC256 最多可以写入64 个字节数据页写操作的启动和字节写一样不同在于传送了一字节数据后主器件允许继续发送63 个字节每发送一个字节后CAT24WC256 将响应一个应答位且内部低6 位地址加1 高位地址保持不变如果主器件在发送停止信号之前发送大于64 个字节地址计数器将自动翻转先前写入的数据被覆盖当所有64 字节接收完毕主器件发送停止信号内部编程周期开始此时所有接收到的数据在单个写周期内写入CAT24WC256应答查询可以利用内部写周期时禁止数据输入这一特性一旦主器件发送停止位指示主器件操作结束时CAT24WC256 启动内部写周期应答查询立即启动包括发送一个起始信号和进行写操作的从器件地址如果CAT24WC256 正在进行内部写操作将不会发送应答信号如果CAT24WC256 已经完成了内部写操作将发送一个应答信号主器件可以继续对CAT24WC256 进行下一次读写操作写保护写保护操作特性可使用户避免由于不当操作而造成对存储区域内部数据的改写当WP 管脚接高时整个寄存器区全部被保护起来而变为只可读取CAT24WC256 可以接收从器件地址和字节地址但是装置在接收到第一个数据字节后不发送应答信号从而避免寄存器区域被编程改写读操作CAT24WC256 读操作的初始化方式和写操作时一样仅把R/W 位置为1 有三种不同的读操作方式立即/当前地址读选择/随机读和连续读立即/当前地址读的地址计数器内容为最后操作字节的地址加1 也就是说如果上次读/写的操作地址为N 则立即读的地址从地址N+1 开始如果N=E 此处E=32767 则计数器将翻转到0 且继续输出数据CAT24WC256接收到从器件地址信号后R/W 位置1 它首先发送一个应答信号然后发送一个8 位字节数据主器件不需发送一个应答信号但要产生一个停止信号选择/随机读选择/随机读操作允许主器件对寄存器的任意字节进行读操作主器件首先通过发送起始信号从器件地址和它想读取的字节数据的地址执行一个伪写操作在CAT24WC256 应答之后主器件重新发送起始信号和从器件地址此时R/W 位置1 CAT24WC256 响应并发送应答信号然后输出所要求的一个8 位字节数据主器件不发送应答信号但产生一个停止信号连续读连续读操作可通过立即读或选择性读操作启动在CAT24WC256 发送完一个8 位字节数据后主器件产生一个应答信号来响应告知CAT24WC256 主器件要求更多的数据对应每个主机产生的应答信号CAT24WC256 将发送一个8 位数据字节当主器件不发送应答信号而发送停止位时结束此操作从CAT24WC256 输出的数据按顺序由N 到N+1 输出读操作时地址计数器在CAT24WC256 整个地址内增加这样整个寄存器区域在可在一个读操作内全部读出当读取的字节超过E 此处E=32767计数器将翻转到零并继续输出数据字节。
FM24C02中文资料
元器件交易网
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Ordering Information FM 24 C XX U F LZ E XXX
Operating Conditions
Ambient Operating Temperature FM24C04U/05U FM24C04UE/05UE FM24C04UV/05UV Positive Power Supply FM24C04U/05U FM24C04UL/05UL FM24C04ULZ/05ULZ 0°C to +70°C -40°C to +85°C -40°C to +125°C 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Product Specifications Absolute Maximum Ratings
Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 seconds) ESD Rating –65°C to +150°C –0.3V to 6.5V +300°C 2000V min.
元器件交易网
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
MTC产品说明书
在一支 MTC 型插入式多测点流量传感器上，配置 4 ～ 12 对高、低端感 压孔（视管径大小而不同）。在检测管中流量信号被平均后输出，其输出则代表 了多个测点的平均流速或流量。当管道内插入多支 MTC 流量传感器时，构成 矩阵分布的面测量方法，就可以准确测量流速分布不均匀的管道截面流量。
在流量测量过程中，流体的各相关参数经变送器转换为相对应的直流电流 信号（4-20 mA.DC），直接传送到DCS系统，运算并显示出管道的瞬时流量值。 或将变送器输出的直流电流信号传输到DZL-2智能流量信号转换仪运算显示出 管道的瞬时流量，并传送到DCS系统显示出瞬时流量。
MTC型 插入式多测点流量测量装置
产品说明书
量制陕字00000212号
西安中航流量技术研究所
1
MTC 型插入式多测点流量测量装置产品说明书
概述
在电力、冶金、石油、化工等诸多行业中有许多输送流体的工艺管道，准 确测量其流体的流量是操控设备自动、安全运行，实现节能降耗、提高生产效 率、保证产品质量的重要环节之一。很多大中型企业，尤其是电厂，设备庞大 且大管道繁多。管道布局受空间限制，大管道的交汇、分支、弯曲、变径等部 位，不能按最佳流态设计。由于阻力件形式繁杂，流量调节阀特性不佳、直管 段过短、流体温度混合不均、流速太低、管道振动、流体夹带大量粉尘及粒状 杂质等诸多因素的制约，造成管道流态复杂、流场紊乱。使得当前各类传统的 经典流量测量装置无法准确测量，不能满足自动测控要求。发明解决低速、管 道流场复杂多变、夹带粉粒杂质的流量测量的先进技术产品，并投放市场，是 我们的重要使命。
24lc256系列中文
I2C™ 串行 EEPROM 系列数据手册
特征：
• 容量从 128 位到 512 千位 • 24AAXX 器件单电源供电，工作电压低至 1.8V • 低功耗 CMOS 技术： - 1 mA 典型工作电流 - 1 µA 典型待机电流 （工业级温度） • 2 线串行接口总线，兼容 I2C™ • 施密特触发器输入以抑制噪声 •输出斜率控制以消除接地反弹 • 兼容 100 kHz （1.8V）和 400 kHz （≥ 2.5V）两 种传输速率 • 24FCXX 器件工作频率为 1 MHz • 自定时擦／写周期 （包括自动擦除） • 页写入缓冲器 • 大部分器件具有硬件写保护功能 • 具有工厂编程 （QTP）功能 • 静电保护电压 > 4,000V • 擦写次数可达 1,000,000 次 • 数据保存超过 200 年 • 8 引脚 PDIP、SOIC、 TSSOP 和 MSOP 封装 • 5 引脚 SOT-23 封装 （大部分容量为 1 到 16 千位的 器件） • 提供 8 引脚 2x3mm 和 5x6mm DFN 封装 • 扩展工作温度范围： - 工业级 （I） ： -40°C 到 +85°C - 汽车级 （E） ：-40°C 到 +125°C
2005 Microchip Technology Inc.
DS21930A_CN 第 3 页
24AAXX/24LCXX/24FCXX
2.0 电气特性
绝对最大额定值 (†)
VCC .............................................................................................................................................................................6.5V 相对于 Vss 的所有输入和输出 ............................................................................................................ -0.6V 到 VCC +1.0V 存储温度 ................................................................................................................................................. -65°C 到 +150°C 环境温度 （使用电源时） ........................................................................................................................ -40°C 到 +125°C 所有引脚静电保护 ....................................................................................................................................................................≥ 4 kV
M24C04-RMB6T中文资料
1/29March 2004M24C16, M24C08M24C04, M24C02, M24C0116Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I²C Bus EEPROMFEATURES SUMMARY■Two Wire I 2C Serial Interface Supports 400kHz Protocol ■Single Supply Voltage:– 4.5 to 5.5V for M24Cxx – 2.5 to 5.5V for M24Cxx-W – 1.8 to 5.5V for M24Cxx-R ■Write Control Input■BYTE and PAGE WRITE (up to 16 Bytes)■RANDOM and SEQUENTIAL READ Modes ■Self-Timed Programming Cycle ■Automatic Address Incrementing ■Enhanced ESD/Latch-Up Behavior ■More than 1 Million Erase/Write Cycles ■More than 40 Year Data RetentionM24C16, M24C08, M24C04, M24C02, M24C01TABLE OF CONTENTSFEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 1.Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2.Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Table 1.Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Power On Reset: VCC Lock-Out Write Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure 3.DIP, SO, TSSOP and MLP Connections (Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . .4SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure 4.Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus . . . . . . . . . . . . . . .5 Figure 5.I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 2.Device Select Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6DEVICE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 3.Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 6.Write Mode Sequences with WC=1 (data write inhibited). . . . . . . . . . . . . . . . . . . . . . . . .8 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 7.Write Mode Sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 8.Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Figure 9.Read Mode Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Acknowledge in Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 4.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132/29M24C16, M24C08, M24C04, M24C02, M24C01DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Table 5.Operating Conditions (M24Cxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 6.Operating Conditions (M24Cxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 7.Operating Conditions (M24Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 8.AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 10.AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 9.Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 10.DC Characteristics (M24Cxx, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 11.DC Characteristics (M24Cxx, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 12.DC Characteristics (M24Cxx-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 13.DC Characteristics (M24Cxx-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 14.DC Characteristics (M24Cxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 15.AC Characteristics (M24Cxx, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 16.AC Characteristics (M24Cxx, Device Grade 3; M24Cxx-W, Device Grade 6 or 3). . . . .18 Table 17.AC Characteristics (M24Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Figure 11.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Figure 12.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . .21 Table 18.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data. . . . . . . . . .21 Figure 13.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . .22 Table 19.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data 22Figure 14.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Outline 23Table 20.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Data.23Figure 15.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . .24 Table 21.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data. . . . . . . . . . . .24 Figure 16.TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline 25Table 22.TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data 25PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Table 23.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 24.How to Identify Current and New Products by the Process Identification Letter. . . . . . .27REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 25.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283/29M24C16, M24C08, M24C04, M24C02, M24C014/29SUMMARY DESCRIPTIONThese I 2C-compatible electrically erasable pro-grammable memory (EEPROM) devices are orga-nized as 2048/1024/512/256/128x 8 (M24C16,M24C08, M24C04, M24C02, M24C01).I C uses a two wire serial interface, comprising a bi-directional data line and a clock line. The devic-es carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I 2C bus definition.The device behaves as a slave in the I 2C protocol,with all memory operations synchronized by the serial clock. Read and Write operations are initiat-ed by a Start condition, generated by the bus mas-ter. The Start condition is followed by a Device Table 2.),terminated by an acknowledge bit.When writing data to the memory, the device in-serts an acknowledge bit during the 9th bit time,following the bus master’s 8-bit transmission.When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.Table 1. Signal NamesPower On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up, the internal reset is held active until V CC has reached the POR threshold value, and all operations are disabled – the device will not respond to any com-mand. In the same way, when V CC drops from the operating voltage, below the POR threshold value,all operations are disabled and the device will not respond to any command.A stable and valid V CC (as defined in Table 6. and Table 7.) must be applied before applying any log-ic signal.Note: 1.NC = Not Connected2.See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.E0, E1, E2Chip Enable SDA Serial Data SCL Serial Clock WC Write Control V CC Supply Voltage V SSGroundM24C16, M24C08, M24C04, M24C02, M24C01 SIGNAL DESCRIPTIONSerial Clock (SCL).This input signal is used to strobe all data in and out of the device. In applica-tions where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to V CC. (Figure 4. indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchro-nization is not employed, and so the pull-up resis-tor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA).This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Se-rial Data (SDA) to V CC. (Figure 4. indicates how the value of the pull-up resistor can be calculated). Chip Enable (E0, E1, E2).These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to V CC or V SS, to establish the Device Select Code.Write Control (WC).This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write opera-tions are disabled to the entire memory array when Write Control (WC) is driven High. When uncon-nected, the signal is internally read as V IL, and Write operations are allowed.When Write Control (WC) is driven High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged.25/29M24C16, M24C08, M24C04, M24C02, M24C012Table 2. Device Select CodeDevice Type Identifier1Chip Enable2,3RW b7b6b5b4b3b2b1b0 M24C01Select Code1010E2E1E0RW M24C02Select Code1010E2E1E0RW M24C04Select Code1010E2E1A8RW M24C08Select Code1010E2A9A8RW M24C16Select Code1010A10A9A8RW Note: 1.The most significant bit, b7, is sent first.2.E0, E1 and E2 are compared against the respective external pins on the memory device.3.A10, A9 and A8 represent most significant bits of the address.6/297/29M24C16, M24C08, M24C04, M24C02, M24C01DEVICE OPERATIONThe device supports the I 2C protocol. This is sum-marized in Figure 5.. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver.The device that controls the data transfer is known as the bus master, and the other as the slave de-vice. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24Cxx device is always a slave in all communication.Start ConditionStart is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition,and will not respond unless one is given.Stop ConditionStop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driv-en High. A Stop condition terminates communica-tion between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EE-PROM Write cycle.Acknowledge Bit (ACK)The acknowledge bit is used to indicate a success-ful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.Data InputDuring data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL).For correct device operation, Serial Data (SDA)must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driv-en Low.Memory AddressingTo start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 2.(on Serial Data (SDA), most significant bit first).The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address”(E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is 1010b.Each device is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the val-ue on the Chip Enable (E0, E1, E2) inputs. How-ever, those devices with larger memory capacities (the M24C16, M24C08 and M24C04) need more address bits. E0 is not available for use on devices that need to use address line A8; E1 is not avail-able for devices that need to use address line A9,and E2 is not available for devices that need to use address line A10 (see Figure 3. and Table 2. for details). Using the E0, E1 and E2 inputs, up to eight M24C02 (or M24C01), four M24C04, two M24C08 or one M24C16 devices can be connect-ed to one I 2C bus. In each case, and in the hybrid cases, this gives a total memory capacity of 16Kbits, 2KBytes (except where M24C01 devic-es are used).The 8th set to 1 for Read and 0 for Write operations.If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Stand-by mode.Table 3. Operating ModesNote: 1.X = V IH or V IL .ModeRW bit WC 1Bytes Initial SequenceCurrent Address Read 1X 1START, Device Select, RW = 1Random Address Read 0X 1START, Device Select, RW = 0, Address 1X reSTART, Device Select, RW = 1Sequential Read 1X ≥ 1Similar to Current or Random Address Read Byte Write 0V IL 1START, Device Select, RW = 0Page WriteV IL≤ 16START, Device Select, RW = 0M24C16, M24C08, M24C04, M24C02, M24C018/29Following a Start condition the bus master sends a Device Select Code with the RW bit reset to 0.The device acknowledges this, as shown in Figure 7., and waits for an address byte. The device re-sponds to the address byte with an acknowledge bit, and then waits for the data byte.When the bus master generates a Stop condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered.A Stop condition at any other time slot does not trigger the internal Write cycle.During the internal Write cycle, Serial Data (SDA)and Serial Clock (SCL) are ignored, and the de-vice does not respond to any requests.Byte WriteAfter the Device Select code and the address byte,the bus master sends one data byte. If the ad-dressed location is Write-protected, by Write Con-trol (WC) being driven High (during the period frombyte), the device replies to the data byte with NoAck, as shown in Figure 6., and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack.The bus master terminates the transfer by gener-ating a Stop condition, as shown in Figure 7..Page WriteThe Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory:that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way.The bus master sends from 1 to 16 bytes of data,each of which is acknowledged by the device if Write Control (WC) is Low. If the addressed loca-ing driven High (during the period from the StartM24C16, M24C08, M24C04, M24C02, M24C01condition until the end of the address byte), the de-vice replies to the data bytes with NoAck, as shown in Figure 6., and the locations are not mod-ified. After each byte is transferred, the internal byte address counter (the 4 least significant ad-dress bits only) is incremented. The transfer is ter-minated by the bus master generating a Stop condition.9/29M24C16, M24C08, M24C04, M24C02, M24C0110/29During the internal Write cycle, the device discon-nects itself from the bus, and writes a copy of the data from its internal latches to the memory cells.The maximum Write time (t w ) is shown in Table 15. to Table 17., but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master.The sequence, as shown in Figure 8., is:–Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction).–Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).Read OperationsRead operations are performed independently of the state of the Write Control (WC) signal.The device has an internal address counter which is incremented each time a byte is read. Random Address ReadA dummy Write is first performed to load the ad-dress into this address counter (as shown in Fig-ure 9.) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the RW bit set to 1. The device acknowledges this, and out-puts the contents of the addressed byte. The bus master must not acknowledge the byte, and termi-nates the transfer with a Stop condition.Current Address ReadFor the Current Address Read operation, following a Start condition, the bus master only sends a De-vice Select Code with the RW bit set to 1. The de-vice acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master ter-minates the transfer with a Stop condition, as shown in Figure 9., without acknowledging the byte.11/29Sequential ReadThis operation can be used after a Current Ad-dress Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the de-vice continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 9.. The output data comes from consecutive address-es, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h.Acknowledge in Read ModeFor all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device termi-nates the data transfer and switches to its Stand-by mode.INITIAL DELIVERY STATEThe device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh).12/2913/29MAXIMUM RATINGStressing the device above the rating listed in the Absolute Maximum Ratings" table may cause per-manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im-plied. Exposure to Absolute Maximum Rating con-ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu-ments.Table 4. Absolute Maximum RatingsNote: pliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, andthe European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2.JEDEC Std JESD22-A114A (C1=100pF, R1=1500 Ω, R2=500 Ω)Symbol ParameterMin.Max.Unit T STG Storage Temperature–65150°C T LEAD Lead Temperature during Soldering See note 1°C V IO Input or Output range –0.50 6.5V V CC Supply Voltage–0.50 6.5V V ESDElectrostatic Discharge Voltage (Human Body model) 2–40004000V14/29DC AND AC PARAMETERSThis section summarizes the operating and mea-surement conditions, and the DC and AC charac-teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de-rived from tests performed under the Measure-ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame-ters.Table 5. Operating Conditions (M24Cxx)Note: 1.This range is Not for New Design, and will soon be replaced by the M24Cxx-W range.Table 6. Operating Conditions (M24Cxx-W)Table 7. Operating Conditions (M24Cxx-R)Symbol ParameterMin.Max.Unit V CC Supply Voltage4.55.5V T AAmbient Operating Temperature (Device Grade 6)–4085°C Ambient Operating Temperature (Device Grade 3)–40125°CSymbol ParameterMin.Max.Unit V CC Supply Voltage2.5 5.5V T AAmbient Operating Temperature (Device Grade 6)–4085°C Ambient Operating Temperature (Device Grade 3)–40125°CSymbol ParameterMin.Max.Unit V CC Supply Voltage1.8 5.5V T AAmbient Operating Temperature–4085°C15/29Table 8. AC Measurement ConditionsTable 9. Input ParametersNote: 1.T A = 25°C, f = 400kHz2.Sampled only, not 100% tested.Table 10. DC Characteristics (M24Cxx, Device Grade 6)Note: 1.This range is Not for New Design, and will soon be replaced by the M24Cxx-Wxx6 range.Symbol ParameterMin.Max.Unit C LLoad Capacitance 100pF Input Rise and Fall Times 50ns Input Levels0.2V CC to 0.8V CC V Input and Output Timing Reference Levels0.3V CC to 0.7V CCVSymbol Parameter 1,2Test ConditionMin .Max .Unit C IN Input Capacitance (SDA)8pF C IN Input Capacitance (other pins)6pF Z WCL WC Input Impedance V IN < 0.5V 570k ΩZ WCH WC Input Impedance V IN > 0.7V CC 500k Ωt NSPulse width ignored(Input Filter on SCL and SDA)Single glitch100nsSymbol ParameterTest Condition(in addition to those in Table 5.)Min.Max.Unit I LI Input Leakage Current (SCL, SDA)V IN = V SS or V CC± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CC Supply CurrentV CC =5V , f c =400kHz (rise/fall time < 30ns)2mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 5V1µA V ILInput Low Voltage(E2, E1, E0, SCL, SDA)–0.450.3V CC V Input Low Voltage (WC)–0.450.5V V IH Input High Voltage(E2, E1, E0, SCL, SDA, WC)0.7V CC V CC +1V V OLOutput Low VoltageI OL = 3mA, V CC = 5V 0.4V16/29Table 11. DC Characteristics (M24Cxx, Device Grade 3)Note: 1.This range is Not for New Design, and will soon be replaced by the M24Cxx-Wxx3 range.Table 12. DC Characteristics (M24Cxx-W, Device Grade 6)Symbol ParameterTest Condition(in addition to those in Table 5.)Min.Max.Unit I LI Input Leakage Current (SCL, SDA)V IN = V SS or V CC± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CC Supply CurrentV CC =5V , f c =400kHz (rise/fall time < 30ns)3mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 5V5µA V ILInput Low Voltage(E2, E1, E0, SCL, SDA)–0.450.3V CC V Input Low Voltage (WC)–0.450.5V V IH Input High Voltage(E2, E1, E0, SCL, SDA, WC)0.7V CC V CC +1V V OLOutput Low VoltageI OL = 3mA, V CC = 5V 0.4VSymbol ParameterTest Condition(in addition to those in Table 6.)Min.Max.Unit I LI Input Leakage Current (SCL, SDA)V IN = V SS or V CC± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CC Supply CurrentV CC =2.5V, f c =400kHz (rise/fall time < 30ns)1mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 2.5V0.5µA V ILInput Low Voltage(E2, E1, E0, SCL, SDA)–0.450.3V CC V Input Low Voltage (WC)–0.450.5V V IH Input High Voltage(E2, E1, E0, SCL, SDA, WC)0.7V CC V CC +1V V OLOutput Low VoltageI OL = 2.1mA, V CC = 2.5V 0.4V。
MTC 25 CC和MTC 25C操作说明书
33July 2017 cranes & access or crane. The product uses the ‘leverage’ and ‘grip or traction’ principal to allow the electric powered non-marking wheels to move such substantial loads. It features a two stage telescoping handle and weighs 75kg with battery. And if you need to move larger loads, combining additional units increases the capacity - ie two can move 50 tonnes, three 75 tonnes etc.Available in two versions - the cordless battery powered MTC 25 CC and mains powered MTC 25C - they use a 24 volt synchronous motor with one kilowatt power output providing smooth, continuous forward and reverse functions and emergency stop. The device uses an adaptor to connect to most steerable skates - such as German made GKS-Perfekt or Jung - and works like the kingpin of a tractor steering and manoeuvring (forward-reverse) a semi-trailer.Powered micro crane/lift Another new hand lift is the Powered Hand Truck from Australian company Makinex which has a maximum capacity of 140kg when working with the hook and 120kg with the fork attachment. It is designed to work on hard surfaces on slopes of up to three degrees. Other attachments include a vacuum lifter, panel lifter and sling. The unit can be folded flat when not in use and carried easily in a van or truck. The unit - which when lifting looks like a chicken wishbone - has a bottom frame with two travel wheels at one end with the handle with lift button and brake that the operator holds at the other. A long telescopic cylinder is connected centrally near the wheels to the moveable lifting arm which has a maximum lift of 1.9 metres. Power is supplied by an 18 volt battery pack.The range of different lifting equipment available or suited for industrial applications is continuously growing and evolving. Whether it involves lifting huge production machinery or just a small engine or pump, an ideal piece of equipment is sure to be available. It is not about the size of the equipment but finding the right tool for the job.clever design and improvements in technology have advanced to the point where battery electric industrial pick & carry, carry deck and spider cranes can perform as well as diesel powered models in terms of speeds, power and the ability to complete a full shift. Stricter manual handling regulations have also lead to the development of a burgeoning variety of smaller hand operated lifting machines, which are growing in popularity and spurring on further development.We have often highlighted the PowerAttack - an innovative lifting/skid tug which looks more like a powered broom handle but can move loads up to 25 tonnes using unpowered skates/dollies and is particularly useful in confined spaces in place of a fork lift truck The right tool forthe job industrial lifting c &a Each PowerAttack can more loads up to 25 tonnes Portable material loader Another interesting hand operated lifting product aimed at the smaller delivery sector is the Portable Self Loading fork lift from American company Innolift. The very clever product can self-load and unload items up to 600kg from the back of a van or truck and then operate in the same way as a walk behind material/fork lift. Maximum lift height is one metre. Once it has helped load the van it can load itself into the back, ready to unload the cargo at the next stop.Up and down the stairs Moving loads up and down stairs is another application that has spurred manufacturers to develop numerous innovative stair climbing cart solutions including rubber tracked carriers. CTE has developed and refined its product offerings in this sector with its Pianoplan 600J range of machines. The various models range from a standard transporter, to the Horizontal model that will maintain a level cargo deck while travelling up a flight of stairs and the Vertical model which will lift and tilt a large bulky load from the end then tilt it to the horizontal for the journey/steps and then raise it back to the upright position when in its final location. Maximum capacityover the pastfew years hascontinued a totaltransformation ofits product range,manufacturingfacilities anddistributionwith many of itsproducts ideal forindustrial lifting.(see Jekko on theMove story p50)Mast boom craneAs we have already seen, liftingand moving a load in an industrialsituation is more about finding theright tool for the job - irrespectiveof size. This year’s Vertikal Daysis 600kg on all three and overallweight of the machines runs from300kg for the standard model to345kg for the vertical.Off road tracked carriersWhen transporting larger loadsacross uneven ground the trackedcarrier - such as those seen onthe JT Cranes stand at this year’sVertikal Days and the 1,200kgcapacity Hoeflon TC1 - are ideal. JTCranes offers two remote controlcarriers with capacities of 4,000kgand 1,500kg and platform heightsof 570mm and 420mm respectively,ideal for moving loads when pickand carry is not an option.JT Cranes is the UK distributorfor Jekko, a company whichalso witnessed the UK debut ofanother unusual product - a mastboom industrial crane - fromGerman manufacturer HematecArbeitsbühnen. Hematec calls itsK 12500 a self-propelled assemblycrane with telescopic jib.&34cranes & access July 2017CTE’s Pianoplan hasa 600kg capacityand can travel up aflight of stairsA 1,200kgcapacity Hoeflon trackedcarrierWhatever its name it has a maximum tip height of 10.5 metres with a 500kg lift capacity, and a maximum radius of almost five metres with a 300kg load at a height of almost seven metres, or take 500kg to a radius of 3.6 metres. The machine can also slew or travel with its maximum capacity even when over the side. Overall width is just 980mm but the weight however is a fairly hefty 4.8 tonnes. Based on the company’s well proven Helix mast boom platform with a three section telescopic luffing jib in place of the basket, the unit is battery operated with direct electric drive and remote controls. The company has so far delivered 12 units to companies such as Audi, Bosch, Borbet, Mercedes-Benz and Volkswagen all of which appreciated its ability to work in restricted space conditions.Battery operatedcarry deck cranesWe reported last year ona new all battery electriccarry deck crane built bySouth Korean manufacturerHoryong and sold in theAmericas as the ZEE Crane.Two models are available- the 4.1 tonne 4500 andthe 8.2 tonne 9000 with a13.6 tonne version in theprototype phase. Poweredby dual battery packs theunits can be fully chargedovernight for an eight hourshift the following day.The 4500 weighs 3.6 tonnesand has a travel speed of 4.5 mph with two mph pick & carry speed. At 8.5metres the 4500 can lift 458kg. A 2.3 metre jib withzero, 25 and 50 degree offsets is available - ideal forrestricted space working - with an easy to changesingle to two fall hook block. Options include non-marking tyres, an in-house designed LMI with built-in diagnostics and a one man work platform.Another battery electric powered carry deck cranespotted at Conexpo in March is the BC-18, fromWisconsin-based Bailey Cranes with a maximumcapacity of 8.2 tonnes a three section boom with 14metre tip height. Pick & carry capacity is 5.3 tonnes.The American-made crane uses direct AC drivemotors for all functions and load sensing hydraulics.Options include a hybrid version and a three metrejib. Overall weight is just over nine tonnes.JMG expandsItalian crane manufacturer JMG Cranes is arelatively recent addition to the pick & carry cranemarket founded in 2007 by Maurizio Manzini, andjoining other Italian companies such as Ormig, Vallaand Galizia. Since then the company has unveileda number of innovations, including the first electricpick & carry crane with a Programmable LogicController in 2013, and the first narrow width -2,290mm wide - 45 tonne pick and carry cranein 2014. Last year the company acquired Lige -another small local industrial crane manufacturerwith 70 years experience - and this year addedthe new MC 580 battery operated electric pick &carry crane to its 17 model line-up, with a 58 tonnemaximum capacity.July 2017 cranes &The ZEE Crane 4500 during assembly Continued on page 49industrial lifting c&aThe MC 580 features a chunky four section, full power telescopic boom with boom nose mounted hook. The counterweight comprises four sections and an extendible wheelbase for additional capacity and greater stability. It has a fully equipped cab with radio remote joystick controls, a seven inch information screen, front wheel AC direct drive, rear 180 degree steer with counter rotating front wheels, allowing it to rotate on the spot through 360 degrees with full load on the hook. Options include a 30 tonne fork attachment, quick fit front levelling outriggers and a winch.Reedyk PC4405and Jekko MPK50 Another new industrial pick & carry crane is the compact Reedyk PC4405 from the Netherlands seen for the first time at Vertikal Days. The unit has been designed with an ATEX option for operating in areas exposed to explosion hazards. Equipped with a lithium ion battery pack, the crane is said to operate emission free for longer than one day on a single charge. The 30 degrees swivel boom assists accurate positioning and the PC4405 comes with a useful pick & carry deck. Maximum capacity is three tonnes, maximum lift height is nine metres with a maximum radius of 5.7 metres. The crane has a one metre overall width and weighs a relatively modest 2.8 tonnes. The PC4405 has an overall length of just2.4 metres with an overall height of1.8 metres.The PC4405 is a new breed ofpick & carry cranes similar toJekko’s remote controlled, batterypowered five tonne MPK50 MiniPicker, which offers a 9.5 metrelift height and a maximum radiusof 6.2 metres. The MPK50 hasan overall width of 1.2 metresand is three metres long. Overallweight is 3,450kg with the optionof a 1,000kg counterweight. TheJekko also has a two sectionmanually telescoped jib and offersfive degrees of slew either side ofcentre. A front stabiliser bar can beused to increase stability and liftcapacity. The Jekko Mini Pickersare pick & carry self-propelledbattery powered electric craneswith radio remote controls. Theycan also be used with Jekkohydraulic manipulators or vacuumlifters for handling and placingglass panels with options such aswinches, jibs, man platforms andlifting beams.The Hoeflon factorAnother mini crane company basedin the Netherlands and makinga concerted effort to expand itsproduct line and sales is Hoeflon. Itsrange now includes four mini cranesincluding the 600kg capacity minicrawler C1, and three spider cranes- the two tonne C4, the three tonneC6 and the four tonne capacity C10.With the range and sales increasingthe company is expanding andmoving to a new facility.HD forklift optionsAnyone needing an ultra heavy-duty‘lift & shift’ forklift cranes will havelooked at the Versa-Lift range ofmachines. The four model rangewas extended earlier this yearwith a new smaller model nowavailable. The 17/25 uses a slightlydifferent design which combinesthe wheelbase of a 6.8 tonnesolid tyre forklift with a moveablecounterweight that extends to therear by 914mm, rather than thewhole frame extending as is thecase with the rest of its range.Maximum capacity is 11.3 tonnesand the three section mast gives a3.7 metre lift height on the forks,which increases to just under sevenmetres when using the optionalboom attachment. Overall weight ofthe 17/25 is 13.6 tonnes.Skid steer crane attachmentOther weird and wonderful liftingdevices include the SkidCrane.Perhaps not primarily aimed at theindustrial lifting market, it is anattachment that converts a skidsteer loader into a unit capable oflifting up to 2.3 tonnes and up to13.1 metres. The SkidCrane is acompact hydraulically controlledcrane attachment that is easy toattach, use and transport and idealfor working in confined spacesparticularly on flat hard surfaces.Remote controls are also available.Earlier this year JMG added the new MC 580 battery operated electric pick & carry craneAnother new industrialpick & carry crane is thecompact Reedyk PC4405The SkidCraneis a compacthydraulicallycontrolled craneattachment for theskid steer loaderA Hoeflon crane in atight spotContinued from page 3549July 2017 cranes & access&50cranes & access July 2017Over the past few years Italian mini and spider crane manufacturer Jekko has been developing at a rapid pace. Cranes & Access caught up with chief executive Diego Tomasella at the opening of a new production hall to learn about the company’s latest developments.Five years ago, Jekko produced just 80 spider cranes a year however with annual growth of around 40 percent is it now forecasting shipments of 250 cranes this year - more than three times as many. However this is set to grow to 400 units a year over the next two years as production is further expanded.A new assembly facility has just opened located five kilometres from its headquarters in Colle Umberto to the north of Treviso, near Venice. Total area is 12,000 square metres - of which 3,900 square metres is covered - while much of the rest includes a large concrete yard. The old facility has been retained and is now used mainly for fabrication, while the new facility is purely an assembly hall with three production lines. Total investment is around €3 million.“The new facility allows us to increase production giving flexibility to cope with the increasing orders and improve the quality of the end product, particularly when one model is very much in demand,” says Tomasella. “Our new challenge with the rapid expansion of sales is the growth of the support within the company, particularly service and sales staff.”To maintain its growth Jekko has expanded its dealer network to 30 companies around the world, including China, Singapore, South Korea, Mexico, Colombia, the UK, Canada and USA. With Fassi taking a 33 percent stake in the company last year, there are several interesting new products including the new JF Jekko on the move tracked articulated loader cranes but also new lithium power packs for the spider and mini crawler cranes. However it is the tracked loader crane which the company thinks will be most popular range in five to 10 years time. Three models have been launched - the JF 545, the JF 30 and JF rgest is the 15.5 tonne capacity JF 545 with a six section main boom and six section jib, giving a maximum capacity of 600kg at 28.1 metres and a maximum lift height with 500kg of 30 metres. In transport mode the unit measures 5.45 metres long, 1.84 metres wide and 2.75 metres high, and weighs 15 tonnes. Outrigger spread is 6.7 metres square and the JF 545 offers a maximum radius of 10 metres at an up and over height of 18 metres. Power is supplied by a Kubota diesel, while options include an auxiliary electric motor, non-marking tracks and a two person 200kg platform with a 31.5 metre working height. Jekko says it has already booked 15 orders for the new JF 545’s. The other two tracked articulated loader cranes include the JF30 and JF40 which are similar in that they have maximum heights of eight and 8.1 metres and a maximum radius off 6.8 metres. Physically similar in size, the JF30 only has a lift capacity of 995kg so does not require a load moment limiter using a lift limiter on the winch. The JF40 has a maximum lift capacity of 2,500kg. Options on both include a 600kg capacity winch, electric power pack and remote control with two manual extensions on theJF30 and a single extension Jekko’s new facility will help boost production to 400 units per year over the next two years on the JF40. The JF 30 has an outrigger spread of 3.4 metres and weighs 1,400kg whereas the JF 40 has a four metre square spread and weighs 1,600kg. Both have a 2.4kph travel speed and gradeability of 20 degrees.“Jekko will not rank among the top two mini crane companies in the coming years, but we can keep pace with the competition,” says Tomasella. “Our goal has always been to come up with new ideas for the market. In a conservative market the smaller cranes can open doors.”New developments include a new colour scheme and decals from next year, the launch of a new MPK05, a new hydraulic jib for the SPX312 and a new nine tonne capacity SPK90 - the big brother of the SPK60.The 15.5 tonne capacity JF 545There are plans for a new nine tonne capacity SPK90 - the big brother of this SPK6051 July 2017 cranes & access。
YAV 8AD-24高精度串口采集卡技术手册DAM7452
YAV8AD-24高精度串口采集卡技术手册V1801武汉亚为电子科技有限公司DAM7452关于本手册为亚为推出的YAV8AD-24数据采集卡的用户手册，主要内容包括功能概述、8路模拟量输入功能、应用实例、性能测试、注意事项及故障排除等。
说明序号版本号编写人编写日期支持对象应用时间特别说明1 1.0郑先科2014.05RS2328AD plus采集卡2 2.0郑先科2016.01YAV8AD采集卡3 3.0郑先科2017.01YAV8AD plus采集卡2017.01适用于RS232\485\WiFi\GPRS ZIGBEE\蓝牙\433M无线4 4.0李雪2017.08YA V8AD-24采集卡目录0.快速上手 (1)产品包装内容 (1)应用软件 (1)接口定义 (1)⏹端子排列 (1)⏹端子描述 (2)通信 (3)采集卡指示灯 (3)1.产品概述 (3)技术指标 (3)⏹模拟信号输入 (4)⏹通信总线 (4)⏹供电 (5)⏹温度参数 (5)硬件特点 (5)原理框图 (6)机械规格 (7)2.采集卡信号接线 (8)AI模拟量接线 (8)DI数字量接线 (8)DO数字量接线 (9)3.模拟量输入功能 (10)模拟量输入 (10)输入采样原理 (10)输入接线 (10)采样值计算 (11)⏹无符号整型 (11)⏹24位精度采集值的计算方法 (11)⏹模拟量值 (12)4.通信协议 (13)MODBUS-RTU通信协议 (13)5.应用实例 (16)采集卡连接 (16)软件功能 (17)软件应用 (17)⏹亚为串口采集卡通用采集平台 (18)⏹LabVIEW (18)⏹MODBUS RTU通信 (19)6.注意事项及故障排除 (19)注意事项 (19)⏹存储说明 (19)⏹出货清单 (19)⏹质保及售后 (20)⏹特别说明 (20)故障排除 (21)⏹无法正常采集数据 (21)⏹VI文件打不开 (21)⏹多卡不识别 (22)⏹不显示波形 (22)⏹采集速度不够 (22)软件弹出错误 (22)7.性能测试 (22)安全规范 (22)耐电压范围测试 (23)环境适应性测试 (23)8.文档权利及免责声明 (24)9.联系方式.........................................................................................................................错误！未定义书签。
atc中文手册
AT24C256中文资料2009-11-1509:43特性与1MHzI2C总线兼容1.8到6.0伏工作电压范围低功耗CMOS技术写保护功能当WP为高电平时进入写保护状态64字节页写缓冲器自定时擦写周期100,000编程/擦写周期可保存数据100年8脚DIPSOIC封装温度范围商业级工业级和汽车级概述CAT24WC256是一个256K位串行CMOSE2PROM内部含有32768个字节每字节为8位CATALYST公司的先进CMOS技术实质上减少了器件的功耗CAT24WC256有一个64字节页写缓冲器该器件通过I2C总线接口进行操作极限参数工作温度工业级-55+125商业级0+75贮存温度-65+150各管脚承受电压-2.0VVcc+2.0VVcc管脚承受电压-2.0V+7.0V封装功率损耗Ta=251.0W焊接温度(10秒)300口输出短路电流100mA功能描述CAT24WC256支持I2C总线数据传送协议I2C总线协议规定任何将数据传送到总线的器件作为发送器任何从总线接收数据的器件为接收器数据传送是由产生串行时钟和所有起始停止信号的主器件控制的CAT24WC256是作为从器件被操作的主器件和从器件都可以作为发送器或接收器但由主器件控制传送数据发送或接收的模式管脚描述SCL串行时钟CAT24WC256串行时钟输入管脚用于产生器件所有数据发送或接收的时钟这是一个输入管脚SDA串行数据/地址双向串行数据/地址管脚用于器件所有数据的发送或接收SDA是一个开漏输出管脚可与其它开漏输出或集电极开路输出进行线或wire-ORWP写保护当WP脚连接到Vcc所有内存变成写保护只能读当WP引脚连接到Vss或悬空允许器件进行读/写操作A0A1器件地址输入这些管脚为硬连线或者不连接对于单总线系统最多可寻址4个CAT24WC256器件参阅器件寻址当这些引脚没有连接时其默认值为0I2C总线协议I2C总线协议定义如下1只有在总线空闲时才允许启动数据传送2在数据传送过程中当时钟线为高电平时数据线必须保持稳定状态不允许有跳变时钟线为高电平时数据线的任何电平变化将被看作总线的起始或停止信号起始信号时钟线保持高电平期间数据线电平从高到低的跳变作为I2C总线的起始信号停止信号时钟线保持高电平期间数据线电平从低到高的跳变作为I2C总线的停止信号器件寻址主器件通过发送一个起始信号启动发送过程然后发送它所要寻址的从器件的地址8位从器件地址的高5位固定为10100见图5接下来的2位A1A0为器件的地址位最多可以连接4个器件到同一总线上这些位必须与硬连线输入脚A1A0相对应从器件地址的最低位作为读写控制位1表示对从器件进行读操作0表示对从器件进行写操作在主器件发送起始信号和从器件地址字节后CAT24WC256监视总线并当其地址与发送的从地址相符时响应一个应答信号通过SDA线CAT24WC256再根据读写控制位R/W的状态进行读或写操作应答信号I2C总线数据传送时每成功地传送一个字节数据后接收器都必须产生一个应答信号应答的器件在第9个时钟周期时将SDA线拉低表示其已收到一个8位数据CAT24WC256在接收到起始信号和从器件地址之后响应一个应答信号如果器件已选择了写操作则在每接收一个8位字节之后响应一个应答信号当CAT24WC256工作于读模式时在发送一个8位数据后释放SDA线并监视一个应答信号一旦接收到应答信号CAT24WC256继续发送数据如主器件没有发送应答信号器件停止传送数据并等待一个停止信号写操作字节写在字节写模式下主器件发送起始信号和从器件地址信息R/W位置0给从器件在从器件送回应答信号后主器件发送两个8位地址字写入CAT24WC256的地址指针主器件在收到从器件的应答信号后再发送数据到被寻址的存储单元CAT24WC256再次应答并在主器件产生停止信号后开始内部数据的擦写在内部擦写过程中CAT24WC256不再应答主器件的任何请求页写在页写模式下单个写周期内CAT24WC256最多可以写入64个字节数据页写操作的启动和字节写一样不同在于传送了一字节数据后主器件允许继续发送63个字节每发送一个字节后CAT24WC256将响应一个应答位且内部低6位地址加1高位地址保持不变如果主器件在发送停止信号之前发送大于64个字节地址计数器将自动翻转先前写入的数据被覆盖当所有64字节接收完毕主器件发送停止信号内部编程周期开始此时所有接收到的数据在单个写周期内写入CAT24WC256应答查询可以利用内部写周期时禁止数据输入这一特性一旦主器件发送停止位指示主器件操作结束时CAT24WC256启动内部写周期应答查询立即启动包括发送一个起始信号和进行写操作的从器件地址如果CAT24WC256正在进行内部写操作将不会发送应答信号如果CAT24WC256已经完成了内部写操作将发送一个应答信号主器件可以继续对CAT24WC256进行下一次读写操作写保护写保护操作特性可使用户避免由于不当操作而造成对存储区域内部数据的改写当WP管脚接高时整个寄存器区全部被保护起来而变为只可读取CAT24WC256可以接收从器件地址和字节地址但是装置在接收到第一个数据字节后不发送应答信号从而避免寄存器区域被编程改写读操作CAT24WC256读操作的初始化方式和写操作时一样仅把R/W位置为1有三种不同的读操作方式立即/当前地址读选择/随机读和连续读立即/当前地址读的地址计数器内容为最后操作字节的地址加1也就是说如果上次读/写的操作地址为N则立即读的地址从地址N+1开始如果N=E此处E=32767则计数器将翻转到0且继续输出数据CAT24WC256接收到从器件地址信号后R/W位置1它首先发送一个应答信号然后发送一个8位字节数据主器件不需发送一个应答信号但要产生一个停止信号选择/随机读选择/随机读操作允许主器件对寄存器的任意字节进行读操作主器件首先通过发送起始信号从器件地址和它想读取的字节数据的地址执行一个伪写操作在CAT24WC256应答之后主器件重新发送起始信号和从器件地址此时R/W位置1CAT24WC256响应并发送应答信号然后输出所要求的一个8位字节数据主器件不发送应答信号但产生一个停止信号连续读连续读操作可通过立即读或选择性读操作启动在CAT24WC256发送完一个8位字节数据后主器件产生一个应答信号来响应告知CAT24WC256主器件要求更多的数据对应每个主机产生的应答信号CAT24WC256将发送一个8位数据字节当主器件不发送应答信号而发送停止位时结束此操作从CAT24WC256输出的数据按顺序由N到N+1输出读操作时地址计数器在CAT24WC256整个地址内增加这样整个寄存器区域在可在一个读操作内全部读出当读取的字节超过E此处E=32767计数器将翻转到零并继续输出数据字节。
74ACT244MTC中文资料
© 2005 Fairchild Semiconductor Corporation DS009943November 1988Revised March 200574AC244 • 74ACT244 Octal Buffer/Line Driver with 3-STATE Outputs74AC244 • 74ACT244Octal Buffer/Line Driver with 3-STATE OutputsGeneral DescriptionThe AC/ACT244 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus-oriented transmitter/receiver which provides improved PC board density.Featuress I CC and I OZ reduced by 50%s 3-STATE outputs drive bus lines or buffer memory address registers s Outputs source/sink 24 mA s ACT244 has TTL-compatible inputsOrdering Code:Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.Pb-Free package per JEDEC J-STD-020B.Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Please use order number as indicated.FACT ¥ is a trademark of Fairchild Semiconductor Corporation.Order Number Package Package DescriptionNumber 74AC244SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74AC244SCX_NL (Note 1)M20B Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74AC244SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74AC244MTC MTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC244MTCX_NL (Note 1)MTC20Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide74AC244PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT244SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACT244SCX_NL (Note 1)M20B Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74ACT244SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT244MSA MSA2020-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74ACT244MTC MTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT244MTCX_NL (Note 1)MTC20Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide74ACT244PCN20A20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 274A C 244 • 74A C T 244Logic SymbolIEEE/IECConnection DiagramPin DescriptionsTruth TablesX ImmaterialZ High ImpedancePin Names DescriptionOE 1, OE 23-STATE Output Enable InputsI 0–I 7Inputs O 0–O 7OutputsInputs OutputsOE 1I n (Pins 12, 14, 16, 18)L L L L H H HXZ Inputs OutputsOE 2I n (Pins 3, 5, 7, 9)L L L L H H HXZ74AC244 • 74ACT244Absolute Maximum Ratings (Note 2)Recommended Operating ConditionsNote 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with-out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT ¥ circuits outside databook specifications.DC Electrical Characteristics for ACNote 3: All outputs loaded; thresholds on input associated with output under test.Note 4: Maximum test duration 2.0 ms, one output loaded at a time.Note 5: I IN and I CC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V CC .Supply Voltage (V CC ) 0.5V to 7.0VDC Input Diode Current (I IK )V I 0.5V 20 mA V I V CC 0.5V 20 mADC Input Voltage (V I )0.5V to V CC 0.5VDC Output Diode Current (I OK )V O 0.5V 20 mA V O V CC 0.5V 20 mADC Output Voltage (V O ) 0.5V to V CC 0.5VDC Output Source or Sink Current (I O )r 50 mA DC V CC or Ground Current per Output Pin (I CC or I GND )r 50 mAStorage Temperature (T STG ) 65q C to 150q CJunction Temperature (T J )PDIP140q CSupply Voltage (V CC )AC 2.0V to 6.0V ACT4.5V to5.5V Input Voltage (V I )0V toV CC Output Voltage (V O )0V to V CCOperating Temperature (T A ) 40q C to 85q CMinimum Input Edge Rate ('V/'t)AC DevicesV IN from 30% to 70% of V CC V CC @ 3.3V, 4.5V, 5.5V 125 mV/nsMinimum Input Edge Rate ('V/'t)ACT Devices V IN from 0.8V to 2.0V V CC @ 4.5V, 5.5V125 mV/nsSymbol Parameter V CC T A 25q C T A 55q C to 125q C T A 40q C to 85q CUnitsConditions (V)Typ Guaranteed Limits V IHMinimum HIGH Level 3.0 1.5 2.1 2.1 2.1V OUT 0.1V Input Voltage4.5 2.25 3.15 3.15 3.15V or V CC 0.1V5.5 2.75 3.85 3.85 3.85V ILMaximum LOW Level 3.0 1.50.90.90.9V OUT 0.1VInput Voltage4.5 2.25 1.35 1.35 1.35Vor V CC 0.1V5.5 2.75 1.65 1.65 1.65V OHMinimum HIGH Level 3.0 2.99 2.9 2.9 2.9Output Voltage4.5 4.49 4.4 4.4 4.4V I OUT 50 P A5.5 5.495.4 5.4 5.43.0 2.56 2.4 2.46I OH 12 mA 4.5 3.86 3.7 3.76VI OH 24 mA 5.54.86 4.7 4.76I OH 24 mA (Note 3)V OLMaximum LOW Level 3.00.0020.10.10.1Output Voltage4.50.0010.10.10.1VI OUT 50 P A 5.50.0010.10.10.13.00.360.500.44I OL 12 mA 4.50.360.500.44VI OL 24 mA 5.50.360.500.44I OL 24 mA (Note 3)I IN Maximum Input 5.5r 0.1r 1.0r 1.0P A V I V CC , GND(Note 5)Leakage Current I OZMaximum V I (OE) V IL , V IH 3-STATE 5.5r 0.25r 5.0r 2.5P AV I V CC , V GND CurrentV O V CC , GND I OLD Minimum Dynamic 5.55075mA V OLD 1.65V Max I OHD Output Current (Note 4) 5.5 50 75mA V OHD 3.85V Min I CC Maximum Quiescent 5.54.080.040.0P AV IN V CC (Note 5)Supply Currentor GND 474A C 244 • 74A C T 244DC Electrical Characteristics for ACTNote 6: All outputs loaded; thresholds on input associated with output under test.Note 7: Maximum test duration 2.0 ms, one output loaded at a time.Symbol ParameterV CC T A 25q C T A 55q C to 125q C T A 40q C to 85q CUnits Conditions (V)Typ Guaranteed Limits V IH Minimum HIGH Level 4.5 1.5 2.0 2.0 2.0V V OUT 0.1V Input Voltage 5.5 1.5 2.0 2.0 2.0or V CC 0.1V V IL Maximum LOW Level 4.5 1.50.80.80.8V V OUT 0.1V Input Voltage 5.5 1.50.80.80.8or V CC 0.1V V OHMinimum HIGH Level 4.5 4.49 4.4 4.4 4.4VI OUT 50 P A Output Voltage5.5 5.495.4 5.4 5.4I OH 124.5 3.86 3.70 3.76VI OH 24 mA 5.54.864.70 4.76I OH 24 mA (Note 6)V OLMaximum LOW Level 4.50.0010.10.10.1VI OUT 50 P A Output Voltage5.50.0010.10.10.1I OL 12 mA4.50.360.500.44V I OL 24 mA5.50.360.500.44I OL 24 mA (Note 6)I IN Maximum Input 5.5r 0.1r 1.0r 1.0P A V I V CC , GND Leakage Current I OZ Maximum 3-STATE 5.5r 0.25r 5.0r 2.5P A V I V IL , V IH Current V O V CC , GND I CCT Maximum 5.50.61.6 1.5mA V I V CC2.1V I CC /InputI OLD Minimum Dynamic 5.55075mA V OLD 1.65V Max I OHD Output Current (Note 7) 5.5 5075mA V OHD 3.85V Min I CCMaximum Quiescent 5.54.080.040.0P AV IN V CC Supply Currentor GND74AC244 • 74ACT244AC Electrical Characteristics for ACNote 8: Voltage Range 3.3 is 3.3V r 0.3VVoltage Range 5.0 is 5.0V r 0.5VAC Electrical Characteristics for ACTNote 9: Voltage Range 5.0 is 5.0V r 0.5VCapacitanceSymbol ParameterV CCT A 25q C T A 55q C to 125q C T A 40q C to 85q CUnits(V)C L 50 pFC L 50 pF C L 50 pF (Note 8)Min Typ Max Min Max Min Max t PLH Propagation Delay 3.3 2.0 6.59.0 1.012.5 1.510.0ns Data to Output 5.0 1.5 5.07.0 1.09.5 1.07.5t PHL Propagation Delay 3.3 2.0 6.59.0 1.012.0 2.010.0ns Data to Output 5.0 1.5 5.07.0 1.09.0 1.07.5t PZH Output Enable Time 3.3 2.0 6.010.5 1.011.5 1.511.0ns 5.0 1.5 5.07.0 1.09.0 1.58.0t PZL Output Enable Time 3.3 2.57.510.0 1.013.0 2.011.0ns 5.0 1.5 5.58.0 1.010.5 1.58.5t PHZ Output Disable Time 3.3 3.07.010.0 1.012.5 1.510.5ns 5.0 2.5 6.59.0 1.010.5 1.09.5t PLZOutput Disable Time3.3 2.57.510.5 1.013.0 2.511.5ns 5.02.06.59.01.011.02.09.5Symbol ParameterV CCT A 25q C T A 55q C to 125q C T A 40q C to 85q CUnits(V)C L 50 pFC L 50 pF C L 50 pF (Note 9)Min Typ Max Min Max Min Max t PLH Propagation Delay 5.02.06.59.01.010.01.510.0ns Data to Output t PHL Propagation Delay 5.02.07.09.01.010.01.510.0nsData to Output t PZH Output Enable Time 5.0 1.5 6.08.5 1.09.5 1.09.5ns t PZL Output Enable Time 5.0 2.07.09.5 1.011.0 1.510.5ns t PHZ Output Disable Time 5.0 2.07.09.5 1.011.0 1.510.5ns t PLZOutput Disable Time5.02.57.510.01.011.52.010.5nsSymbol ParameterTyp Units ConditionsC IN Input Capacitance4.5pF V CC OPEN C PDPower Dissipation Capacitance45.0pFV CC 5.0V 674A C 244 • 74A C T 244Physical Dimensions inches (millimeters) unless otherwise noted20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" WidePackage Number M20B74AC244 • 74ACT244Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M20D 874A C 244 • 74A C T 244Physical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm WidePackage Number MSA2074AC244 • 74ACT244Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage Number MTC201074A C 244 • 74A C T 244 O c t a l B u f f e r /L i n e D r i v e r w i t h 3-S T A T E O u t p u t sPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" WidePackage Number N20AFairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。
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Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
74LCX652
元器件交易网
Functional Description
In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both.
Real-Time Transfer Bus B to Bus A
Real-Time Transfer Bus A to Bus B
OEAB OEBA CPAB CPBA SAB SBA
L
L
X
X XL
Transfer Storage Data to A or B
OEAB OEBA CPAB CPBA SAB SBA
Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW to HIGH transitions at the appropriate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state.
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial = LOW-to-HIGH Clock Transition
Note 2: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
元器件交易网
Logic Symbols
IEEE/IEC
74LCX652
Truth Table
(Note 2)
Inputs
Inputs/Outputs
Operating Mode
OEAB OEBA CPAB CPBA SAB SBA A0 thru A7
B0 thru B7
Ordering Code:
Order Number Package Number
Package Description
74LCX652WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74LCX652MSA
General Description
The LCX652 consists of bus transceiver circuits with Dtype flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to the HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function.
Value −0.5 to +7.0 −0.5 to +7.0 −0.5 to +7.0 −0.5 to VCC + 0.5
−50 −50 +50 ±50 ±100 ±100 −65 to +150
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LCX652MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
IIK
DC Input Diode Current
IOK
DC Output Diode Current
IO ICC IGND TSTG
DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature
The LCX652 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment.
The LCX652 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
Human body model > 2000V Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.
L
X
H or L
X
X Not Specified Input
Hold A, Store B
L
L
X
X Output
Input
Store B in Both Registers
L
L
X
X
X
L Output
Input
Real-Time B Data to A Bus
L
L
X
H or L X
H
Store B Data to A Bus
L L
H H
H or L
H or L
X X
X Input X
Input
Isolation Store A and B Data
X
H
H or L X
X Input
Not Specified Store A, Hold B
H
H
X
X Input
Output
Store A in Both Registers
H
H
X
X
LX
Storage
OEAB OEBA CPAB CPBA SAB SBA
H
L H or L H or L H H
OEAB OEBA CPAB CPBA SAB SBA
X
H
X XX
L
X
X
XX LHFra bibliotekXX3
74LCX652
元器件交易网
4
元器件交易网
74LCX652
Absolute Maximum Ratings(Note 3)
Symbol
Parameter
VCC
Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
H
H
X
X
L
X Input
Output
Real-Time A Data to B Bus
H
H
H or L
X
H
X
Stored A Data to B Bus
H
L
H or L H or L H
H Output