DAC8550中文资料

BurrĆBrown Products
from Texas
Instruments
FEATURES DESCRIPTION
APPLICATIONS
OUT
FB
DAC8550
SLAS476C–MARCH2006–REVISED MARCH2006 16-BIT,ULTRA-LOW GLITCH,VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
•Relative Accuracy:8LSB(Max)The DAC8550is a small,low-power,voltage output,
16-bit digital-to-analog converter(DAC).It is •Glitch Energy:0.1nV-s
monotonic,provides good linearity,and minimizes •Settling Time:10µs to±0.003%FSR
undesired code to code transient voltages.The •Power Supply:+2.7V to+5.5V DAC8550uses a versatile3-wire serial interface that •16-Bit Monotonic Over Temperature operates at clock rates of up to30MHz and is
compatible with standard SPI™,QSPI™,•Micro Power Operation:200µA at5V
Microwire™,and digital signal processor(DSP)•Rail-to-Rail Output Amplifier interfaces.
•Power-On Reset to Midscale
The DAC8550requires an external reference voltage •Power-Down Capability to set its output range.The DAC8550incorporates a •Schmitt-Triggered Digital Inputs power-on reset circuit that ensures that the DAC
output powers up at midscale and remain there until a •SYNC Interrupt Facility
valid write takes place to the device.The DAC8550•2's Complement Input and Reset to Midscale contains a power-down feature,accessed over the
•Operating Temperature Range:-40°C to105°C serial interface,that reduces the current consumption
of the device to200nA at5V.
•Available Packages:
–3mm×5mm MSOP-8The low-power consumption of this device in normal
operation makes it ideal for portable battery-operated
equipment.Power consumption is1mW at5V,
reducing to1µW in power-down mode.
•Process Control
The DAC8550is available in a MSOP-8package.•Data Acquisition Systems
•Closed-Loop Servo-Control Also see the DAC8551binary coded counterpart of •PC Peripherals the DAC8550.
•Portable Instrumentation
•Programmable Attenuation
FUNCTIONAL BLOCK DIAGRAM
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI,QSPI are trademarks of Motorola.
Microwire is a trademark of National Semiconductor.
PRODUCTION DATA information is current as of publication date.Copyright©2006,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas
Instruments standard warranty.Production processing does not
necessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS (1)
ELECTRICAL CHARACTERISTICS
DAC8550
SLAS476C–MARCH 2006–REVISED MARCH 2006
This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION
RELATIVE DIFFERENTIAL SPECIFICATION TRANSPORT PACKAGE PACKAGE PACKAGE ORDERING PRODUCT
ACCURACY
NONLINEARITY
TEMPERATURE
MEDIA,LEAD DESIGNATOR (1)
MARKING
NUMBER (LSB)
(LSB)
RANGE QUANTITY DAC8550IDGKT Tape and Reel,250DAC8550
±12
±1
MSOP-8
DGK
–40°C TO 105°C
D80
DAC8550IDGKR Tape and Reel,2500DAC8550IBDGKT Tape and Reel,250DAC8550B ±8±1MSOP-8DGK –40°C TO 105°C D80
DAC8550IBDGKR
Tape and Reel,2500
(1)
For the most current package and ordering information,see the Package Option Addendum at the end of this document or see the TI website at .
UNIT
Supply voltage,V DD to GND
–0.3V to 6V Digital input voltage range,V I to GND –0.3V to +V DD +0.3V Output voltage,V OUT to GND
–0.3V to +V DD +0.3V
Operating free-air temperature range,T A –40°C to 105°C Storage temperature range,T STG –65°C to 150°C
Junction temperature range,T J(max)150°C Power dissipation (DGK package)
(T J max –T A )/θJA
Thermal impedance,θJA 206°C/W Thermal impedance,θJC
44°C/W
(1)
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device.Exposure to absolute maximum conditions for extended periods may affect device reliability.
V DD =2.7V to 5.5V,–40°C to 105°C range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE (1)
Resolution
16
Bits Measured by line passing DAC8550±5±12LSB E L Relative accuracy through codes -32283and ±3±8LSB DAC8550B
32063
E D Differential nonlinearity 16-bit Monotonic
±0.25±1LSB E O Zero-code error ±2±12mV Measured by line passing through codes -32283E FS Full-scale error ±0.05±0.5%of FSR and 32063.
E G
Gain error
±0.02±0.2
%of FSR Zero-code error drift ±5µV/°C Gain temperature coefficient
±1ppm of FSR/°C PSRR Power supply rejection ratio R L =2k Ω,C L =200pF
0.75
mV/V OUTPUT CHARACTERISTICS (2)
V O
Output voltage range
V REF V
(1)Linearity calculated using a reduced code range of -32283to 32063;output unloaded.(2)Specified by design and characterization,not production tested.
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DAC8550 SLAS476C–MARCH2006–REVISED MARCH2006
ELECTRICAL CHARACTERISTICS(continued)
V DD=2.7V to5.5V,–40°C to105°C range(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
To±0.003%FSR,1200H to8D00H,R L=2kΩ,0810µs
pF<C L<200pF
t sd Output voltage settling time
R L=2kΩ,C L=500pF12µs
SR Slew rate 1.8V/µs
R L=∞470pF Capacitive load stability
R L=2kΩ1000pF
Code change glitch impulse1LSB change around major carry0.1
nV-s Digital feedthrough SCLK toggling,FSYNC high0.1
z o DC output impedance At mid-code input1Ω
V DD=5V50
I OS Short-circuit current mA
V DD=3V20
Coming out of power-down mode V DD=5V 2.5
t on Power-up timeµs
Coming out of power-down mode V DD=3V5
AC PERFORMANCE
Signal-to-noise ratio(1st1995
SNR
harmonics removed)
THD Total harmonic distortion85
BW=20kHz,V DD=5V,f OUT=1kHz dB
SFDR Spurious-free dynamic range87
SINAD Signal-to-noise and distortion84
REFERENCE INPUT
V ref Reference voltage0V DD V
V REF=V DD=5V5075µA
I I(ref)Reference current input range
V REF=V DD=3.6V3045µA
z I(ref)Reference input impedance125kΩLOGIC INPUTS(3)
Input current±1µA
V DD=5V0.8
V IL Low-level input voltage V
V DD=3V0.6
V DD=5V 2.4
V IH High-level input voltage V
V DD=3V 2.1
Pin capacitance3pF POWER REQUIREMENTS
V DD 2.7 5.5V
I DD(normal mode)Input code equals mid-scale,reference current
included,no load
V DD=3.6V to5.5V200250
V IH=V DD and V IL=GNDµA V DD=2.7V to3.6V180240
I DD(all power-down modes)
V DD=3.6V to5.5V V IH=V DD and V IL=GND0.22
µA V DD=2.7V to3.6V0.052
POWER EFFICIENCY
I OUT/I DD I LOAD=2mA,V DD=5V89%
TEMPERATURE RANGE
Specified performance–40105°C
(3)Specified by design and characterization,not production tested.
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PIN CONFIGURATION
V
DD
V
REF
V
FB
V
OUT
GND
D
IN
SCLK
SYNC 1
2
3
4
8
7
6
5
DAC8550
DAC8550
SLAS476C–MARCH2006–REVISED MARCH2006
MSOP-8
(Top View)
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1V DD Power supply input,2.7V to5.5V.
2V REF Reference voltage input.
3V FB Feedback connection for the output amplifier.
4V OUT Analog output voltage from DAC.The output amplifier has rail-to-rail operation.
Level-triggered control input(active LOW).This is the frame synchronization signal for the input data.When SYNC goes
LOW,it enables the input shift register and data is transferred in on the falling edges of the following clocks.The DAC is 5SYNC
updated following the24th clock(unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC acts
as an interrupt and the write sequence is ignored by the DAC8550).
6SCLK Serial clock input.Data can be transferred at rates up to30MHz.
7D IN Serial data input.Data is clocked into the24-bit input shift register on each falling edge of the serial clock input.
8GND Ground reference point for all circuitry on the part.
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TIMING REQUIREMENTS(1)(2)
SERIAL WRITE OPERATION SYNC
D
IN
DAC8550 SLAS476C–MARCH2006–REVISED MARCH2006
V
DD
=2.7V to5.5V,all specifications–40°C to105°C(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V DD=2.7V to3.6V20
t c(3)SCLK cycle time ns
V DD=3.6V to5.5V20
V DD=2.7V to3.6V13
t1SCLK HIGH time ns
V DD=3.6V to5.5V13
V DD=2.7V to3.6V22.5
t2SCLK LOW time ns
V DD=3.6V to5.5V13
V DD=2.7V to3.6V0
t su1SYNC to SCLK rising edge setup time ns
V DD=3.6V to5.5V0
V DD=2.7V to3.6V5
t su2Data setup time ns
V DD=3.6V to5.5V5
V DD=2.7V to3.6V 4.5
t h Data hold time ns
V DD=3.6V to5.5V 4.5
V DD=2.7V to3.6V0
t f SCLK falling edge to SYNC rising edge ns
V DD=3.6V to5.5V0
V DD=2.7V to3.6V50
t3Minimum SYNC HIGH time ns
V DD=3.6V to5.5V33
(1)All input signals are specified with t R=t F=3ns(10%to90%of V DD)and timed from a voltage level of(V IL+V IH)/2.
(2)See Serial Write Operation timing diagram.
(3)Maximum SCLK frequency is30MHz at V DD=3.6V to5.5V and20MHz at V DD=2.7V to3.6V.
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TYPICAL CHARACTERISTICS:V DD =5V
L E − (L S B )
Digital Input Code
D L
E − (L S B )
L E − (L S B )
8192
16384
24576
327684096049152
5734465536
Digital Input Code
D L
E − (L S B )
−6−4−20246L E − (L S B )
−1−0.500.510
8192
1638424576
32768
40960491525734465536
Digital Input Code
D L
E − (L S B )
−50
5
10
−40
40
80120
Temperature − 5C
E r r o r (m V )
120140160180200220240260280300
I DD − Supply Current − m A
f − F r e q u e n c y − H z
−10
−5
−40
40
80
120
Temperature − 5C
E r r o r (m V )
DAC8550
SLAS476C–MARCH 2006–REVISED MARCH 2006
At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
CODE CODE (-40°C)
(25°C)
Figure 1.
Figure 2.
LINEARITY ERROR AND
ZERO-SCALE ERROR
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
vs
CODE TEMPERATURE
(105°C)
Figure 3.
Figure 4.FULL-SCALE ERROR
I DD HISTOGRAM
vs
TEMPERATURE
Figure 5.Figure 6.
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I (SOURCE/SINK) − mA
01
23
456
− O u t p u t V o l t a g e − V
V O U T
Digital Input Code
D D I S u p p l y C u r r e n t − −A
µQ u i e s c e n t C u r r e
n t − A
µ050
100
150
200250
−40
−10
20
50
80
110
Temperature − 5C
D D I S u p p l y C u r r e n t − −A
µV DD − Supply Voltage − V
I
A
µV DD − Supply Voltage − V
D D
− S u p p l y C u r r e n t
−100
500
900
1300
1700
1
2
3
4
5
D D I S u p p l y C u r r e n t − −A
µV (LOGIC) − V
DAC8550
SLAS476C–MARCH 2006–REVISED MARCH 2006
TYPICAL CHARACTERISTICS:V DD =5V (continued)
At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.
SOURCE AND SINK CURRENT CAPABILITY
SUPPLY CURRENT
vs
DIGITAL INPUT CODE
Figure 7.
Figure 8.POWER-SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
TEMPERATURE
SUPPLY VOLTAGE
Figure 9.
Figure 10.
POWER-DOWN CURRENT
SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE
LOGIC INPUT VOLTAGE
Figure 11.Figure 12.
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Time (2 µs/div)
V DD = 5 V,
V REF = 4.096 V,From Code: FFFF T o Code: 0000
Zoomed Falling Edge 1 mV/div
Trigger Pulse 5 V/div
Falling Edge 1 V/div
Time (2 µs/div)
V DD = 5 V,
V REF = 4.096 V,From Code: 0000T o Code: FFFF
Zoomed Rising Edge 1 mV/div
Trigger Pulse 5 V/div
Rising Edge 1 V/div
Time (2 µs/div)
V DD = 5 V,
V REF = 4.096 V,From Code: 4000T o Code: CFFF
Zoomed Rising Edge 1 mV/div
Trigger Pulse 5 V/div
Rising Edge 1 V/div
Time (2 µs/div)
V DD = 5 V,
V REF = 4.096 V,From Code: CFFF T o Code: 4000
Zoomed Falling Edge 1 mV/div
Trigger Pulse 5 V/div
Falling Edge 1 V/div
V DD = 5 V,
V REF = 4.096 V From Code: 8000T o Code: 7FFF Glitch: 0.16 nV-s
Measured Worst Case
Time 400 ns/div
V O U T (500m V /d i v )
V DD = 5 V,
V REF = 4.096 V From Code: 7FFF T o Code: 8000Glitch: 0.08 nV-s
Time 400 ns/div
V O U T (500m V /d i v )
DAC8550
SLAS476C–MARCH 2006–REVISED MARCH 2006
TYPICAL CHARACTERISTICS:V DD =5V (continued)
At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.
FULL-SCALE SETTLING TIME:5-V RISING EDGE
FULL-SCALE SETTLING TIME:5-V FALLING EDGE
Figure 13.
Figure 14.
HALF-SCALE SETTLING TIME:5-V RISING EDGE
HALF-SCALE SETTLING TIME:5-V FALLING EDGE
Figure 15.
Figure 16.
GLITCH ENERGY:5-V,1-LSB STEP,RISING EDGE
GLITCH ENERGY:5-V,1-LSB STEP,FALLING EDGE
Figure 17.Figure 18.
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V DD = 5 V,
V REF = 4.096 V From Code: 8010T o Code: 8000Glitch: 0.08 nV-s
Time 400 ns/div
V O U T (500V /d i v )
m V DD = 5 V,
V REF = 4.096 V From Code: 8000T o Code: 8010Glitch: 0.04 nV-s
Time 400 ns/div
V O U T (500m V /d i v )
V DD = 5 V,V REF = 4.096 V From Code: 80FF T o Code: 8000
Glitch: Not Detected Theoretical Worst Case
Time 400 ns/div
V O U T (5 m V /d i v )
V DD = 5 V,
V REF = 4.096 V From Code: 8000T o Code: 80FF
Glitch: Not Detected Theoretical Worst Case
Time 400 ns/div
V O U T (5 m V /d i v )
84
86889092949698
S N R − S i g n a l -t o -N o i s e R a t i o − d B
f − Output Frequency − kHz
−100
−90−80−70−60−50−4001234
5T H D − T o t a l H a r m o n i c D i s t o r t i o n − d B
Output Tone − kHz
DAC8550
SLAS476C–MARCH 2006–REVISED MARCH 2006
TYPICAL CHARACTERISTICS:V DD =5V (continued)
At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.
GLITCH ENERGY:5-V,16-LSB STEP,RISING EDGE
GLITCH ENERGY:5-V,16-LSB STEP,FALLING EDGE
Figure 19.
Figure 20.
GLITCH ENERGY:5-V,256-LSB STEP,RISING EDGE
GLITCH ENERGY:5-V,256-LSB STEP,FALLING EDGE
Figure 21.
Figure 22.
TOTAL HARMONIC DISTORTION
SIGNAL-TO-NOISE RATIO
vs
vs
OUTPUT FREQUENCY
OUTPUT FREQUENCY
Figure 23.Figure 24.
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100150
200
250
300
350
100
100010000
100000
n V /
H z
− V o l t a g e N o i s e −V n f − Frequency − Hz
f − Frequency − Hz
G a i n − d B
DAC8550
SLAS476C–MARCH 2006–REVISED MARCH 2006
TYPICAL CHARACTERISTICS:V DD =5V (continued)
At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.
POWER SPECTRAL DENSITY
OUTPUT NOISE DENSITY
Figure 25.Figure 26.
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TYPICAL CHARACTERISTICS:V DD =2.7V
L E − (L S B )
Digital Input Code
D L
E − (L S B )
−6−4−20246L E − (L S B )
D L
E − (L S B )
Digital Input Code
L E − (L S B )
Digital Input Code
D L
E − (L S B )
5
10
Temperature − 5C
E r r o r (m V )
300
600
900
1200
1500
120140160180200220240260280300
I DD − Supply Current − m A
f − F r e q u e n c y − H z
−10
−5
05
Temperature − 5C
E r r o r (m V )
DAC8550
SLAS476C–MARCH 2006–REVISED MARCH 2006
At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs DIGITAL
DIFFERENTIAL LINEARITY ERROR vs DIGITAL
INPUT CODE INPUT CODE
(-40°C)
(25°C)
Figure 27.
Figure 28.
LINEARITY ERROR AND
ZERO-SCALE ERROR
DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT
vs
CODE TEMPERATURE
(105°C)
Figure 29.Figure 30.FULL-SCALE ERROR
I DD HISTOGRAM
vs
TEMPERATURE
Figure 31.Figure 32.
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I (SOURCE/SINK) − mA
− O u t p u t V o l t a g e − V
V O U T
Digital Input Code
D D I S u p p l y C u r r e n t − −A
µ
100
300
500
700
00.51 1.5
2 2.5
D D I S u p p l y C u r r e n t − −A
µV (LOGIC)
− V
Q u i e s c e n t C u r r e n t − A
µTemperature − 5C
Time (2 µs/div)
V DD = 2.7 V,V REF = 2.5 V,From Code: 0000T o Code: FFFF
Zoomed Rising Edge 1 mV/div
Trigger Pulse 2.7 V/div
Rising Edge 0.5 V/div
V DD = 2.7 V,V REF = 2.5 V,From Code: FFFF T o Code: 0000
Zoomed Falling Edge 1 mV/div
Trigger Pulse 2.7 V/div
Falling Edge 0.5 V/div
Time (2 µs/div)
DAC8550
SLAS476C–MARCH 2006–REVISED MARCH 2006
TYPICAL CHARACTERISTICS:V DD =2.7V (continued)
At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.
SOURCE AND SINK CURRENT CAPABILITY
SUPPLY CURRENT
vs
DIGITAL INPUT CODE
Figure 33.
Figure 34.
POWER-SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
TEMPERATURE
LOGIC INPUT VOLTAGE
Figure 35.
Figure 36.
FULL-SCALE SETTLING TIME:2.7-V RISING EDGE
FULL-SCALE SETTLING TIME:2.7-V FALLING EDGE
Figure 37.Figure 38.
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Trigger Pulse 2.7 V/div
Zoomed Rising Edge 1 mV / div
V DD = 2.7 V V REF = 2.5 V From code; 4000T o code: CFFF
Rising Edge 0.5 V/div
Time − 2 m s/div V DD = 2.7 V,V REF = 2.5 V,
From Code: CFFF T o Code: 4000
Zoomed Falling Edge 1 mV/div
Trigger Pulse 2.7 V/div
Falling Edge 0.5 V/div
Time (2 µs/div)
V DD = 2.7 V,V REF = 2.5 V
From Code: 7FFF T o Code: 8000Glitch: 0.08 nV-s
Time 400 ns/div V O U T (200 m V /d i v )
V DD = 2.7 V,V REF = 2.5 V From Code: 8000T o Code: 7FFF Glitch: 0.16 nV-s
Measured Worst Case
Time 400 ns/div
V O U T (200 m V /d i v )
V DD = 2.7 V,V REF = 2.5 V From Code: 8000T o Code: 8010Glitch: 0.04 nV-s
Time 400 ns/div
V O U T (200 u V /d i v )
V DD = 2.7 V,V REF = 2.5 V From Code: 8010T o Code: 8000Glitch: 0.12 nV-s
Time 400 ns/div
V /d i v )
V O U T (200 u V /d i v )
DAC8550
SLAS476C–MARCH 2006–REVISED MARCH 2006
TYPICAL CHARACTERISTICS:V DD =2.7V (continued)
At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.
HALF-SCALE SETTLING TIME:2.7-V RISING EDGE
HALF-SCALE SETTLING TIME:2.7-V FALLING EDGE
Figure 39.
Figure 40.
GLITCH ENERGY:2.7-V,1-LSB STEP,RISING EDGE
GLITCH ENERGY:2.7-V,1-LSB STEP,FALLING EDGE
Figure 41.
Figure 42.
GLITCH ENERGY:2.7-V,16-LSB STEP,RISING EDGE
GLITCH ENERGY:2.7-V,16-LSB STEP,FALLING EDGE
Figure 43.Figure 44.
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V DD = 2.7 V,V REF = 2.5 V
From Code: 80FF T o Code: 8000
Glitch: Not Detected Theoretical Worst Case
Time 400 ns/div
V O U T (5 m V /d i v )
AV DD = 2.7 V,V ref = 2.5 V
From Code: 8000T o Code: 80FF
Glitch: Not Detected Theoretical Worst Case
Time 400 ns/div
V O U T (5 m V /d i v )
DAC8550
SLAS476C–MARCH 2006–REVISED MARCH 2006
TYPICAL CHARACTERISTICS:V DD =2.7V (continued)
At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.
GLITCH ENERGY:2.7-V,256-LSB STEP,RISING EDGE
GLITCH ENERGY:2.7-V,256-LSB STEP,FALLING EDGE
Figure 45.Figure 46.
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THEORY OF OPERATION DAC SECTION
V OUT*V REF
2
)
V REF D
65536
(1)
To Output
Amplifier
RESISTOR STRING
SERIAL INTERFACE OUTPUT AMPLIFIER DAC8550
SLAS476C–MARCH2006–REVISED MARCH2006 The architecture consists of a string DAC followed by
an output buffer amplifier.Figure47shows the block
diagram of the DAC
Figure47.DAC8550Architecture
The input coding to the DAC8550is2's complement,
so the ideal output voltage is given by:
where D=decimal equivalent of the2's complement
code that is loaded to the DAC register;D ranges
from-32768to+32767where D=0is centered at
V REF/2.
Figure48.Resistor String
The resistor string section is shown in Figure48.It is
simply a string of resistors,each of The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
The DAC8550has a3-wire serial interface(SYNC, be fed into the output amplifier by closing one of the
SCLK,and D IN),which is compatible with SPI™, switches connecting the string to the amplifier.
QSPI™,and Microwire™interface standards,as well Monotonicity is ensured due to the string resistor
as most DSP interfaces.See the Serial Write architecture.
Operation timing diagram for an example of a typical
write sequence.
The write sequence begins by bringing the SYNC line The output buffer amplifier is capable of generating
LOW.Data from the D IN line is clocked into the24-bit rail-to-rail output voltages with a range of0V to V DD.
shift register on each falling edge of SCLK.The serial It is capable of driving a load of2Ωk in parallel with
clock frequency can be as high as30MHz,making 1000pF to GND.The source and sink capabilities of
the DAC8550compatible with high-speed DSPs.On the output amplifier can be seen in the typical curves.
the24th falling edge of the serial clock,the last data The slewrate is1.8V/µs with a full-scale setting time
bit is clocked in and the programmed function is of8µs with the output unloaded.
excuted(i.e.,a change in DAC register contents The inverting input of the output amplifier is brought and/or a change in the mode of operation).
out to the V FB pin.This allows for better accuracy in
At this point,the SYNC line may be kept LOW or critical applications by tying the V FB point and the
brought HIGH.In either case,it must be brought amplifier output together directly at the load.Other
HIGH for a minimum of33ns before the next write signal conditioning circuitry may also be connected
sequence so that a falling edge of SYNC can initiate between these points for specific applications.
the next write sequence.Since the SYNC buffer
draws more current when the SYNC signal is HIGH
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SYNC INTERRUPT
INPUT SHIFT REGISTER
POWER-ON
RESET
CLK D IN
Valid Write Sequence: Output Updates
on the 24th Falling Edge
24th Falling Edge
24th Falling Edge
DB23DB80DB23DB80
POWER-DOWN MODES
DAC8550
SLAS476C–MARCH 2006–REVISED MARCH 2006
than it does when it is LOW,SYNC should be idled LOW between write sequences for lowest power In a normal write sequence,the SYNC line is kept operation of the part.As mentioned above,it must be LOW for at least 24falling edges of SCLK and the brought HIGH again just before the next write DAC is updated on the 24th falling edge.However,if sequence.
SYNC is brought HIGH before the 24th falling edge,it acts as an interrupt to the write sequence.The shift register is reset and the write sequence is seen as invalid.Neither an update of the DAC register The input shift register is 24bits wide,as shown in contents nor a change in the operating mode occurs,Figure 49.The first six bits are don't care bits.The as shown in Figure 50.
bits (PD1andPD0)are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes).For a more complete description of the various modes see The DAC8550contains a power-on reset circuit that the Power-Down Modes section.The next 16bits are controls the output voltage during power-up.On the data bits.These are transferred to the DAC power-up,the output voltages are set to midscale;it register on the 24th falling edge of SCLK.
remains there until a valid write sequence is made to the DAC.This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up.
X
X
X
X
X
X
PD1
PD0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 49.DAC8550Data Input Register Format
Figure 50.SYNC Interrupt Facility
at 5V.However,for the three power-down modes,the supply current falls to 200nA at 5V (50nA at 3V).Not only does the supply current fall,but the The DAC8550supports four seperate modes of output stage is also internally switched from the operation.These modes are programmable by setting output of the amplifier to a resistor network of known two bits (PD1and PD0)in control register.Table 1values.The advantage with this is that the output shows how the state of the bits corresponds to the impedance of the device is known while in mode of operation of the device.
power-down mode.There are three different options.The output is connected internally to GND through a Table 1.Modes of Operation for the DAC8550
1-k Ωresistor,a 100-k Ωresistor,or it is left open-circuited (High-Z).The output stage is illustrated PD1PD0OPERATING MODE
(DB17)(DB16)in Figure 51.
00Normal operation All analog circuitry is shut down when the ----Power-down modes
power-down mode is activated.However,the 01Output typically 1k Ωto GND contents of the DAC register are unaffected when in power-down.The time to exit power-down is typically 10Output typically 100k Ωto GND 2.5µs for V DD =5V,and 5µs for V DD =3V.See the 1
1
High-Z
Typical Characteristics for more information.
When both bits are set to 0,the device works normally with a typical current consumption of 200µA
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DAC8550to Microwire Interface
OUT
FB
NOTE: (1)Additional pins omitted for clarity.
MICROPROCESSOR INTERFACING
DAC8550TO 8051Interface
DAC8550to 68HC11Interface
NOTE: (1)Additional pins omitted for clarity.
NOTE: (1)Additional pins omitted for clarity.
DAC8550
SLAS476C–MARCH 2006–REVISED MARCH 2006
Figure 53shows an interface between the DAC8550compatible device.Serial data is shifted out on the falling edge of the serial clock and is clocked into the DAC8550on the rising edge of the SK signal.
Figure 51.Output Stage During Power-Down
Figure 53.DAC8550to Microwire Interface See Figure 52for a serial interface between the Figure 54shows a serial interface between the a typical 8051-type microcontroller.and the 68HC11microcontroller.SCK of The setup for the interface is as follows:TXD of the the 68HC11drives the SCLK of the DAC8550,while 8051drives SCLK of the DAC8550,while RXD drives the MOSI output drives the serial data line of the the serial data line of the device.The SYNC signal is DAC.The SYNC signal is derived from a port line derived from a bit-programmable pin on the port of (PC7),similar to the 8051diagram.
the 8051.In this case,port line P3.3is used.When data is to be transmitted to the DAC8550,P3.3is taken LOW.The 8051transmits data in 8-bit bytes;thus only eight falling clock edges occur in the transmit cycle.To load data to the DAC,P3.3is left LOW after the first eight bits are transmitted,then a second write cycle is initiated to transmit the second byte of data.P3.3is taken HIGH following the completion of the third write cycle.The 8051outputs Figure 54.DAC8550to 68HC11Interface the serial data in a format which has the LSB first.The DAC8550requires its data with the MSB as the first bit received.The 8051transmit routine must The 68HC11should be configured so that its CPOL therefore take this into account,and mirror the data bit is 0and its CPHA bit is 1.This configuration as needed.
causes data appearing on the MOSI output to be valid on the falling edge of SCK.When data is being transmitted to the DAC,the SYNC line is held LOW (PC7).Serial data from the 68HC11is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle.(Data is transmitted MSB first.)In order to load data to the DAC8550,PC7is left LOW after the first eight bits are transferred,then a second and third serial write Figure 52.DAC8550to 80C51/80L51Interface
operation is performed to the DAC.PC7is taken HIGH at the end of this procedure.
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