MEMORY存储芯片MT41J256M16RE-107中文规格书
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PLLC Registers
7.3.11PLLC0Divider1Register(PLLDIV1)
The PLLC0divider1register(PLLDIV1)controls the divider for PLL0_SYSCLK1.PLLDIV1is shown in Figure7-12and described in Table7-14.
Figure7-12.PLLC0Divider1Register(PLLDIV1) 3116
Reserved
R-0
1514540 D1EN Reserved RATIO
R/W-1R-0R/W-0
LEGEND:R/W=Read/Write;R=Read only;-n=value after reset
Table7-14.PLLC0Divider1Register(PLLDIV1)Field Descriptions Bit Field Value Description
31-16Reserved0Reserved
15D1EN Divider1enable.
0Divider1is disabled.
1Divider1is enabled.
14-5Reserved0Reserved
4-0RATIO0-1Fh Divider ratio.Divider Value=RATIO+1.RATIO defaults to0(PLL divide by1).
7.3.12PLLC1Divider1Register(PLLDIV1)
The PLLC1divider1register(PLLDIV1)controls the divider for PLL1_SYSCLK1.PLLDIV1is shown in Figure7-13and described in Table7-15.
Figure7-13.PLLC1Divider1Register(PLLDIV1) 3116
Reserved
R-0
1514540 D1EN Reserved RATIO
R/W-0R-0R/W-0
LEGEND:R/W=Read/Write;R=Read only;-n=value after reset
Table7-15.PLLC1Divider1Register(PLLDIV1)Field Descriptions Bit Field Value Description
31-16Reserved0Reserved
15D1EN Divider1enable.
0Divider1is disabled.
1Divider1is enabled.
14-5Reserved0Reserved
4-0RATIO0-1Fh Divider ratio.Divider Value=RATIO+1.RATIO defaults to0(PLL divide by1).
PLLC Registers 7.3.26PLLC0Clock Align Control Register(ALNCTL)
The PLLC0clock align control register(ALNCTL)indicates which PLL0_SYSCLK n needs to be aligned for proper device operation.ALNCTL is shown in Figure7-27and described in Table7-29.
Figure7-27.PLLC0Clock Align Control Register(ALNCTL) 3116
Reserved
R-0
1576543210
Reserved ALN7ALN6ALN5ALN4ALN3ALN2ALN1
R-3h R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1 LEGEND:R/W=Read/Write;R=Read only;-n=value after reset
Table7-29.PLLC0Clock Align Control Register(ALNCTL)Field Descriptions Bit Field Value Description
31-7Reserved3h Reserved
6ALN7PLL0_SYSCLK7needs to be aligned to others selected in this register.
0No
1Yes
5ALN6PLL0_SYSCLK6needs to be aligned to others selected in this register.
0No
1Yes
4ALN5PLL0_SYSCLK5needs to be aligned to others selected in this register.
0No
1Yes
3ALN4PLL0_SYSCLK4needs to be aligned to others selected in this register.
0No
1Yes
2ALN3PLL0_SYSCLK3needs to be aligned to others selected in this register.
0No
1Yes
1ALN2PLL0_SYSCLK2needs to be aligned to others selected in this register.
0No
1Yes
0ALN1PLL0_SYSCLK1needs to be aligned to others selected in this register.
0No
1Yes