SAA4955HL资料

17 (24) 16 (23) 15 (22) IE internal 3 INPUT BUFFER (×3) SERIAL WRITE CONTROLLER write control write acknowledge load write block address
mini cache write control + cache transfer SERIAL WRITE REGISTER 20-WORD (×13) 20 × (12 + 1) PARALLEL WRITE REGISTER 20-WORD (×13) 20 × (12 + 1)
2001பைடு நூலகம்Jul 09
2
Philips Semiconductors
Product specification
2.9-Mbit field memory
BLOCK DIAGRAM
SAA4955
handbook, full pagewidth
D0 to D11 12
IE
WE
RSTW
SWCK
18 (25) 14 to 3 (21 to 18, 16 to 9) DATA INPUT AND WRITE MASK BUFFER (×13) IE internal D0 internal 19 (26) 20 (27) 21 (28) 22 (29) 12 + 1
SAA4955
The maximum storage depth is 245772 words × 12 bits. A FIFO operation with full word continuous read and write could be used as a data delay, for example. A FIFO operation with asynchronous read and write could be used as a data rate multiplier. Here the data is written once, then read as many times as required without being overwritten by new data. In addition to the FIFO operations, a random block access mode is accessible during the pointer reset operation. When this mode is enabled, reading and/or writing may begin at, or proceed from, the start address of any of the 6144 blocks. Each block is 40 words in length. Two or more SAA4955s can be cascaded to provide greater storage depth or a longer delay, without the need for additional circuitry. The SAA4955 contains separate 12-bit wide serial ports for reading and writing. The ports are controlled and clocked separately, so asynchronous read and write operations are supported. Independent read and write clock rates are possible. Addressing is controlled by read and write address pointers. Before a controlled write operation can begin, the write pointer must be set to zero or to the beginning of a valid address block. Likewise, the read pointer must be set to zero or to the beginning of a valid address block before a controlled read operation can begin.
RE Q0 to Q11 OE
SRCK RSTR
The pin numbers in parenthesis refer to the SAA4955HL. Pins VDD(P) should be connected to the supply voltage of the driving circuit that generates the input voltages. This could be, for instance, 5.5 V instead of 3.3 V. Pins VDD and VDD(O) require a 3.3 V supply.
INTEGRATED CIRCUITS
DATA SHEET
SAA4955 2.9-Mbit field memory
Product specification Supersedes data of 1999 Apr 29 File under Integrated Circuits, IC02 2001 Jul 09
Fig.1 Block diagram.
2001 Jul 09
3
Philips Semiconductors
Product specification
2.9-Mbit field memory
PINNING PIN SYMBOL SAA4955HL GNDP GND D11 D10 D9 D8 D7 D6 D5 D4 n.c. D3 D2 D1 D0 SWCK RSTW WE IE VDD VDD(P) VDD(P) VDD(O) OE RE RSTR SRCK Q0 Q1 Q2 n.c. Q3 n.c. Q4 n.c. Q5 Q6 2001 Jul 09 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 SAA4955TJ 1 2 3 4 5 6 7 8 9 10 − 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 − 30 − 31 − 32 33 ground ground digital input digital input digital input digital input digital input digital input digital input digital input − digital input digital input digital input digital input digital input digital input digital input digital input supply supply supply supply digital input digital input digital input digital input digital output digital output digital output − digital output − digital output − digital output digital output ground for protection circuits general purpose ground data input 11 data input 10 data input 9 data input 8 data input 7 data input 6 data input 5 data input 4 not connected data input 3 data input 2 data input 1 data input 0 serial write clock write reset clock write enable input enable I/O DESCRIPTION
Philips Semiconductors
Product specification
2.9-Mbit field memory
FEATURES • 2949264-bit field memory • 245772 × 12-bit organization • 3.3 V power supply • Inputs fully TTL compatible when using an extra 5 V power supply • High speed read and write operations • FIFO operations: – full word continuous read and write – independent read and write pointers (asynchronous read and write access) – resettable read and write pointers • Optional random access by block function (40 words per block) enabled during pointer reset operation • Quasi static (internal self-refresh and clocking pauses of infinite length) • Write mask function • Cascade operation possible • 16 Mbit CMOS DRAM process technology. GENERAL DESCRIPTION The SAA4955 is a 2949264-bit field memory designed for advanced TV applications such as 100/120 Hz TV, PALplus, PIP and 3D comb filter. QUICK REFERENCE DATA SYMBOL Tcy(SWCK) Tcy(SRCK) tACC VDD, VDD(O) VDD(P) IDD(tot) PARAMETER WRITE cycle time (SWCK) READ cycle time (SRCK) READ access time after SRCK supply voltage supply voltage total supply current (IDD(tot) = IDD + IDD(O) + IDD(P)) minimum read/write cycle; outputs open CONDITIONS see Fig.4 see Fig.11 see Fig.11 MIN. 26 26 − 3.0 3.0 − TYP. − − − 3.3 3.3 22
20 × 12
SAA4955TJ (SAA4955HL)
PARALLEL READ REGISTER 20-WORD (×12) 20 × 12 SERIAL READ REGISTER 20-WORD (×12) mini cache read control OE internal INPUT BUFFER (×4) 3 SERIAL READ CONTROLLER read control read acknowledge
MAX. − − 21 3.6 5.5 70
UNIT ns ns ns V V mA
ORDERING INFORMATION TYPE NUMBER SAA4955HL SAA4955TJ PACKAGE NAME LQFP44 SOJ40 DESCRIPTION plastic low profile quad flat package; 44 leads; body 10 × 10 × 1.4 mm plastic small outline package; 40 leads (J-bent); body width 10.16 mm VERSION SOT389-1 SOT449-1
+3.3 V VDD VDD(P) VDD(P) VDD(O)
CLOCK OSCILLATOR refresh clock D0 internal IE internal
WRITE MINI CACHE 12-WORD (×12) 100 nF 12 cache transfer MEMORY ARRAY 245760-WORD (×12)
WRITE ADDRESS COUNTER MEMORY ARBITRATION REFRESH ADDRESS COUNTER LOGIC READ ADDRESS COUNTER
READ MINI CACHE 12-WORD (×12)
GNDP GND GNDO GNDP
1 (7) 2 (8) 39 (5) 40 (6) 12
OE internal
12 DATA MUX DATA OUTPUT BUFFER (×12)
load read block address
(34 to 36, 38, 40, 42 to 44, 1 to 4) 27 to 38 12
(30) (31) (32) (33) 23 24 25 26
MHB914