A Quantitative Analysis of Instruction Prefetching

The sequential prefetch schemes are limited to the prefetching of sequential blocks and, therefore, has a performance problem caused by taken branches. To rectify this problem, Kim et al. proposed a scheme called threaded prefetching 8]. In this scheme, each instruction block has an instruction block pointer called thread. The thread indicates the instruction block to be prefetched when the block containing it is accessed by the processor. The thread is dynamically updated during program execution so that it indicates the instruction block that is most likely to be accessed next. In this scheme, the thread of a block is made to point to the block that was previously accessed after the present block because such a block is most likely to be accessed next by the principles of locality. In 7], an clairvoyant instruction prefetch scheme was described to study the intrinsic limitation of prefetching such as upper bounds on prefetch accuracy. The clairvoyant prefetch scheme is based on a post-mortem analysis of program execution. In the scheme, the instruction reference behavior of a block is rst encoded by what is called a reference pattern. In the reference pattern, each instruction block is represented by a letter. For example, the rst distinct instruction block in the pattern is represented by a and the second distinct instruction block is represented by b and so on. As a result, various reference patterns such as a{a{a..., a{b{a..., a{b{b..., a{b{c..., etc. will be generated according to the reference behavior of each instruction block during program execution. Then, based on these reference patterns, a table is constructed that lists, for each possible pre x of reference patterns, the frequencies of letters that appear after the pre x. For example, there are three possible reference patterns of length 3 that have a{b as their pre x: a{b{a, a{b{b, and a{b{c. If we assume that a{b{a, a{b{b, and a{b{c appeared once, twice, and once, respectively, in the reference patterns, the table has an entry for pre x a{b that has frequencies of 1, 2 and 1 for a, b, and c respectively. The clairvoyant prefetch scheme uses this table to make the prefetch decision in the direction with the highest frequency for each possible pre x of reference patterns. Also, to prefetch the instruction block corresponding to a letter in a reference pattern, the clairvoyant prefetch scheme should have address information associated with each letter. For this purpose, the scheme maintains, for each instruction block, address information for each letter in its reference pattern. To quantitatively analyze the performance of the above three instruction prefetch schemes, we performed simulations based on traces that re ect the multi-programming environment and operating system execution behavior. Traces we used are the SPEC SDM(Software Development Multitasking) benchmark traces gathered at BYU. The computer system used for generating the traces was a 20 MHz Intel 486 DX with 16M main memory. The operat-
2 Prefetching Strategies
Recent advances in electronic technology have drastically reduced processor cycle times. In DRAM technology, however, the cycle time improvement has been slow although density growth has been tremendous. As a result, the processor-memory cycle time disparity increases. One of possible approaches to bridging the disparity is to use prefetching. Prefetching aims at reducing the gap between the processor and memory cycle times by fetching, in advance, instruction and data that are likely to be requested by the processor in the near future. To improve the overall system performance through prefetching, accurate prefetch prediction and su cient prefetch time is required. In particular, prefetching gives rise to prefetch overhead if the prefetch prediction is not correct. Most previous studies on prefetching were limited to proposing a particular prefetch scheme and presenting its performance improvement, largely ignoring its negative aspects. However, prefetching can have adverse e ects on the overall performance because of inaccurate prefetch prediction. A signi cant portion of the prefetch overheads is due to memory contention between demand and prefetch requests. In this paper, we examine quantitatively the e ects of instruction prefetching for a range of conventional bus/memory system con gurations. This allows us to accurately show the cross-