DP1Users_Manual_cs
NVIDIA DOCA DPA执行单元管理工具用户指南说明书
NVIDIA DOCA DPA Execution Unit Management ToolUser GuideTable of ContentsChapter 1. Introduction (1)Chapter 2. Execution Unit Objects (3)Chapter 3. dpaeumgmt Commands (4)3.1. General Commands (4)3.2. Execution Unit Group Commands (4)3.2.1. EU Group Command Flags and Arguments (4)3.2.2. Info EU Group (5)3.2.3. Create EU Group (5)3.2.4. Destroy EU Group (6)3.2.5. Query EU Group (6)3.2.6. Apply EU Group (6)3.3. EU Partition Commands (7)3.3.1. EU Partition Command Flags and Arguments (7)3.3.2. Info EU Partition (7)3.3.3. Create EU Partition (8)3.3.4. Destroy EU Partition (8)3.3.5. Query EU Partition (8)Chapter 4. vHCAs and Partitions (9)Chapter 5. Known Limitations (10)Chapter 1.IntroductionThis table introduces important terms for understanding this document:The DPA EU management tool can run either on the host machine or on the target DPU and allows users to manage the DPA's EUs which are the basic resource of the DPA. TheIntroductiontool enables the resource control of EUs to optimize computation resources usage of the DPA before using DOCA FlexIO SDK API.Without EU allocation, a DPA software thread would lack access to the hardware pipeline/CPU time resource, and consequently not be able to execute. dpaeumgmt serves the following main usages:‣Running a DPA software thread with strict affinity on a DPA EU (i.e., running a DPA thread using only the specific preselected EU). For this purpose, dpaeumgmt provides an option to query the maximum EU ID allowed to use.‣Allowing a DPA software thread to run over a DPA EU from a group of EUs:‣Once a EU group is created, it is allocated a subset of EUs.‣dpaeumgmt provides an ID to the created group which can be used to run DPA applications with group affinity where the affinity ID would be the same as thatgroup's ID.‣EU partition management - the ability to manage EU partitions.When the software stack wishes to run a DPA thread with group affinity type, one of the available EUs from the group's collection is used for the execution.Note: A DPA thread may execute if and only if there is an available EU for it.Chapter 2.Execution Unit ObjectsUpon boot, a default EU partition is automatically created. The default EU partition possesses all the system's EUs. The DPA partition manager function is the only function that belongs to it and can therefore control the entire resources of the system.When running a DPA thread with none affinity, the EU chosen for the DPA thread to run with comes from the partition's pool of EUs. Namely, from the EUs belonging only to the DPA device's current partition which were not assigned to any EU groups (on the current partition). If the aforementioned group of EUs (i.e., the partition's default EU group) is empty, the DPA thread would fail to run with none affinity.Chapter 3.dpaeumgmt Commandsdpaeumgmt enables users to create, destroy, and query EU objects.Note: dpaeumgmt tool must run with root privileges and users must execute sudo mststart before using it.Top-level dpaeumgmt command syntax:Usage: dpaeumgmt {help|version|eu_group|partition}Type "./dpaeumgmt help"for detailed help3.1. General Commands‣Print basic usage information for the tool:dpaeumgmt -h‣Print a detailed help menu of the tool's commands:dpaeumgmt help‣Print version information:dpaeumgmt version3.2. Execution Unit Group Commands The commands listed in the following subsections are used to configure EU groups. 3.2.1. EU Group Command Flags and ArgumentsThe following table lists the flags relevant for eu_group commands. Arguments for the flags must be used within quotes (if more than one) and without extra spaces.3.2.2. Info EU GroupPrint information on the relevant DPA resources for the EU groups:dpaeumgmt eu_group info --dpa_device <device>Example:$ sudo ./dpaeumgmt eu_group info -d mlx5_0Max number of DPA EU groups: 15Max number of DPA EUs in one DPA EU group: 190Max DPA EU number available to use: 190Max EU group name length is 15 chars3.2.3. Create EU GroupCreate an EU group with the specified name on the provided device's partition. The EUs indicated by the range are taken from the DPA device's EU partition.dpaeumgmt eu_group create --dpa_device <device> --name_group <name> --range_eus<range>Example:$ sudo ./dpaeumgmt eu_group create -d mlx5_0 -n "HG hello world1" -r "6-8,16,55,70" Group created successfully-EU group ID: 1EU group name: HG hello worldMember EUs are: 6,7,8,16,55,70Note: After successfully creating an EU group, users can run a DPA thread using groupaffinity with the affinity type set to the group's ID.3.2.4. Destroy EU GroupDestroy a EU group that exists on the device's partition with either the provided group name or ID.dpaeumgmt eu_group destroy --dpa_device <device> [--name_group <name> | --id_group <id>]Example:$ sudo ./dpaeumgmt eu_group destroy -d mlx5_0 -g 1Group with group id: 1, was destroyed successfully3.2.5. Query EU GroupQuery EU groups residing on the provided device's partition. If one of the optional parameters is used, the command only queries the specific group and prints it if it exists: dpaeumgmt eu_group query --dpa_device <device> [--name_group <name> | --id_group<id>]Example:$ sudo ./dpaeumgmt eu_group query -d mlx5_01) EU group ID: 1EU group name: HG hello worldMember EUs are: 6,7,8,16,55,70In total there are 1 EU groups configured.More options:$ sudo ./dpaeumgmt eu_group query -d mlx5_0 -n "HG hello world"$ sudo ./dpaeumgmt eu_group query -d mlx5_0 -g 13.2.6. Apply EU GroupApply the EU groups provided in the file on the device's partition:dpaeumgmt eu_group apply --dpa_device <device> --file_groups <file>File format example:{"eu_groups": [{ "name": "hg1", "range": "178-180"},{ "name": "hg2", "range": "2-10"}]}Note: The command removes all the previous EU groups defined on the EU partition thatthe DPA device belongs to and applies the ones from the file.Example:$ sudo ./dpaeumgmt eu_group apply -d mlx5_0 --file_groups example.json1) EU group ID: 1EU group name: hg1Member EUs are: 178,179,1801) EU group ID: 2EU group name: hg2Member EUs are: 2,3,4,5,6,7,8,9,10In total there are 2 EU groups configured.3.3. EU Partition CommandsThe commands listed in the following subsections are used to configure EU partitions.3.3.1. EU Partition Command Flags andArgumentsThe following table lists the flags relevant for EU partition commands. Arguments for the flags must be used within quotes (if more than one) and without extra spaces.3.3.2. Info EU PartitionPrint the relevant DPA resources of the EU partitions:dpaeumgmt partition info --dpa_device <device>Example:$ sudo ./dpaeumgmt partition info -d mlx5_0Max number of DPA EU partitions: 15Max number of VHCAs associated with a single partition: 32Max number of DPA EU groups: 15Note- an allocation of a partition consumes from the number of DPA EU *groups*available to createMax DPA EU number available to use: 1903.3.3. Create EU PartitionCreate an EU partition on the DPA device:dpaeumgmt partition create --dpa_device <device> --vhca_list <id_list> --range_eus <range> --max_num_eu_group <max_num>Example:$ sudo ./dpaeumgmt partition create -d mlx5_0 -v 1 -r 10-20 -m 2Partition created successfully-EU Partition ID: 1Maximal number of groups: 2The partition has a total of 1 associated VHCA IDs, namely: 1Partition's member EUs are: 10,11,12,13,14,15,16,17,18,19,203.3.4. Destroy EU PartitionDestroy an EU partition that exists on the device's partition:dpaeumgmt partition destroy --dpa_device <device> --id_partition <id> Example:$ sudo ./dpaeumgmt partition destroy -d mlx5_0 -p 1Partition with partition id: 1, was destroyed successfully3.3.5. Query EU PartitionQuery EU partitions that reside on the provided device's partition and print out the partition if it exists:dpaeumgmt partition query --dpa_device <device> [--id_partition <id>] Example:$ sudo ./dpaeumgmt partition query -d mlx5_0 -p 1EU Partition ID: 1Maximal number of groups: 2The partition has a total of 1 associated VHCA IDs, namely: 1Partition's member EUs are: 10,11,12,13,14,15,16,17,18,19,20More options:$ sudo ./dpaeumgmt partition query -d mlx5_0Chapter 4.vHCAs and PartitionsThe following diagram illustrates the ownership and control of a partition by a vHCA and also which vHCAs have claim to (i.e., can use) a partition.Chapter 5.Known Limitations‣Currently, dpaeumgmt is only supported on the DPU not the host‣dpaeumgmt should run before creating a DPA process so all resources are configured ahead of time‣Running the tool over a device with an existing DPA process results in failure‣The EU group name assigned by the user must be unique for every EU group on a specific partition or the EU group create command fails‣The creation of an EU partition consumes from the number of EU groups allowed on the vHCA's partition it is created on:‣ 1 group for the partition itself due to a default group created for each partition ‣<max_num> of groups which is the user's input provided upon partition creation ‣Creating groups or running DPA threads in general (with any affinity) on interfaces other than ECPF, requires a configuration of a valid partition for the specific vHCA ‣Only the default partition is exposed to the real EU numbers, all other partitions the user creates use virtual EUs‣For example, if a user creates a partition with the range of EUs 20-40, querying the partition info from one of its virtual HCAs (vHCAs) would display EUs from0-20. Therefore, the EU whose real number is 39 in this example would correspond to the virtual EU number 19.‣Group IDs on a non-default partition are virtual.‣Different partitions can have completely distinct groups, even if they have the same ID.‣The affinity ID parameter, specified on the FlexIO API, can distinguish between the groups according to the vHCA and application it is running on.‣vHCA ID overlap is not allowed on EU partitions‣It is not possible to query vHCA IDs with dpaeumgmt, these are assumed to be known by the user beforehand‣Partition destruction fails if there are EU objects that exist on that partition‣It is not possible to know which EU has been chosen to run on‣Every vHCA sees the partition it belongs to, and its resources, as the entire world. It only sees:Known Limitations‣Groups and partitions it created‣The number of EUs it was given‣The max_num_eu_group of the partition it belongs to‣No guarantee regarding EU group ID that will be given on group creation‣The default groups (of every partition) cannot be managed by the user‣The EU numbers available are between 0 and the max DPA EU number available to use minus 1 (the upper limit can be queried using the info command specified above)‣dpaeumgmt does not support virtual functions (VFs)‣It is not possible to create partitions on other vHCAs other than the DPA partition manager function‣There are at most 16 hardware EU group entitiesNoticeThis document is provided for information purposes only and shall not be regarded as a warranty of a certain functionality, condition, or quality of a product. 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Use of such information may require a license from a third party under the patents or other intellectual property rights of the third party, or a license from NVIDIA under the patents or other intellectual property rights of NVIDIA.Reproduction of information in this document is permissible only if approved in advance by NVIDIA in writing, reproduced without alteration and in full compliance with all applicable export laws and regulations, and accompanied by all associated conditions, limitations, and notices.THIS DOCUMENT AND ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS, AND OTHER DOCUMENTS (TOGETHER AND SEPARATELY, “MATERIALS”) ARE BEING PROVIDED “AS IS.” NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY, OR OTHERWISE WITH RESPECT TO THE MATERIALS, AND EXPRESSLY DISCLAIMS ALL IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE. 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Other company and product names may be trademarks of the respective companies with which they are associated.Copyright© 2023 NVIDIA Corporation & affiliates. All rights reserved.NVIDIA Corporation | 2788 San Tomas Expressway, Santa Clara, CA 95051。
DP安装手册
HP Data Protector 安装和使用手册目录1安装 Data Protector (2)2 DP软件图形界面中各部分的说明 (3)2.1 添加磁带库 (3)2.2 Clients模块 (3)2.3 Users模块 (5)2.4 Devices & Media模块 (6)2.5 Backup模块 (8)2.5.1 文件系统备份 (8)2.5.2 oracle的备份 (11)3 备份策略的几点说明： (13)1安装 Data Protector插入Windows 安装DVD-ROM，然后运行\i386\setup.exe 启动此向导。
5. 选择Cell Manager，然后按照此向导完成各个步骤（在各个步骤中都使用默认值）。
6. 在帐户信息(Account information) 窗口中，输入您在步骤3 中创建的用户帐户的用户名和密码2DP软件图形界面中各部分的说明2.1 添加磁带库点击“add Device ”NEXT直到添加完成2.2 Clients模块本章节将介绍DP图形界面中各部分的功能，在安装配置过程中也是按照加Clients →加Users →建Media Pool、Devices →定制Backup脚本的顺序来操作的。
DP软件安装后，Cell Manager将自动成为Clients的一员，缺省将安装Disk Agent，Media Agent和User Interface，同时它也将作为一个Installation Server。
添加Client缺省采用的是远程安装的方式，只要在Client上按右键→Add Clients →写入主机名或IP地址，就将看到下图，选择要安装的Components，系统将自动传安装文件到远程主机，并自动安装。
当然也可以采用手工安装，即在Client上手工安装Agent再从Cell Manager中import进来。
2.3 Users模块DP缺省有三种组模式：admin，operator，user，每个组的权限如下示意图。
浪潮Cinder主机插件用户手册说明书
浪潮存储平台主机插件用户手册文档版本发布日期适用版本尊敬的用户：衷心感谢您选用浪潮存储！浪潮存储秉承“云存智用运筹新数据”的新存储之道，致力于为您提供符合新数据时代需求的存储产品和解决方案。
本手册用于帮助您更详细地了解和便捷地使用本存储，涉及的截图仅为示例，最终界面请以实际设备显示的界面为准。
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1.请不要自行拆卸本存储的机箱及机箱内任何硬件设备。
在本存储出现任何硬件故障或您希望对硬件进行任何升级时，请您将机器的详细硬件配置反映给我们的客户服务中心。
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本存储的内存、CPU、CPU散热片、风扇、硬盘托架、硬盘等都是特殊规格的。
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Fujitsu STYLISTIC Q7311 商品说明书
Data SheetFujitsu STYLISTIC Q7311Tablet Mobility Meets Notebook ProductivityThe FUJITSU Tablet STYLISTIC Q7311 is a highly durable and secure 2-in-1 detachable that meets the demands of today’s mobile professionals. Its 33.8 cm (13.3-inch) FHD anti-glare display comes with pen and touch support. The latest 11th generation Intel® Core™ i7 vPro® processor technology and Intel® Thunderbolt™ 4 ensure excellent performance, even when you’re on the go.Combined tablet mobility and notebook productivity in one device - whereever you areThe robust IP42 compliant housing with reinforced corners and port caps protects your device from damages, even outside the office.Highly durable IP42 compliant housing with reinforced cornersPort caps that protect the interfaces like the new Intel® Thunderbolt™ 4 from water spills Optional backlit keyboard dock with LAN and charging port Optional TPU cover for more robustness Always connected and instantly readyConvenience at workSign documents legally secure. The pen is automatically charged within seconds when stored in its pen garage, that protects it also from being lost. Ready whenever you need it. 33.8 cm (13.3-inch) Full HD anti-glare touch display Supporting pen with 4K pressure levelsPen garage with inductive charging functionLean, agile and secureMore freedom to work safely from anywhere at anytime without compromises in security and data protection – integrated IR Cam with Windows Hello support, fingerprint sensor and Smartcard reader protect your device like a mansion.Weight starting at 800 grams, the device offers you ultimate portability Fingerprint sensor & IR Camera supporting Windows Hello Smartcard readerKensington lock supportUp to 10 hours battery runtimeIntel® Iris® Xe GraphicsComponentsBase unit STYLISTIC Q7311Operating systemsOperating system pre-installed Windows 11 Pro. Fujitsu recommends Windows 11 Pro for business.Windows 11 HomeWindows 10 Pro. Fujitsu recommends Windows 11 Pro for business.Operating system compatible FREE Upgrade to Windows 11**Upgrade timing may vary by device. Features and app availability may vary by region. Certain features requirespecific hardware (see aka.ms/windows11-spec).Operating system notes Internet connectivityWindows 10 Support: After the end of the product life Fujitsu will continue to test and support all upcoming Window10 releases for a period of maximum 5 years – depending on the available extension of hardware services throughFujitsu Warranty top ups. For details please see “Fujitsu Service Statement for Windows 10 Semi-Annual-ChannelSupport” at .Processor Intel® Core™ i7-1185G7 processor (4 Cores / 8 Threads)Intel® Core™ i5-1145G7 processor (4 Cores / 8 Threads)Intel® Core™ i5-1135G7 processor (4 Cores / 8 Threads) ** Processor only for retail, SMB, education and governmentHard disk drives (internal)SSD PCIe, SSD 512GB Value PCIe G3 M.2 FDE, SEDSSD PCIe, SSD 512GB MS PCIe G3 M.2 FDE, SEDSSD PCIe, SSD 256GB Value PCIe G3 M.2 FDE, SEDSSD PCIe, SSD 1TB Value PCIe G3 M.2 FDE, SEDSSD PCIe, SSD 1TB MS PCIe G3 M.2 FDE, SEDHard disk notes One Gigabyte equals one billion bytes, when referring to hard disk drive capacity.Accessible capacity may vary, also depending on used software.Up to 20 GB of HDD space is reserved for system recoveryInterface add on cards/components(optional)4G/ LTE (optional)(Downlink speed up to 300 Mbit/s, Uplink speed up to 150 Mbit/s)Display33.8 cm (13.3-inch), IPS, FHD, 1,920 x 1,080 pixel, Anti-glare touchscreen, 400 cd/m², 1500:1MultimediaCamera Front: HD Cam (0.9MP) with LEDFront: IR Cam (0.9MP) supporting Windows Hello with LEDRear: 5M with LEDBase unitBase unit STYLISTIC Q7311General system informationChipset Integrated in CPUSupported capacity RAM (min.)8 GBSupported capacity RAM (max.)16 GBMemory notes8 GB onboard or 16 GB onboardDual channel supportLPDDR4x (4,266 MHz)LAN notes Virtual MAC address. LAN connector via optional keyboard docking, cradle or optional USB to LAN adapter. Integrated WLAN Intel WiFi 6 AX201 - WLAN, BT, SRD cat. 1General system informationBIOS version UEFI Specification 2.7BIOS features InsydeH2O BIOSAudio type On boardAudio codec Realtek ALC255Audio features2x digital array microphones, 2x built-in speakers (stereo)Waterproof / Spillproof IP42Disinfectable noMIL-STD tested Yes, selected MIL-STD-810H tests passed.MIL-STD-810H test results are not a guarantee of future performance under identified test conditions.Accidental damage is not covered under standard international limited warranty.DisplayDiagonal Size33.8 cm (13.3-inch)Display Technology IPSDisplay type Anti-glare touchscreenDisplay Resolution type FHDBrightness - typical400 cd/m²Contrast - typical1500:1Viewing angle (h/v) - typical178°/178°Display notes Wide-view high-bright LED display (for enhanced outdoor viewing)Integrated ambient light sensor for automatic backlight adjustment to the working environment.Toughened glassSensors Ambient Light SensorCompassGyroscopeProximityDigitizer / Touch Technology Wacom Digitizer for pen (AES) input plus capacitive 10 finger multi-touch screenPen AES4k pressure levelPen garageinductive chargingAmbient light sensor IntegratedAmbient light sensor notes While enabled, the ambient light sensor automatically adjusts the display backlightGraphicsBase unit STYLISTIC Q7311TFT resolution (HDMI)up to 4,096 x 2,160 @ 60 HzGraphics brand name Intel® Iris® Xe Graphics (with Dual channel memory)Graphics features 4 Display Support (3 external, 1 internal)HDCP supportDirectX® 12OpenGL® 4.5Graphics notes Shared memory depending on main memory size and operating system3D acceleratorInterfacesDC-in1Audio: line-out / headphone 1 (combo port with Audio line-in)Audio: line-in / microphone 1 (combo port with Audio line-out)Internal microphones2x digital array microphonesUSB 2.0 total1USB 3.2 Gen1 (5 Gbps) total 1 x Type-AUSB 4.0 Gen3 (20 Gbps) total 1 x Type-C Intel® Thunderbolt™ 4 (with Power Delivery functionality)USB Type-C 1 USB 4 Gen3 Thunderbolt™4, Power Delivery (15W)HDMI 1 v1.4Ethernet (RJ-45)-Memory card slots 1 (USH-I) SD 3.0 StandardSD/microSD card: 2GBSDHC/microSDHC card: 32GBSDXC/microSDXC card: 2TBSmartCard slot optionalSIM card slot 1 (Nano-SIM, only for models with integrated 4G/LTE module)Interface Module notes LAN and VGA available via conversion cable.Docking connector for Port Replicator 1 (Cradle)Kensington Lock support1Port Replicator interfaces (optional)USB Type-C PR CradleDC-in 1 (19V/90W required) 1 (19V)Power on switch1---Audio: line-in---1Audio: line-in / line-out1---Audio: line-out---1Audio: comments Combo jack for headset usage---USB 3.2 Gen1 (5 Gbps) total---3DisplayPort1x V1.2 1VGA1x1HDMI text1x------Interface Notes3x Type-A - 5V/0.9A, 4.5W1x Type-C - 15W1x Type-C - Up to 60 W (PD v2.0-1.1) power output toclient or 4.5W inputKensington Lock support no1Ethernet (RJ-45)1 1 (10/100/1000)---Notes Number of simultaneous used displays and its possibleresolutions and frequencies depend on mobile systemand display interface type.Please consult always also the manual of the connectedclient.Wireless technologiesAntennas2x dual band for WLAN, 2x for LTE, Bluetooth shared with WLANBluetooth V5.1Integrated WLAN Intel WiFi 6 AX201 - WLAN, BT, SRD cat. 1WLAN encryption WPA/WPA2/WPA3 (Wi-Fi Protected Access)WLAN notes Import and usage according to country-specific regulations.Integrated WWAN LTE Sierra Wireless EM7421 (Cat.7) - UMTS, LTEWWAN notes Including GPS functionalityImport and usage according to country-specific regulations.LTE Connection Manager (if configured with 4G/LTE)GPS Embedded in 4G module if configured with WWANPower supplyAC adapter19 V / 65 W (3.42 A)20 V / 65 W (3.25 A) Type CNotes65W AC Adapter for usage with system/ min. 90W AC Adapter for usage with Cradle Rated voltage range100 V - 240 V (AC Input)Rated frequency range50 Hz - 60 Hz1st battery Li-Ion battery 3-cell, 38 WhBattery features Quick Charge: 80% in 1hRuntime 1st battery10 hBattery notes Battery runtime information is based on worldwide acknowledged BAPCo® MobileMark® 2018. Refer to www.bapco.com for additional details.The BAPCo® MobileMark® Benchmark provides results that enable direct product comparisons betweenmanufacturers. It does not guarantee any specific battery runtime which actually can be lower and may varydepending on product model, configuration, application and power management settings. The battery capacitydecreases slightly with every re-charge and over its lifetime.Dimensions / Weight / EnvironmentalDimensions (W x D x H)315 x 200.9 x 10.5 mm12.4 x 0.79 x 0.42 inchWeight from 0.800 kg slate only, weight of keyboard docking from 0.465 kgWeight (lbs)from 1.75 lbs slate only, weight of keyboard docking from 1.25 lbsWeight notes Weight may vary depending on actual configurationOperating ambient temperature 5 - 35 °C (41 - 95 °F); Packed -10 - 60 °C (14 - 140 °F)Operating relative humidity Running: 20 - 80% (relative humidity); Packed: 20 - 80% (relative humidity)Product STYLISTIC Q7311Germany GSEurope CECBGlobal TCO Certified 8.0EPEAT® Silver (dedicated regions), depending on configurationMicrosoft Operating Systems (HCT / HCL entry / WHQL)MIL-STD-810H testedRoHS (Restriction of hazardous substances)WEEE (Waste electrical and electronic equipment)Russia EACChina CCCCompliance link https:///sites/certificatesAdditional SoftwareAdditional software (preinstalled)Adobe® Reader® (pdf reader)CyberLink YouCam (webcam software)Fujitsu Display ManagerFujitsu DeskUpdate (driver and utility tool)ShockSensor UtilityPower Saving UtilityFujitsu Plugfree Network (network management utility)EasyGuide online user documentationMicrosoft Office (1 month trial for new Microsoft® Office 365 customers. Buy Microsoft Office.)Additional software (optional)Recovery DVD for Windows®Drivers & Utilities DVD (DUDVD) optionalCyberLink PowerDVD BD (playback software for Blu-ray Disc™)CyberLink PowerDVD DVD (playback software for DVD)CyberLink YouCam (webcam software)Nero (backup and burning software)ManageabilitySecurityPhysical Security Kensington Lock supportSystem and BIOS Security Absolute Persistence® technology capable BIOSEraseDiskTrusted Platform Module (TPM 2.0)User Security Hard disk passwordUser and supervisor BIOS passwordEmbedded fingerprint sensor (optional)Smartcard reader (optional)SystemLock BIOS SmartCard securityAuthConductor Client Basic (secure authentication solution)Packaging informationWarranty Warranty period2 years (for countries within EMEIA)Warranty type Bring-in Service / Collect & Return Service (depending on country)Product Support - the perfect extension Recommended Service 9x5, Onsite Response Time: Next Business DaySpare Parts availabilityat least 5 years after shipment, for details see https:///Recommended AccessoriesThunderbolt™ 4 Port ReplicatorFirst Thunderbolt™ Port Replicator on the market providing enhancedsecurity and full support of Intel® AMT (vPro®).The universal port can easily connect almost everything with a single cable and high speed-data transfer. This smart workspace solution keeps your desk clean and tidy.Order Code: FPCPR401BPUSB Type-C Port Replicator 2Connect to your peripherals. Adapt to the task on demand. The universal USB Type-C interface supports you to get your peripheral devicesconnected easily. Multiply your USB ports to connect your peripherals as well as your external display via HDMI, DisplayPort or VGA.You also can charge your external USB devices without the need of any additional charger.Order Code:S26391-F3327-L100STYLISTIC Q7311, Q7310 andSTYLISTIC Q5010 Family Cradle Flexibility, expandability, desktop replacement, investment protection – to name just a few benefits of Fujitsu’s docking options.Order Code: S26391-F3397-L100USB Type-C AC AdapterRecharge your notebook or tablet at work, at home or on the road with this USB Type-C power source easily. Order Code: S26391-F3326-L502LAN Conversion Cable (USB toLAN) for STYLISTIC Q The FUJITSU USB Type-A to LAN Conversion Cable enables you to connect your compatible STYLISTIC Tablet to a wired network connection. GBit-LAN via USB conversion cable is limited to 480 Mbit/s due to USB 2.0specification. (Picture similar to product)Order Code:S26391-F3398-L840Tablet Stand for STYLISTIC QdevicesThe tablet stand is designed for STYLISTIC devices like latest STYLISTIC Q7312 and can be used universally. Fits for STYLISTIC Q5 and Q7 and the Type-C as well as the Thunderbolt ™ 4 port replicator can be fixed on the stand.Order Code: FPCSK769BPAES PenTake your creativity to the next level, with the most natural pen experience with the AES Pen with replacement stylus tips. With pen nibs that are very thin, you can experience the writing and signing behavior of an ink pen. The pen fits in the device’s integrated pen garage.Order Code:S26391-F3389-L500Car Adapter USB-C-QCOne Car Adapter fits all.Independent of your mobile device charging method this car adapter will fulfill all major requirements and standards for fast charging vendorbrand-independent notebooks and all mobile devices. The Car Adapter USB-C-QC supports USB PD with PPS, Quick Charge (QC), Apple- and Samsung charge.Order Code: S26391-F2613-L630CANVAS HANSEN 14The PLEVIER CANVAS HANSEN 14 leather and canvas case is a compact and classic carrier for on the go. Available for notebooks up to 14 inches with two compartments and two accessory sections, protection for your device ensured. A subtle design canvas and nappa leather shade.Order Code:S26391-F1193-L67Bumper Case KitThe protective bump case kit is designed to prevent damages to yourSTYLISTIC Q7. Openings of the cover allow you to access all ports andbuttons whilest the hand strap on the back of the case gives you a firm grip while working with your tablet outside the office. The integrated stand solution enhances your productivity.Order Code: S26391-F3396-L200Folio Cover STYLISTIC Q7311/Q7310The Folio Cover for the STYLISTIC Q7311 and Q7310 is a thin, tailored protective sleeve for your Fujitsu tablet. It keeps the device safe from damage on the go, and brings a touch of style to your daily work. It can even be used as a stand if you need to display a presentation or watch a clip and fits even the device is connected to its keyboard dock.Inclination stand style 120 to 150 degreeOrder Code:S26391-F3509-L100Wireless Mouse WI860 BTCThe Wireless Mouse WI860 BTC can be paired with up to 3 different clients, 2x Bluetooth and 1x wireless USB Type-C dongle.With the blue optical sensor, it works on nearly all surfaces with an 3-step adjustable DPI selector (800/1600/2400).The mouse charges wirelessly through Qi or by USB Type-C cable.A utility button on the side is programmable. The default functions are optimized for Teams calls.Order Code:S26381-K474-L100Order Code: FPCKG453BPContactAddress: x-xx-x, street, city, state, ZIP code, country Phone: xx-xxxx-xxxx Fax : xx-xxxx-xxxxEmail:********************.com Website: /[country]2023-08-02 CE-ENdelivery subject to availability. Any liability that the data and illustrations are complete, actual or correct is excluded. Designations may be trademarks and/or copyrights of the respective manufacturer, the use of which by third parties for their own purposes may infringe the rights of such ownerMore informationAll rights reserved, including intellectual property rights. Changes to technical data reserved. Delivery subject to availability. Any liability that the data and illustrations are complete, actual or correct is excluded.Designations may be trademarks and/or copyrights of the respective manufacturer, the use of which by third parties for their own purposes may infringe the rights of such owner.For further information see /terms_of_use.html Copyright © Fujitsu Technology Solutions。
Ultimaker S5 安装和使用手册说明书
Ultimaker S5安装和使用手册原始手册 v1.820182免责声明请仔细阅读并理解本安装和使用手册的内容。
如果未阅读本手册，可能会导致人身伤害、打印效果低劣或 Ultimaker S5 受损。
务必确保使用本 3D 打印机的所有人都知道并理解本手册的内容，以便能够充分利用 Ultimaker S5。
由于设备的装配、搬运、存放、使用或处置*条件或方法不受我们控制，也可能不在我们的知晓范围内 因此对于因装配、搬运、存放、使用或处置本产品*产生的，或以任何方式与之相关的损失、人身伤害、设备损坏或费用，我们概不负责，并明确否定此类责任。
本文档中的信息来自于可靠的来源。
但是，这些信息在准确性方面并没有任何明示或隐含的保证。
Ultimaker S5 的预期用途Ultimaker 3D 打印机专为利用 Ultimaker 材料实现熔丝制造而设计和建造，用于商业/业务环境。
Ultimaker 3D 打印机集精确性和速度于一体，是制作概念模型、功能样件和进行小规模生产的理想机器。
虽然我们在使用 Ultimaker Cura 打印 3D 模型方面已经达到很高标准，但用户依然有责任确认并验证打印对象的应用是否符合预期用途，对于严格管制领域（医疗器械和航空）的应用，这一点尤为重要。
虽然Ultimaker采用开放式材料平台，但 Ultimaker 材料匹配打印机能够取得最佳打印效果，并且，我们已努力确保材料属性与机器设置匹配。
* 我们遵循 WEEE 指令。
版权所有 © 2018 Ultimaker。
全球范围内保留所有权利。
本语言版本的手册由制造商验证（原始手册）。
未经 Ultimaker 事先书面许可，本手册的任何部分，包括图片，都不得以打印、复印、微缩拍摄或任何其他方式复制和/或公布。
免责声明 2前言 4认证 5安全与合规 61.1 安全信息 71.2 危险 8简介 92.1 Ultimaker S5 的主要组件 102.2 规格 11拆箱 123.1 拆箱 133.2 安装硬件配件 15首次使用设置 174.1 打印平台板选择 184.2 PrintCore 安装 194.3 装填材料 204.4 网络安装和固件更新 224.5 安装 Ultimaker Cura 23操作 245.1 触摸屏 255.2 材料 265.3 利用 Ultimaker Cura 准备打印成品 285.4 开始打印 305.5 取下打印成品 325.6 卸下支撑材料 335.7 更改打印机配置 355.8 校准 36维护 396.1 更新固件 406.2 材料搬运和存放 416.3 维护计划 426.4 清洁打印机 436.5 轴润滑 476.6 检查轴隙 486.7 检查短皮带的张力 496.8 检查打印头前风扇中是否有残渣 506.9 检查喷嘴盖的质量 516.10 润滑 Z 电机的导向螺丝 536.11 清洁进料装置 546.12 清洁 PrintCore 556.13 润滑进料装置齿轮 586.14 更换鲍登管 596.15 清洁系统风扇 616.16 润滑铰链 62故障排除 637.1 错误消息 647.2 PrintCore 故障排除 657.3 打印质量问题 66本文档是 Ultimaker S5 的安装和使用手册。
PLX SDK User Manual
User’s Manual
Version 4.40 March 2006
© 2006, PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
PLX SOFTWARE LICENSE AGREEMENT
LICENSE Copyright © 2006 PLX Technology,
Inc.
This PLX Software License agreement is a legal agreement between you and PLX Technology, Inc. for the PLX Software, which is provided on the enclosed PLX CD-ROM. PLX Technology owns this PLX Software. The PLX Software is protected by copyright laws and international copyright treaties, as well as other intellectual property laws and treaties, and is licensed, not sold. If you are a rightful possessor of the PLX Software, PLX grants you a license to use the PLX Software as part of or in conjunction with a PLX chip on a per project basis. PLX grants this permission provided that the above copyright notice appears in all copies and derivatives of the PLX Software. Use of any supplied runtime object modules or derivatives from the included source code in any product without a PLX Technology, Inc. chip is strictly prohibited. You obtain no rights other than those granted to you under this license. You may copy the PLX Software for backup or archival purposes. You are not authorized to use, merge, copy, display, adapt, modify, execute, distribute or transfer, reverse assemble, reverse compile, decode, or translate the PLX Software except to the extent permitted by law.
NXP SCM-i.MX 6 Series Yocto Linux 用户指南说明书
© 2017 NXP B.V.SCM-i.MX 6 Series Yocto Linux User'sGuide1. IntroductionThe NXP SCM Linux BSP (Board Support Package) leverages the existing i.MX 6 Linux BSP release L4.1.15-2.0.0. The i.MX Linux BSP is a collection of binary files, source code, and support files that can be used to create a U-Boot bootloader, a Linux kernel image, and a root file system. The Yocto Project is the framework of choice to build the images described in this document, although other methods can be also used.The purpose of this document is to explain how to build an image and install the Linux BSP using the Yocto Project build environment on the SCM-i.MX 6Dual/Quad Quick Start (QWKS) board and the SCM-i.MX 6SoloX Evaluation Board (EVB). This release supports these SCM-i.MX 6 Series boards:• Quick Start Board for SCM-i.MX 6Dual/6Quad (QWKS-SCMIMX6DQ)• Evaluation Board for SCM-i.MX 6SoloX (EVB-SCMIMX6SX)NXP Semiconductors Document Number: SCMIMX6LRNUGUser's GuideRev. L4.1.15-2.0.0-ga , 04/2017Contents1. Introduction........................................................................ 1 1.1. Supporting documents ............................................ 22. Enabling Linux OS for SCM-i.MX 6Dual/6Quad/SoloX .. 2 2.1. Host setup ............................................................... 2 2.2. Host packages ......................................................... 23.Building Linux OS for SCM i.MX platforms .................... 3 3.1. Setting up the Repo utility ...................................... 3 3.2. Installing Yocto Project layers ................................ 3 3.3. Building the Yocto image ....................................... 4 3.4. Choosing a graphical back end ............................... 4 4. Deploying the image .......................................................... 5 4.1. Flashing the SD card image .................................... 5 4.2. MFGTool (Manufacturing Tool) ............................ 6 5. Specifying displays ............................................................ 6 6. Reset and boot switch configuration .................................. 7 6.1. Boot switch settings for QWKS SCM-i.MX 6D/Q . 7 6.2. Boot switch settings for EVB SCM-i.MX 6SoloX . 8 7. SCM uboot and kernel repos .............................................. 8 8. References.......................................................................... 8 9.Revision history (9)Enabling Linux OS for SCM-i.MX 6Dual/6Quad/SoloX1.1. Supporting documentsThese documents provide additional information and can be found at the NXP webpage (L4.1.15-2.0.0_LINUX_DOCS):•i.MX Linux® Release Notes—Provides the release information.•i.MX Linux® User's Guide—Contains the information on installing the U-Boot and Linux OS and using the i.MX-specific features.•i.MX Yocto Project User's Guide—Contains the instructions for setting up and building the Linux OS in the Yocto Project.•i.MX Linux®Reference Manual—Contains the information about the Linux drivers for i.MX.•i.MX BSP Porting Guide—Contains the instructions to port the BSP to a new board.These quick start guides contain basic information about the board and its setup:•QWKS board for SCM-i.MX 6D/Q Quick Start Guide•Evaluation board for SCM-i.MX 6SoloX Quick Start Guide2. Enabling Linux OS for SCM-i.MX 6Dual/6Quad/SoloXThis section describes how to obtain the SCM-related build environment for Yocto. This assumes that you are familiar with the standard i.MX Yocto Linux OS BSP environment and build process. If you are not familiar with this process, see the NXP Yocto Project User’s Guide (available at L4.1.15-2.0.0_LINUX_DOCS).2.1. Host setupTo get the Yocto Project expected behavior on a Linux OS host machine, install the packages and utilities described below. The hard disk space required on the host machine is an important consideration. For example, when building on a machine running Ubuntu, the minimum hard disk space required is about 50 GB for the X11 backend. It is recommended that at least 120 GB is provided, which is enough to compile any backend.The minimum recommended Ubuntu version is 14.04, but the builds for dizzy work on 12.04 (or later). Earlier versions may cause the Yocto Project build setup to fail, because it requires python versions only available on Ubuntu 12.04 (or later). See the Yocto Project reference manual for more information.2.2. Host packagesThe Yocto Project build requires that the packages documented under the Yocto Project are installed for the build. Visit the Yocto Project Quick Start at /docs/current/yocto-project-qs/yocto-project-qs.html and check for the packages that must be installed on your build machine.The essential Yocto Project host packages are:$ sudo apt-get install gawk wget git-core diffstat unzip texinfo gcc-multilib build-essential chrpath socat libsdl1.2-devThe i.MX layers’ host packages for the Ubuntu 12.04 (or 14.04) host setup are:$ sudo apt-get install libsdl1.2-dev xterm sed cvs subversion coreutils texi2html docbook-utils python-pysqlite2 help2man make gcc g++ desktop-file-utils libgl1-mesa-dev libglu1-mesa-dev mercurial autoconf automake groff curl lzop asciidocThe i.MX layers’ host packages for the Ubuntu 12.04 host setup are:$ sudo apt-get install uboot-mkimageThe i.MX layers’ host packages for the Ubuntu 14.04 host s etup are:$ sudo apt-get install u-boot-toolsThe configuration tool uses the default version of grep that is on your build machine. If there is a different version of grep in your path, it may cause the builds to fail. One workaround is to rename the special versi on to something not containing “grep”.3. Building Linux OS for SCM i.MX platforms3.1. Setting up the Repo utilityRepo is a tool built on top of GIT, which makes it easier to manage projects that contain multiple repositories that do not have to be on the same server. Repo complements the layered nature of the Yocto Project very well, making it easier for customers to add their own layers to the BSP.To install the Repo utility, perform these steps:1.Create a bin folder in the home directory.$ mkdir ~/bin (this step may not be needed if the bin folder already exists)$ curl /git-repo-downloads/repo > ~/bin/repo$ chmod a+x ~/bin/repo2.Add this line to the .bashrc file to ensure that the ~/bin folder is in your PATH variable:$ export PATH=~/bin:$PATH3.2. Installing Yocto Project layersAll the SCM-related changes are collected in the new meta-nxp-imx-scm layer, which is obtained through the Repo sync pointing to the corresponding scm-imx branch.Make sure that GIT is set up properly with these commands:$ git config --global "Your Name"$ git config --global user.email "Your Email"$ git config --listThe NXP Yocto Project BSP Release directory contains the sources directory, which contains the recipes used to build, one (or more) build directories, and a set of scripts used to set up the environment. The recipes used to build the project come from both the community and NXP. The Yocto Project layers are downloaded to the sources directory. This sets up the recipes that are used to build the project. The following code snippets show how to set up the SCM L4.1.15-2.0.0_ga Yocto environment for the SCM-i.MX 6 QWKS board and the evaluation board. In this example, a directory called fsl-arm-yocto-bsp is created for the project. Any name can be used instead of this.Building Linux OS for SCM i.MX platforms3.2.1. SCM-i.MX 6D/Q quick start board$ mkdir fsl-arm-yocto-bsp$ cd fsl-arm-yocto-bsp$ repo init -u git:///imx/fsl-arm-yocto-bsp.git -b imx-4.1-krogoth -m scm-imx-4.1.15-2.0.0.xml$ repo sync3.2.2. SCM-i.MX 6SoloX evaluation board$ mkdir my-evb_6sxscm-yocto-bsp$ cd my-evb_6sxscm-yocto-bsp$ repo init -u git:///imx/fsl-arm-yocto-bsp.git -b imx-4.1-krogoth -m scm-imx-4.1.15-2.0.0.xml$ repo sync3.3. Building the Yocto imageNote that the quick start board for SCM-i.MX 6D/Q and the evaluation board for SCM-i.MX 6SoloX are commercially available with a 1 GB LPDDR2 PoP memory configuration.This release supports the imx6dqscm-1gb-qwks, imx6dqscm-1gb-qwks-rev3, and imx6sxscm-1gb-evb. Set the machine configuration in MACHINE= in the following section.3.3.1. Choosing a machineChoose the machine configuration that matches your reference board.•imx6dqscm-1gb-qwks (QWKS board for SCM-i.MX 6DQ with 1 GB LPDDR2 PoP)•imx6dqscm-1gb-qwks-rev3 (QWKS board Rev C for SCM-i.MX 6DQ with 1GB LPDDR2 PoP) •imx6sxscm-1gb-evb (EVB for SCM-i.MX 6SX with 1 GB LPDDR2 PoP)3.4. Choosing a graphical back endBefore the setup, choose a graphical back end. The default is X11.Choose one of these graphical back ends:•X11•Wayland: using the Weston compositor•XWayland•FrameBufferSpecify the machine configuration for each graphical back end.The following are examples of building the Yocto image for each back end using the QWKS board for SCM-i.MX 6D/Q and the evaluation board for SCM-i.MX 6SoloX. Do not forget to replace the machine configuration with what matches your reference board.3.4.1. X11 image on QWKS board Rev C for SCM-i.MX 6D/Q$ DISTRO=fsl-imx-x11 imx6dqscm-1gb-qwks-rev3 source fsl-setup-release.sh -b build-x11$ bitbake fsl-image-gui3.4.2. FrameBuffer image on evaluation board for SCM-i.MX 6SX$ DISTRO=fsl-imx-fb MACHINE=imx6sxscm-1gb-evb source fsl-setup-release.sh –b build-fb-evb_6sxscm$ bitbake fsl-image-qt53.4.3. XWayland image on QWKS board for SCM-i.MX 6D/Q$ DISTRO=fsl-imx-xwayland MACHINE=imx6dqscm-1gb-qwks source fsl-setup-release.sh –b build-xwayland$ bitbake fsl-image-gui3.4.4. Wayland image on QWKS board for SCM-i.MX 6D/Q$ DISTRO=fsl-imx-wayland MACHINE=imx6dqscm-1gb-qwks source fsl-setup-release.sh -b build-wayland$ bitbake fsl-image-qt5The fsl-setup-release script installs the meta-fsl-bsp-release layer and configures theDISTRO_FEATURES required to choose the graphical back end. The –b parameter specifies the build directory target. In this build directory, the conf directory that contains the local.conf file is created from the setup where the MACHINE and DISTRO_FEATURES are set. The meta-fslbsp-release layer is added into the bblayer.conf file in the conf directory under the build directory specified by the –e parameter.4. Deploying the imageAfter the build is complete, the created image resides in the <build directory>/tmp/deploy/images directory. The image is (for the most part) specific to the machine set in the environment setup. Each image build creates the U-Boot, kernel, and image type based on the IMAGE_FSTYPES defined in the machine configuration file. Most machine configurations provide the SD card image (.sdcard), ext4, and tar.bz2. The ext4 is the root file system only. The .sdcard image contains the U-Boot, kernel, and rootfs, completely set up for use on an SD card.4.1. Flashing the SD card imageThe SD card image provides the full system to boot with the U-Boot and kernel. To flash the SD card image, run this command:$ sudo dd if=<image name>.sdcard of=/dev/sd<partition> bs=1M && syncFor more information about flashing, see “P reparing an SD/MMC Card to Boot” in the i.MX Linux User's Guide (document IMXLUG).Specifying displays4.2. MFGTool (Manufacturing Tool)MFGTool is one of the ways to place the image on a device. To download the manufacturing tool for the SCM-i.MX 6D/Q and for details on how to use it, download the SCM-i.MX 6 Manufacturing Toolkit for Linux 4.1.15-2.0.0 under the "Downloads" tab from /qwks-scm-imx6dq. Similarly, download the manufacturing tool for the SCM-i.MX 6SoloX evaluation board under the "Downloads" tab from /evb-scm-imx6sx.5. Specifying displaysSpecify the display information on the Linux OS boot command line. It is not dependent on the source of the Linux OS image. If nothing is specified for the display, the settings in the device tree are used. Find the specific parameters in the i.MX 6 Release Notes L4.1.15-2.0.0 (available at L4.1.15-2.0.0_LINUX_DOCS). The examples are shown in the following subsections. Interrupt the auto-boot and enter the following commands.5.1.1. Display options for QWKS board for SCM-i.MX 6D/QHDMI displayU-Boot > setenv mmcargs 'setenv bootargs console=${console},${baudrate} ${smp}root=${mmcroot} video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24'U-Boot > run bootcmd5.1.2. Display options for EVB for SCM-i.MX 6SXNote that the SCM-i.MX 6SX EVB supports HDMI with a HDMI accessory card (MCIMXHDMICARD) that plugs into the LCD connector on the EVB.Accessory boards:•The LVDS connector pairs with the NXP MCIMX-LVDS1 LCD display board.•The LCD expansion connector (parallel, 24-bit) pairs with the NXP MCIMXHDMICARD adapter board.LVDS displayU-Boot > setenv mmcargs 'setenv bootargs console=${console},${baudrate} ${smp}root=${mmcroot} ${dmfc} video=mxcfb0:dev=ldb,1024x768M@60,if=RGB666 ldb=sep0'U-Boot > run bootcmdHDMI display (dual display for the HDMI as primary and the LVDS as secondary)U-Boot > setenv mmcargs 'setenv bootargs console=${console},${baudrate} ${smp}root=${mmcroot} video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24video=mxcfb1:dev=ldb,LDBXGA,if=RGB666'U-Boot > run bootcmdLCD displayu-boot > setenv mmcargs 'setenv bootargs ${bootargs}root=${mmcroot} rootwait rw video=mxcfb0:dev=lcd,if=RGB565'u-boot> run bootcmd6. Reset and boot switch configuration6.1. Boot switch settings for QWKS SCM-i.MX 6D/QThere are two push-button switches on the QWKS-SCMIMX6DQ board. SW1 (SW3 for QWKS board Rev B) is the system reset that resets the PMIC. SW2 is the i.MX 6Dual/6Quad on/off button that is needed for Android.There are three boot options. The board can boot either from the internal SPI-NOR flash inside the SCM-i.MX6Dual/6Quad or from either of the two SD card slots. The following table shows the switch settings for the boot options.Table 1.Boot configuration switch settingsBoot from top SD slot (SD3)Boot from bottom SD slot (SD2)Boot from internal SPI NORDefault1.References6.2. Boot switch settings for EVB SCM-i.MX 6SoloXThis table shows the jumper configuration to boot the evaluation board from the SD card slot SD3.7. SCM uboot and kernel repositoriesThe kernel and uboot patches for both SCM-i.MX 6 QWKS board and evaluation board are integrated in specific git repositories. Below are the git repos for SCM-i.MX 6 uboot and kernel:uBoot repo: /git/cgit.cgi/imx/uboot-imx.gitSCM Branch: scm-imx_v2016.03_4.1.15_2.0.0_gakernel repo: /git/cgit.cgi/imx/linux-imx.gitSCM branch: scm-imx_4.1.15_2.0.0_ga8. References1.For details about setting up the Host and Yocto Project, see the NXP Yocto Project User’s Guide(document IMXLXYOCTOUG).2.For information about downloading images using U-Boot, see “Downloading images usingU-Boot” in the i.MX Linux User's Guide (document IMXLUG).3.For information about setting up the SD/MMC card, see “P reparing an SD/MMC card to boot” inthe i.MX Linux User's Guide (document IMXLUG).9. Revision historyDocument Number: SCMIMX6LRNUGRev. L4.1.15-2.0.0-ga04/2017How to Reach Us: Home Page: Web Support: /supportInformation in this document is provided solely to enable system and softwareimplementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein.NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequentia l or incidental damages. “Typical”parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be valida ted for each customer application by customer’s technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: /SalesTermsandConditions .NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, Freescale, and the Freescale logo are trademarks of NXP B.V. All other product or service names are the property of their respective owners.ARM, the ARM Powered logo, and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. © 2017 NXP B.V.。
易普特B5交换机快速配置指南说明书
How to Use This GuideUse this guide to quickly set up your Enterasys ®B5 switch.Enterasys Networks recommends that you refer to the Enterasys B5 Gigabit Ethernet Switch Hardware Installation Guide for specifications and safety warnings.The latest B5 documentation is located at /support/manuals.Hardware ComponentsThe following figures show the several types of front panel port and rear panel connections on your B5 switch.Figure 1B5 Switch Front PanelsB5G124-24, B5G124-24P2B5G124-48, B5G124-48P2B5K125-24, B5K125-24P2B5K125-48, B5K125-48P2Figure 2 B5 Switch Back PanelsNon-PoE B5 SwitchesPoE B5 SwitchesKey1Switch status LEDs8Console port2RJ45 10/100/1000 Mbps ports 9Stack connection ports 3SFP slots 10Rotary switch410G slots11Password reset button 5RJ45 status LEDs 12AC power input connector 6SFP port status LEDs 13Redundant power supply 710G port status LEDs(RPS) connectorHandling the SwitchTo prevent electrostatic damage, attach an electrostatic discharge (ESD) wrist strap to your wrist before handling the switch.Unpack the switch as follows:1.Remove the packing material protecting the switch.2.Remove the tape seal on the non ‐conductive bag to remove theswitch.3.Perform a visual inspection of the switch for any signs ofphysical damage. Contact Enterasys Networks if there are any signs of damage. See “Getting Help” for more information on contacting Enterasys Networks.Stacking SwitchesUp to eight B5 switches can be stacked together and connected by high ‐speed stacking cables, which allow the entire stack to operate with a single IP address.The B5 supports the following high ‐speed stacking cables only, which you must order separately:•STK ‐CAB ‐SHORT •STK ‐CAB ‐LONG •STK ‐CAB ‐2M •STK ‐CAB ‐5MFor complete information about stacking, refer to the Enterasys B5 Gigabit Ethernet Switch Hardware Installation Guide.Connecting Power to the SwitchYou can connect to a single, primary source of power, or to two sources of power for redundancy. The example used here describes connecting to two power sources.The following redundant power supplies are available to be purchased from Enterasys Networks for connection to a B5 switch:•STK ‐RPS ‐150PS, a 102‐156 watt DC power supply capable ofproviding power to a fully ‐loaded non ‐PoE switch.•STK ‐RPS ‐500PS, a 500 watt DC power supply recommendedfor full PoE capability.To power ‐up your B5 switch:1.Attach the power cord from your redundant power supplyinto the B5 switch’s redundant power receptacle.2.Attach the AC power cord to the B5 switch’s AC powerreceptacle.3.Plug the redundant power supply and the B5 switch ACpower cords into dedicated, grounded AC outlets.4.Once power is connected, verify that the CPU (system) LEDturns amber until the B5 switch finishes its initialization.If the initialization process is successful, the CPU LED turns green. If the CPU LED does not turn green, refer to the Enterasys B5 Gigabit Ethernet Switch Hardware Installation Guide for troubleshooting information.Caution:The switch can be damaged by electrostatic discharge.You can stack a B5 switch only with other B5 switches.Only qualified personnel should perform Completing Switch Setup and Downloading the Latest FirmwareOnce you have connected power to the B5 switch and verified LED activity, you can complete the setup process as follows. Refer to the Enterasys B5 Gigabit Ethernet Switch Hardware Installation Guide for more information.1.Determine the latest B5 firmware version by visiting theEnterasys Networks download site at:/services/support/downloads/software2.Connect the switch to the network.3.Connect a management station to the console port.4.Verify that the network devices connected to the switch portsare powered on, and that each link/activity LED is on (solid green or blinking green).5.At the device connected to the console port, perform thefollowing:a.Enter admin for Username.b.At the Password prompt, press ENTER (RETURN).c.At the command prompt, determine if the latest firmwareimage is loaded on the switch by entering this command:show versiond.If the output (under FW Version ) displays an older versionnumber than that determined in step 1, download and activate the new version as directed on the download website. (Alternatively, you can use the CLI commands listed in Table 1.)Basic Setup CommandsTable 1 lists CLI commands that are required for setting up the B5 switch with the latest firmware. Table 2 lists additionalconfiguration commands for your B5 switch. For the complete list of CLI commands, see the Enterasys B5 CLI Reference .Table 1Required CLI Setup CommandsStep TaskCLI commands1Set a new password set password [username ]2Set the switch IP addressset ip address ip-address [mask ip-mask ] [gateway ip-gateway ]3Download, activate, and verify new firmware on the switch using TFTP copyNote: You can reboot the system immediately with the set boot systemcommand, or reboot later with the reset command.copytftp://tftp_server_ip_address /filename system:image set boot system filenameshow version Table 2Optional CLI Setup CommandsTaskCLI commands Save the active configuration save configEnable or disable SSH set ssh enable | disable Enable or disable Telnet set telnet {enable | disable} [inbound | outbound | all]Enable or disable HTTP management (WebView)set webview {enable | disable}Enable or disable SNMP port link trapsset port trap port-string{enable | disable}Set the per port broadcast limit set port broadcast port-string threshold-valueConfigure a VLANset vlan create vlan-id set port vlan port-string vlan-id modify-egress Set a Syslog server IP and severity set logging server indexip-addr ip-addr severity severity state enableSpecificationsFor a complete list of specifications, see the Enterasys B5 Gigabit Ethernet Switch Hardware Installation Guide . InterfacesSwitch DimensionsSize:44.1 W x 4.4 H x 36.85 D cm 17.4 W x 1.7 H x 14.5 D inPower ConsumptionInput Voltage: 100 to 240VACTemperature and HumidityOperating temperature: 0°C to 50°C Storage temperature: ‐40°C to +70°C Operating relative humidity: 5% to 95%Getting HelpConfigure and enable a RADIUS serverset radius server index ip-addr port [secret-value ]{realm {management-access | any | network-access} set radius enableTable 3B5 Interface DescriptionsB5G124-24•24 10/100/1000Base-T ports •Four combo SFP portsB5G124-24P2•24 10/100/1000Base-T 802.3af and 802.3at PoE-capable ports •Four combo SFP portsB5G124-48•48 10/100/1000Base-T ports •Four combo SFP portsB5G124-48P2•48 10/100/1000Base-T 802.3af and 802.3at PoE-capable ports •Four combo SFP portsB5K125-24•24 10/100/1000Base-T ports •Two combo SFP ports •Two 10G portsB5K125-24P2•24 10/100/1000Base-T 802.3af and 802.3at PoE-capable ports •Two combo SFP ports •Two 10G portsB5K125-48•48 10/100/1000Base-T ports •Two combo SFP ports •Two 10G portsB5K125-48P2•48 10/100/1000Base-T 802.3af and 802.3at PoE-capable ports •Two combo SFP ports •Two 10G portsWorld Wide Web /support/Phone1-800-872-8440 (toll-free in U.S. and Canada) or 1-978-684-1888To find the Enterasys Networks Support toll-free number in your country:/services/support/contact/Internet mail*********************To expedite your message, type [Switching ] in the subject field of your message.Latest image and release notes/services/support/downloads/software/Table 2Optional CLI Setup Commands (Continued)TaskCLI commandsRelated DocumentsThe latest B5 documentation is located online at: /support/manualsWarrantyWarranty information for the B5 switch is located online at:/support/warranty.aspx/company/literature/enterasys ‐lw ‐ds.pdfNoticeEnterasys Networks reserves the right to make changes in specifications and other information contained in this document and its web site without prior notice. The reader should in all cases consult Enterasys Networks to determine whether any such changes have been made.The hardware, firmware, or software described in this document is subject to change without notice.IN NO EVENT SHALL ENTERASYS NETWORKS BE LIABLE FOR ANY INCIDENTAL,INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS DOCUMENT, WEB SITE, OR THE INFORMATION CONTAINED IN THEM, EVEN IF ENTERASYS NETWORKS HAS BEEN ADVISED OF, KNEW OF, OR SHOULD HAVE KNOWN OF, THE POSSIBILITY OF SUCH DAMAGES.Enterasys Networks,Inc.50 Minuteman Road Andover, MA 01810© 2010 Enterasys Networks,Inc. All rights reserved.Part Number:9034512‐02December 2010ENTERASYS, ENTERASYS NETWORKS, ENTERASYS SECURE NETWORKS, NETSIGHT, ENTERASYS NETSIGHT, and any logos associated therewith, are trademarks or registeredtrademarks of Enterasys Networks, Inc., in the United States and/or other countries. For a complete list of Enterasys trademarks, see /company/trademarks.aspx .All other product names mentioned in this manual may be trademarks or registered trademarks of their respective companies.Regulatory Compliance InformationFederal Communications Commission (FCC) NoticeThis device complies with Part 15 of the FCC rules. Operation is subject to the following twoconditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.NOTE:This equipment has been tested and found to comply with the limits for a class A digital device, pursuant to Part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercialenvironment. This equipment uses, generates, and can radiate radio frequency energy and if not installed in accordance with the operator’s manual, may cause harmful interference to radiocommunications. Operation of this equipment in a residential area is likely to cause interference in which case the user will be required to correct the interference at his own expense.WARNING:Changes or modifications made to this device which are not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment.Industry Canada NoticeThis digital apparatus does not exceed the class A limits for radio noise emissions from digital apparatus set out in the Radio Interference Regulations of the Canadian Department of Communications.Le présent appareil numérique n’émet pas de bruits radioélectriques dépassant les limitesapplicables aux appareils numériques de la class A prescrites dans le Règlement sur le brouillage radioélectrique édicté par le ministère des Communications du Canada.Class A ITE NoticeWARNING:This is a Class A product. In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures.Clase A. Aviso de ITEADVERTENCIA: Este es un producto de Clase A. En un ambiente doméstico este producto puede causar interferencia de radio en cuyo caso puede ser requerido tomar medidas adecuadas.Klasse A ITE AnmerkungWARNHINWEIS: Dieses Produkt zählt zur Klasse A ( Industriebereich ). In Wohnbereichen kann es hierdurch zu Funkstörungen kommen, daher sollten angemessene Vorkehrungen zum Schutz getroffen werden.VCCI NoticeThis is a class A product based on the standard of the Voluntary Control Council for Interference by Information Technology Equipment (VCCI). If this equipment is used in a domestic environment, radio disturbance may arise. When such trouble occurs, the user may be required to take corrective actions.BSMI EMC Statement — TaiwanThis isa class A product. In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures.AS/NZS CISPR 22Hazardous SubstancesThis product complies with the requirements of European Directive, 2002/95/EC, Restriction of Hazardous Substances (RoHS) in Electrical and Electronic Equipment.European Waste Electrical and Electronic Equipment (WEEE) NoticeIn accordance with Directive 2002/96/EC of the European Parliament on waste electrical and electronic equipment (WEEE):1.The symbol above indicates that separate collection of electrical and electronic equipment isrequired and that this product was placed on the European market after August 13, 2005, the date of enforcement for Directive 2002/96/EC.2.When this product hasreached the end of its serviceable life, it cannot be disposed of as unsortedmunicipal waste. It must be collected and treated separately.3.It has been determined by the European Parliament that there are potential negative effects onthe environment and human health as a result of the presence of hazardous substances in electrical and electronic equipment.4.It is the users’ responsibility to utilize the available collection system to ensure WEEE is properlytreated.For information about the available collection system, please go to/services/support/or contact Enterasys Customer Support at 353 61 705586 (Ireland).Safety InformationClass 1 Laser TransceiversThe single mode interface modules use Class 1 laser transceivers. Read the following safety information before installing or operating these modules.The Class 1 laser transceivers use an optical feedback loop to maintain Class 1 operation limits. This control loop eliminates the need for maintenance checks or adjustments. The output is factory set, and does not allow any user adjustment. Class 1 Laser transceivers comply with the following safety standards:•21 CFR 1040.10 and 1040.11 U.S. Department of Health and Human Services (FDA).•IEC Publication 825 (International Electrotechnical Commission).•CENELEC EN 60825 (European Committee for Electrotechnical Standardization).When operating within their performance limitations, laser transceiver output meets the Class 1 accessible emission limit of all three standards. Class 1 levels of laser radiation are not considered hazardous.When the connector is in place, all laser radiation remains within the fiber. The maximum amount of radiant power exiting the fiber (under normal conditions) is ‐12.6 dBm or 55 x 10‐6 watts.Removing the optical connector from the transceiver allows laser radiation to emit directly from the optical port. The maximum radiance from the optical port (under worst case conditions) is 0.8 W cm ‐2 or 8 x 103 W m 2 sr ‐1.Do not use optical instruments to view the laser output. The use of optical instruments to view laser output increases eye hazard. When viewing the output optical port, power must be removed from the network adapter.Safety ComplianceWarning: Fiber Optic Port SafetyWhen using a fiber optic media expansion module, never look at the transmit laser while it is powered on. Also, never look directly at the fiber TX port and fiber cable ends when they are poweredon.Avertissment: Ports pour fibres optiques - sécurité sur le plan optiqueNe regardez jamais le laser tant qu’il est sous tension. Ne regardezjamais directement le port TX (Transmission) à fibres optiques et les emboutsde câbles à fibres optiques tant qu ʹils sont sous tension.Warnhinweis: Faseroptikanschlüsse - Optische SicherheitNiemals ein Übertragungslaser betrachten, während dieseseingeschaltet ist. Niemals direkt auf den Faser ‐TX ‐Anschluß und auf die Faserkabelenden schauen, während diese eingeschaltet sind.Declaration of ConformityApplication of Council Directive(s):2004/108/EC2006/95/ECManufacturer’s Name:Enterasys Networks,Inc.Manufacturer’s Address:50 Minuteman RoadAndover, MA 01810USAEuropean Representative Address:Enterasys Networks Ltd.Nexus House, Newbury Business ParkLondon Road, NewburyBerkshire RG14 2PZ, EnglandConformance toDirective(s)/Product Standards:EC Directive 2004/108/ECEN 55022:2006EN 55024:1998EN 61000‐3‐2:2006EN 61000‐3‐3:1995EC Directive 2006/95/EC EN 60950‐1:2006EN 60825‐1:2007EN 60825‐2:2004Equipment Type/Environment:Information Technology Equipment,for use in a Commercialor Light Industrial Environment.Enterasys Networks,Inc. declares that the equipment packaged with this notice conforms to the above directives.Enterasys ®B5Gigabit Ethernet SwitchQuick ReferenceB5G124-24, B5G124-24P2B5G124-48, B5G124-48P2B5K125-24, B5K125-24P2B5K125-48, B5K125-48P2P/N 9034512-02。
Nuvoton NK-N9H20用户指南说明书
NK-N9H20User ManualThe information described in this document is the exclusive intellectual property ofNuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro™ microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.All data and specifications are subject to change without notice.For additional information or questions, please contact: Nuvoton Technology Corporation.Oct. 02, 2019Table of Contents1Overview (3)2NuDesign HMI-N9H20 Board Introduction (4)2.1NuDesign HMI-N9H20 Jumper Description (8)2.2Pin Assignment for Extended Connectors (11)2.3NuDesign HMI-N9H20/TFT-LCD4.3/SPI2UART(B) PCB Placement (15)2.4NuDesign HMI-N9H20 N9H20K51N’s Control Pin Functions (20)2.5NuDesign HMI-N9H20 BOM (23)2.6NuDesign TFT-LCD4.3 BOM (26)2.7NuDesign SPI2UART(B) BOM (26)3NuDesign HMI-N9H20 Schematics (27)3.1NuDesign HMI-N9H20 Function Blocks Schematic (27)3.2NuDesign HMI-N9H20 N9H20K51N MPU Schematic (28)3.3NuDesign HMI-N9H20 Power Supply Schematic (29)3.4NuDesign HMI-N9H20 Keys and Configuration Schematic (29)3.5NuDesign HMI-N9H20 USB2.0 and SD0 Interface Schematic (30)3.6NuDesign HMI-N9H20 NAND and SPI Flash Memory Schematic (30)3.7NuDesign HMI-N9H20 Headphone Schematic (31)3.8NuDesign HMI-N9H20 JTAG and UART Schematic (32)3.9NuDesign HMI-N9H20 Audio Codec Controller Schematic (33)3.10NuDesign TFT-LCD4.3 LCD Controller Schematic (34)3.11NuDesign SPI2UART(B) Controller Schematic (35)4Revision History (36)Oct. 02, 20191 OverviewThe NK-N9H20 system includes boards NuDesign HMI-N9H20 and NuDesign TFT-LCD4.3 that is a general development board for N9H20K51N series by which users can develop and verify the application program easily. The NuDesign HMI-N9H20 includes Audio controller, USB 2.0 HS Device controller, SPI to UART controller, 24-bit LCD controller and integrated 32MB DDR2 memory, SRAM and external device with DMA request and ack.Oct. 02, 20192 NuDesign HMI-N9H20 Board IntroductionThe following figures show the NuDesign HMI-N9H20 development board, in which the front and back integrated 32-bit microcontroller embeds an outstanding CPU core ARM926EJ-S, runs up to 192MHz, with 16KB I-cache, 16 KB D-cache and MMU,32KB embedded SRAM and 12KB IBR(Internal Boot ROM) for booting from USB and SPI FLASH; Audio controller NAU8822A is a low power, high quality CODEC for portable and general purpose audio applications, it includes drivers for speaker, headphone, and differential or stereo line outputs, and integrates preamps for stereo differential microphones, significantly reducing external component requirements. The board also supports several extended connections. Users can use it to develop and verify applications to emulate the real behavior.Figure 2-1 NuDesign HMI-N9H20 PCB Board (Front)Figure 2-2 NuDesign HMI-N9H20 PCB Board (Back) Oct. 02, 2019Figure 2-3 NuDesign TFT-LCD4.3 PCB Board (Front) Oct. 02, 2019Figure 2-4 NuDesign TFT-LCD4.3 PCB Board (Back) Oct. 02, 2019Oct. 02, 2019 Figure 2-5 NuDesign SPI2UART(B) PCB Board (Front)2.1 NuDesign HMI-N9H20 Jumper Description2.1.1 Power Source●CON3: 5V DC Adaptor input connector.●CON4 & CON5: External Battery connector.●S3: Power ON/OFF Switch.Source Power port VIN VD33 CON3 Connect to 5V DC Adaptor 5V DC 3.3V S3 VD33 & VD18 Power Enable PWREN of U2 & U3 DC 3.3V Table 2-1 System Power ConnectorsOct. 02, 20192.1.2 LED Indicators2.1.3 Debug Connectors●CON11: Connector in target board NuDesign HMI-N9H20 (U1,●CN2: Connector in target board NuDesign SPI2UART(B) (U2, MINI58FDE)Oct. 02, 20192.1.4 USB Connectors●CON6: Mini USB Connector (USB 2.0 HS Device).2.1.5 Extended Connectors●CON1 and CON2: Show all extended pins in NuDesign HMI-N9H20.2.1.6 Buttons and JUMPER●K1~K6: Key pad button in NuDesign HMI-N9H20.●SW3: Reset button in NuDesign HMI-N9H20.●JP1: System configuration setting in NuDesign HMI-N9H20.2.1.7 Audio Connectors●CON9: Headphone Positive Output or Line Output Right and HeadphoneNegative Output or Line Output Left.Oct. 02, 20192.2 Pin Assignment for Extended ConnectorsThe NuDesign HMI-N9H20 provides the N9H20K5DN target chip functions on board and several extended connectors (NU1, NU2, NU3, NU4, NU5 and NU6) for user applications. The following table is the pin assignment for NuDesign HMI-N9H20.Oct. 02, 2019Oct. 02, 2019Oct. 02, 2019Oct. 02, 20192.3 NuDesign HMI-N9H20/TFT-LCD4.3/SPI2UART(B) PCB Placement The following figure shows the NuDesign each PCB placement.Figure 2-3 NuDesign HMI-N9H20 PCB Placement (Front) Oct. 02, 2019Figure 2-4 NuDesign HMI-N9H20 PCB Placement (Back) Oct. 02, 2019Figure 2-5 NuDesign TFT-LCD4.3 PCB Placement (Front) Oct. 02, 2019Figure 2-6 NuDesign TFT_LCD4.3 PCB Placement (Back) Oct. 02, 2019Oct. 02, 2019 Figure 2-7 NuDesign SPI2UART(B) PCB Placement (Front)2.4 NuDesign HMI-N9H20 N9H20K51N’s Control Pin FunctionsThe following table shows the NuDesign HMI-N9H20 Function Control Pins Assignment.Pin No. GPIO ADC AUDIO CMOS I2C I2S JTAG LCM-80 LCM NAND SD SPI SYSTEM UART USB3 GPB.0 SP_CLKO SD1_D1 UHL_DP14 GPB.14 SDA LMVSYNC5 GPB.13 SCL WDT_RSTn6 GPD.12 SPI0_CLK7 GPD.13 SPI0_CS0nOct. 02, 2019Oct. 02, 2019Table 2-13 N9H20K51N Pin Functions Assignment2.5 NuDesign HMI-N9H20 BOMOct. 02, 2019Oct. 02, 2019Oct. 02, 20192.6 NuDesign TFT-LCD4.3 BOM2.7 NuDesign SPI2UART(B) BOMOct. 02, 20193 NuDesign HMI-N9H20 Schematics3.1 NuDesign HMI-N9H20 Function Blocks SchematicOct. 02, 20193.2 NuDesign HMI-N9H20 N9H20K51N MPU SchematicOct. 02, 20193.3 NuDesign HMI-N9H20 Power Supply Schematic3.4 NuDesign HMI-N9H20 Keys and Configuration Schematic3.5 NuDesign HMI-N9H20 USB2.0 and SD0 Interface Schematic3.6 NuDesign HMI-N9H20 NAND and SPI Flash Memory SchematicOct. 02, 2019Oct. 02, 20193.7 NuDesign HMI-N9H20 Headphone SchematicOct. 02, 20193.8 NuDesign HMI-N9H20 JTAG and UART SchematicOct. 02, 20193.9 NuDesign HMI-N9H20 Audio Codec Controller SchematicOct. 02, 20193.10 NuDesign TFT-LCD4.3 LCD Controller SchematicOct. 02, 20193.11 NuDesign SPI2UART(B) Controller SchematicOct. 02, 2019 4 Revision HistoryImportant NoticeNuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton.。
西门子 SIMATIC 组态硬件和通讯连接， STEP 7 V5.3 版本 手册
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组态硬件和通讯连接，STEP 7 V5.3 版本 A5E00446503-01
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STEP 7 文档包
本手册是文档包“STEP 7 基本信息”的一部分。 下表显示了 STEP 7 文档的总览：
文档 STEP 7 基础信息 • • • • • • STEP 7 V5.3，使用入门手册 使用 STEP 7 V5.3 编程 组态硬件和通讯连接，STEP 7 V5.3 版 本 从 S5 到 S7，变频器手册 用于 S7-300/400 的梯形图(LAD)/功能 块图(FBD)/语句表(STL)手册 S7-300/400 的标准功能及系统功能 提供了参考信息，并描述了编程语 6ES7810-4CA07-8BW1 言 LAD、FBD、STL、标准功能以 及系统功能，扩充了 STEP 7 基础 信息的范围。 用途 订货号
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ideskptopx操作手册
iDesktopX/iDesktop操作手册是为了帮助用户更好地使用iDesktopX/iDesktop软件而编写的指南。
手册主要包括以下内容：
1.概述：简要介绍iDesktopX/iDesktop的用途、特点和优势，以便用户了解
该软件的基本情况。
2.安装与配置：详细介绍如何安装和配置iDesktopX/iDesktop软件，包括硬
件要求、软件安装步骤、配置文件设置等，以确保软件正常运行。
3.界面与功能：介绍iDesktopX/iDesktop的界面和功能，包括桌面管理、图
标管理、任务管理、窗口管理等功能，以便用户能够熟练使用该软件。
4.定制与个性化：提供iDesktopX/iDesktop的定制和个性化建议，包括主题
设置、壁纸更换、快捷键设置等，以便用户根据自己的需求和习惯进行个性化设置。
5.常见问题与解决方案：列出使用iDesktopX/iDesktop过程中可能遇到的问
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ksz8851snl_ds
KSZ8851SNL/SNLI Single-Port Ethernet Controller with SPI InterfaceRev. 2.0LinkMD is a registered trademark of Micrel, Inc.Magic Packet is a trademark of Advanced Micro Devices, Inc.MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc. Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies.General DescriptionThe KSZ8851SNL is a single-chip Fast Ethernet controller consisting of a 10/100 physical layer transceiver (PHY), a MAC, and a Serial Peripheral Interface (SPI). The KSZ8851SNL is designed to enable an Ethernet network connectivity with any host micro-controller equipped with SPI interface. The KSZ8851SNL offers the most cost-effective solution for adding high-throughput Ethernet link to traditional embedded systems with SPI interface.The KSZ8851SNL is a single chip, mixed analog/digital device offering Wake-on-LAN technology for effectively addressing Fast Ethernet applications. It consists of a Fast Ethernet MAC controller, SPI interface and incorporates a unique dynamic memory pointer with 4-byte buffer boundary and a fully utilizable 18KB for both TX (allocated 6KB) and RX (allocated 12KB) directions in host buffer interface.The KSZ8851SNL is designed to be fully compliant with the appropriate IEEE 802.3 standards. An industrial temperature-grade version of the KSZ8851SNL, the KSZ8851SNLI is also available (see “Ordering Information” section).LinkMD®Physical signal transmission and reception are enhanced through the use of analog circuitry, making the design more efficient and allowing for lower-power consumption. The KSZ8851SNL is designed using a low-power CMOS process that features a single 3.3V power supply with options for 1.8V, 2.5V or 3.3V VDD I/O. The device includes an extensive feature set that offers management information base (MIB) counters and a fast SPI interface with clock speed up to 40MHz.The KSZ8851SNL includes unique cable diagnostics feature called LinkMD®. This feature determines the length of the cabling plant and also ascertains if there is an open or short condition in the cable. Accompanying software enables the cable length and cable conditions to be conveniently displayed. In addition, the KSZ8851SNL supports Hewlett Packard (HP) Auto-MDIX thereby eliminating the need to differentiate between straight or crossover cables in applications.Functional DiagramFigure 1. KSZ8851SNL/SNLI Functional DiagramFeatures•Integrated MAC and PHY Ethernet Controller fully compliant with IEEE 802.3/802.3u standards•SPI Interface with clock speeds up to 40MHz for high throughput applications•Supports 10BASE-T/100BASE-TX•Supports IEEE 802.3x full-duplex flow control and half-duplex backpressure collision flow control•Supports RXQ and TXQ FIFO DMA for fast data read and write transfers•Supports IP Header (IPv4)/TCP/UDP/ICMP checksum generation and checking•Supports IPv6 TCP/UDP/ICMP checksum generation and checking•Automatic 32-bit CRC generation and checking •Supports simple command and data phases in SPI cycle for RXQ/TXQ FIFO and registers read/write •Supports multiple data frames for TXQ FIFO and RXQ FIFO without additional command phase•Supports flexible Byte (8-bit), Word (16-bit) and Double word (32-bit) read/write access to internal registers •Larger internal memory with 12K Bytes for RX FIFO and 6K Bytes for TX FIFO. Programmable low, high andoverrun watermark for flow control in RX FIFO •Efficient architecture design with configurable host interrupt schemes to minimize host CPU overhead and utilization•Powerful and flexible address filtering scheme •Optional to use external serial EEPROM configuration for MAC address•Single 25MHz reference clock for both PHY and MAC •HBM ESD Rating 6kVPower Modes, Power Supplies, and Packaging •Single 3.3V power supply with options for 1.8V, 2.5V and 3.3V VDD I/O•Built-in integrated 3.3V or 2.5V to 1.8V low noise regulator (LDO) for core and analog blocks •Enhanced power management feature with energy detect mode and soft power-down mode to ensure low-power dissipation during device idle periods •Comprehensive LED indicator support for link, activity and 10/100 speed (2 LEDs)– User programmable•Low-power CMOS design•Commercial Temperature Range: 0o C to +70o C •Industrial Temperature Range: –40o C to +85o C •Available in 32-pin (5mm x 5mm) MLF® package Additional FeaturesIn addition to offering all of the features of a Layer 2 controller, the KSZ8851SNL offers:•Supports to add two-byte before frame header in order for IP frame content with double word boundary• Micrel LinkMD® cable diagnostic capabilities to determine cable length, diagnose faulty cables, anddetermine distance to fault• Wake-on-LAN functionality– Incorporates Magic Packet™, wake-up frame, network link state, and detection of energy signal technology •HP Auto MDI-X™ crossover with disable/enable option •Ability to transmit and receive frames up to 2000 bytes Network Features•10BASE-T and 100BASE-TX physical layer support •Auto-negotiation: 10/100 Mbps full and half duplex• Adaptive equalizer• Baseline wander correctionApplications• Video/Audio Distribution Systems•Voice over IP (VoIP) and Analog Telephone Adapters (ATA)• Building Automation•Home Base Control with Ethernet Connection •Industrial Control Sensor Devices (Temperature, Pressure, Levels, and Valves)•Security, Motion Control and Surveillance Cameras Markets• Fast Ethernet• Embedded Ethernet• Industrial Ethernet• Embedded SystemsOrdering InformationPart Number Temperature Range Package Lead FinishKSZ8851SNL TR 0o C to 70o C 32-Pin MLF® (QFN per JDEC)Pb-FreeMLF® (QFN per JDEC) Pb-FreeKSZ8851SNLI TR –40o C to +85o C 32-PinKSZ8851SNL-Eval Evaluation Board for the KSZ8851SNLRevision HistoryRevision Date Summary of Changes1.0 06/30/2008 First released Information.1.1 2/13/2009 Improved EDS Rating up to 6KV, revised Ordering Information and updated Table contentand description.2.0 8/31/2009 To tri-state the SO output when CSN is de-asserted. To use falling edge of SCLK to senddata out (SO) and to support 40MHz SPI clock rate. Change revision ID from “0” to “1” inCIDER (0xc0) register. To enable software read or write external EEPROM. Update pins5, 9, 23 description for 1.8V VDD_IO supply.ContentsPin Configuration (10)Pin Description (11)Strapping Options (12)Functional Description (13)Functional Overview (13)Power Management (13)Normal Operation Mode (13)Mode (13)DetectEnergyDownMode (14)PowerSoftMode (14)SavingPowerWake-on-LAN (14)Energy (14)ofDetectionLinkup (14)ofDetectionPacket (15)Wake-upMagicPacket (15)Physical Layer Transceiver (PHY) (16)Transmit (16)100BASE-TX100BASE-TXReceive (16)PLL Clock Synthesizer (Recovery) (16)only) (16)(100BASE-TXScrambler/De-scramblerTransmit (16)10BASE-TReceive (16)10BASE-TCrossover (17)AutoMDI/MDI-XStraight Cable (17)CrossoverCable (17)Negotiation (18)AutoLinkMD® Cable Diagnostics (19)Access (19)Usage (20)Media Access Control (MAC) Operation (20)Gap(IPG) (20)PacketInterAlgorithm (20)Back-OffCollision (20)LateControl (20)FlowBackpressure (21)Half-DuplexFunction (21)AddressFilteringGenerator (22)ClockInterface (SPI) (22)SerialPeripheralI/ORegisters Access Operation Timing (23)SPIInternalSPI TXQ/RXQ FIFOs Access Operation Timing (23)Queue Management Unit (QMU) (24)Transmit Queue (TXQ) Frame Format (24)Frame Transmitting Path Operation in TXQ (25)Frame Receiving Path Operation in RXQ (29)Driver Routine for Receive Packet from KSZ8851SNL to Host Processor (30)EEPROM Interface (31)Loopback Support (32)Near-end (Remote) Loopback (32)Far-end (Local) Loopback (32)SPI Interface to I/O Registers (33)I/O Registers (33)Internal I/O Registers Space Mapping (34)Register Map: MAC, PHY and QMU (40)Bit Type Definition (40)0x00 – 0x07: Reserved (40)Chip Configuration Register (0x08 – 0x09): CCR (40)0x0A – 0x0F: Reserved (40)Host MAC Address Registers: MARL, MARM and MARH (40)Host MAC Address Register Low (0x10 – 0x11): MARL (41)Host MAC Address Register Middle (0x12 – 0x13): MARM (41)Host MAC Address Register High (0x14 – 0x15): MARH (41)0x16 – 0x1F: Reserved (41)On-Chip Bus Control Register (0x20 – 0x21): OBCR (41)EEPROM Control Register (0x22 – 0x23): EEPCR (42)Memory BIST Info Register (0x24 – 0x25): MBIR (42)Global Reset Register (0x26 – 0x27): GRR (43)0x28 – 0x29: Reserved (43)Wakeup Frame Control Register (0x2A – 0x2B): WFCR (43)0x2C – 0x2F: Reserved (43)Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0 (43)Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1 (44)Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 (44)Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 (44)Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 (44)Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3 (44)0x3C – 0x3F: Reserved (45)Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0 (45)Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1 (45)Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 (45)Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 (45)Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 (45)Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3 (45)0x4C – 0x4F: Reserved (46)Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0 (46)Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1 (46)Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 (46)Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3 (47)0x5C – 0x5F: Reserved (47)Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC0 (47)Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC1 (47)Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0 (47)Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1 (47)Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2 (47)Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3 (48)0x6C – 0x6F: Reserved (48)Transmit Control Register (0x70 – 0x71): TXCR (48)Transmit Status Register (0x72 – 0x73): TXSR (48)Receive Control Register 1 (0x74 – 0x75): RXCR1 (49)Receive Control Register 2 (0x76 – 0x77): RXCR2 (50)TXQ Memory Information Register (0x78 – 0x79): TXMIR (51)0x7A – 0x7B: Reserved (51)Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR (51)Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR (52)TXQ Command Register (0x80 – 0x81): TXQCR (52)RXQ Command Register (0x82 – 0x83): RXQCR (53)TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR (54)RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR (54)0x88 – 0x8B: Reserved (55)RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR (55)RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR (55)Interrupt Enable Register (0x90 – 0x91): IER (55)Interrupt Status Register (0x92 – 0x93): ISR (56)0x94 – 0x9B: Reserved (57)RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR (57)TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR (57)MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0 (58)MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1 (58)MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2 (58)MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3 (58)0xA8 – 0xAF: Reserved (58)Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR (58)Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR (59)Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR (59)0xB6 – 0xBF: Reserved (59)Chip ID and Enable Register (0xC0 – 0xC1): CIDER (59)0xC2 – 0xC5: Reserved (59)Chip Global Control Register (0xC6 – 0xC7): CGCR (59)Indirect Access Control Register (0xC8 – 0xC9): IACR (59)0xCA – 0xCF: Reserved (60)Power Management Event Control Register (0xD4 – 0xD5): PMECR (60)Go-Sleep & Wake-Up Time Register (0xD6 – 0xD7): GSWUTR (61)PHY Reset Register (0xD8 – 0xD9): PHYRR (62)0xDA – 0xDF: Reserved (62)0xE0 – 0xE3: Reserved (62)PHY 1 MII-Register Basic Control Register (0xE4 – 0xE5): P1MBCR (62)PHY 1 MII-Register Basic Status Register (0xE6 – 0xE7): P1MBSR (63)PHY 1 PHY ID Low Register (0xE8 – 0xE9): PHY1ILR (64)PHY 1 PHY ID High Register (0xEA – 0xEB): PHY1IHR (64)PHY 1 Auto-Negotiation Advertisement Register (0xEC – 0xED): P1ANAR (64)PHY 1 Auto-Negotiation Link Partner Ability Register (0xEE – 0xEF): P1ANLPR (64)0xF0 – 0xF3: Reserved (65)Port 1 PHY Special Control/Status, LinkMD (0xF4 – 0xF5): P1SCLMD (65)Port 1 Control Register (0xF6 – 0xF7): P1CR (66)Port 1 Status Register (0xF8 – 0xF9): P1SR (67)0xFA – 0xFF: Reserved (68)MIB (Management Information Base) Counters (69)Additional MIB Information (70)Absolute Maximum Ratings (71)Operating Ratings (71)Electrical Characteristics (71)Timing Specifications (73)SPI Input and Output Timing (73)Auto Negotiation Timing (74)Timing (75)ResetTiming (76)EEPROMSelection of Isolation Transformers (77)Selection of Reference Crystal (77)Package Information (78)Acronyms and Glossary (79)Figure 1. KSZ8851SNL/SNLI Functional Diagram (1)Figure 2. 32-Pin (5mm x 5mm) MLF® (10)Figure 3. Typical Straight Cable Connection (17)Figure 4. Typical Crossover Cable Connection (18)Figure 5. Auto Negotiation and Parallel Operation (19)Figure 6. SPI Interface to KSZ8851SNL (22)Figure 7. Internal I/O Register Read Timing (23)Figure 8. Internal I/O Register Write Timing (23)Figure 9. RXQ FIFO Read Timing (24)Figure 10. TXQ FIFO Write Timing (24)Figure 11. Host TX Single Frame in Manual Enqueue Flow Diagram (27)Figure 12. Host TX Multiple Frames in Auto- Enqueue Flow Diagram (28)Figure 13. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram (30)Figure 14. PHY Port 1 Near-end (Remote) and Host Far-end (Local) Loopback Paths (32)Figure 15. SPI Interface Data Input Timing (73)Figure 16. SPI Interface Data Output Timing (73)Figure 17. Auto Negotiation Timing (74)Figure 18. Reset Timing (75)Figure 19. EEPROM Read Cycle Timing Diagram (76)Figure 20. 32-Pin (5mm x 5mm) MLF® (QFN per JDEC) Package (78)Table 1. Internal Function Blocks Status (13)Table 2. MDI/MDI-X Pin Definitions (17)Table 3. Address Filtering Scheme (21)Table 4. SPI Operation for Registers Access (22)Table 5. SPI Operation for TXQ/RXQ FIFO Access (23)Table 6. Frame Format for Transmit Queue (25)Table 7. Transmit Control Word Bit Fields (25)Table 8. Transmit Byte Count Format (25)Table 9. Registers Setting for Transmit Function Block (26)Table 10. Frame Format for Receive Queue (29)Table 11. Registers Setting for Receive Function Block (29)Table 12. KSZ8851SNL EEPROM Format (31)Table 13. Format of MIB Counters (69)Table 14. Port 1 MIB Counters Indirect Memory Offsets (70)Table 15. Electrical Characteristics (72)Table 16. SPI Data Input and Output Timing Parameters (73)Table 17. Auto Negotiation Timing Parameters (74)Table 18. Reset Timing Parameters (75)Table 19. EEPROM Timing Parameters (76)Table 20. Transformer Selection Criteria (77)Table 21. Qualified Single Port Magnetics (77)Table 22. Typical Reference Crystal Characteristics (77)Pin ConfigurationFigure 2. 32-Pin (5mm x 5mm) MLF®Pin DescriptionPin Number Pin Name Type Pin FunctionOpu1 LED0Programmable LED output to indicate PHY activity/status.LED is ON when output is LOW; LED is OFF when output is HIGH.LED indicators1 defined as follows:Chip Global Control Register: CGCR bit [9]0 (Default) 1LED1 (pin 32) 100BT ACTLED0 (pin 1) LINK/ACT LINKLink (up) = LED On; Activity = LED Blink; Link/Act = LED On/Blink;Speed = LED On (100BASE-T); LED Off (10BASE-T)2 PME Opu Power Management Event (default active low)It is asserted (low or high depends on polarity set in PMECR register) when one of thewake-on-LAN events is detected by KSZ8851SNL. The KSZ8851SNL is requesting thesystem to wake up from low power mode.InterruptNot3INTRN OpuAn active low signal to host CPU to indicate an interrupt status bit is set. This pin needsan external 4.7K pull-up resistor.4 DGND Gnd Digital IO ground.5 VDD_CO1.8 P 1.8V regulator output . This 1.8V output pin provides power to pins 9 (VDD_A1.8) and 23(VDD_D1.8) for core VDD supply.If VDD_IO is set for 1.8V then this pin should be left floating, pins 9 (VDDA_1.8) and 23(VDD_D1.8) will be sourced by the external 1.8V supply that is tied to pins 25 and 30(VDD_IO) with appropriate filtering.6 EED_IO Ipd/O In/Out Data from/to external EEPROMConfig Mode: The pull-up/pull-down value is latched as with/without EEPROM duringpower-up / reset. See “Strapping Options” section for details.7 EESK Opd EEPROM Serial ClockA 4μs (OBCR[1:0]=11 on-chip bus speed @ 25MHz) or 800ns (OBCR[1:0]=00 on-chipbus speed @ 125 MHz) serial output clock to load configuration data from the serialEEPROM.ground.Analog8 AGNDGnd9 VDD_A1.8 P 1.8V analog power supply from VDD_CO1.8 (pin 5) with appropriate filtering. If VDD_IO is1.8V, this pin must be supplied power from the same source as pins 25 and 30 (VDD_IO)with appropriate filtering.10 EECS Opd EEPROM Chip SelectThis signal is used to select an external EEPROM device.11 RXP I/O Physical receive (MDI) or transmit (MDIX) signal (+ differential).12 RXM I/O Physical receive (MDI) or transmit (MDIX) signal (– differential).Analogground.Gnd13 AGND14 TXP I/O Physical transmit (MDI) or receive (MDIX) signal (+ differential).15 TXM I/O Physical transmit (MDI) or receive (MDIX) signal (– differential).16 VDD_A3.3 P 3.3V analog V DD input power supply with well decoupling capacitors.17 ISET O Set physical transmits output current.Pull-down this pin with a 3.01K 1% resistor to ground.ground.Analog18 AGNDGndNot.ResetIpu19 RSTNPin NumberPin NameTypePin FunctionHardware reset pin (active Low). This reset input must be held low for a minimum of 10ms after stable supply voltage 3.3V.20 X1 I 21 X2 O25MHz crystal or oscillator clock connection.Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerantoscillator and X2 is a no connect. Note: Clock requirement is +/- 50ppm for either crystal or oscillator. 22 DGND Gnd Digital IO ground23VDD_D1.8P1.8V digital power supply from VDD_CO1.8 (pin 5) with appropriate filtering. If VDD_IO is 1.8V, this pin must be supplied power from the same source as pins 25 and 30 (VDD_IO) with appropriate filtering. 24 DGND Gnd Digital IO ground25 VDD_IO P 3.3V, 2.5V or 1.8V digital V DD input power supply for IO with well decoupling capacitors. 26CSNIpuSPI slave mode: Chip Select Not Active low input pin for SPI interface.27SOOSPI slave mode: Serial data out for SPI interface. This SO is tri-stated output when CSN is negated and this pin must have external 4.7K pull-up to keep the SO line high while the driver is tri-stated.28 SCLK I SPI slave mode: Serial clock input for SPI interface. This clock speed can run up to 40MHz.29 DGND Gnd Digital IO ground30 VDD_IO P 3.3V, 2.5V or 1.8V digital V DD input power supply for IO with well decoupling capacitors. 31 SI Ipd SPI slave mode: Serial data in for SPI interface.32LED1OpuProgrammable LED1 output to indicate PHY activity/status (see LED0 description at pin1)Legend:P = Power supply Gnd = GroundI/O = Bi-directional I = Input O = Output.Ipd = Input with internal pull-down (58K +/-30%). Ipu = Input with internal pull-up (58K +/-30%).Opd = Output with internal pull-down (58K +/-30%). Opu = Output with internal pull-up (58K +/-30%).Ipu/O = Input with internal pull-up (58K +/-30%) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (58K +/-30%) during power-up/reset; output pin otherwise.Strapping OptionsPin NumberPin NameTypePin Function6 EED_IO Ipd/O EEPROM select:Pull-up = EEPROM presentFloating (NC) or Pull-down = EEPROM not present (default)During power-up / reset, this pin value is latched into register CCR, bit 9Note: Ipd/O = Input with internal pull-down (58K +/-30%) during power-up/reset; output pin otherwise. Pin strap-ins are latched during power-up or reset.Functional DescriptionThe KSZ8851SNL is a single-chip Fast Ethernet MAC/PHY controller consisting of a 10/100 physical layer transceiver (PHY), a MAC, and an industry standard Serial Peripheral Interface (SPI). The host CPU is via SPI interface to read/writeKSZ8851SNL internal registers either byte (8-bit), word (16-bit) or double word (32-bit) and to access KSZ8851SNLRXQ/TXQ FIFOs for packet receive/transmit.The KSZ8851SNL is fully compliant to IEEE802.3u standards.Functional OverviewPower ManagementThe KSZ8851SNL supports enhanced power management feature in low power state with energy detection to ensure low-power dissipation during device idle periods. There are four operation modes under the power management functionwhich is controlled by two bits in PMECR (0xD4) register as shown below:PMECR[1:0] = 00 Normal Operation ModePMECR[1:0] = 01 Energy Detect ModePMECR[1:0] = 10 Soft Power Down ModePMECR[1:0] = 11 Power Saving ModeTable 1 indicates all internal function blocks status under four different power management operation modes.KSZ8851SNLPower Management Operation ModesFunction Blocks Normal mode Power saving mode Energy detect mode Soft power down mode Internal PLL Clock Enabled Enabled Disabled DisabledTx/Rx PHY Enabled Rx unused block disabled Energy detect at Rx DisabledDisabledDisabled MAC EnabledEnabledSPI Interface Enabled Enabled Disabled DisabledTable 1. Internal Function Blocks StatusNormal Operation ModeThis is the default setting bit[1:0]=00 in PMECR register after the chip power-up or hardware reset (pin 67). WhenKSZ8851SNL is in this normal operation mode, all PLL clocks are running, PHY and MAC are on and the host interface isready for CPU read or write.During the normal operation mode, the host CPU can set the bit[1:0] in PMECR register to transit the current normal operation mode to any one of the other three power management operation modes.Energy Detect ModeThe energy detect mode provides a mechanism to save more power than in the normal operation mode when theKSZ8851SNL is not connected to an active link partner. For example, if cable is not present or it is connected to a powered down partner, the KSZ8851SNL can automatically enter to the low power state in energy detect mode. Onceactivity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851SNL can automaticallypower up to normal power state in energy detect mode.Energy detect mode consists of two states, normal power state and low power state. While in low power state, theKSZ8851SNL reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. Theenergy detect mode is entered by setting bit[1:0]=01 in PMECR register. When the KSZ8851SNL is in this mode, it will monitor the cable energy. If there is no energy on the cable for a time longer than pre-configured value at bit[7:0] Go-Sleep time in GSWUTR register, KSZ8851SNL will go into a low power state. When KSZ8851SNL is in low power state, itwill keep monitoring the cable energy. Once the energy is detected from the cable and is continuously presented for atime longer than pre-configured value at bit[15:8] Wake-Up time in GSWUTR register, the KSZ8851SNL will enter eitherthe normal power state if the auto-wakeup enable bit[7] is set in PMECR register or the normal operation mode if bothauto-wakeup enable bit[7] and wakeup to normal operation mode bit[6] are set in PMECR register.The KSZ8851SNL will also assert PME output pin if the corresponding enable bit[8] is set in PMECR (0xD4) register or generate interrupt to signal an energy detect event occurred if the corresponding enable bit[2] is set in IER (0x90) register. Once the power management unit detects the PME output asserted or interrupt active, it will power up the host CPU and issue a wakeup command which is any one of registers read or write access to wake up the KSZ8851SNL from the low power state to the normal power state in case the auto-wakeup enable bit[7] is disabled. When KSZ8851SNL is at normal power state, it is able to transmit or receive packet from the cable.Soft Power Down ModeThe soft power down mode is entered by setting bit[1:0]=10 in PMECR register. When KSZ8851SNL is in this mode, all PLL clocks are disabled, the PHY and the MAC are off, all internal registers value will not change, and the host interface is only used to wake-up this device from current soft power down mode to normal operation mode.In order to go back the normal operation mode from this soft power down mode, the only way to leave this mode is through a host wake-up command which the CPU issues any one of registers read or write access.Power Saving ModeThe power saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting bit[1:0]=11 in PMECR register and bit [10]=1 in P1SCLMD register. When KSZ8851SNL is in this mode, all PLL clocks are enabled, MAC is on, all internal registers value will not change, and host interface is ready for CPU read or write. In this mode, it mainly controls the PHY transceiver on or off based on line status to achieve power saving. The PHY remains transmitting and only turns off the unused receiver block. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851SNL can automatically enabled the PHY power up to normal power state from power saving mode.During this power saving mode, the host CPU can program the bit[1:0] in PMECR register and set bit[10]=0 in P1SCLMD register to transit the current power saving mode to any one of the other three power management operation modes. Wake-on-LANWake-up frame events are used to wake the system whenever meaningful data is presented to the system over the network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote administrator, or simply network traffic directly targeted to the local system. In all of these instances, the network device is pre-programmed by the policy owner or other software with information on how to identify wake frames from other network traffic. The KSZ8851SNL controller can be programmed to notify the host of the wake-up frame detection with the assertion of the interrupt signal (INTRN) or assertion of the power management event signal (PME).A wake-up event is a request for hardware and/or software external to the network device to put the system into a powered state (working).A wake-up signal is caused by:1. Detection of energy signal over a pre-configured value (bit 2 in ISR register)2. Detection of a linkup in the network link state (bit 3 in ISR register)3. Receipt of a Magic Packet (bit 4 in ISR register)4. Receipt of a network wake-up frame (bit 5 in ISR register)There are also other types of wake-up events that are not listed here as manufacturers may choose to implement these in their own way.Detection of EnergyThe energy is detected from the cable and is continuously presented for a time longer than pre-configured value, especially when this energy change may impact the level at which the system should re-enter to the normal power state. Detection of LinkupLink status wake events are useful to indicate a linkup in the network’s connectivity status.。
浪潮存储系统 DP1000-M1 硬件维护手册说明书
浪潮存储系统DP1000-M1硬件维护手册V2.3尊敬的浪潮存储系统用户：衷心感谢您选用了浪潮存储系统！本手册介绍了浪潮存储DP1000-M1备份系统的技术特性与系统的安装、设置和使用，有助于您更详细地了解和便捷地使用本款存储系统。
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摘要手册介绍本存储系统的规格信息、硬件操作、软件设置、服务条款、故障诊断等与维护工作密切相关的内容。
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目标受众本手册主要适用于以下人员：●技术支持工程师●产品维护工程师建议由具备存储知识的专业工程师参考本手册进行存储运维操作。
目录摘要 (3)目标受众 (3)目录 (4)1安全说明 (6)2产品规格介绍 (11)2.1 简介 (11)2.2特性和规格 (12)2.3前面板 (13)2.4后面板 (15)2.5主板布局 (17)2.6主板跳线介绍 (19)3 BIOS设置 (20)3.1设置系统BIOS方法 (20)3.2 BIOS设置 (21)4 BMC设置 (64)4.1简介 (64)4.2功能模块 (64)4.3 Web界面介绍 (66)4.4远程控制 (70)4.5电源和散热 (71)4.6 BMC设置 (72)4.7日志 (76)4.8故障诊断 (77)4.9系统维护 (78)5硬件维护 (80)5.1工具准备 (80)5.2更换部件 (80)6常见故障及诊断排除 (95)6.1常见故障 (95)6.2诊断排除说明 (96)附录：环境声明 (98)1安全说明警告：以下警告表示存在可能导致财产损失、人身伤害或死亡的潜在危险。
适马 dp1 软件使用手册说明书
S I G M A P h o t o P r o用户手册此为适马数码相机之专用软件3.5 版重要事项:在开始使用本软件前，请先阅读以下条文多谢阁下选购适马产品。
为令阁下能够享受到本产品所提供之最佳效能；而不会导致任何损坏和受伤；请务必在使用本产品前，小心阅读本用户手册。
通告在未获得批准前，请勿以任何方式，另行编辑此手册之全部或部份内容。
警告 !!如忽视此警告标志，在使用本产品时可能会导致严重受伤或危险结果。
警告请不要将本产品内附之光盘放在音频光盘播放器内。
如使用本产品内附之光盘放在音乐光盘播放器内，并利用耳筒聆听，可能令听力受损。
而使用本产品内附之光盘放在音乐光盘目录重要事项在开始使用本软件前，请先阅读以下条文 : i 1 用戶手册简介 1目录4.1将图像从数码相机复制到个人计算机12将相机连接到计算机。
(12)将图像档案从相机转传到计算机。
(12)使用读卡器, 以复制图像到计算机。
(12)目录在主窗口内用幻灯片展示观看图像。
(19)6图像检视206.1检视窗口21开启检视窗口 (21)目录使用多重检视窗口作图像比较 (27)使用多重检视窗口的图像比较模式 (27)7图像处理和储存287.1在主窗口处理图像29目录阅览 矩形图 (Histogram) (37)在高光提示选择使用、不使用和数值设定 (37)8.5修改白平衡38在X3F档案中更改白平衡 (38)8.6更改色彩模式(只适用于D P2和S D15之R A W数据)381用戶手册简介在此章节中，你会学到…•Sigma Photo Pro 的主要特性。
•如何使用此用户手册。
1.1 关于 S I G M A P h o t o P r o你可以利用 SIGMA Photo Pro 作什么用途 ? 欢迎光临快速虚拟旅程 !以下是适马数码相机所用之SIGMA Photo Pro 图像处理软件的不同窗口和调色版。
请按入任何窗口和调色板，便可以跳到详细解说的画面里。
icprints普通用户使用手册
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NVIDIA DOCA DPU CLI 用户指南说明书
GuideTable of ContentsChapter 1. Introduction (1)Chapter 2. General Commands (2)Chapter 3. DPU/DOCA Commands (4)Chapter 1.IntroductionThis guide provides a concise guide on useful commands for DOCA deployment and configuration.This tables in this guide provide two categories of commands:‣General commands for Linux/networking environment‣DOCA/DPU-specific commandsNote: For more information about these commands, such as usage instructions, flagoptions, arguments and so on, use the -h option after the command or use the manual(e.g., man lspci).Chapter 2.General CommandsGeneral CommandsChapter 3.DPU/DOCA CommandsDPU/DOCA CommandsNoticeThis document is provided for information purposes only and shall not be regarded as a warranty of a certain functionality, condition, or quality of a product. NVIDIA Corporation nor any of its direct or indirect subsidiaries and affiliates (collectively: “NVIDIA”) make no representations or warranties, expressed or implied, as to the accuracy or completeness of the information contained in this document and assume no responsibility for any errors contained herein. NVIDIA shall have no liability for the consequences or use of such information or for any infringement of patents or other rights of third parties that may result from its use. This document is not a commitment to develop, release, or deliver any Material (defined below), code, or functionality.NVIDIA reserves the right to make corrections, modifications, enhancements, improvements, and any other changes to this document, at any time without notice.Customer should obtain the latest relevant information before placing orders and should verify that such information is current and complete.NVIDIA products are sold subject to the NVIDIA standard terms and conditions of sale supplied at the time of order acknowledgement, unless otherwise agreed in an individual sales agreement signed by authorized representatives of NVIDIA and customer (“Terms of Sale”). NVIDIA hereby expressly objects to applying any customer general terms and conditions with regards to the purchase of the NVIDIA product referenced in this document. No contractual obligations are formed either directly or indirectly by this document.NVIDIA products are not designed, authorized, or warranted to be suitable for use in medical, military, aircraft, space, or life support equipment, nor in applications where failure or malfunction of the NVIDIA product can reasonably be expected to result in personal injury, death, or property or environmental damage. NVIDIA accepts no liability for inclusion and/or use of NVIDIA products in such equipment or applications and therefore such inclusion and/or use is at customer’s own risk.NVIDIA makes no representation or warranty that products based on this document will be suitable for any specified use. Testing of all parameters of each product is not necessarily performed by NVIDIA. It is customer’s sole responsibility to evaluate and determine the applicability of any information contained in this document, ensure the product is suitable and fit for the application planned by customer, and perform the necessary testing for the application in order to avoid a default of the application or the product. Weaknesses in customer’s product designs may affect the quality and reliability of the NVIDIA product and may result in additional or different conditions and/or requirements beyond those contained in this document. NVIDIA accepts no liability related to any default, damage, costs, or problem which may be based on or attributable to: (i) the use of the NVIDIA product in any manner that is contrary to this document or (ii) customer product designs.No license, either expressed or implied, is granted under any NVIDIA patent right, copyright, or other NVIDIA intellectual property right under this document. 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Use of such information may require a license from a third party under the patents or other intellectual property rights of the third party, or a license from NVIDIA under the patents or other intellectual property rights of NVIDIA.Reproduction of information in this document is permissible only if approved in advance by NVIDIA in writing, reproduced without alteration and in full compliance with all applicable export laws and regulations, and accompanied by all associated conditions, limitations, and notices.THIS DOCUMENT AND ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS, AND OTHER DOCUMENTS (TOGETHER AND SEPARATELY, “MATERIALS”) ARE BEING PROVIDED “AS IS.” NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY, OR OTHERWISE WITH RESPECT TO THE MATERIALS, AND EXPRESSLY DISCLAIMS ALL IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE. 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Other company and product names may be trademarks of the respective companies with which they are associated.Copyright© 2023 NVIDIA Corporation & affiliates. All rights reserved.NVIDIA Corporation | 2788 San Tomas Expressway, Santa Clara, CA 95051。
Intel oneAPI DPC++ Library 用户指南说明书
Get Started with the Intel® oneAPI DPC ++ LibraryGet Started with the Intel® oneAPI DPC++ LibraryContentsChapter 1: Get Started with the Intel® oneAPI DPC++ Library 2Get Started with the Intel® oneAPI DPC++ Library 1Intel® oneAPI DPC++ Library (oneDPL) works with the Intel® oneAPI DPC++/C++ Compiler to provide high-productivity APIs to developers, which can minimize SYCL* programming efforts across devices for high performance parallel applications.oneDPL consists of the following components:•Parallel API•API for SYCL Kernels•MacrosFor general information about oneDPL, visit the oneDPL GitHub* repository, or visit the Intel® oneAPI DPC++ Library Guide and the Intel® oneAPI DPC++ Library main page.Quick StartInstallationVisit the oneDPL Release Notes page for:•Where to Find the Release•Overview•New Features•Fixed Issues•Known Issues and LimitationsInstall the Intel® oneAPI Base Toolkit (Base Kit) to use oneDPL.To use Parallel API, include the corresponding header files in your source code.All oneDPL header files are in the oneapi/dpl directory. Use #include <oneapi/dpl/…> to include them. oneDPL uses the namespace oneapi::dpl for most its classes and functions.To use tested C++ standard APIs, you need to include the corresponding C++ standard header files and use the std namespace.pkg-config SupportThe pkg-config program is used to retrieve information about your installed libraries, and to compile and link against one or more libraries.Use pkg-config with oneDPLUse pkg-config with the --cflags flag to get the include path to the oneDPL directory:dpcpp test.cpp $(pkg-config --cflags dpl)The --msvc-syntax flag is required when you use a Microsoft Visual C++* compiler. This flag converts your compiling and linking flags to the appropriate form:dpcpp test.cpp $(pkg-config --msvc-syntax --cflags dpl)NOTE Use the pkg-config tool to get rid of large hard-coded paths and make compilation moreportable.Usage Examples31 Get Started with the Intel® oneAPI DPC++ LibraryoneDPL sample code is available from the oneAPI GitHub samples repository. Each sample includes a readme with build instructions.<oneapi/dpl/random> Header Usage ExampleThis example illustrates oneDPL random number generator usage. The sample below shows you how to create an random number generator engine object (the source of pseudo-randomness), a distribution object (specifying the desired probability distribution), and how to generate the random numbers themselves. Random number generation is performed in a vectorized manner to improve the speed of your computations. This example performs its computations on your default SYCL device. You can set the SYCL_DEVICE_TYPE environment variable to CPU or GPU.template<int VecSize>void random_fill(float* usmptr, std::size_t n) {auto zero = oneapi::dpl::counting_iterator<std::size_t>(0);std::for_each(oneapi::dpl::execution::dpcpp_default,zero, zero + n/VecSize,[usmptr](std::size_t i) {auto offset = i * VecSize;oneapi::dpl::minstd_rand_vec<VecSize> engine(seed, offset);oneapi::dpl::uniform_real_distribution<sycl::vec<float, VecSize>> distr;auto res = distr(engine);res.store(i, sycl::global_ptr<float>(usmptr));});}Pi Benchmark Usage ExampleThis example uses a Monte Carlo method to estimate the value of π. The basic idea is to generate random points within a square, and to check what fraction of these random points lie in a quarter-circle inscribed within that square. The expected value is the ratio of the areas of the quarter-circle and the square (π/4). You can take the observed fraction of points in the quarter-circle as an estimate of π/4.This example shows you how to create an random number generator engine object (the source of pseudo-randomness), a distribution object (specifying the desired probability distribution), generate the random numbers themselves, and then perform a reduction to count quantity of points that fit into the square S. Random number generation is performed in scalar manner to simplify your code.4Get Started with the Intel® oneAPI DPC++ Library 1float estimated_pi;{sycl::queue q(sycl::gpu_selector{});auto policy = oneapi::dpl::execution::make_device_policy(q);float sum = std::transform_reduce( policy,oneapi::dpl::counting_iterator<int>(0),oneapi::dpl::counting_iterator<int>(N),0.0f,std::plus<float>{},[=](int n){float local_sum = 0.0f;oneapi::dpl::minstd_rand engine(SEED, n * ITER * 2);oneapi::dpl::uniform_real_distribution<float> distr;for(int i = 0; i < ITER; ++i) {float x = distr(engine);float y = distr(engine);if (x * x + y * y <= 1.0)local_sum += 1.0;}return local_sum / (float)ITER;});estimated_pi = 4.0f * (float)sum / N;}Find More51 Get Started with the Intel® oneAPI DPC++ Library6。
mfc-dp01系列说明书
MFC-DP01系列多功能打印设备使用说明书MFC-DP01系列是一款多功能打印设备，具有打印、复印和扫描等多种功能。
以下是MFC-DP01系列的使用说明书：一、产品简介MFC-DP01系列是一款高品质的打印设备，适用于家庭、办公室等多种场合。
该系列打印机具有打印、复印和扫描等功能，可以满足用户的不同需求。
二、使用步骤1. 连接打印机将打印机与电脑或其他设备进行连接。
请确保使用正确的连接线或设置正确的网络连接。
2. 安装驱动程序在电脑上下载并安装相应的驱动程序。
请确保选择正确的驱动程序版本，以确保设备正常工作。
3. 打开文档或图像打开需要打印的文档或图像，并进行必要的编辑和设置。
4. 选择打印选项在打印机的操作界面中选择打印选项，根据需要选择打印份数、纸张大小、质量等参数。
5. 开始打印确认设置无误后，点击“开始打印”按钮，等待打印完成。
6. 复印功能将需要复印的文档或图像放置在打印机上，选择复印选项，根据需要选择复印份数、纸张大小等参数，点击“开始复印”按钮即可。
7. 扫描功能将扫描仪与打印机连接，打开扫描软件，将需要扫描的文档或图像放置在扫描仪上，根据需要选择扫描分辨率、格式等参数，点击“开始扫描”按钮即可。
三、注意事项1. 在使用过程中，请勿随意拆卸打印机或扫描仪，以免造成损坏。
2. 请勿在打印机附近放置易燃物品或液体，以免引起火灾或污染打印机。
3. 在使用过程中，请勿触摸打印头或激光扫描仪等高温部位，以免造成烫伤。
4. 在使用过程中，请勿在打印机附近使用手机或传呼机等通讯设备，以免干扰打印机的正常运行。
5. 在使用过程中，请定期清理打印机的废墨盒和纸张通道，以确保打印质量。
6. 请勿使用假冒伪劣的墨盒或纸张，以免引起打印机故障或降低打印质量。
7. 在使用过程中，如遇到任何问题或故障，请及时联系产品厂家或专业维修人员进行处理。
四、产品维护与保养1. 定期清理打印机表面和内部的灰尘和污垢，以确保设备的正常运行和保持良好的外观。
Intel oneAPI DPC++ C++编译器简介说明书
Get Started with the Intel® oneAPI DPC ++/C++ CompilerGet Started with the Intel® oneAPI DPC++/C++ CompilerContentsChapter 1: Get Started with the Intel® oneAPI DPC++/C++ Compiler Get Started on Linux* (4)Get Started on Windows* (7)Compile and Execute Sample Code (10)2Get Started with the Intel® oneAPI DPC++/C++ Compiler 1The Intel® oneAPI DPC++/C++ Compiler provides optimizations that help your applications run faster onIntel® 64 architectures on Windows* and Linux*, with support for the latest C, C++, and SYCL languagestandards. This compiler produces optimized code that can run significantly faster by taking advantage of the ever-increasing core count and vector register width in Intel® Xeon® processors and compatible processors.The Intel® Compiler will help you boost application performance through superior optimizations and SingleInstruction Multiple Data (SIMD) vectorization, integration with Intel® Performance Libraries, and byleveraging the OpenMP* 5.0/5.1 parallel programming model.The Intel® oneAPI DPC++/C++ Compiler compiles C++-based SYCL* source files for a wide range ofcompute accelerators.The Intel® oneAPI DPC++/C++ Compiler is part of the Intel® oneAPI Toolkits.Find MoreNotices and DisclaimersIntel technologies may require enabled hardware, software or service activation.No product or component can be absolutely secure.31 Get Started with the Intel® oneAPI DPC++/C++ CompilerYour costs and results may vary.© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.Get Started on Linux*Before You BeginSet Environment VariablesBefore you can use the compiler, you must first set the environment variables by sourcing the environment script using the initialization utility. This initializes all the tools in one step.1.Determine your installation directory,<install_dir>:a.If your compiler was installed in the default location by a root user or sudo user, the compiler willbe installed under/opt/intel/oneapi. In this case, <install_dir> is /opt/intel/oneapi.b.For non-root users, your home directory under intel/oneapi is used. In this case,<install_dir> will be $HOME/intel/oneapi.c.For cluster or enterprise users, your admin team may have installed the compilers on a sharednetwork file system. Check with your local admin staff for the location of installation(<install_dir>).2.Source the environment-setting script for your shell:a.bash: source <install_dir>/setvars.sh intel64b.csh/tcsh: source <install_dir>/setvars.csh intel64Install GPU Drivers or Plug-ins (Optional)You can develop oneAPI applications using C++ and SYCL* that will run on Intel, AMD*, or NVIDIA* GPUs. To develop and run applications for specific GPUs you must first install the corresponding drivers or plug-ins:•To use an Intel GPU, install the latest Intel GPU drivers.•To use an AMD GPU, install the oneAPI for AMD GPUs plugin from Codeplay.•To use an NVIDIA GPU, install the oneAPI for NVIDIA GPUs plugin from Codeplay.Option 1: Use the Command Line®4Get Started with the Intel® oneAPI DPC++/C++ Compiler 1Invoke the compiler using the following syntax:{compiler driver} [option] file1 [file2...]For example:icpx hello-world.cppFor SYCL compilation, use the -fsycl option with the C++ driver:icpx -fsycl hello-world.cppNOTE When using -fsycl, -fsycl-targets=spir64 is assumed unless the -fsycl-targets isexplicitly set in the command.51 Get Started with the Intel® oneAPI DPC++/C++ CompilerIf you are targeting an AMD or NVIDIA GPU, refer to the corresponding Codeplay plugin get started guide for detailed compilation instructions:•oneAPI for AMD GPUs Get Started Guide•oneAPI for NVIDIA GPUs Get Started GuideOption 2: Use the Eclipse* CDTFollow these steps to invoke the compiler from within the Eclipse* CDT.Install the Intel® Compiler Eclipse CDT plugin.1.Start Eclipse2.Select Help > Install New Software3.Select Add to open the Add Site dialog4.Select Archive, browse to the directory <install_dir>/compiler/<version>/linux/ide_support,select the .zip file that starts with piler, then select OK5.Select the options beginning with Intel, select Next, then follow the installation instructions6.When asked if you want to restart Eclipse*, select YesBuild a new project or open an existing project.1.Open Existing Project or Create New Project on Eclipse2.Right click on Project > Properties > C/C++ Build > Tool chain Editor3.Select Intel DPC++/C++ Compiler from the right panelSet build configurations.1.Open Existing Project on Eclipse2.Right click on Project > Properties > C/C++ Build > Settings3.Create or manage build configurations in the right panelBuild a Program From the Command LineUse the following steps to test your compiler installation and build a program.e a text editor to create a file called hello-world.cpp with the following contents:#include <iostream>int main(){std::cout << “Hello, world!\n”;return 0;}pile hello-world.cpp:icpx hello-world.cpp -o hello-worldThe -o option specifies the file name for the generated output.3.Now you have an executable called hello-world which can be run and will give immediate feedback: hello-worldWhich outputs:Hello, world!You can direct and control compilation with compiler options. For example, you can create the object file and output the final binary in two steps:6Get Started with the Intel® oneAPI DPC++/C++ Compiler 1 pile hello-world.cpp:icpx hello-world.cpp -cThe -c option prevents linking at this step.e the icpx compiler to link the resulting application object code and output an executable:icpx hello-world.o -o hello-worldThe -o option specifies the generated executable file name.Refer to Compiler Options for details about available options.© Codeplay Software Limited. Intel, the Intel logo, Codeplay, Codeplay logo and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Get Started on Windows*Before You BeginSet Environment VariablesThe compiler integrates into the following versions of Microsoft Visual Studio*:•Visual Studio 2022•Visual Studio 2019•Visual Studio 2017NOTE Support for Microsoft Visual Studio 2017 is deprecated as of the Intel® oneAPI 2022.1 release and will be removed in a future release.For full functionality within Visual Studio, including debugging and development, Visual Studio Community Edition or higher is required. Visual Studio Express Edition allows only command-line builds. For all versions, Microsoft C++ support must be selected as part of the Visual Studio install. For Visual Studio 2017 and later, you must use a custom install to select this option.You typically do not need to set the environment variables on Windows, as the compiler command-line window sets these variables for you automatically. If you need to set the environment variables, run the environment script as described in the suite-specific Get Started documentation.The default installation directory (<install_dir>) is C:\Program Files (x86)\Intel\oneAPI.Install GPU Drivers (Optional)To develop and run applications for Intel GPUs you must first install the latest Intel GPU drivers.Option 1: Use the Command Line in Microsoft Visual Studio®71 Get Started with the Intel® oneAPI DPC++/C++ CompilerInvoke the compiler using the following syntax:{compiler driver} [option] file1 [file2...]To invoke the compiler using the command line from within Microsoft Visual Studio, open a command prompt and enter your compilation command. For example:icx hello-world.cppFor SYCL compilation, use the -fsycl option with the C++ driver:icx -fsycl hello-world.cpp8Get Started with the Intel® oneAPI DPC++/C++ Compiler 1 NOTE When using -fsycl, -fsycl-targets=spir64 is assumed unless the -fsycl-targets isexplicitly set in the command.Option 2: Use Microsoft Visual StudioProject Support for the Intel® DPC++/C++ Compiler in Microsoft Visual StudioNew Microsoft Visual Studio projects for DPC++ are automatically configured to use the Intel® oneAPI DPC+ +/C++ Compiler.New Microsoft Visual C++* (MSVC) projects must be manually configured to use the Intel® oneAPI DPC++/C ++ Compiler.NOTE .NET-based CLR C++ project types are not supported by the Intel® oneAPI DPC++/C++Compiler. The specific project types will vary depending on your version of Visual Studio, for example: CLR Class Library, CLR Console App, or CLR Empty Project.Use the Intel® DPC++/C++ Compiler in Microsoft Visual StudioExact steps may vary depending on the version of Microsoft Visual Studio in use.1.Create a Microsoft Visual C++ (MSVC) project or open an existing project.2.In Solution Explorer, select the project(s) to build with the Intel® oneAPI DPC++/C++ Compiler.3.Open Project > Properties .4.In the left pane, expand the Configuration Properties category and select the General propertypage.5.In the right pane change the Platform Toolset to the compiler you want to use:•For C++ with SYCL, select Intel® oneAPI DPC++ Compiler.•For C/C++, there are two toolsets.Select Intel C++ Compiler <major version> (example 2021) to invoke icx.Select Intel C++ Compiler <major.minor> (example 19.2) to invoke icl.Alternatively, you can specify a compiler version as the toolset for all supported platforms andconfigurations of the selected project(s) by selecting Project > Intel Compiler > Use InteloneAPI DPC++/C++ Compiler.6.Rebuild, using either Build > Project only > Rebuild for a single project or Build > RebuildSolution for a solution.Select Compiler VersionIf you have multiple versions of the Intel® oneAPI DPC++/C++ Compiler installed, you can select which version you want from the Compiler Selection dialog box:1.Select a project, then go to Tools > Options > Intel Compilers and Libraries > <compiler> >Compilers, where <compiler> values are C++ or DPC++.e the Selected Compiler drop-down menu to select the appropriate version of the compiler.3.Select OK.Switch Back to the Microsoft Visual Studio C++ CompilerIf your project is using the Intel® oneAPI DPC++/C++ Compiler, you can choose to switch back to the Microsoft Visual C++ compiler:1.Select your project in Microsoft Visual Studio.2.Right-click and select Intel Compiler > Use Visual C++ from the context menu.91 Get Started with the Intel® oneAPI DPC++/C++ CompilerThis action updates the solution file to use the Microsoft Visual Studio C++ compiler. All configurations of affected projects are automatically cleaned unless you select Do not clean project(s). If you choose not to clean projects, you will need to rebuild updated projects to ensure all source files are compiled with the new compiler.Build a Program From the Command LineUse the following steps to test your compiler installation and build a program.e a text editor to create a file called hello-world.cpp with the following contents:#include <iostream>int main(){std::cout << “Hello, world!\n”;return 0;}pile hello-world.cpp:icx hello-world.cpp3.Now you have an executable called hello-world.exe which can be run and will give immediatefeedback:hello-world.exeWhich outputs:Hello, world!You can direct and control compilation with compiler options. For example, you can create the object file and output the final binary in two steps:pile hello-world.cpp:icx hello-world.cpp /c /Fohello-world.objThe /c option prevents linking at this step and /Fo specifies the name for the object file.e the icx compiler to link the resulting application object code and output an executable:icx hello-world.obj /Fehello-world.exeThe /Fe option specifies the generated executable file name.Refer to Compiler Options for details about available options.Compile and Execute Sample CodeMultiple code samples are provided for the Intel® oneAPI DPC++/C++ Compiler so that you can explore compiler features and familiarize yourself with how it works. For example:Sample Project DescriptionOpenMP Offload Sample The OpenMP* Offload sample demonstrates someof the new OpenMP Offload features supported bythe Intel® oneAPI DPC++/C++ Compiler.10Get Started with the Intel® oneAPI DPC++/C++ Compiler 1 Base: Vector Add Sample The Vector Add sample is the equivalent of a 'Hello,World!' sample for data parallel programs. Buildingand running the code sample verifies that yourdevelopment environment is set up correctly anddemonstrates the use of the core features of DPC++.Matrix Multiply Sample The Matrix Multiply sample is a simple program thatmultiplies together two large matrices and verifiesthe results. This program is implemented in twoways: Using Data Parallel C++ (DPC++) and usingOpenMP (OMP).Adaptive Noise Reduction Sample The Adaptive Noise Reduction sample is a DPC++reference design that demonstrates a highlyoptimized image sensor adaptive noise reduction(ANR) algorithm on an FPGA.Next Steps•Use the latest oneAPI Code Samples and follow along with the Intel® oneAPI Training Resources.•Explore the Intel® oneAPI DPC++/C++ Compiler Developer Guide and Reference on the Intel® Developer Zone.11。
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基本操作 曝光模式选择
37 37
自动模式 ...............................................................................37 P 程序式自动曝光 .....................................................................39 A 光圈先决自动曝光 .................................................................40 S 快门先决自动曝光 .................................................................41 M 手动控制曝光 ........................................................................42
• SD
记忆卡是不包含在标准包装配件内。阁下可自行选购所需品牌、 容量、型号 。
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随机包装 ／ 配件内容 ......................................................................2 目 录 ..........................................................................................3 安全注意事项 ................................................................................6 相机保护及留意事项 ......................................................................9 相机各部件说明 .......................................................................... 11 彩色 LCD 显示屏提示 ..................................................................13 基本操作和快速参考 ....................................................................14
使用内置闪光灯
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使用内置闪光灯 ..........................................................................43
3
对 焦
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如何自动对焦 ..............................................................................45 AF 对焦范围选择 .........................................................................46 对焦锁定 .....................................................................................46 手动对焦 .....................................................................................47
检视及删除图像 快速预视
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准备事项
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肩带安装 .....................................................................................17 镜头遮盖 .....................................................................................18 装置电池 .....................................................................................19 电量检查 / 显示 .............................................................................22 使用室内交流电源供应操作 ( 另外购置 ) ........................................23 语言显示 .....................................................................................24 时间、日期设定 ..........................................................................25 数码相机设定选单 .......................................................................26 选单功能列表 ..............................................................................28 更改彩色 LCD 显示屏之显示画面 ...............................................32 安装及移除记忆卡 .......................................................................33 记忆卡格式化 ..............................................................................35 快门释放钮 .................................................................................36
进阶功能操作
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调整设定白平衡（ WB） ..............................................................50 感光度（ ISO ）设定 .....................................................................53 图像档案设定 ..............................................................................54 图像参数和色域 ..........................................................................55 测光模式选择 ..............................................................................57 自动曝光锁定 ..............................................................................58 曝光补偿 .....................................................................................60 自动包围曝光 ..............................................................................61 图像色彩设定 ..............................................................................63 数码变焦 .....................................................................................64 附声音图像 .................................................................................65 使用外置闪光灯 ..........................................................................66
Foveon, Inc. 商标。 ■ IBM PC/AT 系列计算机是 International Business Machines Corporation (IBM) 在美国的之商标或注册商标。 ■ Microsoft 和 Windows 是在美国和其它国家的 Microsoft Corporation 之注册商标或商标。 ■ Macintosh 和 MAC OS 是在美国和其它国家的 Apple Inc. 之注册商标。 ■ Adobe 和 Photoshop 均为 Adobe Systems Incorporated 之注册商标。 ■ 本手册内所述之其它公司和产品的名称均为它们公司或相关公司的商 标或注册商标持有者。
驱动模式操作
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单一拍摄 .....................................................................................48 连续拍摄 .....................................................................................49 自拍计时 .....................................................................................49