74HC595

© 2004 Fairchild Semiconductor Corporation DS005342September 1983Revised July 2004MM74HC595 8-Bit Shift Registers with Output LatchesMM74HC5958-Bit Shift Registers with Output LatchesGeneral DescriptionThe MM74HC595 high speed shift register utilizes advanced silicon-gate CMOS technology. This device pos-sesses the high noise immunity and low power consump-tion of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads.This device contains an 8-bit serial-in, parallel-out shift reg-ister that feeds an 8-bit D-type storage register. The stor-age register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register.The shift register has a direct-overriding clear, serial input,and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge trig-gered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register.The 74HC logic family is speed, function, and pin-out com-patible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to V CC and ground.Featuress Low quiescent current: 80 µA maximum (74HC Series)s Low input current: 1 µA maximums 8-bit serial-in, parallel-out shift register with storage s Wide operating voltage range: 2V–6V s Cascadables Shift register has direct clears Guaranteed shift frequency: DC to 30 MHzOrdering Code:Devices also available in T ape and Reel. Specify by appending the suffix letter “X ” to the ordering code.Connection Diagram Top ViewTruth TableOrder Number Package NumberPackage DescriptionMM74HC595M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC595SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WideMM74HC595MTC MTC1616-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC595NN16E16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" WideRCK SCK SCLR G FunctionX X X H Q A thru Q H = 3-STATE XXLLShift Register cleared Q ’H = 0X↑H L Shift Register clocked Q N = Q n-1, Q 0 = SER↑X H L Contents of Shift Register transferred to output latches 2M M 74H C 595Logic Diagram(positive logic)MM74HC595Absolute Maximum Ratings (Note 1)(Note 2)Recommended Operating ConditionsNote 1: Absolute Maximum Ratings are those values beyond which dam-age to the device may occur.Note 2: Unless otherwise specified all voltages are referenced to ground.Note 3: Power Dissipation temperature derating — plastic “N ” package: −12 mW/°C from 65°C to 85°C.DC Electrical Characteristics (Note 4)Note 4: For a power supply of 5V ±10% the worst case output voltages (V OH , and V OL ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case V IH and V IL occur at V CC = 5.5V and 4.5V respectively. (The V IH value at 5.5V is 3.85V.) The worst case leakage cur-rent (I IN , I CC , and I OZ ) occur for CMOS at the higher voltage and so the 6.0V values should be used.Supply Voltage (V CC )−0.5 to +7.0V DC Input Voltage (V IN )−1.5 to V CC +1.5V DC Output Voltage (V OUT )−0.5 to V CC +0.5VClamp Diode Current (I IK , I OK )±20 mA DC Output Current, per pin (I OUT )±35 mA DC V CC or GND Current,per pin (I CC )±70 mAStorage Temperature Range (T STG )−65°C to +150°CPower Dissipation (P D )(Note 3)600 mW S.O. Package only 500 mWLead Temperature (T L ) (Soldering 10 seconds)260°C MinMax Units Supply Voltage (V CC )26VDC Input or Output Voltage (V IN , V OUT )V CCVOperating Temperature Range (T A )−40+85°C Input Rise or Fall Times (t r , t f ) V CC = 2.0V1000ns V CC = 4.5V 500ns V CC = 6.0V400nsSymbol ParameterConditionsV CC T A = 25°C T A = −40 to 85°C T A = −55 to 125°C UnitsTypGuaranteed LimitsV IHMinimum HIGH Level 2.0V 1.5 1.5 1.5V Input Voltage4.5V 3.15 3.15 3.156.0V 4.2 4.2 4.2V ILMaximum LOW Level 2.0V 0.50.50.5V Input Voltage4.5V 1.35 1.35 1.356.0V1.81.81.8V OHMinimum HIGH Level V IN = V IH or V IL Output Voltage|I OUT | ≤ 20 µA2.0V 2.0 1.9 1.9 1.9V4.5V 4.5 4.4 4.4 4.46.0V6.05.95.95.9Q ’HV IN = V IH or V IL |I OUT | ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7V|I OUT | ≤ 5.2 mA6.0V5.25.485.345.2Q A thru Q HV IN = V IH or V IL |I OUT | ≤ 6.0 mA 4.5V 4.2 3.98 3.84 3.7V|I OUT | ≤ 7.8 mA6.0V5.75.485.345.2V OLMaximum LOW Level V IN = V IH or V IL Output Voltage|I OUT | ≤ 20 µA2.0V 00.10.10.1V4.5V 00.10.10.16.0V0.10.10.1Q ’HV IN = V IH or V IL |I OUT | ≤ 4 mA 4.5V 0.20.260.330.4V|I OUT | ≤ 5.2 mA6.0V0.20.260.330.4Q A thru Q HV IN = V IH or V IL |I OUT | ≤ 6.0 mA 4.5V 0.20.260.330.4V |I OUT | ≤ 7.8 mA6.0V 0.20.260.330.4I IN Maximum Input V IN = V CC or GND6.0V±0.1±1.0±1.0µACurrentI OZ Maximum 3-STATE V OUT = V CC or GND 6.0V±0.5±5.0±10µAOutput Leakage G = V IHI CCMaximum Quiescent V IN = V CC or GND 6.0V8.080160µASupply CurrentI OUT = 0 µA 4M M 74H C 595AC Electrical CharacteristicsV CC = 5V, T A = 25°C, t r = t f = 6 nsNote 5: This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be connected together in which case the stor-age register state will be one clock pulse behind the shift register.AC Electrical CharacteristicsV CC = 2.0−6.0V, C L = 50 pF, t r = t f = 6 ns (unless otherwise specified)Symbol ParameterConditions Typ GuaranteedUnits Limit f MAX Maximum Operating 5030MHz Frequency of SCK t PHL , t PLH Maximum Propagation C L = 45 pF 1220ns Delay, SCK to Q ’H t PHL , t PLH Maximum Propagation C L = 45 pF 1830nsDelay, RCK to Q A thru Q H t PZH , t PZL Maximum Output Enable R L = 1 k ΩTime from G to Q A thru Q H C L = 45 pF 1728ns t PHZ , t PLZ Maximum Output Disable R L = k Ω1525ns Time from G to Q A thru Q H C L = 5 pFt S Minimum Setup Time 20ns from SER to SCK t S Minimum Setup Time 20ns from SCLR to SCK t SMinimum Setup Time 40nsfrom SCK to RCK (Note 5)t H Minimum Hold Time 0ns from SER to SCK t WMinimum Pulse Width 16nsof SCK or RCKSymbol ParameterConditions V CC T A = 25°C T A = −40 to 85°C T A = −55 to 125°C UnitsTyp Guaranteed Limitsf MAXMaximum Operating C L = 50 pF2.0V 106 4.8 4.0MHz Frequency4.5V 453024206.0V 50352824t PHL , t PLH Maximum PropagationC L = 50 pF 2.0V 58210265315ns Delay from SCK to Q ’HC L = 150 pF 2.0V 83294367441C L = 50 pF 4.5V 14425363ns C L = 150 pF 4.5V 17587488C L = 50 pF 6.0V 10364554ns C L = 150 pF6.0V 14506376t PHL , t PLH Maximum PropagationC L = 50 pF 2.0V 70175220265ns Delay from RCK to Q A thru Q H C L = 150 pF2.0V 105245306368C L = 50 pF 4.5V 21354453ns C L = 150 pF 4.5V 28496174C L = 50 pF 6.0V 18303745ns C L = 150 pF6.0V 26425363t PHL , t PLH Maximum Propagation2.0V 175221261ns Delay from SCLR to Q ’H4.5V 3544526.0V303744t PZH , t PZL Maximum Output EnableR L = 1 k Ωfrom G to Q A thru Q HC L = 50 pF 2.0V 75175220265ns C L = 150 pF 2.0V 100245306368C L = 50 pF 4.5V 15354453ns C L = 150 pF 4.5V 20496174C L = 50 pF 6.0V 13303745nsC L = 150 pF6.0V17425363MM74HC595AC Electrical Characteristics (Continued)Note 6: C PD determines the no load dynamic power consumption, P D = C PD V CC 2f + I CC V CC , and the no load dynamic current consumption,I S = C PD V CC f + I CC .SymbolParameterConditions V CC T A = 25°C T A = −40 to 85°C T A = −55 to 125°C UnitsTyp Guaranteed Limits t PHZ , t PLZ Maximum Output DisableR L = 1 k Ω 2.0V 75175220265nsTime from G to Q A thru Q HC L = 50 pF4.5V 153544536.0V13303745t SMinimum Setup Time 2.0V 100125150nsfrom SER to SCK4.5V 2025306.0V 172125t RMinimum Removal Time 2.0V 506375nsfrom SCLR to SCK4.5V 1013156.0V 91113t SMinimum Setup Time 2.0V 100125150nsfrom SCK to RCK4.5V 2025306.0V 172126t HMinimum Hold Time 2.0V 555nsSER to SCK4.5V 5556.0V 555t WMinimum Pulse Width 2.0V 3080100120nsof SCK or SCLR4.5V 91620246.0V 8141822t r , t fMaximum Input Rise and 2.0V 100010001000nsFall Time, Clock4.5V 5005005006.0V 400400400t THL , t TLH Maximum Output2.0V 25607590nsRise and Fall Time 4.5V 7121518Q A –Q H6.0V 6101315t THL , t TLH Maximum Output2.0V 7595110nsRise & Fall Time 4.5V 151922Q'H6.0V131619C PDPower Dissipation G = V CC 90pFCapacitance, Outputs G = GND150Enabled (Note 6)C IN Maximum Input 5101010pF Capacitance C OUTMaximum Output 15202020pFCapacitance 6M M 74H C 595Timing Diagram MM74HC595Physical Dimensions inches (millimeters) unless otherwise noted16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" NarrowPackage Number M16A 8M M 74H C 595Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M16D MM74HC595Physical Dimensions inches (millimeters) unless otherwise noted (Continued)16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage Number MTC1610M M 74H C 595 8-B i t S h i f t R e g i s t e r s w i t h O u t p u t L a t c h e sPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" WidePackage Number N16EFairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。