FPGA可编程逻辑器件芯片EP4SGX230FF35C2XN中文规格书

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Stratix II Device Handbook, Volume 2
configuration file and cannot be dynamically controlled during user-mode operation.
(2) Only the CLKn pins on the top and bottom for the device feed to regional clock
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Logic
Static Clock Select (1)
Enable/ Disable
Internal Logic
RCLK
Notes to Figure 1–53: (1) These clock select signals can only be dynamically controlled through a
For the regional clock select block, the clock source selection can only be controlled statically using configuration bits. Any of the inputs to the clock select multiplexer can be set as the clock source.
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Stratix II Device Handbook, Volume 1
Clock Feedback Modes
Figure 1–10. Phase Relationship between PLL Clocks in No Compensation Mode
Phase Aligned
PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port (1), (2)
External PLL Clock Outputs (2)
Notes to Figure 1–10. (1) Internal clocks fed by the PLL are phase-aligned to each other. (2) The PLL clock outputs can lead or lag the PLL input clocks.
tD I P
Minimum Timing Industrial Commercial
-3 Speed Grade
(3)
-3 Speed Grade
(4)
-4 Speed Grade
-5 Speed Grade
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select blocks.
For the global clock select block, the clock source selection can be controlled either statically or dynamically. You have the option to statically select the clock source in configuration file generated by the Quartus II software, or you can control the selection dynamically by using internal logic to drive the multiplexer select inputs. When selecting statically, the clock source can be set to any of the inputs to the select multiplexer. When selecting the clock source dynamically, you can either select two PLL outputs (such as CLK0 or CLK1), or a combination of clock pins or PLL outputs.
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Timing Model
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 6 of 8)
I/O Standard
Drive Strength
Parameter
Differential
8 mA
The Stratix II and Stratix II GX clock networks can be disabled (powered down) by both static and dynamic approaches. When a clock net is powered down, all the logic fed by the clock net is in an off-state, thereby reducing the overall power consumption of the device.
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin. The external clock output pin will have a phase delay relative to the clock input pin if connected in this mode. In normal mode, the delay introduced by the GCLK or RCLK network is fully compensated. Figure 1–11 shows an example waveform of the PLL clocks’ phase relationship in this mode.
tD I P
6 mA
tO P
tD I P
8 mA
tO P
tD I P
10 mA tO P
tD I P
12 mA tO P
tD I P
Differential SSTL-18 Class II
8 mA
tO P
tD I P
16 mA tO P
tD I P
18 mA tO P
tD I P
20 mA tO P
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Stratix II Device Handbook, Volume 2
Clock Control Block
Figure 1–53. Regional Clock Control Block
PLL Counter Outputs (3)
CLKp CLKn Pin Pin (2)
2
Internal
tO P
SSTL-2 Class I
tD I P
12 mA tO P
tD I P
Differential
16 mA tO P
SSTL-2 Class II
tD I P
20 mA tO P
tD I P
24 mA tO P
tD I P
Differential SSTL-18 Class I
4 mA
tO P
When using the altclkctrl megafunction to implement clock source (dynamics) selection, the inputs from the clock pins feed the inclock[0..1] ports of the multiplexer, while the PLL outputs feed the inclock[2..3] ports. You can choose from among these inputs using the CLKSELECT[1..0] signal.