Design of a 1-V Operational Passive Sigma-Delta Modulator

Design of a 1-V Operational Passive Sigma-DeltaModulatorToru Sai and Yasuhiro Sugimoto*Chuo UniversityDepartment of Electrical, Electronic, and Communication EngineeringTokyo, Japansai@comp.elect.chuo-u.ac.jp, *sugimoto@elect.chuo-u.ac.jpAbstract— The 1-V operation of a passive sigma-delta modulator has been realized. The dc voltage in the signal paths in the second-order switched capacitor filter section was set at 0.2 V so that metal-oxide-semiconductor (MOS) switches in the signal paths would have enough gate-to-source voltage to turn on without using a voltage boosting scheme. The input switch was replaced by a passive resistor to avoid floating. By modifying gain coefficients in the feedback and the input paths, the bias voltage of digital-to-analog converter (DAC) can be set to 1 V and 0 V and MOS switches become easily activated. Moreover, the correlated double sampling (CDS) scheme was adopted to suppress the 1/f noise and offset voltage produced at the input of a comparator. Successful operation from 1-V supply voltage was confirmed by circuit simulation using the 0.18-um complementary MOS (CMOS) process.I.I NTRODUCTIONThe scaling of CMOS devices has accompanied the reduction of supply voltage for large-scale integration (LSI) circuits in the nanometer processing era. In a 32-nm CMOS process, for example, the supply voltage becomes less than 1.0 V [1]. However, it becomes extremely difficult to achieve high performance for analog circuits with this low supply voltage. As the passive sigma-delta modulator (PSDM) [2]-[5] does not need operational amplifiers (Op-amps) or operational transconductance amplifiers (OTAs), in other words, any analog circuitry, it seems to be the way for future analog circuits to take. The main advantage of PSDM is that the filter does not suffer from non-linearity, bandwidth, and power supply introduced by active elements. On the other hand, as the comparator input signal is very small, its input signal may have to be amplified in order to minimize the influence of the comparator 1/f noise and offset voltage. However, this amplifier does not need to be linear, as only the sign of its output signal has to be considered [5]. Although previous study [3] realized 1.5-V operation by using a 0.13-um CMOS process, further reduction of the supply voltage is difficult because of problems such as the floating state in switches [6], the decrease of the signal to noise and distortion ratio (SNDR) due to the offset voltage in differential signal paths and the 1/f noise at the input of a comparator. A hybrid-type combined structure of active and passive filters has been proposed [7] to solve the SNDR issue. However, the supply voltage is still 1.5 V and analog circuits are used in it. Considering use in the nanometer processing era, in this paper we propose circuits to realize 1-V operation and solve noise issues while employing a PSDM.II.O BSTRACLES OF A CHIEVING L OW-V OLTAGEO PERATIONA. Floating SwitchFig. 1 shows the second-order passive filter of a PSDM in which the switched capacitor circuit technique is used without an operational amplifier. Each part in a dashed-line box acts as a resistor and realizes the second-order filter as a whole. All switches consist of MOS transistors. In Fig. 1, the voltage at the in and out terminals is commonly chosen as half the supply voltage, that is, VDD/2. This means the voltage at the in and out terminals becomes 0.5 V when VDD is 1 V. At that point it is very much difficult for a MOS switch to be turned on in a state of low on-resistance with 0.5 V or less of gate-to-source voltage, and the MOS switch becomes a floating switch. Although in the past the gate voltage could easily be boosted to activate a MOS switch, this is no longer the case, because the gate voltage can-not be raised due to the questionable reliability. The maximum gate voltage for a MOS switch should be equal to VDD.Fig. 1. A circuit of a conventional second-order passive filter.B. 1/f Noise at the Input of a ComparatorFig. 2 shows the block diagram of the PSDM. Eq standsfor the quantization noise, G for the comparator gain, Ecomfor noise at the comparator input and H for the transferfunction of the filter [3]. The actual PSDM consists of MOSswitches, capacitors, a comparator and a latch.Fig. 2. Block diagram of a passive sigma-delta modulator.The input signal is modulated by the data sequence of themodulator output in Fig. 2 and has high-frequencycomponents around fs/2, where fs is the clock frequency ofthe modulator. As the filter has no positive voltage gain andattenuates high-frequency signals, the signal at the input of acomparator becomes very small. This means that the Ecom inFig. 2 should be small enough in comparison with the outputsignal from the filter. Therefore, the size of input transistorsof a comparator should be large in order to have small 1/fnoise. However, this deteriorates comparison speed.C. Offset Voltage at the Input of a ComparatorAs the signal that comes out of a filter in Fig. 2 is verysmall, the reference voltage of a comparator should,theoretically, be kept absolutely constant. However, this isimpossible and, in actual circuits, the differential signal isused as the input of a comparator, as shown in Fig. 3. Thereare two filters, xscfp and xscfm, in differential channels.When the offset voltage voff exists in a comparator xcmp, asshown in Fig. 3, voltages becomes vcom+(voff/2) at node‘cp’ and vcom-(voff/2) at node ‘cm’. There is a settlingdifference between those nodes and, as a result, thedistortion deteriorates. It becomes important to reduce thecomparator offset voltage to have a good signal-to-distortionratio.Fig. 3. Comparator offset voltage and its influence.III.T HE R EALIZATION OF THE L OW-V OLTAGE O PERATIONA. Lowering the Signal Path Voltage TechniqueLowering the voltage in the signal path of a filter easilyturns on a MOS switch. Fig. 4 shows the circuit of a newlydesigned filter in a PSDM. In this design, the relationshipamong voltages at terminals ‘a’, ‘vin’ and ‘vbias’ becomes)vbiasvin(b1cra1cra1crvbiasva−+−= (1)If we chose vbias=0.3 V, vin=0.5 V, and cr1a=cr1b, thenva=0.2V, which means the common mode voltage from node‘a’ to node ‘vout’ is biased in low voltage (vcom=0.2 V)throughout. In this situation, switches have enough Vgsvoltage (0.8 V under no signal condition) and, therefore,floating never occurs.Although the voltage at internal nodes is lowered, thevoltage at terminal vin remains VDD/2, because it needs tointerface with the outside of the modulator. As the staticvoltage of the input terminal vin becomes 0.5 V, a MOSswitch cannot have enough gate to source voltage from the 1-V supply voltage. For this reason, the input switch is replacedby a linear resistor Rin [8], as shown in Fig. 4.The need to boost the gate voltage for a MOS switch iscompletely eliminated in this setup.Also it becomes easy to design a comparator by low biasvoltage (vcom=0.2V), because the current source can beinserted at the input of differential PMOS transistors in thecomparator.Fig. 4. A newly designed passive switched capacitor filter.Fig. 5. DAC circuit.B. Optimization of Switch Bias in the DACFig. 5 shows DAC circuit. The voltages ‘vrep’ and ‘vrem’ are conventionally chosen such that ‘vrep-vbias’ becomes equal to vbias-vrem’, that is, 0.6V and 0V, respectively, when vbias=0.3V. This results in entering the floating state for DAC switches. By modifying the input and feedback gain coefficient, the floating switch can be avoided.In Fig. 5, ‘y’ is the feedback data from the modulator output, and φ1 and φ2 are clocks. In synchronizing with φ1, data ‘y’ decides which switch of vrep and vrem becomes on. The φ2 resets the charge stored on cr1b. The timing diagram of DAC control clocks φ1 and φ2 and modulator output signal ‘y’ is shown in Fig. 5. The signal swing of ‘y’ is 1V. The following relationship holds()rem ,rep in bias swing v a2cr a 1cr a 2cr v v 2a 2cr a 1cr a1cr v ++−+=(2)where vswing is the voltage swing at node ‘a’ in Fig. 5 and vrep,rem is the voltage swing of signal ‘y’. By substituting values crla=600 fF, cr1b=200 fF, vbias=0.3 V, vin=0.5 V ±80 mV and vrep,rem=1 V, equation (2) becomesrem ,rep in swing v 25.045.0v 75.0v ++−= (3)The gain scaling of the input signal vin and feedback DAC data vrep,rem is shown in Fig. 6. The scaled DAC feedback signal is subtracted from the scaled input signal and becomes the SPICE simulated waveform shown in Fig. 7. Clock frequency fs is 100 MHz and vin is 0.5 V ±80 mV.Fig. 6. Gain scaling in the input and the feedback loop.Fig. 7. Waveform of node a (Va) in Fig.5.By performing the scaling described above, the voltage of ‘vrep’ in Fig. 5 can be 1 V and that of ‘vrem’ 0 V. As a result, MOS switches that connect to vrep and vrem can be turned on easily because 1 V is used for the gate-to-source voltage of a switch transistor. In Fig. 7, the effective signal swing at node ‘a’ is 0.12 V peak to peak (0.75 times the input signal), and the effective feedback signal swing becomes 0.25 V peak to peak (0.25 times VDD) centered at 0.2 V of dc voltage. The maximum voltage is limited to 0.385 V, and this ensures turning on of a MOS switch in low resistance.C. 1/f Noise Reduction and Offset Voltage Cancellation of a ComparatorAs previously discussed in section II-B, the noise at the input of a comparator greatly affects the overall signal-to-noise ratio (SNR) of the PDSM. Considering comparison speed, the transistor size in the first stage of a comparator should be small. As a result, 1/f noise of a MOS transistor is large, and this limits the SNR of the modulator.In Fig. 8, the 1/f noise voltage v 1/f is assumed to exist at the input of ‘cmpa1’. First, switches sw3, sw4, sw5 and sw6 turn on while sw1 and sw2 turn off. At this time, 1/f noise at inputs of ‘cmpa1’ is sampled across capacitors cp1 plus cp2 by the amount of (Av 1/f )/(1+A), where A is the voltage gain of ‘cmpa1’. Next, sw1 and sw2 become on and sw3, sw4, sw5 and sw6 turn off, allowing signals from filters applied to ‘cmpa1’ through capacitors cp1 and cp2. Low-frequency noise such as 1/f noise does not change its voltage during the short period of time when a high-frequency clock signal controls those switches. Therefore, 1/f noise at input terminals ‘ainmx’ and ‘ainpx’ of ‘cmpa1’ becomes (Av 1/fNEW )/2(1+A) and {v 1/fNEW -(Av 1/fOLD )/2(1+A)}, where v 1/fNEW and v 1/fOLD are the current and memorized 1/f noises, respectively, and approximately v 1/fNEW of 1/f noise appears at the output of ‘cmpa1’ while the signal is A times amplified. This means the 1/f noise is reduced relative to the signal. The offset voltage is suppressed in the same manner. In this way, 1/f noise and offset voltage are reduced.Fig. 8. A comparator and a latch with CDS.IV. C IRCUIT D ESIGN OF A S IGMA -D ELTA M ODULATOR Rin, cr1a and cr1b in Fig. 5 are set at 1/3k Ω, 600 fF and 200 fF, respectively. The minimum capacitor value throughout the circuit is 200 fF, and the total capacitor value is 95 pF. The DAC switches are CMOS switches, while the other switches are n-type MOS (NMOS) switches. The size of the NMOS is 32 um/0.18 um (W/L), and that of thePMOS is 64 um/0.18 um (W/L). The frequency bandwidth of this sigma-delta modulator is 100 kHz. The first pole and the second pole of this second-order filter are 80 kHz and 340 kHz, respectively, and the zero is 7.5 MHz. Circuits are differentially configured, and the common-mode feedback is applied to each stage of a comparator. To have small 1/f noise and to interface with 0.2 V of dc output voltage of the previous stage, we set the input differential pair of the first to fourth stages of a comparator to use PMOS transistors.V. S IMULATION R ESULTSThe designed circuit is SPICE simulated using device parameters of the 0.18-um CMOS process. The supply voltage is 1.0 V, and the clock frequency, fs, is 100 MHz. A. The Effect of Lowering the Signal Path VoltageFig. 9 is the fast Fourier transform (FFT) results of two different designs with the input signal frequency of 30 kHz and amplitude of ±1/2FS. One is the conventional design, where the signal path voltage of a filter is 0.5 V. The other is the newly designed setup in which the signal path voltage is lowered to 0.2 V. It is clearly seen in Fig. 9 that the newly designed setup is suitable to 1-V operation.Fig.9. Comparison of FFT result.B. CDS EffectsThe time-domain 1/f noise source is applied to the input of a comparator to determine the influence on noise and distortion. In this simulation, the voltage gain and the bandwidth of the first-stage comparator are 24 dB and 150 MHz, respectively, while the voltage gain and bandwidth of the whole comparator are 118 dB and 80 MHz. Taking 1/f noise parameters of a transistor into account, which are based on the actual noise measurements of a transistor, the Ecom value is estimated to be 32 uVrms.When the input signal with a frequency of 100 kHz and an amplitude of 0.32 V peak to peak (±1/2FS) is applied in a differential manner, the FFT plot of the output pulse-width modulation (PWM) waveform is obtained, as shown in Fig. 10. The noise and distortion level of the curve with CDS is about 8 dB lower than those of the curve without CDS. Considering the frequency bandwidth 100 kHz, the SNR becomes 76dB in the case with CDS even with time-domain 1/f noise source. Table 1 compares the performance of thisdesign with previous designs. Only our work realizes 1-V operation of a PSDM without deteriorating the performance.Fig.10. FFT plot of the output PWM waveform.Table 1. Performance comparison of various designs.VI. C ONCLUSIONThe realization possibility of a 1-V operational passive sigma-delta modulator has been examined. By lowering the voltage of signal paths in a filter, by using a linear resistor for the input, by modifying the gain in the feedback data path and by introducing CDS and offset canceling techniques for a comparator, 1-V operation of a PSDM becomes possible. We confirmed this via circuit simulation using device parameters of the 0.18-um CMOS process. R EFERENCES[1] International Technology Roadmap for Semiconductors:2008[2] Feng Chen and Bosco Leung, “A 0.25mW 13b Passive ΣΔ Modulatorfor 10MHz IF input,” ISSCC Dig. Tech. Paper, pp. 58-59, February 1995.[3] Feng Chen, Srinath Ramaswamy, and Bertan Bakkaloglu, “A 1.5V1mA 80dB Passive ΣΔADC in 0.13um Digital CMOS Process,” ISSCC Dig. Tech. Papers, pp. 54-55, February 2003.[4] Toru Choi, Tatsuya Sakamoto, and Yasuhiro Sugimoto, “A Study toRealize a 1-V Operational Passive Σ-Δ Modulator by Using a 90nm CMOS Process,” IEICE Trans. Electronics, vol. E90-C, pp. 1304-1306, June 2007.[5] Philippe BENABES, Richard KIELBASA, “Passive Sigma-Deltaconverters design,” IEEE Instrument and Measurement Technology Conference, pp. 469-474, May, 2002.[6] Mustafa Keskin, Un-Ku Moon, and Gabor C. Temes, “A 1-V 10-MHzClock-Rate 13-Bit CMOS ΔΣ Modulator Using Unity-Gain-Reset Opams,” IEEE J. Solid-State Circuit, vol.37, pp. 817-824, July 2002. [7] Tongyu Song, Zhiheng Cao, and Shouli Yan, “A 2.7mW 2-MHzContinuous-Time ΣΔ Modulator With a Hybrid Active-Passive Loop Filter,” IEEE J. Solid-State Circuit, vol.43, pp. 330-341, February 2008. [8] Min Gyu Kim, Gil-Cho Ahn, Pavan Kumar Hanumolu, Sang-HyeonLee, Sang-Ho Kim, Seung-Bin You, Jae-Whui Kim, Gabor C. Tems, and Un-Ku Moon, “A 0.9V 92dB Double-Sampled Switched-RC Delta-Sigma Audio ADC,” IEEE J. Solid-State Circuit ., vol.43, pp. 1195-1206, May 2008.。