分频器VHDL20120407

常用的分频电路分为整数分频和小数分频，在整数分频中，又分为偶数倍分频和奇数倍分频，而且占空比也是需要考虑的问题
一占空比为50%
1.偶数倍分频
下面以8分频为例：
library ieee;
use ieee.std_logic_1164.all;
entity fredevider is
port
(clkin:in std_logic;
clkout:out std_logic);
end;
architecture devider of fredevider is
constant n:integer:=3;
--改变n的值即可改变分频数，且分频为2(n+1)；n为整数且大于或等于0. signal counter:integer range 0 to n;
signal clk:std_logic;
begin
process(clkin)
begin
if rising_edge(clkin) then
--此处为上升沿翻转，也可以改为下降沿翻转：if falling_edge(clkin) then if counter=n then
counter<=0;
clk<=not clk;
else
counter<=counter+1;
end if;
end if;
end process;
clkout<=clk;
end;
其波形图如下：
2.奇数倍分频
实现奇数倍分频有种方法，最简单的是错位“异或”法
下面以3分频为例
library ieee;
use ieee.std_logic_1164.all;
entity fredevider3 is
port
(clkin:in std_logic;
clkout1,clkout2,clkout:out std_logic);
end;
architecture devider of fredevider3 is
constant n:integer:=2;
--改变n的值即可改变分频数，且分频为n+1；n为偶数才会得到占空比为50%的奇数倍分频.
signal counter:integer range 0 to n;
signal temp1,temp2:std_logic;
begin
process(clkin)
begin
if rising_edge(clkin) then
if counter=n then
counter<=0;
temp1<=not temp1;
else
counter<=counter+1;
end if;
end if;
if falling_edge(clkin) then
if counter=n/2 then
temp2<=not temp2;
end if;
end if;
end process;
clkout1<=temp1; --2n上升沿翻转输出
clkout2<=temp2; --2n下降沿翻转输出
clkout<=temp1 xor temp2;---n+1分频输出
end;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fredevider3 IS
PORT (
inclk: IN STD_LOGIC; --时钟源
preset: IN STD_LOGIC_VECTOR(3 DOWNTO 0); --预置分频值N outclk1: OUT STD_LOGIC;
outclk2: BUFFER STD_LOGIC ); --输出时钟
END fredevider3;
ARCHITECTURE deccount_arch OF fredevider3 IS
SIGNAL clk, divide2: STD_LOGIC;
SIGNAL count: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
clk<=inclk XOR divide2; --inclk与divide2异或后作为模N计数器的时钟
outclk1<=inclk;
PROCESS(clk)
BEGIN
IF(clk'event AND clk='1') THEN
IF(count="0000") THEN
count<=preset-1; --置整数分频值N
outclk2<='1';
ELSE
count<=count-1; --模N计数器减法计数
outclk2<='0';
END IF;
END IF;
END PROCESS;
PROCESS(outclk2)
BEGIN
IF(outclk2'event AND outclk2='1') THEN
divide2<=NOT divide2; --输出时钟二分频
END IF;
END PROCESS;
END deccount_arch;
以二的6次幂分频为例：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------
entity shizhong is
port( sysclk : in std_logic; --定义系统时钟50M为输入
a1: out std_logic;
a0: out std_logic
);
end ;
architecture rtl of shizhong is
signal clk:std_logic_vector(6 downto 0);--修改6为数字可得到其他分频begin
process(sysclk)
begin
if sysclk'event and sysclk='1' then
clk<=clk+1;
end if;
a1<=clk(6); --2的6次幂分频
a0<=clk(5); --2的5次幂分频
end process;
end;。