LCD Controller

Design Objectives
• Use the Liquid Crystal Display (LCD) on the Altera SOPC board to display information • Implement a design on the APEX 20KE452-1X that interfaces to the Hitachi LCD controller
rs= 1 rw= 1 e= 0 wr_done= 0
Idle
Write1 Write3
rs= write_rs rw= 0 e= 0 wr_done= 1
Write2
rs= write_rs rw= 0 e= 1 wr_done= 0
rs= write_rs rw= 0 e= 0 wr_done= 0
LCD Controller
Example Design Review Dr. Gruenbacher AprilHale Waihona Puke 12, 2004Topics
• • • • • • • Objectives Block Diagram Model Interface Definition Design Description Design and Test Plan Current Status Issues
S tart_Mode
write_data = 8'h06; write_rs = 1'b0; begin_write = 1'b1;
~ wr_done
Wait_D
write_data = 8'h44; write_rs = 1'b0; begin_write = 1'b0;
Wait_H
write_data = 8'h48; write_rs = 1'b0; begin_write = 1'b0;
Wait_Clear
write_data = 8'h01; write_rs = 1'b0; begin_write = 1'b0;
wr_done
Wait_Display
write_data = 8'h0f; write_rs = 1'b0; begin_write = 1'b0;
wr_done ~ wr_done ~ wr_done ~ wr_done wr_done
• DB7 indicates a busy flag during reads • Intermediate SN74LVT245BDW controlled by the RW line
Design Description
• Clock divider
– // Generate slower FSM clock by dividing clk_fast by 2^14
• Synthesis using Synopsys Design Compiler
– final target will be APEX20K400
• Final place and route using Altera QuartusII • Test and verification on APEX SOPC board
Bus state machine
~ busy begin_write ~ begin_write rs= 1 rw= 1 e= 0 wr_done= 0 rs= 1 rw= 1 e= 0 wr_done= 0 busy
Read1
Read2
rs= 1 rw= 1 e= 1 wr_done= 0
R ead3
begin_write is asserted by the data state machine busy is the value of bit DB7during a read wr_done is used to indicate the main state machine that a write transaction has finished (used by data state machine)
always @(negedge ar or posedge clk_fast) if(~ar) clkdiv_cntr <= 4'b0; else clkdiv_cntr <= clkdiv_cntr + 1; assign fsm_clk = clkdiv_cntr[13];
• Bus state machine • Data state machine
Design and Test Plan
• All designs and test benches written in Verilog • Behavioral compile and simulation using Synopsys VCS
– Test bench will allow verification of intended bus protocol, but will (cannot) verify Hitachi LCD operation
Bus code
• Three state (bidirectional) implementation:
assign lcd_db = ~lcd_rw ? write_data_reg : 8'bzzzzzzzz;
Data is registered (clocked) to prevent glitches:
write_data = 8'h01; write_rs = 1'b0; begin_write = 1'b1;
S tart_Display
write_data = 8'h0f; write_rs = 1'b0; begin_write = 1'b1;
~ wr_done
Reset
write_data = 8'h00; write_rs = 1'b0; begin_write = 1'b0;
Wait_Mode
write_data = 8'h06; write_rs = 1'b0; begin_write = 1'b0;
D
write_data = 8'h44; write_rs = 1'b0; begin_write = 1'b1;
wr_done
H
write_data = 8'h48; write_rs = 1'b0; begin_write = 1'b1;
• Reading the busy flag caused a space to be inserted between each character • Removing/bypassing the read cycles has temporarily avoided this problem
Summary Info.
• Blah, blah, blah….. • Other information you may provide in your presentation:
– Individual assignments/responsibilities – Design Hierarchy (how you are breaking the design into separate modules) – ???
wr_done
Data state machine code (Ex.)
always @(negedge ar or posedge fsm_clk) if(~ar) cs = Reset; else cs = ns; always @(cs or wr_done) begin case(cs) D: begin
• Test bench
– 100% written
• 100% verified in VCS
Issues
• Resolved
– Maximum bus speed to LCD Controller
• Runs well with 8 kHz fsm_clk
• Outstanding
– Busy flag read from LCD Controller
– Visual confirmation of the characters displayed on LCD
Current Status
• Design
– 100% code written – 100% synthesized in Design Compiler – 100% place and route in Quartus
// Write the letter D write_data <= 8'h44; write_rs <= 1'b1; begin_write <= 1'b1; ns <= Wait_D;
end Wait_D : begin write_data <= 8'h44; write_rs <= 1'b1; begin_write <= 1'b0; // Don't allow another write to begin if(wr_done) ns <= L; else ns <= Wait_D; end …
External Interfaces
• Asynchronous Reset (ar, active low) • Clock : 66 MHz
– Divide by 2^(13) for internal clock rate