HD74HC123ARP中文资料

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HC123资料

TL F 5206MM54HC123A MM74HC123A Dual Retriggerable Monostable MultivibratorJanuary 1988MM54HC123A MM74HC123ADual Retriggerable Monostable MultivibratorGeneral DescriptionThe MM54 74HC123A high speed monostable multivibra-tors (one shots)utilize advanced silicon-gate CMOS tech-nology They feature speeds comparable to low power Schottky TTL circuitry while retaining the low power and high noise immunity characteristic of CMOS circuitsEach multivibrator features both a negative A and a posi-tive B transition triggered input either of which can be used as an inhibit input Also included is a clear input that when taken low resets the one shot The ’HC123can be triggered on the positive transition of the clear while A is held low and B is held highThe ’HC123A is retriggerable That is it may be triggered repeatedly while their outputs are generating a pulse and the pulse will be extendedPulse width stability over a wide range of temperature and supply is achieved using linear CMOS techniques The out-put pulse equation is simply PW e (R EXT )(C EXT ) where PW is in seconds R is in ohms and C is in farads All inputs are protected from damage due to static discharge by diodes to V CC and groundFeaturesY Typical propagation delay 25ns Y Wide power supply range 2V–6VY Low quiescent current 80m A maximum (74HC Series)Y Low input current 1m A maximum Y Fanout of 10LS-TTL loadsY Simple pulse width formula T e RC Y Wide pulse range 400ns to %(typ)Y Part to part variation g 5%(typ)YSchmitt Trigger A B inputs enable infinite signal input rise and fall timesConnection DiagramDual-In-Line PackageTL F 5206–1Top ViewOrder Number MM54HC123A or MM74HC123ATiming ComponentTL F 5206–2Note Pin 6and Pin 14must behard-wired to GNDTruth TableInputs OutputsClear A B Q Q L X X L H X H X L H X X LL H H L uHvHuLHH e High Level L e Low Levelu e Transition from Low to High v eTransition from High to Lowe One High Level Pulsee One Low Level Pulse X e IrrelevantC 1995National Semiconductor Corporation RRD-B30M105 Printed in U S AAbsolute Maximum Ratings(Notes1 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage(V CC)b0 5V to a7 0V DC Input Voltage(V IN)b1 5V to V CC a1 5V DC Output Voltage(V OUT)b0 5V to V CC a0 5V Clamp Diode Current(I IK I OK)g20mA DC Output Current per pin(I OUT)g25mA DC V CC or GND Current per pin(I CC)g50mA Storage Temperature Range(T STG)b65 C to a150 C Power Dissipation(P D)(Note3)600mW S O Package only500mW Lead Temperature(T L)(Soldering10seconds)260 C Operating ConditionsMin Max Units Supply Voltage V CC V DC Input or Output Voltage V CC V V IN V OUTOperating Temp Range(T A)MM HC b a C MM HC b a C Input Rise or Fall Times(Clear Input)V CC e Vt r t f ns V CC e V nsV CC e V nsDC Electrical Characteristics(Note4)T A e25 C74HC54HCSymbol Parameter Conditions V CC T A eb40to85 C T A eb55to125 C UnitsTyp Guaranteed LimitsV IH Minimum High Level Input V V Voltage V VV V V IL Maximum Low Level Input V V Voltage V VV V V OH Minimum High Level V IN e V IH or V ILOutput Voltage l I OUT l s m A V VV VV VV IN e V IH or V IL Vl I OUT l s mA V Vl I OUT l s mA V V V OL Maximum Low Level V IN e V IH or V ILOutput Voltage l I OUT l s m A V VV VV VV IN e V IH or V IL Vl I OUT l s mA V Vl I OUT l s mA V V I IN Maximum Input Current V IN e V CC or GND V g g g m APinsI IN Maximum Input Current V IN e V CC or GND V g g g m Aall other pinsI CC Maximum Quiescent Supply V IN e V CC or GND V m ACurrent standby I OUT e m AI CC Maximum Active Supply V IN e V CC or GND V m ACurrent per R C EXT e V CC V mA monostable V mA Note1 Maximum Ratings are those values beyond which damage to the device may occurNote2 Unless otherwise specified all voltages are referenced to groundNote3 Power Dissipation Temperature DeratingPlastic‘‘N’’Package b12mW C from65 C to85 CCeramic‘‘J’’Package b12mW C from100 C to125 CNote4 For a power supply of5V g10%the worst-case output voltages(V OH V OL)occur for HC at4 5V Thus the4 5V values should be used when designing with this supply Worst-case V IH and V IL occur at V CC e5 5V and4 5V respectively (The V IH value at5 5V is3 85V )The worst-case leakage current(I IN I CC and I OZ)occur for CMOS at the higher voltage and so the6 0V values should be used2AC Electrical Characteristics V CC e5V T A e25 C C L e15pF t r e t f e6ns Symbol Parameter Conditions Typ Limit Unitst PLH Maximum Trigger Propagation Delay nsA B or Clear to Qt PHL Maximum Trigger Propagation Delay nsA B or Clear to Qt PHL Maximum Propagation Delay Clear to Q ns t PLH Maximum Propagation Delay Clear to Q ns t W Minimum Pulse Width A B or Clear ns t REM Minimum Clear Removal Time nst WQ MIN Minimum Output Pulse Width C EXT e pF nsR EXT e k Xt WQ Output Pulse Width C EXT e pF m sR EXT e k XAC Electrical Characteristics C L e50pF t r e t f e6ns(unless otherwise specified)T A e25 C 74HC54HCSymbol Parameter Conditions V CC T A eb40to85 C T A eb55to125 C UnitsTyp Guaranteed Limitst PLH Maximum Trigger Propagation V ns Delay A B or Clear to Q V nsV ns t PHL Maximum Trigger Propagation V ns Delay A B or Clear to Q V nsV ns t PHL Maximum Propagation Delay V ns Clear to Q V nsV ns t PLH Maximum Propagation Delay V ns Clear to Q V nsV ns t W Minimum Pulse Width V nsA B Clear V nsV ns t REM Minimum Clear V ns Removal Time V nsV ns t TLH t THL Maximum Output V ns Rise and Fall Time V nsV ns t WQ MIN Minimum Output C EXT e pF V m s Pulse Width R EXT e k X V nsR EXT e k X V CC e V V ns t WQ Output Pulse Width C EXT e m F Min V msR EXT e k X Max V ms C IN Maximum Input pFCapacitance PinsC IN Maximum Input pFCapacitance other inputsC PD Power Dissipation Note pFCapacitanceNote5 C PD determines the no load dynamic power consumption P D e C PD V CC2f a I CC V CC and the no load dynamic current consumption I S e C PD V CC f a I CC3Logic DiagramTL F 5206–5 Theory of OperationTL F 5206–6 j POSITIVE EDGE TRIGGER m POSITIVE EDGE RE-TRIGGER(PULSE LENGTHENING)k NEGATIVE EDGE TRIGGER n RESET PULSE SHORTENINGl POSITIVE EDGE TRIGGER o CLEAR TRIGGERFIGURE1TRIGGER OPERATIONAs shown in Figure1and the logic diagram before an input trigger occurs the one shot is in the quiescent state with the Q output low and the timing capacitor C EXT completely charged to V CC When the trigger input A goes from V CC to GND(while inputs B and clear are held to V CC)a valid trig-ger is recognized which turns on comparator C1and N-channel transistor N1j At the same time the output latch is set With transistor N1on the capacitor C EXT rapidly dis-charges toward GND until V REF1is reached At this point the output of comparator C1changes state and transistor N1turns off Comparator C1then turns off while at the same time comparator C2turns on With transistor N1off the capacitor C EXT begins to charge through the timing re-4sistor R EXT toward V CC When the voltage across C EXT equals V REF2 comparator C2changes state causing the output latch to reset (Q goes low)while at the same time disabling comparator C2 This ends the timing cycle with the monostable in the quiescent state waiting for the next trig-gerA valid trigger is also recognized when trigger inputB goes from GND to V CC (while input A is at GND and input clear is at V CC k ) The ’HC123A can also be triggered when clear goes from GND to V CC (while A is at GND and B is at V CC o )It should be noted that in the quiescent state C EXT is fully charged to V CC causing the current through resistor R EXT to be zero Both comparators are ‘‘off’’with the total device current due only to reverse junction leakages An added feature of the ’HC123A is that the output latch is set via the in-put trigger without regard to the capacitor voltage Thus prop-agation delay from trigger to Q is independent of the value of C EXT R EXT or the duty cycle of the input waveform RETRIGGER OPERATIONThe ’HC123A is retriggered if a valid trigger occurs l fol-lowed by another trigger m before the Q output has re-turned to the quiescent (zero)state Any retrigger after the timing node voltage at the R C EXT pin has begun to rise from V REF1 but has not yet reached V REF2 will cause an increase in output pulse width T When a valid retrigger is initiated m the voltage at the R C EXT pin will again drop to V REF1before progressing along the RC charging curvetoward V CC The Q output will remain high until time T after the last valid retriggerBecause the trigger-control circuit flip-flop resets shortly af-ter C X has discharged to the reference voltage of the lower reference circuit the minimum retrigger time t rr is a function of internal propagation delays and the discharge time of C Xt rr 20a187V CC b 0 7a 565a (0 256V CC )C XV CC b 0 7 2Another removal retrigger time occurs when a short clearpulse is used Upon receipt of a clear the one shot must charge the capacitor up to the upper trip point before the one shot is ready to receive the next trigger This time is dependent on the capacitor used and is approximatelyt rr e 196a640V CC b 0 7a522a (0 3V CC )C X(V CC b 0 7)2nsRESET OPERATIONThese one shots may be reset during the generation of the output pulse In the reset mode of operation an input pulse on clear sets the reset latch and causes the capacitor to be fast charged to V CC by turning on transistor Q1n When the voltage on the capacitor reaches V REF2 the reset latch will clear and then be ready to accept another pulse If the clear input is held low any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change Since the Q output is reset when an input low level is detected on the Clear input the output pulse T can be made significantly shorter than the minimum pulse width specificationTypical Output Pulse Width vs Timing Components TL F 5206–7Typical Distribution of Output Pulse Width Part to PartTL F 5206–8Typical 1ms Pulse Width Variation vs SupplyTL F 5206–9Minimum R EXT vs Supply Voltage TL F 5206–10Typical 1ms Pulse Width Variation vs TemperatureTL F 5206–11Note R and C are not subjected to temperature The C is polypropylene5M M 54H C 123A M M 74H C 123A D u a l R e t r i g g e r a b l e M o n o s t a b l e M u l t i v i b r a t o rPhysical Dimensions inches (millimeters)Dual-In-Line Package (J)Order Number MM54HC123AJ or MM74HC123AJNS Package Number J16ADual-In-Line Package (N)Order Number MM74HC123AN NS Package Number N16ELIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a)are intended for surgical implant support device or system whose failure to perform can into the body or (b)support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectivenessbe reasonably expected to result in a significant injury to the userNational Semiconductor National Semiconductor National Semiconductor National Semiconductor CorporationEuropeHong Kong LtdJapan Ltd1111West Bardin RoadFax (a 49)0-180-530858613th Floor Straight Block Tel 81-043-299-2309。

74HC123

5. Pinning information
5.1 Pinning
74HC123BQ
1 1A 16 VCC
1A 1 1B 2 1RD 3 1Q 4 2Q 5 2CEXT 6 2REXT/CEXT 7 GND 8
74HC123 74HCT123
16 VCC 15 1REXT/CEXT 14 1CEXT 13 1Q 12 2Q 11 2RD 10 2B 9 2A
Fig 1. Functional diagram
1CEXT 14
1REXT/CEXT 15
S Q
T
Q RD
1Q 13 1Q 4
2CEXT 6
2REXT/CEXT 7
S Q
T
Q RD
2Q 5 2Q 12
001aaa610
1 1A 9 2A
2 1B 10 2B
3 1RD 11 2RD
1CEXT 14 2CEXT 6
1REXT/CEXT 15 2REXT/CEXT 7
S Q
T
Q RD
1Q 13 2Q 5
1Q 4 2Q 12
mna515
Fig 2. Logic symbol
14 CX
15
RCX
13
1 &
2
4
3 R
6 CX
7 RCX
5
9 &
10
12
11
R
mna516
Fig 3. IEC logic symbol
74HC_HCT123_4
74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset

74ls123中文资料汇总（74ls123引脚图及功能

74ls123中文资料汇总（74ls123引脚图及功能74ls123推荐工作条件74ls123静态特性【1】：测试条件中的“最大”和“最小”用推荐工作条件中的相应值。

【2】：若在Q测VOH，/Q测VOL，Q测IOS时：'123 的Cext 接地；LS123 的Rext/Cext接地，B和CLR接VIH，A接 2V到 0V的脉冲电压。

若在/Q 测 VOH、Q 测 VOL、/Q 测 IOS 时：'123 的 Cext 开路【3】：测'123 时：Cext=0.02μF，Rext=25kΩ。

静态：所有A 和 CLR 接 2.4V，所有 B 接地。

触发态：所有 B 和 CLR 接 2.4V，所有 B 接地。

测'LS123 时：所有 A、B、CLR 接 4.5V，时钟瞬时接地后接 4.5V。

74ls123动态特性【4】：tPLH－输出由低到高电平传输延迟时间tPHL－输出由高到低电平传输延迟时间tWQ－Q端输出脉冲宽度三款74ls123应用电路及原理应用电路一：振铃检测、模拟摘机电路如图2，振铃检测电路是由光耦TLP521-1和74LS123构成。

当有电话呼入时，电话线上传输的25HZ、90V 的交流振铃信号由C1、C2隔离直流后由整流桥整流，整流后的直流电压值较高，经光电隔离器U1后输出TTL脉冲信号，该脉冲经74LS123整形成大方波信号，该方波信号送至单片机的P3.5引脚进行计数，当计数值达到预设值时，单片机P1.0引脚输出高电平，三极管Q1导通则继电器K1动作，将负载电阻R5（330Ω）接入电路实现模拟摘机。

这里所说的模拟摘机是指将R5接入电路后，电话线上就会出现大于10mA的电流，交换中心检测到这一电流后就不再输出振铃信号而是转为接通电话。

人们手动摘机接通电话时的工作过程与此一致，因此称为模拟摘机。

如果振铃信号没有达到预设值就消失，则单片机的计数值清零，控制器不动作。

HD74AC123AFP中文资料

*0.42 ± 0.08 0.40 ± 0.06
0.15 0.12 M
*Dimension including the plating thickness Base material dimension
*0.22 ± 0.05 0.20 ± 0.04
Unit: mm
7.80
+ –
0.20 0.30
1.15
+ –
0.14
*0.42 ± 0.08 0.40 ± 0.06
0.15 0.25 M
*Dimension including the plating thickness Base material dimension
1.75 Max
*0.22 ± 0.03 0.20 ± 0.03
Unit: mm
6.10
Voltage Range 5.0 is 5.0 V ± 0.5 V
Ta = –40°C to +85°C CL = 50 pF
Max Min Max Unit Condition
19.0 1.0
22.0 ns Cext = 0 pF
15.0 1.0
17.0
Rest = 5 kΩ
19.0 1.0
22.0 ns
Trigger Inputs (Active Falling Edge) Trigger Inputs (Active Rising Edge) Direct Clear Inputs (Active Low) Positive Pulse Outputs Negative Pulse Outputs
5
元器件交易网
20.00 Max
16
9
1
8

M74HC123A中文资料

M54HC123/123A M74HC123/123AOctober 1993DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORB1R(Plastic Package)ORDER CODES :M54HCXXXF1R M74HCXXXM1R M74HCXXXB1R M74HCXXXC1RF1R(Ceramic Package)M1R(Micro Package)C1R (Chip Carrier)PIN CONNECTIONS (top view)NC =No Internal Connecti o n.HIGH SPEEDt PD =25ns (TYP)at V CC =5V .LOW POWER DISSIPATIONSTANDBYSTATE I CC =4µA (MAX.)AT T A =25°C ACTIVE STATE I CC =200µA (TYP.)AT V CC =5V .HIGH NOISE IMMUNITYV NIH =V NIL =28%V CC (MIN.).OUTPUT DRIVE CAPABILITY 10LSTTL LOADS.SYMMETRICAL OUTPUT IMPEDANCE I OH =I OL =4mA (MIN.).BALANCED PROPAGATION DELAYS t PLH =t PHL.WIDE OPERATING VOLTAGE RANGE V CC (OPR)=2V TO 6V.WIDE OUTPUT PULSE WIDTH RANGE t WOUT =120ns ∼60s OVER AT V CC =4.5V .PIN AND FUNCTION COMPATIBLE WITH 54/74LS123The M54/74HC123is a high speed CMOS MONO-STABLE multivibrator fabricated with silicon gate C 2MOS technology.It achieves the high speed operation similar to equivalent LSTTL while main-taining the CMOS low power dissipation.There are two trigger inputs,A INPUT (negative edge)and 8INPUT (positive edge).These inputs are valid for slow rising/falling signals,(tr =tf =I sec).The device may also be triggered by using the CLR input (posi-tive-edge)because of the Schmitt-trigger input ;after triggering the output maintains the MONO-STABLE state for the time period determined by the external resistor Rx and capacitor Cx.When Cx ≥10nF and Rx ≥10K Ω,the output pulse width value is approssimatively given by the formula:t w(out)=K •Cx •Rx.Two different pulse width constant are available:K ≅0.45for HC123K ≅1for HC123A.Taking CLR low breaks this MONOSTABLE STATE.If the next trigger pulse occurs during the MONOSTABLEperiod it makes the MONOSTABLE period longer.Limit for values of Cx and Rx :Cx :NO LIMITRx :V CC <3.0V 5K Ωto 1M ΩV CC ≥3.0V 1K Ωto 1M ΩAll inputs are equipp ed with protection circuitsDESCRIPTION1/14M54/M74HC123/123A SYSTEM DIAGRAMTIMING CHART2/14BLOCK DIAGRAMNote:(1)Cx,Rx,Dx are external compo nents.(2)Dx is a clamping diode.The external capacitor is charged toV CC inthe stand-by state,i.e.no trigger.When the supply voltage is turned off Cx is discha rged mainly through an internal para sitic diode(see figures).If Cx is sufficiently large and V CC dec reases rapidy,there will be some pos sibility of da-maging the I.C.with a surg e current or latch-up.If the voltage sup ply filter capac itor is large eno ugh and V CC decrease slowly,the surg e current is automatically limited and damage the I.C.is avo ided.The maximum forward current of the parasitic diode is app roximately20 mA.In cases where Cx is large the time taken for the sup ply voltage to fall to0.4V CC canbe calculated as follows:t f≥(V CC–0.7)⋅Cx/20mAIn cases where t f is too short an external clamping diode is required to protect the I.C.from the surge current.FUNCTIONAL DESCRIPTIONSTAND-BY STATEThe external capacitor,Cx,is fully charged to V CC in the stand-by state.Hence,before triggering,tran-sistor Qp and Qn(connected to the Rx/Cx node)are both turned-off.The two comparators that control the timing and the two reference voltage sources stop operating.The total supply current is therefore only leakage current.TRIGGER OPERATIONTriggering occurs when:1st)A is”low”and B has a falling edge;2nd)B is”high”and A has a rising edge;3rd)A is low and B is high and C1has a rising edge. After the multivibrator has been retrigger ed com-parator C1and C2start operating and Qn is turned on.Cx then discharges through Qn.The voltage at the node R/C external falls.When it reaches V REFL the output of comparator C1 becomes low.This in turn resets the flip-flop and Qn is turned off.At this point C1stops functioning but C2continues to operate.The voltage at R/C external begins to rise with a time constant set by the external components Rx,Cx. Triggering the multivibrator causes Q to go high after internal delay due to the flip-flop and the gate.Q re-mains high until the voltage at R/C external rises again to V REFH.At this point C2output goes low and O goes low.C2stop operating.That means that after triggering when the voltage R/C external re-turns to V REFH the multivibrator has returned to its MONOSTABLE STATE.In the case where Rx⋅Cx are large enough and the discharge time of the ca-pacitor and the delay time in the I.C.can be ignored, the width of the output pulse tw(out)is as follows: t W(OUT)=0.46Cx⋅Rx(HC123)t W(OUT)=Cx⋅Rx(HC123A)M54/M74HC123/123A3/14FUNCTIONAL DESCRIPTION(continued)RE-TRIGGERED OPERATIONWhen a second trigger pulse follows the first its ef-fect will depend on the state of the multivibrator.If the capacitor Cx is being charged the voltage level of R/C external falls to Vrefl again and Q remains high i.e.the retrigger pulse arrives in a time shorter than the period Rx⋅Cx seconds,the capacitor charging time constant.If the second trigger pulse is very close to the initial trigger pulse it is ineffective ;i.e.the second trigger must arrive in the capacitor discharge cycle to be ineffective;Hence the mini-mum time for a second trigger to be effective de-pends on V CC and Cx.RESET OPERATIONCL is normally high.If CL is low,the trigger is not ef-fective because Q output goes low and trigger con-trol flip-flop is reset.Also transistor Op is turned on and Cx is charged quicky to V CC.This means if CL input goes low,the IC becomes waiting state both in operating and non operatin g state.TRUTH TABLEINPUTS OUTPUTSNOTEA B CL Q QH H OUTPUT ENABLEX L H L H INHIBITH X H L H INHIBITL H OUTPUT ENABLE L H OUTPUT ENABLE X X L L H INHIBITX:Don’t Care Z:High ImpedanceINPUT AND OUTPUT EQUIVALENT CIRCUITM54/M74HC123/123A4/14PIN DESCRIPTIONPIN No SYMBOL NAME AND FUNCTION 1,91A,2A Trigger Inputs(NegativeEdge Triggered) 2,101B,2B Trigger Inputs(PositiveEdge Triggered)3,111CLR,2CLR Direct Reset LOW and Trigger Action at Positive Edge4,121Q,2Q Outputs(Active LOW) 72R EXT/C EXT External ResistorCapacitor Connection 13,51Q,2Q Outputs(Active HIGH)14,61C EXT2C EXT External Capacitor Connection151R EXT/C EXT External ResistorCapacitor Connection8GND Ground(0V)16V CC Positive Supply VoltageIEC LOGIC SYMBOLABSOLUTE MAXIMUM RATINGSymbol Parameter Value Unit V CC Supply Voltage-0.5to+7V V I DC Input Voltage-0.5to V CC+0.5V V O DC Output Voltage-0.5to V CC+0.5VI IK DC Input Diode Current±20mAI OK DC Output Diode Current±20mAI O DC Output Source Sink Current Per Output Pin±25mAI CC or I GND DC V CC or Ground Current±50mAP D Power Dissipation500(*)mW T stg Storage Temperature-65to+150o C T L Lead Temperature(10sec)300o C Absolute Maximum Ratings are those values beyond whichdamage to the device may occu r.Functiona l ope ration und er these cond ition isnotimplied. (*)500mW:≅65o C derate to300mW by10mW/o C:65o C to85o CM54/M74HC123/123A5/14DC SPECIFICATIONSSymbolParameterTest ConditionsValueUnitV CC (V)T A =25oC 54HC and 74HC -40to 85o C 74HC -55to 125o C54HC Min.Typ.Max.Min.Max.Min.Max.V IHHigh Level Input Voltage 2.0 1.5 1.5 1.5V4.5 3.15 3.15 3.156.0 4.24.24.2V ILLow Level Input Voltage 2.00.50.50.5V4.5 1.35 1.35 1.356.0 1.81.81.8V OHHigh Level Output Voltage2.0V I =V IH orV IL I O =-20µA 1.9 2.0 1.9 1.9V4.5 4.4 4.5 4.4 4.46.05.96.0 5.9 5.94.5I O =-4.0mA4.18 4.31 4.13 4.106.0I O =-5.2mA 5.685.8 5.635.60V OLLow Level Output Voltage2.0V I =V IH orV IL I O =20µA 0.00.10.10.1V4.50.00.10.10.16.00.00.10.10.14.5I O =4.0mA 0.170.260.330.406.0I O =5.2mA 0.180.260.330.40I I Input Leakage Current6.0V I =V CC or GND ±0.1±1±1µA I I R/C Terminal Off State Current 6.0V I =V CC or GND ±0.1±1±1µA I CC Quiescent Supply Current6.0V I =V CC or GND 44080µA I CC ’Active StateSupply Current (1)2.0V I =V CC or GND Pin 7or 15V IN =V CC /245200260320µA 4.5500600780960µA 6.00.711.31.6mA(1):Per CircuitRECOMMENDED OPERATING CONDITIONSSymbol ParameterValue Unit V CC Supply Voltage 2to 6V V I Input Voltage 0to V CC V V O Output Voltage0to V CC VT op Operating Temperature:M54HC SeriesM74HC Series-55to +125-40to +85o C oC t r ,t fInput Rise and Fall Time0to 1000ns0to 5000to 400C X External Capacitor NO LIMITATIONpFR XExternal ResistorV CC <3V 5K to 1M ΩV CC ≥3V1K to 1M(*)The maximum allowable values of Cx and Rx are a function of leakage of capa citor Cx,the leakage of device and leakage due to the board layout and surface resistance.Susce ptibility to externally induced noise may occur for Rx >1M ΩM54/M74HC123/123A6/14AC ELECTRICAL CHARACTERISTICS(C L=50pF,Input t r=t f=6ns)Symbol ParameterTest Conditions ValueUnit V CC(V)T A=25o C54HC and74HC-40to85o C74HC-55to125o C54HCMin.Typ.Max.Min.Max.Min.Max.t TLH t THL Output TransitionTime2.0307595110ns4.581519226.07131619t PLH t PHL PropagationDelay Time(A,B-Q,Q)2.0102210265315ns4.5294253636.022364554t PLH t PHL PropagationDelay Time(C L RTR IGGE R-Q,Q)2.0102235295355ns4.5314759716.023405060t PLH t PHL PropagationDelay Time(CLR-Q,Q)2.068160200240ns4.5203240486.016273441t WOUT Output PulseWidth(for HC123)2.0C X=100pFR X=10KΩ1.4µs 4.5 1.26.0 1.12.0C X=0.1µFR X=100KΩ4.6ms 4.5 4.46.0 4.3t WOUT Output PulseWidth(for HC123A)2.0C X=100pFR X=10KΩ1.9µs 4.5 1.66.0 1.52.0C X=0.1µFR X=100KΩ9.8ms 4.59.56.09.4∆t WOUT Output PulseWidth ErrorBetween Circuitsin Same Package ±1%t W(H) t W(L)Minimum PulseWidth2.07595110ns4.51519226.0131619t W(L)Minimum PulseWidth(CLR)2.07595110ns 4.51519226.0131619t rr MinimumRetrigger Time 2.0C X=100pFR X=1KΩ325ns 4.51086.0782.0C X=0.1µFR X=100KΩ5µs 4.5 1.46.0 1.2C IN Input Capacitance5101010pFC PD(*)Power DissipationCapacitance 162pF(*)C PD is defined as the value of the IC’s internal equivalent capac itanc e which is calculated from the operating current con sump tion without load. (RefertoTestCircuit).Average opertingcurrent canbeobtained by thefollowing equation.I CC(opr)=C PD•V CC•f IN+I CC’Duty/100+I C/2(per monos table) (I CC’:Active Supply Current)(Duty:%)M54/M74HC123/123A7/14Output Pulse Width Constant Characteristics (for HC123)Output Pulse Width Characteristics(for HC123)Output Pulse Width Constant Characteristics (for HC123A)Output Pulse Width Characteristics(for HC123A)M54/M74HC123/123A 8/14M54/M74HC123/123A TEST CIRCUIT I CC(Opr)*TRANSITION TIME OF INPUT WAVEFORM IS THE SAME ASTHAT IN SASE OF SWITCHINGCHARACTERISTICS TESTS.SWITCHING CHARACTERISTICS TEST WAVEFORM9/14M54/M74HC123/123APlastic DIP16(0.25)MECHANICAL DATAmm inch DIM.MIN.TYP.MAX.MIN.TYP.MAX.a10.510.020B0.77 1.650.0300.065 b0.50.020b10.250.010D200.787 E8.50.335e 2.540.100e317.780.700F7.10.280I 5.10.201L 3.30.130Z 1.270.050P001C 10/14Ceramic DIP16/1MECHANICAL DATAmm inchDIM.MIN.TYP.MAX.MIN.TYP.MAX. A200.787 B70.276 D 3.30.130E0.380.015e317.780.700F 2.29 2.790.0900.110 G0.40.550.0160.022 H 1.17 1.520.0460.060 L0.220.310.0090.012 M0.51 1.270.0200.050 N10.30.406 P7.88.050.3070.317 Q 5.080.200P053DSO16(Narrow)MECHANICAL DATAmm inchDIM.MIN.TYP.MAX.MIN.TYP.MAX.A 1.750.068 a10.10.20.0040.007 a2 1.650.064 b0.350.460.0130.018 b10.190.250.0070.010 C0.50.019c145°(typ.)D9.8100.3850.393 E 5.8 6.20.2280.244 e 1.270.050e38.890.350F 3.8 4.00.1490.157G 4.6 5.30.1810.208 L0.5 1.270.0190.050 M0.620.024 S8°(max.)P013HPLCC20MECHANICAL DATAmm inchDIM.MIN.TYP.MAX.MIN.TYP.MAX. A9.7810.030.3850.395 B8.899.040.3500.356 D 4.2 4.570.1650.180 d1 2.540.100d20.560.022E7.378.380.2900.330 e 1.270.050e3 5.080.200F0.380.015G0.1010.004 M 1.270.050M1 1.140.045P027AInformation furnished is believed to be accurate and reliable.However,SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use.No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.Specificationsmentioned in this publication are subject to change without notice.This publication supersedes and replaces all information previously supplied.SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics.©1994SGS-THOMSON Microelectronics-All Rights ReservedSGS-THOMSON Microelectronics GROUP OF COMPANIESAustralia-Brazil-France-Germany-Hong Kong-Italy-Japan-Korea-Malaysia-Malta-Morocco-The Netherlands-Singapore-Spain-Sweden-Switzerland-Taiwan-Thailand-United Kingdom-U.S.A。

HD74HC123中文资料

DP-16 Conforms Conforms 1.07 g
元器件交易网
10.06
10.5 Max
16
9
5.5
1
8
0.80 Max
2.20 Max
0.10 ± 0.10
1.27
*0.42 ± 0.08 0.40 ± 0.06
0.15 0.12 M
*Dimension including the plating thickness Base material dimension
Output rise time tTLH
2.0
— — 75 — 95 ns
4.5
— 5 15 — 19
6.0
— — 13 — 16
Output fall time tTHL
2.0
— — 75 — 95 ns
4.5
— 5 15 — 19
6.0
— — 13 — 16
Pulse width
tw
2.0
150 — — 190 — ns A, B, Clear
VCC (V) 2.0 4.5
Min Typ Max Min — — 210 — — 22 42 —
Max Unit 265 ns 53
Test Conditions A, B or Clear to Q
6.0
— — 36 — 45
t PHL
2.0
— — 240 — 300 ns A, B or Clear to Q
4.5
— 1.0 — — — ms Cext = 0.1 µF, Rext = 10 kΩ
—
— 5 10 — 10 pF
Caution in use: In order to prevent any malfunctions due to noise, connect a high-frequency performance

IN74HC123中文资料

• • • •
ORDERING INFORMATION IN74HC123N Plastic IN74HC123D SOIC TA = -55° to 125° C for all packages
PIN ASSIGNMENT
PIN 16 =VCC PIN 8 = GND FUNCTION TABLE Inputs Outputs Note A B CRL Q Q H H Output Enable X L H L* H* Inhibit * * H X H L H Inhibit L H Output Enable L H Output Enable X X L L H Inhibit X = don’t care * - except for monostable period
元器件交易网
IN74HC123
DUAL LE MONOSTABLE MULTIVIBRATOR
The IN74HC123 is identical in pinout to the LS/ALS123. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. There are two trigger inputs, A INPUT (negative edge) and B INPUT (positive edge). These inputs are valid for rising/falling signals. The device may also be triggered by using the CLR input (positive-edge) because of the Schmitt-trigger input; after triggering the output maintains the MONOSTABLE state for the time period determined by the external resistor RX and capacitor CX. Taking CRL low breaks this MONOSTABLE STATE. If the next trigger pulse occurs during the MONOSTABLE period it makes the MONOSTABLE period longer. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 3.0 to 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices LOGIC DIAGRAM

74HC123中文资料

Product speciﬁcation
74HC/HCT123
ORDERING INFORMATION
TYPE NUMBER
74HC123N; 74HCT123N 74HC123D; 74HCT123D 74HC123DB; 74HCT123DB 74HC123PW; 74HCT123PW
NAME DIP16
26 26 ns
nRD to nQ, nQ
REXT = 5 kΩ; CEXT = 0 pF
20
23
ns
CI
input capacitance
3.5 3.5 pF
CPD
power dissipation
capacitance per
notes 1 and 2 54 56 pF
monostable
Notes
An internal connection from nRD to the input gates makes it possible to trigger the circuit by a positive-going signal at input nRD as shown in the function table. Figures 7 and 8 illustrate pulse control by retriggering
2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V
1998 Jul 08
2
元器件交易网
Philips Semiconductors
Dual retriggerable monostable multivibrator with reset

常用74系列标准数字电路的中文名称资料

常用74系列标准数字电路的中文名称资料收藏常用74系列标准数字电路的中文名称资料器件代号器件名称74 74LS 74HC00 四2输入端与非门√√√01 四2输入端与非门(OC) √√02 四2输入端或非门√√√03 四2输入端与非门(OC) √√04 六反相器√√√05 六反相器(OC) √√06 六高压输出反相器(OC,30V) √√07 六高压输出缓冲,驱动器(OC,30V) √√√08 四2输入端与门√√√09 四2输入端与门(OC) √√√10 三3输入端与非门√√√11 三3输入端与门√√12 三3输入端与非门(OC) √√√13 双4输入端与非门√√√14 六反相器√√√15 三3输入端与门(OC) √√16 六高压输出反相器(OC,15V) √17 六高压输出缓冲,驱动器(OC,15V) √20 双4输入端与非门√√√21 双4输入端与门√√√22 双4输入端与非门(OC) √√25 双4输入端或非门(有选通端) √√√26 四2输入端高压输出与非缓冲器√√√27 三3输入端或非门√√√28 四2输入端或非缓冲器√√√器件代号器件名称74 74LS 74HC30 8输入端与非门√√√32 四2输入端或门√√√33 四2输入端或非缓冲器(OC) √√37 四2输入端与非缓冲器√√38 四2输入端与非缓冲器(OC) √√40 双4输入端与非缓冲器√√√42 4线-10线译码器(BCD输入) √√43 4线-10线译码器(余3码输入) √44 4线-10线译码器(余3葛莱码输入) √48 4线-7段译码器√49 4线-7段译码器√50 双2路2-2输入与或非门√√√51 2路3-3输入,2路2-2输入与或非门√√√52 4路2-3-2-2输入与或门√53 4路2-2-2-2输入与或非门√54 4路2-3-3-2输入与或非门√√55 2路4-4输入与或非门√60 双4输入与扩展器√√61 三3输入与扩展器√62 4路2-3-3-2输入与或扩展器√64 4路4-2-3-2输入与或非门√65 4路4-2-3-2输入与或非门(OC) √70 与门输入J-K触发器√71 与或门输入J-K触发器√72 与门输入J-K触发器√器件代号器件名称74 74LS 74HC74 双上升沿D型触发器√√78 双D型触发器√√85 四位数值比较器√86 四2输入端异或门√√√87 4位二进制原码/反码√95 4位移位寄存器√101 与或门输入J-K触发器√102 与门输入J-K触发器√107 双主-从J-K触发器√108 双主-从J-K触发器√74F74是高速的TTL芯片和74HC一样就是速度高109 双主-从J-K触发器√110 与门输入J-K触发器√111 双主-从J-K触发器√√112 双下降沿J-K触发器√113 双下降沿J-K触发器√114 双下降沿J-K触发器√116 双4位锁存器√120 双脉冲同步驱动器√121 单稳态触发器√√√122 可重触发单稳态触发器√√√123 可重触发双稳态触发器√√√125 四总线缓冲器√√√126 四总线缓冲器√√√128 四2输入端或非线驱动器√√√132 四2输入端与非门√√√d触发器芯片有:74HC74 74LS90 双D触发器74LS7474LS364八D触发器（三态）7474、74 H74、74F74、74ALS74、74L74、74LS74A、74S74、74HC73、74C74双D型正沿触发器（带预置和清除端）74174、74LS174、74F174、74ALS174、74S174、74HC174、74C174六D型触发器（带清除端）74175、74LS175、74F175、74ALS175、74S175、74HC175、74C175 四D型触发器（带清除端）74273、74LS273、74S273、74F273、74ALS273、74HC273 八D型触发器（带清除端）74LS364八D触发器（三态）74LS377、74F377、74S3777八D 触发器74LS378、74F378、74S378、74HC378六D 触发器74LS379、74F379、74S379、74HC379八D 触发器。

74hc系列芯片的功能介绍

74hc系列芯片的功能介绍74HC01 2输入四与非门 (oc)74HC02 2输入四或非门74HC03 2输入四与非门 (oc)74HC04 六倒相器74HC05 六倒相器(oc)74HC06 六高压输出反相缓冲器/驱动器(oc,30v) 74HC07 六高压输出缓冲器/驱动器(oc,30v)74HC08 2输入四与门74HC09 2输入四与门(oc)74HC10 3输入三与非门74HC11 3输入三与门74HC12 3输入三与非门 (oc)74HC13 4输入双与非门 (斯密特触发)74HC14 六倒相器(斯密特触发)74HC15 3输入三与门 (oc)74HC16 六高压输出反相缓冲器/驱动器(oc,15v) 74HC17 六高压输出缓冲器/驱动器(oc,15v)74HC18 4输入双与非门 (斯密特触发)74HC19 六倒相器(斯密特触发)74HC20 4输入双与非门74HC21 4输入双与门74HC22 4输入双与非门(oc)74HC23 双可扩展的输入或非门74HC24 2输入四与非门(斯密特触发)74HC25 4输入双或非门(有选通)74HC26 2输入四高电平接口与非缓冲器(oc,15v) 74HC27 3输入三或非门74HC28 2输入四或非缓冲器74HC30 8输入与非门74HC31 延迟电路74HC32 2输入四或门74HC33 2输入四或非缓冲器(集电极开路输出) 74HC34 六缓冲器74HC35 六缓冲器(oc)74HC36 2输入四或非门(有选通)74HC37 2输入四与非缓冲器74HC38 2输入四或非缓冲器(集电极开路输出) 74HC39 2输入四或非缓冲器(集电极开路输出) 74HC40 4输入双与非缓冲器74HC41 bcd-十进制计数器74HC42 4线-10线译码器(bcd输入)74HC43 4线-10线译码器(余3码输入)74HC44 4线-10线译码器(余3葛莱码输入) 74HC45 bcd-十进制译码器/驱动器74HC46 bcd-七段译码器/驱动器74HC47 bcd-七段译码器/驱动器74HC48 bcd-七段译码器/驱动器74HC49 bcd-七段译码器/驱动器(oc)74HC50 双二路2-2输入与或非门(一门可扩展) 74HC51 双二路2-2输入与或非门74HC51 二路3-3输入,二路2-2输入与或非门74HC52 四路2-3-2-2输入与或门(可扩展)74HC53 四路2-2-2-2输入与或非门(可扩展) 74HC53 四路2-2-3-2输入与或非门(可扩展) 74HC54 四路2-2-2-2输入与或非门74HC54 四路2-3-3-2输入与或非门74HC54 四路2-2-3-2输入与或非门74HC55 二路4-4输入与或非门(可扩展)74HC60 双四输入与扩展74HC61 三3输入与扩展74HC62 四路2-3-3-2输入与或扩展器74HC63 六电流读出接口门74HC64 四路4-2-3-2输入与或非门74HC65 四路4-2-3-2输入与或非门(oc)74HC70 与门输入上升沿jk触发器74HC71 与输入r-s主从触发器74HC72 与门输入主从jk触发器74HC73 双j-k触发器(带清除端)74HC74 正沿触发双d型触发器(带预置端和清除端)74HC75 4位双稳锁存器74HC76 双j-k触发器(带预置端和清除端)74HC77 4位双稳态锁存器74HC78 双j-k触发器(带预置端,公共清除端和公共时钟端) 74HC80 门控全加器74HC81 16位随机存取存储器74HC82 2位二进制全加器(快速进位)74HC83 4位二进制全加器(快速进位)74HC84 16位随机存取存储器74HC85 4位数字比较器74HC86 2输入四异或门74HC87 四位二进制原码/反码/oi单元74HC89 64位读/写存储器74HC90 十进制计数器74HC91 八位移位寄存器74HC92 12分频计数器(2分频和6分频)74HC93 4位二进制计数器74HC94 4位移位寄存器(异步)74HC95 4位移位寄存器(并行io)74HC96 5位移位寄存器74HC97 六位同步二进制比率乘法器74HC100 八位双稳锁存器74HC103 负沿触发双j-k主从触发器(带清除端)74HC106 负沿触发双j-k主从触发器(带预置,清除,时钟) 74HC107 双j-k主从触发器(带清除端)74HC108 双j-k主从触发器(带预置,清除,时钟)74HC109 双j-k触发器(带置位,清除,正触发)74HC110 与门输入j-k主从触发器(带锁定)74HC111 双j-k主从触发器(带数据锁定)74HC112 负沿触发双j-k触发器(带预置端和清除端) 74HC113 负沿触发双j-k触发器(带预置端)74HC114 双j-k触发器(带预置端,共清除端和时钟端) 74HC116 双四位锁存器74HC120 双脉冲同步器/驱动器74HC121 单稳态触发器(施密特触发)74HC122 可再触发单稳态多谐振荡器(带清除端)74HC123 可再触发双单稳多谐振荡器74HC125 四总线缓冲门(三态输出)74HC126 四总线缓冲门(三态输出)74HC128 2输入四或非线驱动器74HC131 3-8译码器74HC132 2输入四与非门(斯密特触发)74HC133 13输入端与非门74HC134 12输入端与门(三态输出)74HC135 四异或/异或非门74HC136 2输入四异或门(oc)74HC137 八选1锁存译码器/多路转换器74HC138 3-8线译码器/多路转换器74HC139 双2-4线译码器/多路转换器74HC140 双4输入与非线驱动器74HC141 bcd-十进制译码器/驱动器74HC142 计数器/锁存器/译码器/驱动器74HC145 4-10译码器/驱动器74HC147 10线-4线优先编码器74HC148 8线-3线八进制优先编码器74HC150 16选1数据选择器(反补输出)74HC151 8选1数据选择器(互补输出)74HC152 8选1数据选择器多路开关74HC153 双4选1数据选择器/多路选择器74HC154 4线-16线译码器74HC155 双2-4译码器/分配器(图腾柱输出)74HC156 双2-4译码器/分配器(集电极开路输出) 74HC157 四2选1数据选择器/多路选择器74HC158 四2选1数据选择器(反相输出)74HC160 可预置bcd计数器(异步清除)74HC161 可预置四位二进制计数器(并清除异步) 74HC162 可预置bcd计数器(异步清除)74HC163 可预置四位二进制计数器(并清除异步) 74HC164 8位并行输出串行移位寄存器74HC165 并行输入8位移位寄存器(补码输出) 74HC166 8位移位寄存器74HC167 同步十进制比率乘法器74HC168 4位加/减同步计数器(十进制)74HC169 同步二进制可逆计数器74HC170 4*4寄存器堆74HC171 四d触发器(带清除端)74HC172 16位寄存器堆74HC173 4位d型寄存器(带清除端)74HC174 六d触发器74HC175 四d触发器74HC176 十进制可预置计数器74HC177 2-8-16进制可预置计数器74HC178 四位通用移位寄存器74HC179 四位通用移位寄存器74HC180 九位奇偶产生/校验器74HC181 算术逻辑单元/功能发生器74HC182 先行进位发生器74HC183 双保留进位全加器74HC184 bcd-二进制转换器74HC185 二进制-bcd转换器74HC190 同步可逆计数器(bcd,二进制)74HC191 同步可逆计数器(bcd,二进制)74HC192 同步可逆计数器(bcd,二进制)74HC193 同步可逆计数器(bcd,二进制)74HC199 八位移位寄存器74HC210 2-5-10进制计数器74HC213 2-n-10可变进制计数器74HC221 双单稳触发器74HC230 八3态总线驱动器74HC231 八3态总线反向驱动器74HC240 八缓冲器/线驱动器/线接收器(反码三态输出) 74HC241 八缓冲器/线驱动器/线接收器(原码三态输出) 74HC242 八缓冲器/线驱动器/线接收器74HC243 4同相三态总线收发器74HC244 八缓冲器/线驱动器/线接收器74HC245 八双向总线收发器74HC246 4线-七段译码/驱动器(30v)74HC247 4线-七段译码/驱动器(15v)74HC248 4线-七段译码/驱动器74HC249 4线-七段译码/驱动器74HC251 8选1数据选择器(三态输出)74HC253 双四选1数据选择器(三态输出)74HC256 双四位可寻址锁存器74HC257 四2选1数据选择器(三态输出)74HC258 四2选1数据选择器(反码三态输出) 74HC259 8为可寻址锁存器74HC260 双5输入或非门74HC261 4*2并行二进制乘法器74HC265 四互补输出元件74HC266 2输入四异或非门(oc)74HC270 2048位rom (512位四字节,oc) 74HC271 2048位rom (256位八字节,oc) 74HC273 八d触发器74HC274 4*4并行二进制乘法器74HC275 七位片式华莱士树乘法器74HC276 四jk触发器74HC278 四位可级联优先寄存器74HC279 四s-r锁存器74HC280 9位奇数/偶数奇偶发生器/较验器74HC28174HC283 4位二进制全加器74HC290 十进制计数器74HC291 32位可编程模74HC293 4位二进制计数器74HC294 16位可编程模74HC295 四位双向通用移位寄存器74HC298 四-2输入多路转换器(带选通)74HC299 八位通用移位寄存器(三态输出)74HC348 8-3线优先编码器(三态输出)74HC352 双四选1数据选择器/多路转换器74HC353 双4-1线数据选择器(三态输出)74HC354 8输入端多路转换器/数据选择器/寄存器,三态补码输出74HC355 8输入端多路转换器/数据选择器/寄存器,三态补码输出74HC356 8输入端多路转换器/数据选择器/寄存器,三态补码输出74HC357 8输入端多路转换器/数据选择器/寄存器,三态补码输出74HC365 6总线驱动器74HC366 六反向三态缓冲器/线驱动器74HC367 六同向三态缓冲器/线驱动器74HC368 六反向三态缓冲器/线驱动器74HC373 八d锁存器74HC374 八d触发器(三态同相)74HC375 4位双稳态锁存器74HC377 带使能的八d触发器74HC378 六d触发器74HC379 四d触发器74HC381 算术逻辑单元/函数发生器74HC382 算术逻辑单元/函数发生器74HC384 8位*1位补码乘法器74HC385 四串行加法器/乘法器74HC386 2输入四异或门74HC390 双十进制计数器74HC391 双四位二进制计数器74HC395 4位通用移位寄存器74HC396 八位存储寄存器74HC398 四2输入端多路开关(双路输出)74HC399 四-2输入多路转换器(带选通)74HC422 单稳态触发器74HC423 双单稳态触发器74HC440 四3方向总线收发器,集电极开路74HC441 四3方向总线收发器,集电极开路74HC442 四3方向总线收发器,三态输出74HC443 四3方向总线收发器,三态输出74HC444 四3方向总线收发器,三态输出74HC445 bcd-十进制译码器/驱动器,三态输出74HC446 有方向控制的双总线收发器74HC448 四3方向总线收发器,三态输出74HC449 有方向控制的双总线收发器74HC465 八三态线缓冲器74HC466 八三态线反向缓冲器74HC467 八三态线缓冲器74HC468 八三态线反向缓冲器74HC490 双十进制计数器74HC540 八位三态总线缓冲器(反向)74HC541 八位三态总线缓冲器74HC589 有输入锁存的并入串出移位寄存器74HC590 带输出寄存器的8位二进制计数器74HC591 带输出寄存器的8位二进制计数器74HC592 带输出寄存器的8位二进制计数器74HC593 带输出寄存器的8位二进制计数器74HC594 带输出锁存的8位串入并出移位寄存器74HC595 8位输出锁存移位寄存器74HC596 带输出锁存的8位串入并出移位寄存器74HC597 8位输出锁存移位寄存器74HC598 带输入锁存的并入串出移位寄存器74HC599 带输出锁存的8位串入并出移位寄存器74HC604 双8位锁存器74HC605 双8位锁存器74HC606 双8位锁存器74HC607 双8位锁存器74HC620 8位三态总线发送接收器(反相)74HC621 8位总线收发器74HC622 8位总线收发器74HC623 8位总线收发器74HC640 反相总线收发器(三态输出)74HC641 同相8总线收发器,集电极开路74HC642 同相8总线收发器,集电极开路74HC643 8位三态总线发送接收器74HC644 真值反相8总线收发器,集电极开路74HC645 三态同相8总线收发器74HC646 八位总线收发器,寄存器74HC647 八位总线收发器,寄存器74HC648 八位总线收发器,寄存器74HC649 八位总线收发器,寄存器74HC651 三态反相8总线收发器74HC652 三态反相8总线收发器74HC653 反相8总线收发器,集电极开路74HC654 同相8总线收发器,集电极开路74HC668 4位同步加/减十进制计数器74HC669 带先行进位的4位同步二进制可逆计数器74HC670 4*4寄存器堆(三态)74HC671 带输出寄存的四位并入并出移位寄存器74HC672 带输出寄存的四位并入并出移位寄存器74HC673 16位并行输出存储器,16位串入串出移位寄存器74HC674 16位并行输入串行输出移位寄存器74HC681 4位并行二进制累加器74HC682 8位数值比较器(图腾柱输出)74HC683 8位数值比较器(集电极开路)74HC684 8位数值比较器(图腾柱输出)74HC685 8位数值比较器(集电极开路)74HC686 8位数值比较器(图腾柱输出)74HC687 8位数值比较器(集电极开路)74HC688 8位数字比较器(oc输出)74HC689 8位数字比较器74HC690 同步十进制计数器/寄存器(带数选,三态输出,直接清除) 74HC691 计数器/寄存器(带多转换,三态输出)74HC692 同步十进制计数器(带预置输入,同步清除)74HC693 计数器/寄存器(带多转换,三态输出)74HC696 同步加/减十进制计数器/寄存器(带数选,三态输出,直接清除)74HC697 计数器/寄存器(带多转换,三态输出)74HC698 计数器/寄存器(带多转换,三态输出)74HC699 计数器/寄存器(带多转换,三态输出)74HC716 可编程模n十进制计数器74HC718 可编程模n十进制计数器。

HD74LV123AFP中文资料

HD74LV123ADual Retriggerable Monostable MultivibratorsADE-205-258C (Z)4th EditionJanuary 2001 DescriptionThe HD74LV123A features output pulse-duration control by three methods. In the first method, the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.The basic pulse duration is programmed by selecting external resistance and capacitance values.The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VccTo obtain variable pulse durations, connect an external variable resistance between Rext/Cext and Vcc. Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or high-level-active (B) input. Pulse duration can be reduced by taking CLR low.Features•V CC = 2.0 V to 5.5 V operation•All inputs V IH (Max.) = 5.5 V (@V CC = 0 V to 5.5 V)•All outputs V O (Max.) = 5.5 V (@V CC = 0 V)•Output current ±6 mA (@V CC = 3.0 V to 3.6 V), ±12 mA (@V CC = 4.5 V to 5.5 V)HD74LV123ARev.4, Jan. 2001, page 2 of 19Function TableInputs Outputs CLR A B Q Q L X X L H H H X L H H X L LHH L↑H ↓H ↑LHNote:H:High level L:Low level X:Immaterial↑:Low to high transition ↓:High to low transition :High level pulse :Low level pulsePin ArrangementHD74LV123ARev.4, Jan. 2001, page 3 of 19Absolute Maximum RatingsItemSymbol Ratings Unit ConditionsSupply voltage range V CC –0.5 to 7.0V Input voltage range *1V I –0.5 to 7.0V Output voltage range *V O –0.5 to V CC + 0.5V Output: H or L –0.5 to 7.0V CC : OFF Input clamp current I IK –20mA V I < 0Output clamp currentI OK ±50mA V O < 0 or V O > V CC Continuous output current I O±25mA V O = 0 to V CCContinuous current through V CC or GNDI CC or I GND ±50mA Maximum power dissipationat Ta = 25°C (in still air)*3P T785mWSOP 500TSSOPStorage temperatureTstg –65 to 150°CNotes:The absolute maximum ratings are values which must not individually be exceeded, and furthermore,no two of which may be realized at the same time.1.The input and output voltage ratings may be exceeded if the input and output clamp-currentratings are observed.2.This value is limited to 5.5 V maximum.3.The maximum package power dissipation was calculated using a junction temperature of 150°C.HD74LV123ARecommended Operating ConditionsItem Symbol Min Typ Max Unit Conditions Supply voltage range V CC 2.0— 5.5VInput voltage range V I0— 5.5VOutput voltage range V O0—V CC VOutput current I OH——–50µA V CC = 2.0 V——–2mA V CC = 2.3 to 2.7 V——–6V CC = 3.0 to 3.6 V——–12V CC = 4.5 to 5.5 VI OL——50µA V CC = 2.0 V——2mA V CC = 2.3 to 2.7 V——6V CC = 3.0 to 3.6 V——12V CC = 4.5 to 5.5 V Input transition rise or fall rate∆t /∆v0—200ns/V V CC = 2.3 to 2.7 V0—100V CC = 3.0 to 3.6 V0—20V CC = 4.5 to 5.5 V External timing registance Rext5——kΩV CC = 2.0 V1——V CC≥ 2.3 V External timing capacitance Cext—Unlimited—FPower-up ramp rate∆t /∆V CC1——ms/VOperating free-air temperature Ta–40—85°CNote:Unused or floating inputs must be held high or low.Rev.4, Jan. 2001, page 4 of 19HD74LV123A Logic DiagramRev.4, Jan. 2001, page 5 of 19HD74LV123ARev.4, Jan. 2001, page 6 of 19DC Electrical CharacteristicsTa = –40 to 85°CItem Symbol V CC (V)*Min Typ Max Unit Test ConditionsInput voltageV IH2.0 1.5——V2.3 to 2.7V CC × 0.7——3.0 to 3.6V CC × 0.7——4.5 to5.5V CC × 0.7——V IL2.0——0.52.3 to 2.7——V CC × 0.33.0 to 3.6——V CC × 0.34.5 to5.5——V CC × 0.3Output voltageV OHMin to Max V CC – 0.1——VI OH = –50 µA 2.3 2.0——I OH = –2 mA 3.0 2.48——I OH = –6 mA 4.53.8——I OH = –12 mA V OLMin to Max ——0.1I OL = 50 µA 2.3——0.4I OL = 2 mA 3.0——0.44I OL = 6 mA4.5——0.55I OL = 12 mA Input current I IN 0 to5.5——±1µA V IN = 5.5 V or GND Input current Rext / Cext I IN 5.5——±2.5µA V IN = V CC or GND Quiescent supply current I CC 5.5——20µA V IN = V CC or GND, I O = 0Active state supply current (per circuit)∆I CC2.3——220µA V IN = V CC or GND Rext/Cext = 0.5 V CC3.0——2804.5——6505.5——975Output leakage current I OFF 0——5µA V O = 5.5 V InputcapacitanceC IN3.3—4.0—pFV I = V CC or GNDNote:For conditions shown as Min or Max, use the appropriate values under recommended operatingconditions.HD74LV123ARev.4, Jan. 2001, page 7 of 19Switching CharacteristicsV CC = 2.5 ± 0.2 VTa = 25°CTa = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Test Conditions FROM (Input)TO(Output)Propa-gation delay timet PLH t PHL—13.531.41.037.0nsC L = 15 pFA or BQ or Q—16.036.0 1.042.0C L = 50 pF —11.025.0 1.029.5C L = 15 pF CLRQ or Q—13.032.8 1.034.5C L = 50 pF —14.033.4 1.039.0C L = 15 pF CLR Q or Q—16.038.0 1.044.0C L = 50 pF(Trigger)Output pulse widtht wQ—170260—320nsC L = 50 pF,Cext = 28 pF, Rext = 2 k Ω9010011090110µs C L = 50 pF,Cext = 0.01 µF, Rext = 10 k Ω0.91.0 1.10.9 1.1ms C L = 50 pF,Cext = 0.1 µF, Rext = 10 k Ω∆t wQ—±1———%C L = 50 pF Pulse width t w 6.0—— 6.5—ns A , B or CLRRetrigger timet rr—40———ns A , or B(Rext = 1 k Ω, Cext = 100 pF)—1.5———µsA , or B(Rext = 1 k Ω, Cext = 0.01 µF)HD74LV123ARev.4, Jan. 2001, page 8 of 19Switching Characteristics (cont)V CC = 3.3 ± 0.3 VTa = 25°CTa = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Test Conditions FROM (Input)TO(Output)Propa-gation delay timet PLH t PHL—9.720.61.024.0nsC L = 15 pFA or BQ or Q—11.524.1 1.027.5C L = 50 pF —8.015.8 1.018.5C L = 15 pF CLRQ or Q—9.519.3 1.022.0C L = 50 pF —9.922.4 1.026.0C L = 15 pF CLR Q or Q—11.525.9 1.029.5C L = 50 pF(Trigger)Output pulse widtht wQ—150240—300nsC L = 50 pF,Cext = 28 pF, Rext = 2 k Ω9010011090110µs C L = 50 pF,Cext = 0.01 µF, Rext = 10 k Ω0.91.0 1.10.9 1.1ms C L = 50 pF,Cext = 0.1 µF, Rext = 10 k Ω∆t wQ—±1———%C L = 50 pF Pulse width t w 5.0—— 5.0—ns A , B or CLRRetrigger timet rr—30———ns A , or B(Rext = 1 k Ω, Cext = 100 pF)—1.2———µsA , or B(Rext = 1 k Ω, Cext = 0.01 µF)HD74LV123ARev.4, Jan. 2001, page 9 of 19Switching Characteristics (cont)V CC = 5.0 ± 0.5 VTa = 25°CTa = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Test Conditions FROM (Input)TO(Output)Propa-gation delay timet PLH t PHL—7.312.01.014.0nsC L = 15 pFA or BQ or Q—8.514.0 1.016.0C L = 50 pF — 5.99.4 1.011.0C L = 15 pF CLRQ or Q—7.511.4 1.013.0C L = 50 pF —7.312.9 1.015.0C L = 15 pF CLR Q or Q—8.714.9 1.017.0C L = 50 pF(Trigger)Output pulse widtht wQ—140200—240nsC L = 50 pF,Cext = 28 pF, Rext = 2 k Ω9010011090110µs C L = 50 pF,Cext = 0.01 µF, Rext = 10 k Ω0.91.0 1.10.9 1.1ms C L = 50 pF,Cext = 0.1 µF, Rext = 10 k Ω∆t wQ—±1———%C L = 50 pF Pulse width t w 5.0—— 5.0—ns A , B or CLRRetrigger timet rr—20———ns A , or B(Rext = 1 k Ω, Cext = 100 pF)—0.95———µsA , or B(Rext = 1 k Ω, Cext = 0.01 µF)HD74LV123ARev.4, Jan. 2001, page 10 of 19Operating CharacteristicsC L = 50 pFTa = 25°CItem Symbol V CC (V)Min Typ Max Unit Test Conditions Power dissipation capacitanceC PD3.3—74.0—pFf = 10 MHz5.0—86.0—Test CircuitTiming diagramApplication DataPackage DimensionsDisclaimer1.Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,copyright, trademark, or other intellectual property rights for information contained in this document.Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.2.Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.3.Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as in aerospace, aeronautics, nuclear power, combustion control, transportation,traffic, safety equipment or medical equipment for life support.4.Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installationconditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safe devices,so that the equipment incorporating the Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.5.This product is not designed to be radiation resistant.6.No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.7.Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.Sales OfficesHitachi, Ltd.Semiconductor & Integrated Circuits.Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109Copyright Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.Hitachi Asia Ltd. Hitachi Tower16 Collyer Quay #20-00, Singapore 049318Tel : <65>-538-6533/538-8577 Fax : <65>-538-6933/538-3877URL : .sg URLNorthAmerica : /Europe : /hel/ecg Asia : Japan : http://www.hitachi.co.jp/Sicd/indx.htmHitachi Asia Ltd.(Taipei Branch Office)4/F, No. 167, Tun Hwa North Road, Hung-Kuo Building, Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TPURL : Hitachi Asia (Hong Kong) Ltd.Group III (Electronic Components) 7/F., North Tower, World Finance Centre,Harbour City, Canton Road Tsim Sha Tsui, Kowloon, Hong KongTel : <852>-(2)-735-9218 Fax : <852>-(2)-730-0281URL : Hitachi Europe Ltd.Electronic Components Group.Whitebrook ParkLower Cookham Road MaidenheadBerkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000Fax: <44> (1628) 585160Hitachi Europe GmbHElectronic Components Group Dornacher Stra§e 3D-85622 Feldkirchen, Munich GermanyTel: <49> (89) 9 9180-0Fax: <49> (89) 9 29 30 00Hitachi Semiconductor (America) Inc.179 East Tasman Drive,San Jose,CA 95134 Tel: <1> (408) 433-1990Fax: <1>(408) 433-0223For further information write to:Colophon 2.0。

74hc123d中文资料

摘要RTL8019AS封装有100引脚PQFP，其主要功能如下：超前角1-4,97-100：中断控制int0-7;角度33：复位控制;引脚34：使能控制角AEN，低电平有效;引脚6,7,70,89：数字电源+ 5V;针脚14、28、83、86：数字GND；47,57针：模拟电源：+ 5V；引脚44,52：模拟地；引脚7-13、15、16、18-27：ISA地址总线；引脚36-43、87、88、90-95：ISA数据总线；引脚31：引导ROM读取操作控制；引脚32：Boot ROM写操作控制；引脚62：Rx的LED1引脚接收数据显示；引脚63：TX的LED 2引脚发送数据显示;引脚58,59：在+/-中接收数据TP；引脚45,46：将数据TP输出+/-引脚50,51：外部晶体。

特性产品类别：单稳态多谐振荡器逻辑系列：74hc逻辑类型：双单稳态多谐振荡器包装/盒：sot-109传播延迟时间：51 NS最大功耗：500 MW最高工作温度：125 C最低工作温度：-40 C封装：管安装方式：SMD / SMT工作电源电压：2 V至6 V规格编辑产品种类: 单稳态多谐振荡器逻辑系列: 74HC逻辑类型: Dual Monostable Multivibrator封装/ 箱体: SOT-109传播延迟时间: 51 ns最大工作温度: 125 C最小工作温度: - 40 C封装: Tube安装风格: SMD/SMT工作电源电压: 2 V to 6 VPin description Symbol Pin Description1A 1 negative-edge triggered input 1（负边沿触发输入）1B 2 positive-edge triggered input 1（正面边缘触发输入）1RD 3 direct reset LOW and positive-edge triggered input 1 （直接复位低和正边缘触发输入）1Q 4 active LOW output 1（低电平输出）2Q 5 active HIGH output 2（高电平输出）2CEXT 6 external capacitor connection 2（外部电容连接）2REXT/CEXT 7 external resistor and capacitor connection 2（外部电容和电阻连接）GND 8 ground (0V)2A 9 negative-edge triggered input 2（负边沿触发输入）2B 10 positive-edge triggered input 2（正边沿触发输入）2RD 11 direct reset LOW and positive-edge triggered input 2 （直接复位低和正边缘触发输入）2Q 12 active LOW output 21Q 13 active HIGH output 11CEXT 14 external capacitor connection 11REXT/CEXT 15 external resistor and capacitor connection 1VCC 16 supply voltage。

M74HC123中文资料

sHIGH SPEED : t PD = 23 ns (TYP.) at V CC = 6V sLOW POWER DISSIPATION:STAND BY STATE :I CC =4µA (MAX.) at T A =25°C ACTIVE STATE :I CC =200µA (MAX.) at V CC = 5V sHIGH NOISE IMMUNITY:V NIH = V NIL = 28 % V CC (MIN.)sSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 4mA (MIN)sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsWIDE OPERATING VOLTAGE RANGE:V CC (OPR) = 2V to 6VsWIDE OUTPUT PULSE WIDTH RANGE : t WOUT = 120 ns ~ 60 s OVER AT V CC = 4.5 V sPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 123DESCRIPTIONThe M74HC123 is an high speed CMOS MONOSTABLE MULTIVIBRATOR fabricated with silicon gate C 2MOS technology.There are two trigger inputs, A INPUT (negative edge) and B INPUT (positive edge). These inputs are valid for slow rising/falling signals, (tr=tf=l sec).The device may also be triggered by using the CLR input (positive-edge) because of the Schmitt-trigger input; after triggering the output maintains the MONOSTABLE state for the time period determined by the external resistor Rx and capacitor Cx. When Cx > 10nF and Rx > 10K Ω,the output pulse width value is approsimatively given by the formula : tW(OUT) = K · Cx · Rx.(K ≅ 0.45).Taking CLR low breaks this MONOSTABLE STATE. If the next trigger pulse occurs during the MONOSTABLE period it makes the MONOSTABLE period longer. Limit for values of Cx and Rx : Cx : NO LIMIT Rx : V cc < 3.0V 5K Ω to 1M Ω V cc > 3.0V 1K Ω to 1M ΩAll inputs are equipped with protection circuits against static discharge and transient excess voltage.M74HC123DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORPIN CONNECTION AND IEC LOGIC SYMBOLSORDER CODESPACKAGE TUBE T & RDIP M74HC123B1R SOP M74HC123M1RM74HC123RM13TR TSSOPM74HC123TTRM74HC1232/12INPUT AND OUTPUT EQUIVALENT CIRCUITPIN DESCRIPTIONTRUTH TABLEPIN No SYMBOL NAME AND FUNCTION 1,91A, 2A Trigger Inputs (Negative Edge Triggered)2, 101B, 2B Trigger Inputs (Positive Edge Triggered)3, 11 1 CLR 2 CLR Direct Reset LOW and trigger Action at Positive Edge4, 121Q, 2Q Outputs (Active Low)72R X /C X External ResistorCapacitor Connection 13, 51Q, 2Q Outputs (Active High)14, 6 1C X 2C X External Capacitor Connection151R X /C X External ResistorCapacitor Connection 8GND Ground (0V)16VccPositive Supply VoltageM74HC123 SYSTEM DIAGRAMThis logic diagram has not be used to estimate propagation delaysTIMING CHART3/12M74HC1234/12BLOCK DIAGRAM(2) Dx is a clamping diode.The external capacitor is charged to Vcc in the stand-by-state, i.e. no trigger. When the supply voltage is turned off Cx is di scharged mainly trough an internal parasitic diode(see figures). If Cx is sufficiently large and Vcc decreases rapidly, there will be some possibility of damaging the I.C. with a surge current or latch-up. If the voltage supply filter capacitor is large enough and Vcc decrease slowly, the surge current is automatically limited and damage to the I.C. is avoided. The maximum forward current of the parasitic diode is approximately 20 mA. In cases where Cx is large the time taken for the supply voltage to fall to 0.4 Vcc can be calculated as follows : t f > (Vcc - 0.7) x Cx/20mAIn cases where t f is too short an external clamping diode is required to protect the I.C. from the surge current.FUNCTIONAL DESCRIPTION STAND-BY STATEThe external capacitor,Cx, is fully charged to Vcc in the stand-by state. Hence, before triggering,transistor Qp and Qn (connected to the Rx/Cx node) are both turned-off. The two comparators that control the timing and the two reference voltage sources stop operating. The total supply current is therefore only leakage current.TRIGGER OPERATION Triggering occurs when :1 st) A is "LOW" and B has a falling edge;2 nd) B is "HIGH" and A has a rising edge;3 rd) A is "LOW" and B is HIGH and C1 has a rising edge;After the multivibrator has been retriggered comparator C1 and C2 start operating and Qn is turned on. Cx then discharges through Qn. The voltage at the node R/C external falls.When it reaches V REFL the output of comparator C1 becomes low. This in turn reset the flip-flop and Qn is turned off.At this point C1 stops functioning but C2 continues to operate.The voltage at R/C external begins to rise with a time constant set by the external components Rx,Cx.Triggering the multivibrator causes Q to go high after internal delay due to the flip-flop and the gate. Q remains high until the voltage at R/C external rises again to V REFH . At this point C2output goes low and O goes low. C2 stop operating. That means that after triggering when the voltage R/C external returns to V REFH the multivibrator has returned to its MONOSTABLE STATE. In the case where Rx · Cx are large enough and the discharge time of the capacitor and the delay time in the I.C. can be ignored, the width of the output pulse tw (out) is as follows :tW(OUT) = 0.45 Cx · RxRE - TRIGGERED OPERATIONWhen a second trigger pulse follows the first its effect will depend on the state of the multivibrator.If the capacitor Cx is being charged the voltage level of R/C external falls to V REFL again and Q remains High i.e. the retrigger pulse arrives in a time shorter than the period Rx · Cx seconds, the capacitor charging time constant. If the second trigger pulse is very close to the initial trigger pulse it is ineffective ; i.e. the second trigger must arrive in the capacitor discharge cycle to be ineffective;Hence the minimum time for a second trigger to be effective depends on Vcc and Cx RESET OPERATIONCL is normally high. If CL is low, the trigger is not effective because Q output goes low and trigger control flip-flop is reset.Also transistor Op is turned on and Cx is charged quickly to Vcc. This means if CL input goes low the IC becomes waiting state both in operating and non operating state.M74HC1235/12ABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°CRECOMMENDED OPERATING CONDITIONSThe Maximum allowable values of Cx and Rx are a function of leakage of capacitor Cx, the leakage of device and leakage due to the board layout and surface resistance. Susceptibility to externally induced noise may occur for Rx > 1M ΩSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7V V I DC Input Voltage -0.5 to V CC + 0.5V V O DC Output Voltage -0.5 to V CC + 0.5V I IK DC Input Diode Current ± 20mA I OK DC Output Diode Current ± 20mA I O DC Output Current ± 25mA I CC or I GND DC V CC or Ground Current± 50mA P D Power Dissipation 500(*)mW T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°CSymbol ParameterValue Unit V CC Supply Voltage 2 to 6V V I Input Voltage 0 to V CC V V O Output Voltage 0 to V CC V T op Operating Temperature -55 to 125°C t r , t f Input Rise and Fall TimeV CC = 2.0V 0 to 1000ns V CC = 4.5V 0 to 500ns V CC = 6.0V 0 to 400ns Cx External Capacitor NO LIMITATIONpFRxExternal Resistor Vcc < 3V 5K to 1M ΩVcc > 3V1K to 1MM74HC1236/12DC SPECIFICATIONS(1) : Per CircuitSymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.V IHHigh Level Input Voltage2.0 1.5 1.5 1.5V 4.53.15 3.15 3.156.04.24.24.2V ILLow Level Input Voltage2.00.50.50.5V4.5 1.35 1.35 1.356.0 1.81.81.8V OHHigh Level Output Voltage2.0I O =-20 µA 1.9 2.0 1.9 1.9V4.5I O =-20 µA 4.4 4.5 4.4 4.46.0I O =-20 µA5.96.0 5.9 5.94.5I O =-4.0 mA 4.18 4.31 4.13 4.106.0I O =-5.2 mA 5.685.8 5.635.60V OLLow Level Output Voltage2.0I O =20 µA 0.00.10.10.1V 4.5I O =20 µA 0.00.10.10.16.0I O =20 µA 0.00.10.10.14.5I O =4.0 mA 0.170.260.330.406.0I O =5.2 mA 0.180.260.330.40I I Input Leakage Current6.0V I = V CC or GND ± 0.1± 1± 1µA I CC Quiescent Supply Current6.0V I = V CC or GND 44080µA I CC’Active StateSupply Current (1)2.0V I = V CC or GND Pin 7 or 15V IN = V CC /245200260320µA 4.5500600780960µA 6.00.711.31.6mAM74HC1237/12AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = t f = 6ns)CAPACITIVE CHARACTERISTICS1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC ’ Duty/100 + Ic/2(per monostable) (I cc ’ : Active Supply current) (Duty : %)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.t TLH t THL Output TransitionTime 2.0307595110ns 4.581519226.07131619t PLH t PHL Propagation DelayTime(A, B - Q, Q)2.0102210265315ns4.5294253636.022364554t PLH t PHL Propagation DelayTime(CLRTRIGGER - Q, Q) 2.0102235295355ns4.5314759716.023405060t PLH t PHL Propagation DelayTime(CLR - Q, Q)2.068160200240ns4.5203240486.016273441t WOUTOutput Pulse Width2.0Cx = 100 pF Rx = 10K Ω 1.4µs4.5 1.26.0 1.12.0Cx = 0.1µF Rx = 100K Ω4.6ms4.5 4.46.04.3∆t WOUTOutput Pulse Width Error Between Circuits in Same Package±1%t W(H) t W(L)Minimum Pulse Width2.07595110ns4.51519226.0131619t W(L)Minimum Pulse Width (CLR) 2.07595110ns4.51519226.0131619t rrMinimum Retrigger Time2.0Cx = 100 pF Rx = 10K Ω325ns4.51086.0782.0Cx = 0.1µF Rx = 100K Ω5µs4.5 1.46.01.2SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.C IN Input Capacitance 5.05101010pF C PDPower Dissipation Capacitance (note 1)5.0162pFM74HC1238/12TEST CIRCUITL R T = Z OUT of pulse generator (typically 50Ω)WAVEFORM : SWITCIHNG CHARACTERISTICS TEST WAVEFORM(f=1MHz; 50% duty cycle)M74HC123Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.© The ST logo is a registered trademark of STMicroelectronics© 2001 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - MoroccoSingapore - Spain - Sweden - Switzerland - United Kingdom© 12/12。

74HC123下载资料

6.0
II输入电流（最大）
V1=VCC或GND (其它输入端))
6.0
Icc 电源电流（最大）
Icc 电源电流（最大）
V1=VCC或GND
6.0
IO=0µA
V1=VCC 或 GND 2.0
4.5
Rext/Cext=0.5Vcc
6.0
规 54/74HC TA=25℃
1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9
（最大）
VCC
规
范
值
单
数
测试条件 (V) 54/74HC 74HC
54HC
位
TA=25℃ TA=全温 TA=全温
2.0 169
194
210
,B, →Q
4.5
42
51
57
ns
6.0
32
39
44
2.0 197
229
250
,B, → Q
4.5
48
60
67
ns
6.0
38
46
51
tPHL 传输延迟时间
（最大）
VCC=2.0V….…...≤ 1000ns
功率耗散
PD*………………...500mW
储存温度范围
TS…………...-65℃~+150℃
焊接温度 (10 秒)TL。
T L…………………..300℃
注：高温下的PD降低值：塑料双列-12mW/℃（从 65℃至 85℃）
陶瓷双列-12mW/℃（从 100℃至 125℃）
3.7 5.2
0.1 0.1 0.1
单位 V V V V V

HD74HC193中文资料

QC Load
QD D C
(Top view)
16 VCC 15 Data A 14 Clear
Inputs
13 Borrow 12 Carry
Outputs
11 Load
10 Data C Inputs
9 Data D
2
Logic Diagram
HD74HC192
Count Down Count Up
6.0
— — 13 — 16
Input capacitance Cin
—
— 5 10 — 10 pF
Test Conditions Data to Load
HD74HC192/HD74HC193
Synchronous Up/Down Decade Counter (Dual Clock Line) Synchronous Up/Donw 4-bit Binary Counter (Dual Clock Line)
Description
The HD74HC192 is a decade counter, and the HD74HC193 is a binary counter. Both counters have two separate clock inputs, an up count input and a down count input. All outputs of the flip-flops are simultaneously triggered on the low to high transition of either clock while the other input is held high. The direction of counting is determined by which input is clocked. These counters may be preset by entering the desired data on the data A, data B, data C, and data D inputs. When the load input is taken low the data is loaded independently of either clock input. This feature allows the counters to be used as divide-by-n counters by modifying the count length with the preset inputs. In addition both counters can also be cleared. This is accomplished by inputting a high on the clear input. All 4 internal stages are set to a low level independently of either count input. Both a borrow and carry output are provided to enable cascading of both up and down counting functions. The borrow output produces a negative going pulse when the counter underflows and the carry outputs a pulse when the counter overflows. The counters can be cascaded by connecting the carry and borrow outputs of one device to the count up and count down inputs, respectively, of the next device.

74HC123中文资料_数据手册_参数

The 74HC123; 74HCT123 are dual retriggerable monostable multivibrators with output pulse width control by three methods:
1. The basic pulse is programmed by selection of an external resistor (REXT) and capacitor (CEXT).
Version SOT109-1 SOT338-1 SOT403-1 SOT763-1
4. Functional diagram
$ % 5'
$ % 5'
Fig 1. Functional diagram
6 4
7 4
5'
6 4
7 4
5'
&(;7 5(;7&(;7 4
2. Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as desired. Alternatively an output delay can be terminated at any time by a LOW-going edge on input nRD, which also inhibits the triggering.

74VHC123AMTCX中文资料

74VHC123A Dual Retriggerable Monostable Multivibrator元器件交易网74VHC123A Dual Retriggerable Monostable MultivibratorConnection Diagram Pin DescriptionLogic SymbolIEEE/IECTruth TableH = HIGH Voltage Level L = LOW Voltage Level = HIGH-to-LOW Transition = LOW-to-HIGH Transition X = Don't CarePin NamesDescriptionA Trigger Inputs (Negative Edge)B Trigger Inputs (Positive Edge)CLR Reset InputsC x External Capacitor R x External Resistor Q, QOutputsInputs OutputsFunctionABCLRQ QH H Output Enable X L H L H Inhibit H XH LHInhibit L HOutput Enable L H Output Enable XXLLHReset元器件交易网74VHC123A Dual Retriggerable Monostable MultivibratorBlock DiagramsNote A: C x , R x , D x are external Capacitor, Resistor, and Diode, respectively. Note B: External clamping diode, D x ;External capacitor is charged to V CC level in the wait state, i.e. when no trigger is applied.If the supply voltage is turned off, C x discharges mainly through the internal (parasitic) diode. If C x is sufficiently large and V CC drops rapidly, there will be some possibility of damaging the IC through in rush current or latch-up. If the capacitance of the supply voltage filter is large enough and V CC drops slowly, the in rush current is automatically limited and damage to the IC is avoided.The maximum value of forward current through the parasitic diode is ±20mA. In the case of a large Cx, the limit of fall time of the supply voltage is determined as follows:t f ≥ (V CC –0.7) C x / 20mA(t f is the time between the supply voltage turn off and the supply voltage reaching 0.4 V CC )In the event a system does not satisfy the above condition, an external clamping diode (D x) is needed to protect the ICfrom rush current.元器件交易网74VHC123A Dual Retriggerable Monostable MultivibratorSystem DiagramTiming Chart元器件交易网Functional Description1.Stand-by StateThe external capacitor (C x) is fully charged to V CC in the Stand-by State. That means, before triggering, the Q P and Q N transistors which are connected to the R x/C x node are in the off state. Two comparators that relate to the timing of the output pulse, and two refer-ence voltage supplies turn off. The total supply cur-rent is only leakage current.2.T rigger OperationTrigger operation is effective in any of the following three cases. First, the condition where the A input is LOW, and B input has a rising signal; second, where the B input is HIGH, and the A input has a falling sig-nal; and third, where the A input is LOW and the B input is HIGH, and the CLR input has a rising signal.After a trigger becomes effective, comparators C1 and C2start operating, and Q N is turned on. The external capacitor discharges through Q N. The volt-age level at the R x/C x node drops. If the R x/C x volt-age level falls to the internal reference voltage V ref L, the output of C1 becomes LOW. The flip-flop is then reset and Q N turns off. At that moment C1 stops but C2 continues operating.After Q N turns off, the voltage at the R x/C x node starts rising at a rate determined by the time constant of external capacitor C x and resistor R x.Upon triggering, output Q becomes HIGH, following some delay time of the internal F/F and gates. It stays HIGH even if the voltage of R x/C x changes from fall-ing to rising. When R x/C x reaches the internal refer-ence voltage V ref H, the output of C2 becomes LOW,the output Q goes LOW and C2 stops its operation.That means, after triggering, when the voltage level of the R x/C x node reaches V ref H, the IC returns to its MONOSTABLE state.With large values of C x and R x, and ignoring the dis-charge time of the capacitor and internal delays of the IC, the width of the output pulse, t W (OUT), is as follows:t W (OUT) = 1.0 C x R x3.Retrigger operation (74VHC123A)When a new trigger is applied to either input A or B while in the MONOSTABLE state, it is effective only if the IC is charging C x. The voltage level of the R x/C x node then falls to V ref L level again. Therefore the Q output stays HIGH if the next trigger comes in before the time period set by C x and R x.If the new trigger is very close to a previous trigger, such as an occurrence during the discharge cycle, it will have no effect.The minimum time for a trigger to be effective 2nd trigger, t RR (Min), depends on V CC and C x.4.Reset OperationIn normal operation, the CLR input is held HIGH. If CLR is LOW, a trigger has no affect because the Q output is held LOW and the trigger control F/F is reset. Also, Q p turns on and C x is charged rapidly to V CC.This means if CLR is set LOW, the IC goes into a wait state.元器件交易网74VHC123A Dual Retriggerable Monostable Multivibrator74VHC123A Dual Retriggerable Monostable MultivibratorAbsolute Maximum RatingsStresses exceeding the absolute maximum ratings may damage the device. The device may not function or beoperable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.Recommended Operating Conditions (1)The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.Notes:1.Unused inputs must be held HIGH or LOW. They may not float.2.The maximum allowable values of C x and R x are a function of the leakage of capacitor C x , the leakage of the device, and leakage due to board layout and surface resistance. Susceptibility to externally induced noise signals may occur for R x > 1M Ω.Symbol ParameterRatingV CC Supply Voltage –0.5V to +7.0V V IN DC Input Voltage –0.5V to +7.0V V OUT DC Output Voltage –0.5V to V CC + 0.5VI IK Input Diode Current –20mA I OK Output Diode Current ±20mA I OUT DC Output Current ±25mA I CC DC V CC /GND Current ±50mAT STG Storage Temperature–65°C to +150°CT LLead Temperature (Soldering, 10 seconds)260°CSymbol ParameterRatingV CC Supply Voltage 2.0V to +5.5V V IN Input Voltage 0V to +5.5V V OUT Output Voltage 0V to V CCT OPR Operating Temperature–40°C to +85°C t r , t fInput Rise and Fall Time (CLR only) V CC = 3.3V ± 0.3V V CC = 5.0V ± 0.5V 0ns/V ∼ 100ns/V 0ns/V ∼ 20ns/V External Capacitor, C x No Limitation (2) F External Resistor, R x>5k Ω(2) (V CC = 2.0V)>1k Ω(2) (V CC > 3.0V)元器件交易网Note:3.Per circuit.Current I CCActive—State (3)Supply Current3.0V IN = V CC or GND, R x /C x = 0.5 V CC160250280µA4.53805006505.5560750975Notes:4.Refer to Timing Chart.5.C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation:I CC (opr.) = C PD • V CC • f IN+ I CC 1 • Duty / 100 + I CC / 2 (per Circuit)I CC 1: Active Supply Current Duty: %R x = 1k Ω5.0 ± 0.50.91.0 1.10.91.1∆t WOUTOutput Pulse Width Error Between Circuits (In same Package)±1%C IN Input Capacitance V CC = Open41010pF C PDPower Dissipation Capacitance(5)73pF74VHC123A Dual Retriggerable Monostable MultivibratorAC Operating Requirement (6)Note:6.Refer to Timing Chart.SymbolParameterV CC (V)Conditions T A = 25°CT A = –40°C to +85°C UnitsMin.Typ.Max.Min.Max.t W (L), t W (H)Minimum Trigger Pulse Width 3.3 5.0 5.0ns5.0 5.0 5.0t W (L)Minimum Clear Pulse Width 3.3 5.0 5.0ns 5.0 5.05.0t RRMinimum Retrigger Time3.3 ± 0.3R x = 1k Ω, C X = 100pF 60ns 5.0 ± 0.5393.3R x = 1k Ω, C X = 0.01µF1.5µs5.01.2Device Characteristicst wout*C x Characteristics (Typ.)Output Pulse Width Constant K-Supply Voltage(Typ.)t RR*V CC Characteristics (Typ.)Input Equivalent Circuit74VHC123A Dual Retriggerable Monostable Multivibrator74VHC123A Dual Retriggerable Monostable Multivibrator The™。

74系列功能大全(中文)

74系列功能大全（中文）74、74HC、74LS系列芯片资料，从网上下的，集合了一下系列电平典型传输延迟ns 最大驱动电流(-Ioh/Lol)mAAHC CMOS 8.5 -8/8AHCT COMS/TTL 8.5 -8/8HC COMS 25 -8/8HCT COMS/TTL 25 -8/8ACT COMS/TTL 10 -24/24F TTL 6.5 -15/64ALS TTL 10 -15/64LS TTL 18 -15/24注：同型号的74系列、74HC系列、74LS系列芯片，逻辑功能上是一样的。

74LSxx的使用说明如果找不到的话，可参阅74xx或74HCxx的使用说明。

有些资料里包含了几种芯片，如74HC161资料里包含了74HC160、74HC161、74HC162、74HC163四种芯片的资料。

找不到某种芯片的资料时，可试着查看一下临近型号的芯片资料。

7400 QUAD 2-INPUT NAND GATES 与非门7401 QUAD 2-INPUT NAND GATES OC 与非门7402 QUAD 2-INPUT NOR GATES 或非门7403 QUAD 2-INPUT NAND GATES 与非门7404 HEX INVERTING GATES 反向器7406 HEX INVERTING GATES HV 高输出反向器7408 QUAD 2-INPUT AND GATE 与门7409 QUAD 2-INPUT AND GATES OC 与门7410 TRIPLE 3-INPUT NAND GATES 与非门7411 TRIPLE 3-INPUT AND GATES 与门74121 ONE-SHOT WITH CLEAR 单稳态74132 SCHMITT TRIGGER NAND GATES 触发器与非门7414 SCHMITT TRIGGER INVERTERS 触发器反向器74153 4-LINE TO 1 LINE SELECTOR 四选一74155 2-LINE TO 4-LINE DECODER 译码器74180 PARITY GENERATOR/CHECKER 奇偶发生检验74191 4-BIT BINARY COUNTER UP/DOWN 计数器7420 DUAL 4-INPUT NAND GATES 双四输入与非门7426 QUAD 2-INPUT NAND GATES 与非门7427 TRIPLE 3-INPUT NOR GATES 三输入或非门7430 8-INPUT NAND GATES 八输入端与非门7432 QUAD 2-INPUT OR GATES 二输入或门7438 2-INPUT NAND GATE BUFFER 与非门缓冲器7445 BCD-DECIMAL DECODER/DRIVER BCD译码驱动器7474 D-TYPE FLIP-FLOP D型触发器7475 QUAD LATCHES 双锁存器7476 J-K FLIP-FLOP J-K触发器7485 4-BIT MAGNITUDE COMPARATOR 四位比较器7486 2-INPUT EXCLUSIVE OR GATES 双端异或门74HC00 QUAD 2-INPUT NAND GATES 双输入与非门74HC02 QUAD 2-INPUT NOR GATES 双输入或非门74HC03 2-INPUT OPEN-DRAIN NAND GATES 与非门74HC04 HEX INVERTERS 六路反向器74HC05 HEX INVERTERS OPEN DRAIN 六路反向器74HC08 2-INPUT AND GATES 双输入与门74HC107 J-K FLIP-FLOP WITH CLEAR J-K触发器74HC109A J-K FLIP-FLOP W/PRESET J-K触发器74HC11 TRIPLE 3-INPUT AND GATES 三输入与门74HC112 DUAL J-K FLIP-FLOP 双J-K触发器74HC113 DUAL J-K FLIP-FLOP PRESET 双JK触发器74HC123A RETRIGGERABLE MONOSTAB 可重触发单稳74HC125 TRI-STATE QUAD BUFFERS 四个三态门74HC126 TRI-STATE QUAD BUFFERS 六三态门74HC132 2-INPUT TRIGGER NAND 施密特触发与非门74HC133 13-INPUT NAND GATES 十三输入与非门74HC137 3-TO-8 DECODERS W/LATCHES 3-8线译码器74HC138 3-8 LINE DECODER 3线至8线译码器74HC139 2-4 LINE DECODER 2线至4线译码器74HC14 TRIGGERED HEX INVERTER 六触发反向器74HC147 10-4 LINE PRIORITY ENCODER 10-4编码器74HC148 8-3 LINE PRIORITY ENCODER 8-3编码器74HC149 8-8 LINE PRIORITY ENCODER 8-8编码器74HC151 8-CHANNEL DIGITAL MUX 8通道多路器74HC153 DUAL 4-INPUT MUX 双四输入多路器74HC154 4-16 LINE DECODER 4线至16线译码器74HC155 2-4 LINE DECODER 2线至4线译码器74HC157 QUAD 2-INPUT MUX 四个双端多路器74HC161 BINARY COUNTER 二进制计数器74HC163 DECADE COUNTERS 十进制计数器74HC164 SERIAL-PARALLEL SHIFT REG 串入并出74HC165 PARALLEL-SERIAL SHIFT REG 并入串出74HC166 SERIAL-PARALLEL SHIFT REG 串入并出74HC173 TRI-STATE D FLIP-FLOP 三态D触发器74HC174 HEX D FLIP-FLOP W/CLEAR 六D触发器74HC175 HEX D FLIP-FLOP W/CLEAR 六D触发器74HC181 ARITHMETIC LOGIC UNIT 算术逻辑单元74HC182 LOOK AHEAD CARRYGENERATR 进位发生器74HC190 BINARY UP/DN COUNTER 二进制加减计数器74HC191 DECADE UP/DN COUNTER 十进制加减计数器74HC192 DECADE UP/DN COUNTER 十进制加减计数器74HC193 BINARY UP/DN COUNTER 二进制加减计数器74HC194 4BIT BI-DIR SHIFT 4位双向移位寄存器74HC195 4BIT PARALLEL SHIFT 4位并行移位寄存器74HC20 QUAD 4-INPUT NAND GATE 四个四入与非门74HC221A NON-RETRIG MONOSTAB 不可重触发单稳74HC237 3-8 LINE DECODER 地址锁3线至8线译码器74HC242/243 TRI-STAT TRANSCEIVER 三态收发器74HC244 OCTAL 3-STATE BUFFER 八个三态缓冲门74HC245 OCTAL 3-STATE TRANSCEIVER 三态收发器74HC251 8-CH 3-STATE MUX 8路3态多路器74HC253 DUAL 4-CH 3-STATE MUX 4路3态多路器74HC257 QUAD 2-CH 3-STATE MUX 4路3态多路器74HC258 2-CH 3-STATE MUX 2路3态多路器74HC259 3-8 LINE DECODER 8位地址锁存译码器74HC266A 2-INPUT EXCLUSIVE NOR GATE 异或非74HC27 TRIPLE 3-INPUT NOR GATE三个3输入或非门74HC273 OCTAL D FLIP-FLOP CLEAR 8路D触发器74HC280 9BIT ODD/EVEN GENERATOR 奇偶发生器74HC283 4BIT BINARY ADDER CARRY 四位加法器74HC299 3-STATE UNIVERSAL SHIFT 三态移位寄存74HC30 8-INPUT NAND GATE 8输入端与非门74HC32 QUAD 2-INPUT OR GATE 四个双端或门74HC34 NON-INVERTER 非反向器74HC354 8-CH 3-STATE MUX 8路3态多路器74HC356 8-CH 3-STATE MUX 8路3态多路器74HC365 HEX 3-STATE BUFFER 六个三态缓冲门74HC366 3-STATE BUFFER INVERTER 缓冲反向器74HC367 3-STATE BUFFER INVERTER 缓冲反向器74HC368 3-STATE BUFFER INVERTER 缓冲反向器74HC373 3-STATE OCTAL D LATCHES 三态D型锁存器74HC374 3-STATE OCTAL D FLIPFLOP 三态D触发器74HC393 4-BIT BINARY COUNTER 4位二进制计数器74HC4016 QUAD ANALOG SWITCH 四路模拟量开关74HC4020 14-Stage Binary Counter 14输出计数器74HC4017 Decade Counter/Divider with 10 Decoded Outputs 十进制计数器带10个译码输出端74HC4040 12 Stage Binary Counter 12出计数器74HC4046 PHASE LOCK LOOP 相位监测输出器74HC4049 LEVEL DOWN CONVERTER 电平变低器74HC4050 LEVEL DOWN CONVERTER 电平变低器74HC4051 8-CH ANALOG MUX 8通道多路器74HC4052 4-CH ANALOG MUX 4通道多路器74HC4053 2-CH ANALOG MUX 2通道多路器74HC4060 14-STAGE BINARY COUNTER 14阶BIN计数74HC4066 QUAD ANALOG MUX 四通道多路器74HC4075 TRIPLE 3-INPUT OR GATE 3输入或门74HC42 BCD TO DECIMAL BCD转十进制译码器74HC423A RETRIGGERABLE MONOSTAB 可重触发单稳74HC4511 BCD-7 SEG DRIVER/DECODER 7段译码器74HC4514 4-16 LINE DECODER 4至16线译码器74HC4538A RETRIGGERAB MONOSTAB 可重触发单稳74HC4543 LCD BCD-7 SEG LCD用的BCD-7段译码驱动74HC51 AND OR GATE INVERTER 与或非门74HC521 8BIT MAGNITUDE COMPARATOR 判决定路74HC533 3-STATE D LATCH 三态D锁存器74HC534 3-STATE D FLIP-FLOP 三态D型触发器74HC540 3-STATE BUFFER 三态缓冲器74HC541 3-STATE BUFFER INVERTER三态缓冲反向器74HC58 DUAL AND OR GATE 与或门74HC589 3STATE 8BIT SHIFT 8位移位寄存三态输出74HC594 8BIT SHIFT REG 8位移位寄存器74HC595 8BIT SHIFT REG 8位移位寄存器出锁存74HC597 8BIT SHIFT REG 8位移位寄存器入锁存74HC620 3-STATE TRANSCEIVER 反向3态收发器74HC623 3-STATE TRANSCEIVER 八路三态收发器74HC640 3-STATE TRANSCEIVER 反向3态收发器74HC643 3-STATE TRANSCEIVER 八路三态收发器74HC646 NON-INVERT BUS TRANSCEIVER 总线收发器74HC648 INVERT BUS TRANCIVER 反向总线收发器74HC688 8BIT MAGNITUDE COMPARATOR 8位判决电路74HC7266 2-INPUT EXCLUSIVE NOR GATE 异或非门74HC73 DUAL J-K FLIP-FLOP W/CLEAR 双JK触发器74HC74A PRESET/CLEAR D FLIP-FLOP 双D触发器74HC75 4BIT BISTABLE LATCH 4位双稳锁存器74HC76 PRESET/CLEAR JK FLIP-FLOP 双JK触发器74HC85 4BIT MAGNITUDE COMPARATOR 4位判决电路74HC86 2INPUT EXCLUSIVE OR GATE 2输入异或门74HC942 BAUD MODEM 300BPS低速调制解调器74HC943 300 BAUD MODEM 300BPS低速调制解调器74LS00 QUAD 2-INPUT NAND GATES 与非门74LS02 QUAD 2-INPUT NOR GATES 或非门74LS03 QUAD 2-INPUT NAND GATES 与非门74LS04 HEX INVERTING GATES 反向器74LS05 HEX INVERTERS OPEN DRAIN 六路反向器74LS08 QUAD 2-INPUT AND GATE 与门74LS09 QUAD 2-INPUT AND GATES OC 与门74LS10 TRIPLE 3-INPUT NAND GATES 与非门74LS109 QUAD 2-INPUT AND GATES OC 与门74LS11 TRIPLE 3-INPUT AND GATES 与门74LS112 DUAL J-K FLIP-FLOP 双J-K触发器74LS113 DUAL J-K FLIP-FLOP PRESET 双JK触发器74LS114 NEGATIVE J-K FLIP-FLOP 负沿J-K触发器74LS122 Retriggerable Monostab 可重触发单稳74LS123 Retriggerable Monostable 可重触发单稳74LS125 TRI-STATE QUAD BUFFERS 四个三态门74LS13 QUAL 4-in NAND TRIGGER 4输入与非触发器74LS160 BCD DECADE 4BIT BIN COUNTERS 计数器74LS136 QUADRUPLE 2-INPUT XOR GATE 异或门74LS138 3-8 LINE DECODER 3线至8线译码器74LS139 2-4 LINE DECODER 2线至4线译码器74LS14 TRIGGERED HEX INVERTER 六触发反向器74HC147 10-4 LINE PRIORITY ENCODER 10-4编码器74HC148 8-3 LINE PRIORITY ENCODER 8-3编码器74HC149 8-8 LINE PRIORITY ENCODER 8-8编码器74LS151 8-CHANNEL DIGITAL MUX 8通道多路器74LS153 DUAL 4-INPUT MUX 双四输入多路器74LS155 2-4 LINE DECODER 2线至4线译码器74LS156 2-4 LINE DECODER/DEMUX 2-4译码器74LS157 QUAD 2-INPUT MUX 四个双端多路器74LS158 2-1 LINE MUX 2-1线多路器74LS160A BINARY COUNTER 二进制计数器74LS161A BINARY COUNTER 二进制计数器74LS162A BINARY COUNTER 二进制计数器74LS163A DECADE COUNTERS 十进制计数器74LS164 SERIAL-PARALLEL SHIFT REG 串入并出74LS168 BI-DIRECT BCD TO DECADE 双向计数器74LS169 4BIT UP/DN BIN COUNTER 四位加减计数器74LS173 TRI-STATE D FLIP-FLOP 三态D触发器74LS174 HEX D FLIP-FLOP W/CLEAR 六D触发器74LS175 HEX D FLIP-FLOP W/CLEAR 六D触发器74LS190 BINARY UP/DN COUNTER 二进制加减计数器74LS191 DECADE UP/DN COUNTER 十进制加减计数器74LS192 DECADE UP/DN COUNTER 十进制加减计数器74LS193 BINARY UP/DN COUNTER 二进制加减计数器74LS194A 4BIT BI-DIR SHIFT 4位双向移位寄存器74LS195A 4BIT PARALLEL SHIFT4位并行移位寄存器74LS20 QUAD 4-INPUT NAND GATE 四个四入与非门74LS21 4-INPUT AND GATE 四输入端与门74LS240 OCTAL 3-STATE BUFFER 八个三态缓冲门74LS244 OCTAL 3-STATE BUFFER 八个三态缓冲门74LS245 OCTAL 3-STATE TRANSCEIVER 三态收发器74LS253 DUAL 4-CH 3-STATE MUX 4路3态多路器74LS256 4BIT ADDRESS LATCH 四位可锁存锁存器74LS257 QUAD 2-CH 3-STATE MUX 4路3态多路器74LS258 2-CH 3-STATE MUX 2路3态多路器74LS27 TRIPLE 3-INPUT NOR GATES 三输入或非门74LS279 QUAD R-S LATCHES 四个RS非锁存器74LS28 QUAD 2-INPUT NOR BUFFER 四双端或非缓冲74LS283 4BIT BINARY ADDER CARRY 四位加法器74LS30 8-INPUT NAND GATES 八输入端与非门74LS32 QUAD 2-INPUT OR GATES 二输入或门74LS352 4-1 LINE SELECTOR/MUX 4-1线选择多路器74LS365 HEX 3-STATE BUFFER 六个三态缓冲门74LS367 3-STATE BUFFER INVERTER 缓冲反向器74LS368A 3-STATE BUFFER INVERTER 缓冲反向器74LS373 OCT LATCH W/3-STATE OUT三态输出锁存器74LS76 Dual JK Flip-Flop w/set 2个JK触发器74LS379 QUAD PARALLEL REG 四个并行寄存器74LS38 2-INPUT NAND GATE BUFFER 与非门缓冲器74LS390 DUAL DECADE COUNTER 2个10进制计数器74LS393 DUAL BINARY COUNTER 2个2进制计数器74LS42 BCD TO DECIMAL BCD转十进制译码器74LS48 BCD-7 SEG BCD-7段译码器74LS49 BCD-7 SEG BCD-7段译码器74LS51 AND OR GATE INVERTER 与或非门74LS540 OCT Buffer/Line Driver 8路缓冲驱动器74LS541 OCT Buffer/LineDriver 8路缓冲驱动器74LS74 D-TYPE FLIP-FLOP D型触发器74LS682 8BIT MAGNITUDE COMPARATOR 8路比较器74LS684 8BIT MAGNITUDE COMPARATOR 8路比较器74LS75 QUAD LATCHES 双锁存器74LS83A 4BIT BINARY ADDER CARRY 四位加法器74LS85 4BIT MAGNITUDE COMPARAT 4位判决电路74LS86 2INPUT EXCLUSIVE OR GATE 2输入异或门74LS90 DECADE/BINARY COUNTER 十/二进制计数器74LS95B 4BIT RIGHT/LEFT SHIFT 4位左右移位寄存74LS688 8BIT MAGNITUDE COMPARAT 8位判决电路74LS136 2-INPUT XOR GATE 2输入异或门74LS651 BUS TRANSCEIVERS 总线收发器74LS653 BUS TRANSCEIVERS 总线收发器74LS670 3-STATE 4-BY-4 REG 3态4-4寄存器74LS73A DUAL J-K FLIP-FLOP W/CLEAR 双JK触发器。

HD74HC238RP中文资料

HD74HC2383-to-8-line Decoder/DemultiplexerREJ03D0593–0200(Previous ADE-205-470)Rev.2.00Jan 31, 2006 DescriptionThe HD74HC238 has 3 binary select inputs (A, B and C). If the device is enabled these inputs determine which one of the eight normally high outputs will go low. Two active low and one active high enables (G1, G2A and G2B) are provided to ease the cascading of decoders.Features• High Speed Operation: t pd (Data to Y) = 15 ns typ (C L = 50 pF)• High Output Current: Fanout of 10 LSTTL Loads• Wide Operating Voltage: V CC = 2 to 6 V• Low Input Current: 1 µA max• Low Quiescent Supply Current: I CC (static) = 4 µA max (Ta = 25°C)• Ordering InformationPart Name Package TypePackage Code(Previous Code)PackageAbbreviationTaping Abbreviation(Quantity)HD74HC238P DILP-16pin PRDP0016AE-B(DP-16FV)P —HD74HC238FPEL SOP-16 pin (JEITA) PRSP0016DH-B(FP-16DAV)FP EL (2,000 pcs/reel)HD74HC238RPEL SOP-16 pin (JEDEC) PRSP0016DG-A(FP-16DNV)RP EL (2,500 pcs/reel)Note: Please consult the sales office for the above package availability.Function TableInputsEnable SelectOutputsG1G2A G2B C B A Y0Y1Y2Y3Y4Y5Y6Y7 X X H X X X L L L L L L L L X H X X X X L L L L L L L L L X X X X X L L L L L L L LH L L L L L H L L L L L L LH L L L L H L H L L L L L LH L L L H L L L H L L L L LH L L L H H L L L H L L L LH L L H L L L L L L H L L LH L L H L H L L L L L H L LH L L H H L L L L L L L H LH L L H H H L L L L L L L H H : High levelL : Low levelX : IrrelevantPin ArrangementLogic DiagramAbsolute Maximum RatingsItem Symbol Ratings UnitSupply voltage range V CC –0.5 to 7.0 V Input / Output voltage V IN , V OUT –0.5 to V CC +0.5 V Input / Output diode current I IK , I OK ±20 mA Output current I O ±35 mA V CC , GND current I CC or I GND ±75 mA Power dissipation P T 500 mW Storage temperature Tstg –65 to +150 °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two ofwhich may be realized at the same time.Recommended Operating ConditionsItem Symbol Ratings Unit ConditionsSupply voltage V CC 2 to 6 V Input / Output voltage V IN , V OUT 0 to V CC V Operating temperature Ta –40 to 85 °C 0 to 1000 V CC = 2.0 V0 to 500 V CC = 4.5 V Input rise / fall time *1 t r , t f 0 to 400 ns V CC = 6.0 V Notes: 1. This item guarantees maximum limit when one input switches.Waveform: Refer to test circuit of switching characteristics.Electrical CharacteristicsTa = 25°C Ta = –40 to+85°CItem Symbol V CC (V)Min Typ Max Min MaxUnitTest Conditions2.0 1.5 — — 1.5— 4.5 3.15 — — 3.15 — V IH6.0 4.2 — — 4.2 —V 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35Input voltageV IL6.0 — — 1.8 — 1.8V 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — I OH = –20 µA 4.5 4.18 — — 4.13 — I OH = –4 mA V OH6.0 5.68 — — 5.63— V Vin = V IH or V IL I OH = –5.2 mA2.0 — 0.0 0.1 —0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 I OL = 20 µA 4.5 — — 0.26 — 0.33 I OL = 4 mA Output voltage V OL6.0 — — 0.26 —0.33 V Vin = V IH or V IL I OL = 5.2 mA Off-state output currentI OZ 6.0— — ±0.5 — ±5.0 µA Vin = V IH or V IL ,Vout = V CC or GNDInput current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = V CC or GNDQuiescent supply current I CC 6.0— — 4.0 — 40 µA Vin = V CC or GND, Iout = 0 µASwitching Characteristics(C L = 50 pF, Input t r = t f = 6 ns)Ta = 25°C Ta = –40 to +85°CItem Symbol V CC (V)Min Typ Max MinMaxUnit Test Conditions2.0 — — 150 — 190 4.5 — 15 30 — 38 6.0 — — 26 — 33 ns Select to Y 2.0 — — 150 — 190 4.5 — 13 30 — 38 Propagation delaytimet PLHt PHL6.0 — — 26 — 33ns Enable to Y 2.0 — — 75 — 95 4.5 — 5 15 — 19 Output rise/falltimet TLH t THL 6.0 — — 13 — 16 ns Input capacitance Cin— — 5 10 — 10 pFTest CircuitWaveformsPackage Dimensions RENESAS SALES OFFICESRefer to "/en/network" for the latest and detailed information.Renesas Technology America, Inc.450 Holger Way, San Jose, CA 95134-1368, U.S.ATel: <1> (408) 382-7500, Fax: <1> (408) 382-7501Renesas Technology Europe LimitedDukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900Renesas Technology (Shanghai) Co., Ltd.Unit 205, AZIA Center, No.133 Yincheng Rd (n), Pudong District, Shanghai 200120, ChinaTel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898Renesas Technology Hong Kong Ltd.7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong KongTel: <852> 2265-6688, Fax: <852> 2730-6071Renesas Technology Taiwan Co., Ltd.10th Floor, No.99, Fushing North Road, Taipei, TaiwanTel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999Renesas Technology Singapore Pte. Ltd.1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632Tel: <65> 6213-0200, Fax: <65> 6278-8001Renesas Technology Korea Co., Ltd.Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, KoreaTel: <82> (2) 796-3115, Fax: <82> (2) 796-2145Renesas Technology Malaysia Sdn. BhdUnit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, MalaysiaTel: <603> 7955-9390, Fax: <603> 7955-9510© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.。

74vhc123a程序设计

74vhc123a程序设计74VHC123A是一款常见的集成电路芯片，它是双重可编程单多谐振荡器，适用于各种数字系统中的时序和定时应用。

本文将从功能、原理、应用领域等方面对74VHC123A进行详细介绍。

我们来了解一下74VHC123A的基本功能。

它具有两个独立的可编程单多谐振荡器，每个振荡器都有一个可编程的分频比。

它能够通过控制端提供的输入来选择不同的分频比，从而实现不同的时序和定时功能。

此外，它还具有复位和使能功能，以便更好地控制振荡器的工作状态。

接下来，我们来看一下74VHC123A的工作原理。

它采用了内部振荡器和外部电容来实现多谐振荡器的功能。

通过改变外部电容的值，可以改变振荡器的频率。

而通过控制端提供的输入信号，可以选择不同的分频比，从而改变振荡器的输出频率。

此外，复位和使能功能通过控制输入信号的状态来控制振荡器的启停和复位。

在实际应用中，74VHC123A有着广泛的应用领域。

首先，它可以用于数字系统中的时序控制。

通过调整分频比，可以实现不同的时序要求，如时钟分频、信号延迟等。

其次，在通信系统中，它可以用于定时控制。

通过调整振荡器的频率，可以实现精确的定时功能，如脉冲生成、数据同步等。

此外，它还可以用于计算机系统中的时序控制、仪器仪表中的定时测量、工业自动化中的时序控制等领域。

总结一下，74VHC123A是一款功能强大的集成电路芯片，适用于各种数字系统中的时序和定时应用。

它具有双重可编程单多谐振荡器的特点，能够通过控制输入信号来实现不同的分频比和频率调节。

在实际应用中，它可以用于时序控制、定时测量、脉冲生成等多个领域。

通过合理的设计和使用，可以充分发挥其功能，满足各种应用需求。

通过本文的介绍，相信读者对74VHC123A这款集成电路芯片有了更深入的了解。

它的功能和应用领域广泛，可以满足不同系统的时序和定时需求。

在今后的数字系统设计中，我们可以充分发挥74VHC123A的优势，提高系统的性能和稳定性。