8051 instruction set summary
8051微控制器硬件手册及应用注释说明书
1API Program ExamplesReferences•Atmel 8051 Microcontrollers Hardware Manual1. IntroductionThis Application Note provides to customers C program examples for Api usages.24365A–80C51–07/0434365A–80C51–07/042. API for Standard C512.1 flash_eeprom_api.c/*C************************************************************************ NAME: flash_eeprom_api.c*-------------------------------------------------------------------------* Copyright (c) 2004 Atmel.*-------------------------------------------------------------------------* RELEASE:* REVISION: 1.0*-------------------------------------------------------------------------* PURPOSE:* Read/Write flash* CAUTTION : add #define ONCHIP_EEPROM for on-chip eeprom products* (defined by default in the standard delivery)**************************************************************************//*_____ I N C L U D E - F I L E S _______________________________________*/#include "reg_C51.h"/*_____ D E C L A R A T I O N ___________________________________________*/#define ONCHIP_EEPROM //define it only for on-chip eeprom products/*---- API for FLASH access --------------------------------------------*//*************************************************************************/#define __api_rd_code_byte(address) (*((unsigned char code*) (address)))unsigned char__api_wr_code_byte(int , unsigned char)small;unsigned char__api_wr_code_page(int , int, unsigned char)small;/*---- API for EEPROM access -------------------------------------------*//*************************************************************************/#ifdef ONCHIP_EEPROMvoid __api_wr_eeprom_byte(unsigned int adr, unsigned char value);unsigned char __api_rd_eeprom_byte(unsigned int adr);#endif/*_____ G L O B A L S ___________________________________________________*/sfr16 DPTR = 0x82;/*_____ L O C A L S _____________________________________________________*/#define MSK_AUXR1_ENBOOT0x20#define MSK_AUXR_M00x20#define MAP_BOOT AUXR1 |= MSK_AUXR1_ENBOOT;#define UNMAP_BOOTAUXR1 &= ~MSK_AUXR1_ENBOOT;/*_____ EXTERNAL - F U N C T I O N S - D E C L A R A T I O N ____________*/extern void ASM_MOV_R1_A(void);extern void __API_FLASH_ENTRY_POINT(void);/*F************************************************************************ NAME: __api_wr_code_byte*-------------------------------------------------------------------------* PARAMS:* int address : address to program* unsigned char value : data to write* unsigned char return :* return = 0x00 -> pass* return != 0x00 -> fail*-------------------------------------------------------------------------* PURPOSE:* Program data byte in Flash memory**************************************************************************/unsigned char __api_wr_code_byte (int address, unsigned char value) small{bit ea_save;ea_save = EA;EA = 0;DPTR = address;ACC = 0x02;ASM_MOV_R1_A();ACC = value;MAP_BOOT;__API_FLASH_ENTRY_POINT();UNMAP_BOOT;EA = ea_save; // restore interrupt statereturn (ACC);}/*F************************************************************************ NAME: __api_wr_code_page*-------------------------------------------------------------------------* PARAMS:* int add_flash : address of the first byte to program in the Flash* int add_xram : address in XRAM of the first data to program* unsigned char nb_data : number of bytes to program*unsigned char return :* return = 0x00 -> pass* return != 0x00 -> fail*-------------------------------------------------------------------------* PURPOSE:* Program until 128 Datas in Flash memory.* Number of bytes to program is limited such as the Flash write remains in a* single 128 bytes page.**************************************************************************/unsigned char __api_wr_code_page (int add_flash, int add_xram, unsigned charnb_data) small{unsigned char save_auxr1;bit ea_save;44365A–80C51–07/0454365A–80C51–07/04ea_save = EA;EA = 0;save_auxr1 = AUXR1;AUXR1 &= ~0x01; // Set DPTR=DPTR0DPTR = add_flash;AUXR1++; // DPTR = DPTR1DPTR = add_xram;ACC = 0x09;ASM_MOV_R1_A();ACC = nb_data;AUXR1 &= ~0x01; // Set DPTR = DPTR0MAP_BOOT__API_FLASH_ENTRY_POINT();UNMAP_BOOT;AUXR1 = save_auxr1;EA = ea_save; // restore interrupt statereturn (ACC);}/*F************************************************************************ NAME: __api_rd_eeprom_byte*-------------------------------------------------------------------------* PARAMS:* unsigned int adr: The EEDATA memory location to read* return: value*-------------------------------------------------------------------------* PURPOSE:* This function reads one byte in the on-chip EEPROM data.*-------------------------------------------------------------------------* EXAMPLE:* val=__api_rd_eeprom_byte(128);*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS:**************************************************************************/unsigned char __api_rd_eeprom_byte(unsigned int adr){unsigned char val;bit ea_save;while (EECON&1);//Eeprom_busy()ea_save=EA;EA=0;EECON |= 0x02;//Enable eeprom data;val=*(unsigned char xdata*)adr;EECON &= ~0x02;//Disable eeprom data;EA=ea_save;return val;}/*F************************************************************************ NAME: __api_wr_eeprom_byte*-------------------------------------------------------------------------* PARAMS:* unsigned int adr: The EEDATA memory location to read* unsigned char value: The data byte to write* return: none*-------------------------------------------------------------------------* PURPOSE:* This function writes one byte in the on-chip EEPROM data.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS:**************************************************************************/void __api_wr_eeprom_byte(unsigned int adr, unsigned char value){bit ea_save;while(EECON & 0x01);// wait bit busyea_save=EA;EA=0;EECON |= 0x02;//Enable eeprom data*(unsigned char xdata*)adr=value;EECON &= ~0x02;//Disable eeprom dataEA=ea_save;}64365A–80C51–07/0474365A–80C51–07/042.2 flash_lib.a51NAME FLASH_LIB;;*A51********************************************************************; FILE_NAME : FLASH_LIB.a51 ;------------------------------------------------------------------------ ;------------------------------------------------------------------------; FILE_PURPOSE: low level function for API;************************************************************************USING 0PUBLIC ASM_MOV_R1_APUBLIC __API_FLASH_ENTRY_POINTAUXR1 EQU0A2hSTART SEGMENT CODERSEG START;************************************************************************; FUNCTION_NAME: ASM_MOV_A_R1;************************************************************************ASM_MOV_R1_A:Mov R1, ARet;************************************************************************; FUNCTION_NAME: __API_FLASH_ENTRY_POINT;************************************************************************__API_FLASH_ENTRY_POINT:PUSHAR2PUSHAR4PUSHAR6LCALL 0FFF0hPOPAR6POPAR4POPAR2RetEND3. API for USB products3.1 flash_eeprom_api.c/*C************************************************************************ NAME: flash_eeprom_api.c*-------------------------------------------------------------------------* Copyright (c) 2004 Atmel.*-------------------------------------------------------------------------* RELEASE:* REVISION:*-------------------------------------------------------------------------* PURPOSE:* This file contains whole of functions to access AT89C5131 Flash and* EEPROM and AT89C51SND1.* CAUTTION : add #define ONCHIP_EEPROM for on-chip eeprom products* (defined by default in the standard delivery)**************************************************************************//*_____ I N C L U D E S _________________________________________________*/#include "reg_C51.h"/*_____ D E F I N I T I O N _____________________________________________*/#define ONCHIP_EEPROM //define it only for build-in eeprom chipsunsigned char data api_command _at_ 0x1C;unsigned char data api_value _at_ 0x1D;#define MSK_AUXR1_ENBOOT 0x20#define MAP_BOOT AUXR1 |= MSK_AUXR1_ENBOOT;#define UNMAP_BOOT AUXR1 &= ~MSK_AUXR1_ENBOOT;#define __API_FLASH_ENTRY_POINT (*((const void(code*)(void)) 0xFFC0 ))/*_____ D E C L A R A T I O N ___________________________________________*//*---- API for FLASH access --------------------------------------------*//*************************************************************************/unsigned char __api_rd_code_byte (unsigned char code * pt_address);unsigned char __api_wr_code_byte (unsigned char xdata* , unsigned char);unsigned char __api_wr_code_page (unsigned char xdata* pt_code,unsigned char xdata* pt_xram,unsigned char nb_data);/*---- API for EEPROM access -------------------------------------------*//*************************************************************************/#ifdef ONCHIP_EEPROMunsigned char __api_rd_eeprom_byte(unsigned char xdata *);unsigned char __api_wr_eeprom_byte(unsigned char xdata *, unsigned char);#endif84365A–80C51–07/0494365A–80C51–07/04/*F************************************************************************ NAME: __api_rd_code_byte*-------------------------------------------------------------------------* PARAMS:* unsigned int address : address in flash memory to read* return:* unsigned char device : read value*-------------------------------------------------------------------------* PURPOSE:* This function allows to read a flash memory byte.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS:**************************************************************************/unsigned char __api_rd_code_byte (unsigned char code * pt_address){return(*pt_address);}/*F************************************************************************ NAME: __api_wr_code_byte*-------------------------------------------------------------------------* PARAMS:* unsigned int address : address to program* unsigned char value : data to write* return:* unsigned char return :* return = 0x00 -> pass* return != 0x00 -> fail*-------------------------------------------------------------------------* PURPOSE:* This function allows to program data byte in Flash memory.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS:**************************************************************************/unsigned char __api_wr_code_byte (unsigned char xdata * pt_address, unsigned char value){bit ea_save;ea_save = EA;EA = 0;api_command = 0x0D; //_COMMAND_WR_CODE_BYTE;FCON = 0x08;*pt_address = value;MAP_BOOT;__API_FLASH_ENTRY_POINT();UNMAP_BOOT;EA = ea_save; // restore interrupt statereturn(api_value);}/*F************************************************************************ NAME: __api_wr_code_page*-------------------------------------------------------------------------* PARAMS:* unsigned int add_flash : address of the first byte to program* in the Flash* unsigned int add_xram : address in XRAM of the first data to program* unsigned char nb_data : number of bytes to program* return:* unsigned char return :* return = 0x00 -> pass* return != 0x00 -> fail*-------------------------------------------------------------------------* PURPOSE:* This function allows to program until 128 Datas in Flash memory.* Number of bytes to program is limited such as the Flash write remains* in a single 128 bytes page.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:* This function used Dual Data Pointer DPTR0&1. At the end of this* function.* DPTR = DPTR0.*-------------------------------------------------------------------------* REQUIREMENTS:**************************************************************************/unsigned char __api_wr_code_page (unsigned char xdata * pt_code,unsigned char xdata * pt_xram,unsigned char nb_data){unsigned char data i, temp, temp_nb_data;bit ea_save;unsigned int data add_pt_code, add_pt_xram;add_pt_xram = pt_xram;add_pt_code = pt_code;temp_nb_data = nb_data;104365A–80C51–07/04114365A–80C51–07/04ea_save = EA;EA = 0;api_command = 0x0D;for (i=0 ; i< temp_nb_data; i++,add_pt_xram++,add_pt_code++){temp = *(unsigned char xdata *)add_pt_xram;FCON = 0x08;*(unsigned char xdata *)add_pt_code = temp;FCON = 0x00;}MAP_BOOT;__API_FLASH_ENTRY_POINT();UNMAP_BOOT;EA = ea_save; // restore interrupt statereturn(api_value);}#ifdef ONCHIP_EEPROM/*F************************************************************************ NAME: api_rd_eeprom*-------------------------------------------------------------------------* PARAMS:* unsigned char xdata *address : address to read* return:*-------------------------------------------------------------------------* PURPOSE:* This function allows to read a byte in Eeprom.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS: The EEPROM mustn't be busy to perform the read access.* eeprom status :(EECON & 0x01)=1 busy, =0 free**************************************************************************/unsigned char __api_rd_eeprom_byte(unsigned char xdata *address){unsigned char val;bit ea_save;ea_save = EA;EA = 0;EECON = 0x02;val = *address;EECON = 0x00;EA = ea_save;return (val);}/*F************************************************************************ NAME: api_wr_eeprom_byte*-------------------------------------------------------------------------* PARAMS:* unsigned char xdata* address : address to read* unsigned char value : data to write* return:*-------------------------------------------------------------------------* PURPOSE:* This function allows to program a byte in Eeprom.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS: The EEPROM mustn't be busy to perform the read access.* eeprom status :(EECON & 0x01)=1 busy, =0 free**************************************************************************/unsigned char __api_wr_eeprom_byte (unsigned char xdata *address,unsigned char value){bit ea_save;while(EECON & 0x01);// wait bit busyea_save = EA;EA = 0;EECON = 0x02;*address = value;/* addr is a pointer to external data mem */EECON = 0x50;EECON = 0xA0;EA = ea_save;return (1);}#endif124365A–80C51–07/04134365A–80C51–07/044. Example4.1 test_api.c/*C*********************************************************************** NAME: test_api.c*------------------------------------------------------------------------* Copyright (c) 2004 Atmel.*------------------------------------------------------------------------* RELEASE:* REVISION: 1.0*------------------------------------------------------------------------* PURPOSE: usage example of flash_eeprom_api.c*************************************************************************//*_____ I N C L U D E S ________________________________________________*/#include "flash_eeprom_api.c"/*F************************************************************************ NAME: main*-------------------------------------------------------------------------* PARAMS:*-------------------------------------------------------------------------* PURPOSE: usage example of flash_eeprom_api.c*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS:*************************************************************************/void main (void){int adress;char i=0;char data_tmp;/* write code page example */for(adress=0x0000;adress<0x007F;adress++){/* write 0x55 between 0x0000 and 0x007F of xram */*((unsigned char xdata*) adress)=0x55;}/* copy xram page to flash at 0x1100 */__api_wr_code_page(0x1100,0x0000,0x7F);/* write code byte example */i=0;for(adress=0x1000;adress<0x1006;adress++){/* write "ABCDEF" at 0x1000 */__api_wr_code_byte(adress,0x41+i++);}/* read and write code byte example */for(adress=0x1000;adress<0x1006;adress++){/* copy 0x1000-0x1006 to 0x1010-0x1016 in flash memory */data_tmp = __api_rd_code_byte(adress);__api_wr_code_byte(adress+0x0010,data_tmp);}#ifdef ONCHIP_EEPROM/* write eeprom byte example */i=0;for (adress=0x000;adress<0x400;adress++) /* write 1Ko of eeprom */{/* write a byte, write time = 10ms to 20ms */__api_wr_eeprom_byte(adress,i++);}/* read eeprom byte example */for (adress=0x000;adress<0x400;adress++){/* copy previous writed data from eeprom to flash at 0x1200 */data_tmp=__api_rd_eeprom_byte(adress);__api_wr_code_byte(0x1200+adress,data_tmp);}#endifwhile(1); /* endless */}144365A–80C51–07/04154365A–80C51–07/044.2 SFR Register Definition/*H**************************************************************************** NAME: AT89C51XD2.h*----------------------------------------------------------------------------* PURPOSE: SFR Description file for AT89C51xD2 products* ON KEIL compiler*****************************************************************************/#define Sfr(x, y) sfr x = y#define Sbit(x, y, z) sbit x = y^z#define Sfr16(x,y) sfr16 x = y/*----------------------------------------*//* Include file for 8051 SFR Definitions *//*----------------------------------------*//* BYTE Register */Sfr (P0 , 0x80);Sbit (P0_7 , 0x80, 7);Sbit (P0_6 , 0x80, 6);Sbit (P0_5 , 0x80, 5);Sbit (P0_4 , 0x80, 4);Sbit (P0_3 , 0x80, 3);Sbit (P0_2 , 0x80, 2);Sbit (P0_1 , 0x80, 1);Sbit (P0_0 , 0x80, 0);Sfr (P1 , 0x90);Sbit (P1_7 , 0x90, 7);Sbit (P1_6 , 0x90, 6);Sbit (P1_5 , 0x90, 5);Sbit (P1_4 , 0x90, 4);Sbit (P1_3 , 0x90, 3);Sbit (P1_2 , 0x90, 2);Sbit (P1_1 , 0x90, 1);Sbit (P1_0 , 0x90, 0);Sfr (P2 , 0xA0);Sbit (P2_7 , 0xA0, 7);Sbit (P2_6 , 0xA0, 6);Sbit (P2_5 , 0xA0, 5);Sbit (P2_4 , 0xA0, 4);Sbit (P2_3 , 0xA0, 3);Sbit (P2_1 , 0xA0, 1);Sbit (P2_0 , 0xA0, 0);Sfr (P3 , 0xB0);Sbit (P3_7 , 0xB0, 7);Sbit (P3_6 , 0xB0, 6);Sbit (P3_5 , 0xB0, 5);Sbit (P3_4 , 0xB0, 4);Sbit (P3_3 , 0xB0, 3);Sbit (P3_2 , 0xB0, 2);Sbit (P3_1 , 0xB0, 1);Sbit (P3_0 , 0xB0, 0);Sbit (RD , 0xB0, 7);Sbit (WR , 0xB0, 6);Sbit (T1 , 0xB0, 5);Sbit (T0 , 0xB0, 4);Sbit (INT1 , 0xB0, 3);Sbit (INT0 , 0xB0, 2);Sbit (TXD , 0xB0, 1);Sbit (RXD , 0xB0, 0);Sfr (P4 , 0xC0);Sbit (P4_7 , 0xC0, 7);Sbit (P4_6 , 0xC0, 6);Sbit (P4_5 , 0xC0, 5);Sbit (P4_4 , 0xC0, 4);Sbit (P4_3 , 0xC0, 3);Sbit (P4_2 , 0xC0, 2);Sbit (P4_1 , 0xC0, 1);Sbit (P4_0 , 0xC0, 0);Sfr (P5 , 0xE8);Sbit (P5_7 , 0xE8, 7);Sbit (P5_6 , 0xE8, 6);Sbit (P5_5 , 0xE8, 5);Sbit (P5_4 , 0xE8, 4);Sbit (P5_3 , 0xE8, 3);Sbit (P5_2 , 0xE8, 2);Sbit (P5_1 , 0xE8, 1);Sbit (P5_0 , 0xE8, 0);Sfr (PSW , 0xD0);Sbit (CY , 0xD0 , 7);Sbit (AC , 0xD0 , 6);164365A–80C51–07/04174365A–80C51–07/04Sbit (RS1 , 0xD0 , 4);Sbit (RS0 , 0xD0 , 3);Sbit (OV , 0xD0 , 2);Sbit (UD , 0xD0 , 1);Sbit (P , 0xD0 , 0);Sfr (ACC , 0xE0);Sfr (B , 0xF0);Sfr (SP , 0x81);Sfr (DPL , 0x82);Sfr (DPH , 0x83);Sfr (PCON , 0x87);Sfr (CKCON0 , 0x8F);Sfr (CKCON1 , 0xAF);/*------------------ TIMERS registers ---------------------*/Sfr (TCON , 0x88);Sbit (TF1 , 0x88, 7);Sbit (TR1 , 0x88, 6);Sbit (TF0 , 0x88, 5);Sbit (TR0 , 0x88, 4);Sbit (IE1 , 0x88, 3);Sbit (IT1 , 0x88, 2);Sbit (IE0 , 0x88, 1);Sbit (IT0 , 0x88, 0);Sfr (TMOD , 0x89);Sfr (T2CON , 0xC8);Sbit (TF2 , 0xC8, 7);Sbit (EXF2 , 0xC8, 6);Sbit (RCLK , 0xC8, 5);Sbit (TCLK , 0xC8, 4);Sbit (EXEN2 , 0xC8, 3);Sbit (TR2 , 0xC8, 2);Sbit (C_T2 , 0xC8, 1);Sbit (CP_RL2, 0xC8, 0);Sfr (T2MOD , 0xC9);Sfr (TL0 , 0x8A);Sfr (TL1 , 0x8B);Sfr (TL2 , 0xCC);Sfr (TH0 , 0x8C);Sfr (TH1 , 0x8D);Sfr (TH2 , 0xCD);Sfr (RCAP2L , 0xCA);Sfr (RCAP2H , 0xCB);Sfr (WDTRST , 0xA6);/*------------------- UART registers ------------------------*/Sfr (SCON , 0x98);Sbit (SM0 , 0x98, 7);Sbit (FE , 0x98, 7);Sbit (SM1 , 0x98, 6);Sbit (SM2 , 0x98, 5);Sbit (REN , 0x98, 4);Sbit (TB8 , 0x98, 3);Sbit (RB8 , 0x98, 2);Sbit (TI , 0x98, 1);Sbit (RI , 0x98, 0);Sfr (SBUF , 0x99);Sfr (SADEN , 0xB9);Sfr (SADDR , 0xA9);/*-------------------- Internal Baud Rate Generator --------*/Sfr (BRL , 0x9A);Sfr (BDRCON , 0x9B);/*-------------------- IT registers -----------------------*/Sfr (IEN0 , 0xA8);Sfr (IEN1 , 0xB1);Sfr (IPH0 , 0xB7);Sfr (IPH1 , 0xB3);Sfr (IPL0 , 0xB8);Sfr (IPL1 , 0xB2);/* IEN0 */Sbit (EA , 0xA8, 7);Sbit (EC , 0xA8, 6);Sbit (ET2 , 0xA8, 5);Sbit (ES , 0xA8, 4);Sbit (ET1 , 0xA8, 3);Sbit (EX1 , 0xA8, 2);Sbit (ET0 , 0xA8, 1);Sbit (EX0 , 0xA8, 0);/*--------------------- PCA registers -----------------------------*/Sfr (CCON , 0xD8);Sfr (CMOD , 0xD9);Sfr (CH , 0xF9);184365A–80C51–07/04194365A–80C51–07/04Sfr (CCAP0H , 0xFA);Sfr (CCAP0L , 0xEA);Sfr (CCAPM0 , 0xDA);Sfr (CCAP1H , 0xFB);Sfr (CCAP1L , 0xEB);Sfr (CCAPM1 , 0xDB);Sfr (CCAP2H , 0xFC);Sfr (CCAP2L , 0xEC);Sfr (CCAPM2 , 0xDC);Sfr (CCAP3H , 0xFD);Sfr (CCAP3L , 0xED);Sfr (CCAPM3 , 0xDD);Sfr (CCAP4H , 0xFE);Sfr (CCAP4L , 0xEE);Sfr (CCAPM4 , 0xDE);/* CCON */Sbit (CF , 0xD8, 7);Sbit (CR , 0xD8, 6);Sbit (CCF4 , 0xD8, 4);Sbit (CCF3 , 0xD8, 3);Sbit (CCF2 , 0xD8, 2);Sbit (CCF1 , 0xD8, 1);Sbit (CCF0 , 0xD8, 0);/*------------------ T W I registers ------------------------------*/Sfr ( SSCON , 0x93);Sfr ( SSCS , 0x94);Sfr ( SSDAT , 0x95);Sfr ( SSADR , 0x96);Sfr ( PI2, 0xF8);Sbit (PI2_1 , 0xF8, 1);Sbit (PI2_0 , 0xF8, 0);/*-------------------- OSC control registers ----------------------*/Sfr ( CKSEL , 0x85 );Sfr ( OSCCON , 0x86 );Sfr ( CKRL , 0x97 );/*-------------------- Keyboard control registers -----------------*/Sfr ( KBLS , 0x9C );Sfr ( KBE , 0x9D );Sfr ( KBF , 0x9E );/*-------------------- SPI ---------------------- -----------------*/Sfr ( SPCON, 0xC3 );Sfr ( SPSTA, 0xC4 );Sfr ( SPDAT, 0xC5 );/*------ Misc ----------------------------------------------------*/Sfr( AUXR , 0x8E);Sfr ( AUXR1, 0xA2);Sfr ( FCON, 0xD1);/*------ E data --------------------------------------------------*/Sfr ( EECON, 0xD2 );204365A–80C51–07/04Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. 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8051单片机实验报告
8051单片机实验报告练习题一1-1修改例程一的源程序：（1）将A寄存器的初值改为80H（正逻辑，数据位为1表示发光二极管点亮），再对源程序进行简单修改，使程序运行后发光二极管点亮情况与修改前相同。
（2）将LED向左循环移位点亮改为向右循环移位点亮。
（3）加快LED循环移位点亮的速度。
（1）在源程序MOV A，#080H后加CPL A（对A取反，80H取反后为7FH）。
（2）将RR A改为RL A。
（3）删除几个CALL DELAY。
1-2将例程二0-F的循环显示改为0-9的循环显示。
将源程序中CJNE A，#10H，MAIN改为CJNE A，#0AH，MAIN.练习题二2-1通过对例程5的程序进行修改和上机调试，改变原程序的功能。
（1）将KEY2，KEY4的功能对调。
（2）每次停下再启动后，更改发光二极管点亮的循环方向。
（1）将ORG 0003H改为0013H，将ORG 0013H改为0003H；将MOV IP，#01H改为MOV IP，#04H；将SETB EX1改为SETB EX0，将SETB EX0改为SETB EX1，将CLR EX0改为CLR EX1；将CLR IE1改为CLR IE0，将CLR IE0改为CLR IE1；（2）程序如下，主要利用两个循环分别进行左移与右移。
$include (C8051F020.inc)ORG 0000HLJMP INITIALORG 0013HLJMP STARORG 0003HLJMP STOPORG 0100HINITIAL: LCALL Init_DeviceMOV R4,#0FHMOV P3,#0FFHMOV A,#0FFHMOV DPTR,#7F80HMOVX @DPTR,AMOV A,#0FEHMOV R1,#1HMOV IP,#04HMOV TCON,#05HSETB EX0SETB EALOOP1: CLR EACJNE R4,#0FH,LOOP2RL ACJNE R4,#0FH,LOOP2MOV P3,ACJNE R4,#0FH,LOOP2INC R1CJNE R4,#0FH,LOOP2SETB EALCALL DELAY1LCALL DELAY1LCALL DELAY1LCALL DELAY1CJNE R1,#8,LOOP1MOV R1,#0HSJMP LOOP1LOOP2: CLR EACJNE R4,#0F0H,LOOP1RR ACJNE R4,#0F0H,LOOP1MOV P3,ACJNE R4,#0F0H,LOOP1DEC R1SETB EALCALL DELAY1LCALL DELAY1LCALL DELAY1LCALL DELAY1CJNE R1,#0,LOOP2MOV R1,#8SJMP LOOP2STOP: PUSH ACCMOV A,R1MOV DPTR,#TABMOVC A,@A+DPTRMOV DPTR,#7F80HMOVX @DPTR,ASETB EX1JNZ $MOV A,#0FFHMOVX @DPTR,ACLR EX1POP ACCCLR IE0RETISTAR: MOV A,#00HCLR IE1PUSH ACCMOV A,R4CPL AMOV R4,APOP ACCRETITAB: DB 0C0H,0F9H,0A4H,0B0H,099HDB 092H,082H,0F8H,080H DELAY1: MOV R6,#0D1: MOV R7,#0DJNZ R7,$DJNZ R6,D1RET$include (Init_Device.inc) ;END2-2修改例程6，将计数范围由0-F扩展至00-FF（使用定时器/计时器0），并在2位数码管上用10进制数显示计数结果（00-99）。
温度监测中英文翻译
土壤温度测量的设计1.简介温度是土壤的一个十分重要的环境因素，它直接影响微生物的活跃性及有机物的分解，影响植物的根吸收水分与矿物质，同时它在植物生长率及根的范围上发挥着重要作用。
据统计，植物的根一般在地下50厘米范围内，因此测量这一范围内不同深度的土壤温度变得十分有意义。
目前，土壤温度测量仪器可分为三类。
第一种，是利用热敏电阻与土壤温度之间的关系测量实际温度。
在使用这类仪器前，系统参数需要校正，同时当解决系统遇到的问题时，十分不便。
第二种是非接触式的土壤测温仪器，它通过红外线测量温度，这种设备价格昂贵。
第三种，通过数字温度计测量温度。
目前，这类仪器不仅可测量一点的土壤温度，还可将数据进行存储与传输。
总之，上述设备因为价格过于昂贵或功能过于简单，而得不到广泛应用。
因此，一种价格更廉价，更能更强大的仪器需要去开发设计。
2.设计与原理本设计运用高品质单片机C8051F310作为核心控制器，它主要包括以下功能模块，如数据采集模块、显示与存储模块、时钟模块、串行通信模块、键控控制块及电源模块。
如图1所示系统组成及如何工作。
图 1 系统框图该系统可在不同深度测量10点的土壤温度，在采集数据的同时，并将温度及时间数据予以显示之后，系统通过串行通信接口将数据传送到计算机。
用户可以通过按键设置系统参数及运行系统。
经过试验，这种效率高成本低的便携式的仪器能平稳工作且运行良好。
2.1硬件设计在硬件设计中，系统可利用的部分包括C8051F310单片机、DS18B20数字温度传感器、ISL6292可编程锂电池充电管理芯片、NCP500电压管理芯片以及DS1302时钟芯片，它们通过相应的外围电路连接在一起，同时这几部分是系统的核心结构。
下面就介绍这些核心部分及其外围电路。
2.1.1高质量C8051F310单片机C8051F310是一款兼容8051指令集的完全集成的混合信号ISP型MCU芯片。
C8051F310主要由CIP-51内核、外围模拟电路、数字I/O口及电源模块组成。
汇编指令大全
ORG 0000HNOP ;空操作指令AJMP L0003 ;绝对转移指令L0003: LJMP L0006 ;长调用指令L0006: RR A ;累加器A内容右移(先置A为88H)INC A ; 累加器A 内容加1INC 01H ;直接地址(字节01H)内容加1INC @R0 ; R0的内容(为地址) 的内容即间接RAM加1;(设R0=02H,02H=03H,单步执行后02H=04H)INC @R1 ; R1的内容(为地址) 的内容即间接RAM加1;(设R1=02H,02H=03H,单步执行后02H=04H)INC R0 ; R0的内容加1 (设R0为00H,单步执行后查R0内容为多少) INC R1 ; R1的内容加1(设R1为01H,单步执行后查R1内容为多少) INC R2 ; R2的内容加1 (设R2为02H,单步执行后查R2内容为多少) INC R3 ; R3的内容加1(设R3为03H,单步执行后查R3内容为多少) INC R4 ; R4的内容加1(设R4为04H,单步执行后查R4内容为多少) INC R5 ; R5的内容加1(设R5为05H,单步执行后查R5内容为多少) INC R6 ; R6的内容加1(设R6为06H,单步执行后查R6内容为多少) INC R7 ; R7的内容加1(设R7为07H,单步执行后查R7内容为多少) JBC 20H,L0017; 如果位(如20H,即24H的0位)为1,则转移并清0该位L0017: ACALL S0019 ;绝对调用S0019: LCALL S001C ;长调用S001C: RRC A ;累加器A的内容带进位位右移(设A=11H,C=0;单步执行后查A和C内容为多少)DEC A ;A的内容减1DEC 01H ;直接地址(01H)内容减1DEC @R0 ;R0间址减1,即R0的内容为地址,该地址的内容减1 DEC @R1 ; R1间址减1DEC R0 ; R0内容减1DEC R1 ; R1内容减1DEC R2 ; R2内容减1DEC R3 ; R3内容减1DEC R4 ; R4内容减1DEC R5 ; R5内容减1DEC R6 ; R6内容减1DEC R7 ; R7内容减1JB 20H,L002D;如果位(20H,即24H的0位)为1则转移L002D: AJMP L0017 ;绝对转移RET ;子程序返回指令RL A ;A左移ADD A,#01H ;A的内容与立即数(01H)相加ADD A,01H ; A的内容与直接地址(01H内容)相加ADD A,@R0 ; A的内容与寄存器R0的间址内容相加ADD A,@R1 ; A的内容与寄存器R1的间址内容相加ADD A,R0 ; A的内容与寄存器R0的内容相加ADD A,R1 ; A的内容与寄存器R1的内容相加ADD A,R2 ; A的内容与寄存器R2的内容相加ADD A,R3 ; A的内容与寄存器R3的内容相加ADD A,R4 ; A的内容与寄存器R4的内容相加ADD A,R5 ; A的内容与寄存器R5的内容相加ADD A,R6 ; A的内容与寄存器R6的内容相加ADD A,R7 ; A的内容与寄存器R7的内容相加JNB 30H,L0041 ;直接位(30H)为0相对转移L0041: ACALL S0100 ;绝对调用RETI ;中断返回指令RLC A ;带进位位左移ADDC A,#02H ;A带进位位与立即数(#02H)相加ADDC A,02H ; A带进位位与直接地扯(02H内容)相加ADDC A,@R0 ; A带进位位与R0间扯内容相加ADDC A,@R1 ; A带进位位与R1间扯内容相加ADDC A,R0 ; A带进位位与R0内容相加ADDC A,R1 ; A带进位位与R1内容相加ADDC A,R2 ; A带进位位与R2内容相加ADDC A,R3 ; A带进位位与R3内容相加ADDC A,R4 ; A带进位位与R4内容相加ADDC A,R5 ; A带进位位与R5内容相加ADDC A,R6 ; A带进位位与R6内容相加ADDC A,R7 ; A带进位位与R7内容相加JC L0095 ;进位为1转移NOPAJMP L0017 ;绝对转移ORL 02H,A ;直接地址内容与A或ORL 02H,#02H ; 直接地址内容与立即数或ORL A,#44H ;A与立即数或ORL A,02H ; A与直接地址内容或ORL A,@R0 ; A与R0间址内容或ORL A,@R1 ; A与R1间址内容或ORL A,R0 ; A与R0内容或ORL A,R1 ; A与R1内容或ORL A,R2 ; A与R2内容或ORL A,R3 ; A与R3内容或ORL A,R4 ; A与R4内容或ORL A,R5 ; A与R5内容或ORL A,R6 ; A与R6内容或ORL A,R7 ; A与R7内容或JNC L0017 ;进位为0转移ACALL L0017 ;绝对调用ANL 02H,A ; 直接地址与A与ANL 02H,#02H ; 立即数与直接地址与ANL A,#02H ; A与立即数与ANL A,02H ;A与直接地址与ANL A,@R0 ; A与R0间址与ANL A,@R1 ; A与R1间址与ANL A,R0 ; A与R0与ANL A,R1 ; A与R1与ANL A,R2 ; A与R2与ANL A,R3 ; A与R3与ANL A,R4 ; A与R4与ANL A,R5 ; A与R5与ANL A,R6 ; A与R6与ANL A,R7 ; A与R7与JZ L0084 ;A为零转移L0084: AJMP L0017 ;绝对转移XRL 01H,A ;直接地址与A异或XRL 02H,#01H ; 直接地址与立即数异或XRL A,#01H ;A与立即数异或XRL A,01H ; A与直接地址异或XRL A,@R0 ; A与R0间址址异或XRL A,@R1 ; A与R1间址址异或XRL A,R0 ; A与R0异或XRL A,R1 ; A与R1异或XRL A,R2 ; A与R2异或XRL A,R3 ; A与R3异或XRL A,R4 ; A与R4异或L0095: XRL A,R5 ; A与R5异或XRL A,R6 ; A与R6异或XRL A,R7 ; A与R7异或JNZ L0084 ;A不为零转L009A: ACALL L0084 ;绝对调用ORL C,01H ;直接位或到进位JMP @A+DPTR;相对于DPTR间接转MOV A,#01H ;立即数送AMOV 01H,#02H ;立即数送直接地址MOV @R0,#01H ;立即数送间址R0 MOV @R1,#02H ; 立即数送间址R1 MOV R0,#01H ; 立即数送R0MOV R1,#01H ; 立即数送R1MOV R2,#01H ; 立即数送R2MOV R3,#01H ; 立即数送R3MOV R4,#01H ; 立即数送R4MOV R5,#01H ; 立即数送R5MOV R6,#01H ; 立即数送R6MOV R7,#01H ; 立即数送R7SJMP L00BA ;短转移L00BA: AJMP L0095 ;绝对转移ANL C,02H ;直接地址与进位与ORG 00C0H ;MOV 02H,01H ;直接地址送直接地址MOV 01H,@R0;间址R0送直接地址MOV 01H,@R1; 间址R1送直接地址MOV 01H,R0 ; R0送直接地址MOV 01H,R1 ; R1送直接地址MOV 01H,R2 ; R2送直接地址MOV 01H,R3 ; R3送直接地址MOV 01H,R4 ; R4送直接地址MOV 01H,R5 ; R5送直接地址MOV 01H,R6 ; R6送直接地址MOV 01H,R7 ; R7送直接地址NOPMOV DPTR,#1234H;建立数据指针地址为1234HACALL L00BA ;绝对调用MOV 03H,C ;进位送03H位(即20H的03位)MOVC A,@A+DPTR ;由A+DPTR寻扯的程序存贮器字节送A SUBB A,#01H ;A减去立即数和进位位SUBB A,02H ; A减去直接地址内容和进位位SUBB A,@R0 ; A减去R0间接RAM和进位位SUBB A,@R1 ; A减去R1间接RAM和进位位SUBB A,R0 ; A减去R0和进位位SUBB A,R1 ; A减去R1和进位位SUBB A,R2 ; A减去R2和进位位SUBB A,R3 ; A减去R3和进位位SUBB A,R4 ; A减去R4和进位位SUBB A,R5 ; A减去R5和进位位SUBB A,R6 ; A减去R6和进位位SUBB A,R7 ; A减去R7和进位位ORL C,/00H ;直接位的反或到进位AJMP L0084 ;绝对转移MOV C,03H ;直接位数送进位INC DPTR ;数据指针加1MUL AB ;A乘以BNOP ;A5H为二字节空操作指令NOPMOV @R0,05H ;直接字芯送R0间接RAMMOV @R1,05H ; 直接字芯送R1间接RAMMOV R0,05H ; 直接字芯送R0MOV R1,05H ; 直接字芯送R1S0100: MOV R2,05H ; 直接字芯送R2MOV R3,05H ; 直接字芯送R3MOV R4,05H ; 直接字芯送R4MOV R5,05H ; 直接字芯送R5MOV R6,05H ; 直接字芯送R6MOV R7,05H ; 直接字芯送R7ANL C,/04H ; 直接位的反与到进位ACALL S0100 ;绝对调用CPL 04H ;直接位取反CPL C ;进位取反CJNE A,#01H,L0139 ;立即数与A比较,不相等则转移CJNE A,01H,L0139 ; 直接字节与A比较,不相等则转移CJNE @R0,#01H,L0139 ; 立即数与R0间接RAM比较,不相等则转移CJNE @R1,#01H,L0139 ; 立即数与R1间接RAM比较,不相等则转移CJNE R0,#01H,L0139 ; 立即数与R0比较,不相等则转移CJNE R1,#01H,L0139 ; 立即数与R1比较,不相等则转移CJNE R2,#01H,L0139 ; 立即数与R2比较,不相等则转移CJNE R3,#01H,L0139 ; 立即数与R3比较,不相等则转移CJNE R4,#01H,L0139 ; 立即数与R4比较,不相等则转移CJNE R5,#01H,L0139 ; 立即数与R5比较,不相等则转移CJNE R6,#01H,L0139 ; 立即数与R6比较,不相等则转移CJNE R7,#01H,L0139 ; 立即数与R7比较,不相等则转移PUSH 00H ;直接字节进栈,SP加1L0139: AJMP L0084 ;绝对转移CLR 04H ;直接位清零CLR C ;清零进位SWAP A ;A左环移四位(A的二个半字节交换)XCH A,05H ;交换A和直接字节XCH A,@R0 ; 交换A和R0间接RAMXCH A,@R1 ; 交换A和R1间接RAMXCH A,R0 ; 交换A和R0XCH A,R1 ; 交换A和R1XCH A,R2 ; 交换A和R2XCH A,R3 ; 交换A和R3XCH A,R4 ; 交换A和R4XCH A,R5 ; 交换A和R5XCH A,R6 ; 交换A和R6XCH A,R7 ; 交换A和R7POP 00H ;直接字节出栈,SP减1ACALL L0139 ;绝对调用SETB 03H ;置位直接位SETB C ;置位进位DA A ;A的十进制加法调熊DJNZ 01H,L0139 ;直接字节减1,不为零则转移XCHD A,@R0 ;交换A和R0间接RAM的低4位XCHD A,@R1 ; 交换A和R1间接RAM的低4位L0158: DJNZ R0,L0139 ; R0减1,不为零则转移DJNZ R1,L0158 ; R1减1,不为零则转移DJNZ R2,L0158 ; R2减1,不为零则转移DJNZ R3,L0158 ; R3减1,不为零则转移DJNZ R4,L0158 ; R4减1,不为零则转移DJNZ R5,L0158 ; R5减1,不为零则转移DJNZ R6,L0158 ; R6减1,不为零则转移DJNZ R7,L0158 ; R7减1,不为零则转移MOVX A,@DPTR ;外部数据(16位地址)送AL0169: NOPAJMP L0139 ;绝对转移MOVX A,@R0 ;R0间址即外部数据(8位地址)送A MOVX A,@R1 ; R1间址即外部数据(8位地址)送A CLR A ;清零AMOV A,05H ;直接字节送AMOV A,@R0 ;R0间接RAM送AMOV A,@R1 ; R1间接RAM送AMOV A,R0 ; R0送AMOV A,R1 ; R1送AMOV A,R2 ; R2送AMOV A,R3 ; R3送AMOV A,R4 ; R4送AMOV A,R5 ; R5送AMOV A,R6 ; R6送AMOV A,R7 ; R7送AMOVX @DPTR,A ;A送外部数据(16位地址)NOPACALL L0169 ;绝对调用MOVX @R0,A ;A送R0间址即外部数据(8位地址) MOVX @R1,A ; A送R1间址即外部数据(8位地址) CPL A ;A取反MOV 05H,A ;A送直接字节MOV @R0,A ; A送R0间址即间接RAMMOV @R1,A ; A送R1间址即间接RAMMOV R0,A ; A送R0MOV R1,A ; A送R1MOV R2,A ; A送R2MOV R3,A ; A送R3MOV R4,A ; A送R4MOV R5,A ; A送R5MOV R6,A ; A送R6MOV R7,A ; A送R7END51的汇编控制指令详细列表8051 INSTRUCTION SET1.Arithmetic operations:Mnemonic Byte CycADD A,@Ri 1 1ADD A,Rn 1 1ADD A,direct 2 1ADD A,#data 2 1ADDC A,@Ri 1 1ADDC A,Rn 1 1ADDC A,direct 2 1ADDC A,#data 2 1SUBB A,@Ri 1 1SUBB A,Rn 1 1SUBB A,direct 2 1SUBB A,#data 2 1INC A 1 1INC @Ri 1 1INC Rn 1 1INC DPTR 1 1INC direct 2 1INC direct 2 1DEC A 1 1DEC @Ri 1 1DEC Rn 1 1DEC direct 2 1MUL AB 1 4DIV AB 1 4DA A 1 18051的汇编控制指令，占用字节，执行周期列表3.Data transfer:Mnemonic Byte CycMOV A,@Ri 1 1MOV DPTR,#data16 3 2MOV A,Rn 1 1MOVC A,@A+DPTR 1 2MOV A,direct 2 1MOVC A,@A+PC 1 2MOV A,#data 2 1MOVX A,@Ri 1 2 8051的汇编控制指令，占用字节，执行周期列表2. Logical opreations:ANL A,@Ri 1 1XRL A,@Ri 1 1ANL A,Rn 1 1XRL A,Rn 1 1ANL A,direct 2 1XRL A,direct 2 1ANL A,#data 2 1XRL A,#data 2 1ANL direct,A 2 1XRL direct,A 2 1ANL direct,#data 3 2XRL direct,#data 3 2ORL A,@Ri 1 1CLR A 1 1ORL A,Rn 1 1CPL A 1 1ORL A,direct 2 1RL A 1 1ORL A,#data 2 1RLC A 1 1ORL direct,A 2 1RR A 1 1ORL direct,#data 3 2RRC A 1 1SWAP A 1 18051的汇编控制指令，占用字节，执行周期列表4.Boolean variable manipulation:Mnemonic Byte CycCLR C 1 1ANL C,bit 2 2SETB C 1 1ANL C,/bit 2 2CPL C 1 1ORL C,bit 2 2CLR bit 2 1ORL C,/bit 2 2SETB bit 2 1MOV C,bit 2 1CPL bit 2 1MOV bit,C 2 2MOV @Ri,A 1 1MOVX A,@DPTR 1 2 MOV @Ri,direct 2 2 MOVX @Ri,A 1 2 MOV @Ri,#data 2 1 MOVX @DPTR,A 1 2 MOV Rn,A 1 1 PUSH direct 2 2 MOV Rn,direct 2 2 POP direct 2 2MOV Rn,#data 2 1 XCH A,@Ri 1 1 MOV direct,A 2 1 XCH A,Rn 1 1MOV direct,@Ri 2 2 XCH A,direct 2 1 MOV direct,Rn 2 2 XCHD A,@Ri 1 1 MOV direct,direct 3 2 MOV direct,#data 3 2 8051的汇编控制指令，占用字节，执行周期列表5.Program and machine control:Mnemonic Byte CycNOP 1 1JZ rel 2 2RET 1 2JNZ rel 2 2RETI 1 2JC rel 2 2ACALL addr11 2 2JNC rel 2 2AJMP addr11 2 2JB bit,rel 3 2LCALL addr16 3 2JNB bit,rel 3 2LJMP addr16 3 2JBC bit,rel 3 2SJMP rel 2 2CJNE A,direct,rel 3 2JMP @A+DPTR 1 2CJNE A,#data,rel 3 2DJNZ Rn,rel 2 2CJNE @Ri,#data,rel 3 2DJNZ direct,rel 3 2CJNE Rn,#data,rel 3 2。
8051兼容安全微控制器DS2252T数据表说明书
GENERAL DESCRIPTIONThe DS2252T secure microcontroller module is an 8051-compatible microcontroller based on nonvolatile RAM technology. It is designed for systems that need to protect memory contents from disclosure. This includes key data, sensitive algorithms, and proprietary information of all types. Like other members of the secure microcontroller family, it provides full compatibility with the 8051 instruction set, timers, serial port, and parallel I/O ports. By using NV RAM instead of ROM, the user can program, then reprogram the microcontroller while in-system. This allows frequent changing of sensitive processes with minimal effort. PIN CONFIGURATIONOperating information and detailed summary of this product’ssecurity features are contained in the Secure Microcontroller User’s Guide. This data sheet provides ordering information,pinout, and electrical specifications.FEATURES8051-Compatible Microcontroller 8, 32, or 64kbytes of Nonvolatile SRAM for Program and/or Data Memory Storage In-System Programming via On-Chip Serial Port Capable of Modifying its Own Program and/or Data Memory in the End System Firmware Security Features Memory Stored in Encrypted Form Encryption Using On-Chip 64-Bit Key Automatic True Random Key Generator Self-Destruct Input (SDI) Improved Security Over Previous Generations Protects Memory Contents from PiracyCrashproof OperationMaintains All Nonvolatile Resources Up to 10 Years in the Absence of V CC at Room Temperature Power-Fail Reset Early Warning Power-Fail Interrupt Watchdog Timer Precision Reference for Power Monitor Fully 8051 Compatible 128 Bytes Scratchpad RAM Two Timer/Counters On-Chip Serial Port 32 Parallel I/O Port Pins Permanently Powered Real-Time ClockORDERING INFORMATIONPARTRAM SIZE (kB)MAX CRYSTAL SPEED (MHz)TIMEKEEPING?DS2252T-64-16 64 16 Yes DS2252T-64-16# 64 16 Yes DS2252T-128-16 128 16 Yes DS2252T-128-16# 12816Yes# Denotes RoHS-compliant device that may contain lead exempt under the RoHS requirements.DS2252TSoft Microcontroller ModuleDETAILED DESCRIPTIONThe DS2252T provides an array of mechanisms to prevent an attacker from examining the memory. It is designed to resist all levels of threat including observation, analysis, and physical attack. As a result, a massive effort would be required to obtain any information about memory contents. Furthermore, the “Soft” nature of the DS2252T allows frequent modification of secure information. This minimizes that value of any information that is obtained.Using a security system based on the DS5002FP, the DS2252T protects the memory contents from disclosure. It loads program memory via its serial port and encrypts it in real time prior to storing it in SRAM. Once encrypted, the RAM contents and the program flow are unintelligible. The real data exists only inside the processor chip after being decrypted. Any attempt to discover the on-chip data, encryption keys, etc., results in its destruction. Extensive use of nonvolatile lithium-backed technology creates a microcontroller that retains data for over 10 years at room temperature, but which can be erased instantly if tampered with. The DS2252T even interfaces directly to external tamper protection hardware.The DS2252T provides a permanently powered real time lock with interrupts for time stamp and date. It keeps time to one hundredth of a second using its onboard 32 kHz crystal.Like other Secure Microcontrollers in the family, the DS2252T provides crashproof operation in portable systems or systems with unreliable power. These features include the ability to save the operating state, Power-fail Reset, Power-fail Interrupt, and Watchdog Timer. All nonvolatile memory and resources are maintained for over 10 years at room temperature in the absence of power.A user loads programs into the DS2252T via its on-chip Serial Bootstrap Loader. This function supervises the loading of software into NV RAM, validates it, then becomes transparent to the user. It also manages the loading of new encryption keys automatically. Software is stored in onboard CMOS SRAM. Using its internal Partitioning, the DS2252T can divide a common RAM into user selectable program and data segments. This Partition can be selected at program loading time, but can be modified anytime later. The microcontroller will decode memory access to the SRAM, access memory via its Byte-wide bus and write-protect the memory portion designated as program (ROM).DS2252T BLOCK DIAGRAM Figure 1PIN ASSIGNMENTPIN NAME PIN NAME1 P1.0 11 P1.52 V CC12 P0.4 3 P1.1 13 P1.6 4 P0.0 14 P0.55 P1.215 P1.76 P0.1 16 P0.67 P1.3 17 RST8 P0.2 18 P0.79 P1.4 19 P3.0/RXD 10 P0.3 20 SDIINSTRUCTION SETThe DS2252T executes an instruction set that is object code-compatible with the industry standard 8051 microcontroller. As a result, software development packages such as assemblers and compilers that have been written for the 8051 are compatible with the DS2252T. A complete description of the instruction set and operation are provided in the Secure Microcontroller User’s Guide.MEMORY ORGANIZATIONFigure 2 illustrates the memory map accessed by the DS2252T. The entire 64k of program and 64k of data are available to the Byte-wide bus. This preserves the I/O ports for application use. An alternate configuration allows dynamic Partitioning of a 64k space as shown in Figure 3. Any data area not mapped into the NV RAM is reached via the Expanded bus on Ports 0 and 2. Off-board program memory is not available for security reasons. Selecting PES = 1 provides access to the real-time clock as shown in Figure 4. These selections are made using Special Function Registers. The memory map and its controls are covered in detail in the Secure Microcontroller User’s Guide.DS2252T MEMORY MAP IN NON-PARTITIONABLE MODE (PM = 1) Figure 2DS2252T MEMORY MAP IN PARTITIONABLE (PM = 0) Figure 3NV RAM PROGRAM NV RAM DATAPROGRAM MEMORY DATA MEMORY (MOVX)FFFFh --0000h ---- 64KNV RAM PROGRAMNV RAM DATAPROGRAM MEMORYDATA MEMORY (MOVX)FFFFh --0000h --PARTITIONNOTE: PARTITIONABLE MODE IS NOT SUPPORTED ON THE 128KB VERSION OF THE DS2252T.LEGEND:=NV RAM MEMORY= EXPANDED BUS (PORTS 0 AND 2)=NOT AVAILABLEDS2252T MEMORY MAP WITH (PES = 1) Figure 4POWER MANAGEMENTThe DS2252T monitors V CC to provide power-fail reset, early warning power-fail interrupt, and switchover to lithium backup. It uses an internal band-gap reference in determining the switch points. These are called V PFW , V CCMIN , and V LI respectively. When V CC drops below V PFW , the DS2252T will perform an interrupt vector to location 2Bh if the power-fail warning is enabled. Full processor operation continues regardless. When power falls further to V CCMIN , the DS2252T invokes a reset state. No further code execution will be performed unless power rises back above V CCMIN . All decoded chip enables and the R/W signal go to an inactive (logic 1) state. V CC is still the power source at this time. When V CC drops further to below V LI , internal circuitry will switch to the built-in lithium cell for power. The majority of internal circuits will be disabled and the remaining nonvolatile states will be retained. The Secure Microcontroller User’s Guide has more information on this topic. The trip points V CCMIN and V PFW are listed in the electrical specifications.NV RAM PROGRAMPROGRAM MEMORY DATA MEMORY (MOVX)FFFFh --0000h --PARTITION=NOT ACCESSIBLEREAL-TIME CLOCKC000h --B000h --4000h ---- 64K-- 16KABSOLUTE MAXIMUM RATINGSVoltage Range on Any Pin Relative to Ground……………………………………...-0.3V to (V CC + 0.5V) Voltage Range on V CC Relative to Ground…………………………………………………-0.3V to +6.0V Operating Temperature Range……………………………………………………………...-40°C to +85°C Storage Temperature (Note 1)…………………………………………………………….-55°C to +125°C Soldering Temperature………………………………………………………………+260°C for 10 seconds This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.Note 1: Storage temperature is defined as the temperature of the device when V CC = 0V and V LI = 0V. In this state the contents of SRAM are not battery-backed and are undefined.DC CHARACTERISTICSDC CHARACTERISTICS (continued)(V CC = 5V ±10%, T A = 0°C to +70°C.)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESWith BAT = 3.0V 4.0 4.25Reset Trip Point in StopMode With BAT =3.3V4.4 4.65V 1SDI Input High Voltage V IHS 2.0 V CC V 1,2 SDI Input High Voltage V IHS 2.0 3.5 V 1,2 SDI Pulldown Resistor R SDI 25 60 kΩAC CHARACTERISTICS(V CC = 0V to 5V, T A = 0°C to +70°C.)PARAMETER SYMBOL MIN TYP MAX UNITS NOTES(4.5V < V CC < 5.5V) t SPR 2SDI Pulse Reject(V CC = 0V, V BAT = 2.9V) 4µs 10(4.5V < V CC < 5.5V) t SPA 10 SDI PulseAccept (VCC = 0V,V BAT = 2.9V) 50µs 10AC CHARACTERISTICS—EXPANDED BUS MODE TIMING SPECIFICATIONSEXPANDED DATA MEMORY READ CYCLEEXPANDED DATA MEMORY WRITE CYCLEAC CHARACTERISTICS—EXTERNAL CLOCK DRIVE (V CC = 5V ±10%, T A = 0°C to +70°C.)# PARAMETER SYMBOL MIN MAX UNITS At 12MHz 20 28 External Clock High Time At 16MHz t CLKHPW 15 nsAt 12MHz 2029 External Clock Low Time At 16MHz t CLKLPW 15 nsAt 12MHz 2030 External Clock Rise Time At 16MHz t CLKR 15 nsAt 12MHz20 31 External Clock Fall Time At 16MHzt CLKF15nsEXTERNAL CLOCK TIMINGAC CHARACTERISTICS—POWER CYCLE TIMING(V CC = 5V ±10%, T A = 0°C to +70°C.)# PARAMETER SYMBOL MIN MAX UNITS 32 Slew Rate from V CCMIN to 3.3V t F 130µs8)33 Crystal Startup Time t CSU (Note34 Power-On Reset Delay t POR 21,504t CLK POWER CYCLE TIMINGAC CHARACTERISTICS—SERIAL PORT TIMING: MODE 0(V CC = 5V ±10%, T A = 0°C to +70°C.)# PARAMETER SYMBOL MIN MAX UNITS35 Serial Port Clock Cycle Time t SPCLK 12t CLK µs36 Output Data Setup to Rising Clock Edge t DOCH 10t CLK - 133 ns37 Output Data Hold after Rising Clock Edge t CHDO 2t CLK - 117 ns38 Clock Rising Edge to Input Data Valid t CHDV 10t CLK - 133 nsns 39 Input Data Hold after Rising Clock Edge t CHDIV 0SERIAL PORT TIMING: MODE 0NOTES:1. All voltage referenced to ground.2. SDI should be taken to a logic high when V CC = +5V, and to approximately 3V when V CC < 3V.3. SDI is deglitched to prevent accidental destruction. The pulse must be longer than t SPR to pass thedeglitcher, but SDI is not guaranteed unless it is longer than t SPA.4. Maximum operating I CC is measured with all output pins disconnected; XTAL1 driven with t CLKR,t CLKF=10 ns, V IL = 0.5V; XTAL2 disconnected; RST = PORT0 = V CC.5. Idle mode I IDLE is measured with all output pins disconnected; XTAL1 driven with t CLKR, t CLKF = 10ns, V IL = 0.5V; XTAL2 disconnected; PORT0 = V CC, RST = V SS.6. Stop mode I STOP is measured with all output pins disconnected; PORT0 = V CC; XTAL2 notconnected; RST = XTAL1 = V SS.7. Pin capacitance is measured with a test frequency—1 MHz, T A = +25°C.8. Crystal startup time is the time required to get the mass of the crystal into vibrational motion from thetime that power is first applied to the circuit until the first clock pulse is produced by the on-chiposcillator. The user should check with the crystal vendor for a worst-case specification on this time.PACKAGE DRAWINGDIM MIN MAXA 2.645 2.655B 2.379 2.389C 0.995 1.005D 0.395 0.405E 0.245 0.255F 0.050 BSCG 0.075 0.085H 0.245 0.255I 0.950 BSCJ 0.120 0.130K 1.320 1.330L 1.445 1.455M 0.057 0.067N - 0.300O - 0.165P 0.047 0.054DATA SHEET REVISION SUMMARYThe following represent the key differences between 12/13/95 and 08/16/96 version of the DS2252T data sheet. Please review this summary carefully.1. Change V CC slew rate specification to reference 3.3V instead of V LI.2. Add minimum value to PCB thickness.The following represent the key differences between 08/16/96 and 05/28/97 version of the DS2252T data sheet. Please review this summary carefully.1. AC characteristics for battery-backed SDI pulse specification added.The following represent the key differences between 05/28/97 and 11/08/99 version of the DS2252T data sheet. Please review this summary carefully. (PCN I80903)1. Correct Absolute Maximum Ratings to reflect changes to DS5002FP microprocessor.2. Add note clarifying that SRAM contents are not defined under storage temperature conditions. The following represent the key differences between 11/08/99 and 01/18/00 version of the DS2252T data sheet. Please review this summary carefully.1. Data sheet conversion from Interleaf to Word.The following represent the key differences between 01/18/00 and 06/13/06 version of the DS2252T data sheet. Please review this summary carefully.1. Updated reference in Features (Crashproof Operation) to 10-year NV RAM data life to includeroom temperature caveat.2. Added RoHS-compliant packages to Ordering Information table.3. Replaced references to “Secure Microcontroller Data Book” with “Secure MicrocontrollerUser’s Guide.”16 of 16Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.。
8051_assembler
8051 CROSS ASSEMBLER.USER'S MANUALCopyright (c) 1984, 1985, 1986, 1987, 1988, 1989, 1990 MetaLink Corp.1. 8051 OVERVIEW1.1. IntroductionThe 8051 series of microcontrollers are highly integrated single chip microcomputers with an 8-bit C PU, memory, interrupt controller, timers, serial I/O and digital I/O on a single piece of silicon. The current members of the 8051 family of components include:80C152JA/JB/JC/JD, 83C152JA/JC, 80C15780C154, 83C154, 85C1548044, 8344, 874480C451, 83C451, 87C45180C452, 83C452, 87C4528051, 8031, 8751, 80C51, 80C31, 87C5180512, 8053280515, 80535, 80C535, 80C51580C517, 80C53780C51FA, 83C51FA, 87C51FA, 83C51FB, 87C51FB, 83C51FC, 87C51FC 8052, 8032, 875280C321, 80C521, 87C521, 80C541, 87C5418053, 9761, 875380C552, 83C552, 87C55280C652, 83C652, 87C65283C654, 87C65483C751, 87C75183C752, 87C75280C851, 83C851All members of the 8051 series of microcontrollers share a common architecture. They all have the same instruction set, addressing modes, addressing range and memory spaces. The primary differences between different 8051 based products are the amount of memory on chip, the amount and types of I/O and peripheral functions, and the component's technology (see Table 1-1).In the brief summary of the 8051 architecture that follows, the term 8051 is used to mean collectively all available members of the 8051 family. Please refer to reference (1) for a complete description of the 8051 architecture and the specifications for all the currently available 8051 based products.1.2. 8051 ArchitectureThe 8051 is an 8-bit machine. Its memory is organized in bytes and practically all its instruction deal with byte quantities. It uses an Accumulator as the primary register for instruction results. Other operands can be accessed using one of the four different addressing modes available: register implicit, direct,indirect or immediate. Operands reside in one of the five memory spaces of the 8051.The five memory spaces of the 8051 are: Program Memory, External Data Memory, Internal Data Memory, Special Function Registers and Bit Memory.The Program Memory space contains all the instructions, immediate data and constant tables and strings. It is principally addressed by the 16-bit Program C ounter (PC), but it can also be accessed by a few instructions using the 16-bit Data Pointer (DPTR). The maximum size of the Program Memory space is 64Kbytes. Several 8051 family members integrate on-chip some amount of either masked programmed ROM or EPROM as part of this memory space (refer to Table 1-1).The External Data Memory space contains all the variables, buffers and data structures that can't fit on-chip. It is principally addressed by the 16-bit Data Pointer (DPTR), although the first two general purpose register (R0,R1) of the currently selected register bank can access a 256-byte bank of External Data Memory. The maximum size of the External Data Memory space is 64Kbytes. External data memory can only be accessed using the indirect addressing mode with the DPTR, R0 or R1.The Internal Data Memory space is functionally the most important data memory space. In it resides up to four banks of general purpose registers, the program stack, 128 bits of the 256-bit memory, and all the variables and data structures that are operated on directly by the program. The maximum size of the Internal Data Memory space is 256-bytes. However, different 8051 family members integrate different amounts of this memory space on chip (see Amnt of RAM in Table 1-1). The register implicit, indirect and direct addressing modes can be used in different parts of the Internal Data Memory space.The Special Function Register space contains all the on-chip peripheral I/O registers as well as particular registers that need program access. These registers include the Stack Pointer, the PSW and the Accumulator. The maximum number of SpecialFunction Registers (SFRs) is 128, though the actual number on a particular 8051 family member depends on the number and type of peripheral functions integrated on-chip (see Table 1-1). The SFRs all have addresses greater than 127 and overlap the address space of the upper 128 bytes of the Internal Data Memory space. The two memory spaces are differentiated by addressing mode. The SFRs can only be accessed using the Direct addressing mode while the upper 128 bytes of the Internal Data Memory (if integrated on-chip) can only be accessed using the Indirect addressing mode.The Bit Memory space is used for storing bit variables and flags. There are specific instructions in the 8051 that operate only in the Bit Memory space. The maximum size of the Bit Memory space is 256-bits. 128 of the bits overlap with 16-bytes of the Internal Data Memory space and 128 of the bits overlap with 16 Special Function Registers. Bits can only be accessed using the bit instructions and the Direct addressing mode.The 8051 has a fairly complete set of arithmetic and logical instructions. It includes an 8X8multiply and an 8/8 divide. The 8051 is particularly good at processing bits (sometimes called Boolean Processing). Using the Carry Flag in the PSW as a single bit accumulator, the 8051 can move and do logical operations between the Bit Memory space and the Carry Flag. Bits in the Bit Memory space can also be used as general purpose flags for the test bit and jump instructions.Except for the MOVE instruction, the 8051 instructions can only operate on either the Internal Data Memory space or the Special Function Registers. The MOVE instruction operates in all memory spaces, including the External Memory space and Program Memory space.Program control instructions include the usual unconditional calls and jumps as well as conditional relative jumps based on the C arry Flag, the Accumulator's zero state, and the state of any bit in the Bit Memory space. Also available is a Compare and Jump if Not Equal instruction and a Decrement C ounter and Jump if Not Zero loop instruction. See C hapter 4 for a description of the complete 8051 instruction set.1.3. Summary of the 8051 Family of ComponentsComponent Technology ROM Type of ROM RAM No. of SFRs Serial I/O Type 8031HMOS0-128 b21Start/Stop Async 8051HMOS 4 Kb Masked128 b21Start/Stop Async 8751HMOS 4 Kb EPROM128 b21Start/Stop Async 8053HMOS8 Kb Masked128 b21Start/Stop Async 9761HMOS8 Kb EPROM128 b21Start/Stop Async 8751HMOS8 Kb EPROM128 b21Start/Stop Async 80C31CMOS0-128 b21Start/Stop Async 80C51CMOS 4 Kb Masked128 b21Start/Stop Async 87C51CMOS 4 Kb EPROM128 b21Start/Stop Async 8032HMOS0-256 b26Start/Stop Async 8052HMOS8 Kb Masked256 b26Start/Stop Async 8752HMOS8 Kb EPROM256 b26Start/Stop Async 80C32CMOS0-256 b26Start/Stop Async 80C52CMOS8 Kb Masked256 b26Start/Stop Async 87C52CMOS8 Kb EPROM256 b26Start/Stop Async 8044HMOS 4 Kb Masked192 b34HDLC/SDLC 8344HMOS0-192 b34HDLC/SDLC 8744HMOS 4 Kb EPROM192 b34HDLC/SDLC 80535HMOS0-256 b41Start/Stop Async 80515HMOS8 Kb Masked256 b41Start/Stop Async 80C535CHMOS0-256 b41Start/Stop Async 80C515CHMOS8 Kb Masked256 b41Start/Stop Async 80532HMOS0-128 b28Start/Stop Async 80512HMOS 4 Kb Masked128 b28Start/Stop Async 80C152CHMOS0-256 b56CSMA/CD83C152CHMOS8 Kb Masked256 b56CSMA/CD80C154CMOS0-256 b27Start/Stop Async 83C154CMOS16 Kb Masked256 b27Start/Stop Async 85C154CMOS16 Kb EPROM256 b27Start/Stop Async 80C51FA CHMOS0-256 b47Start/Stop Async 83C51FA CHMOS8 Kb Masked256 b47Start/Stop Async 87C51FA CHMOS8 Kb EPROM256 b47Start/Stop Async 83C51FB CHMOS16 Kb Masked256 b47Start/Stop Async 87C51FB CHMOS16 Kb EPROM256 b47Start/Stop Async 83C51FC CHMOS32 Kb Masked256 b47Start/Stop Async 87C51FC CHMOS32 Kb EPROM256 b47Start/Stop Async 80C537CHMOS0-256 b41Start/Stop Async 80C517CHMOS8 Kb Masked256 b82Start/Stop Async 80C451CMOS0-128 b24Parallel I/F 83C451CMOS 4 Kb Masked128 b24Parallel I/F 87C451CMOS 4 Kb EPROM128 b24Parallel I/F 80C452CHMOS0-256 b55U.P.I.83C452CHMOS8 Kb-256 b55U.P.I.87C452CHMOS8 Kb-256 b55U.P.I.80C552CMOS0-256 b54Start/Stop Async 83C552CMOS8 Kb Masked256 b54Start/Stop Async 87C552CMOS8 Kb EPROM256 b54Start/Stop Async 80C652CMOS0-256 b24Start/Stop Async 83C652CMOS8 Kb Masked256 b24Start/Stop Async 87C652CMOS8 Kb EPROM256 b24Start/Stop Async 83C654CMOS16 Kb Masked256 b24Start/Stop Async 87C654CMOS16 Kb EPROM256 b24Start/Stop Async 83C752CMOS 2 Kb Masked64 b25I2C87C752CMOS 2 Kb EPROM64 b25I2C83C751CMOS 2 Kb Masked64 b20I2C87C751CMOS 2 Kb EPROM64 b20I2C80C521CMOS0-256 b26Start/Stop Async 80C321CMOS8 Kb Masked256 b26Start/Stop Async 87C521CMOS8 Kb EPROM256 b26Start/Stop Async 80C541CMOS16 Kb Masked256 b26Start/Stop Async 87C541CMOS16 kb EPROM256 b26Start/Stop Async 80C851CMOS0-128 b21Start/Stop Async 83C851CMOS 4 Kb Masked128 b21Start/Stop Async Table 1-1: 8051 Family of Components1.4. References1) Intel Corp., 8-Bit Embedded Controllers, 1990.2) Siemens Corp., Microcontroller Component 80515, 1985.3) AMD Corp., Eight-Bit 80C51 Embedded Processors, 1990.4) Signetics Corp., Microcontroller Users' Guide, 1989.2. 8051 CROSS ASSEMBLER OVERVIEW2.1. IntroductionThe 8051C ross Assembler takes anassembly language source file created with a text editor and translates it into a machine language object file. This translation process is done in two passes over the source file. During the first pass, the C ross Assembler builds a symbol table from the symbols and labels used in the source file. It's during the second pass that the C ross Assembler actually translates the source file into the machine language object file. It is also during the second pass that the listing is generated.The following is a discussion of the syntax required by the C ross Assembler to generate error free assemblies.2.2. SymbolsSymbols are alphanumeric representations of numeric constants, addresses, macros, etc. The legal character set for symbols is the set of letters, both upper and lower case (A..Z,a..z), the set of decimal numbers (0..9) and the special characters, question mark (?) and underscore (_). To ensure that the CrossAssembler can distinguish between a symbol and a number, all symbols must start with either a letter or special character (? or _). The following are examples of legal symbols:PISerial_Port_BufferLOC_4096?_?_?In using a symbol, the C ross Assembler converts all letters to upper case. As a result, the Cross Assembler makes no distinction between upper and lower case letters. For example, the following two symbols would be seen as the same symbol by the Cross Assembler:Serial_Port_BufferSERIAL_PORT_BUFFERSymbols can be defined only once. Symbols can be up to 255 characters in length, though only the first 32 are significant. Therefore, for symbols to be unique, they must have a unique character pattern within the first 32 characters. In the following example, the first two symbols would be seen by the Cross Assembler as duplicate symbols, while the third and fourth symbols are unique.BEGINNING_ADDRESS_OF_CONSTANT_TABLE_1BEGINNING_ADDRESS_OF_CONSTANT_TABLE_2CONSTANT_TABLE_1_BEGINNING_ADDRESSCONSTANT_TABLE_2_BEGINNING_ADDRESSThere are certain symbols that are reserved and can't be defined by the user. These reserved symbols are listed in Appendix C and include the assembler directives, the 8051 instruction mnemonics, implicit operand symbols, and the following assembly time operators that have alphanumeric symbols: EQ, NE, GT, GE, LT, LE, HIGH, LOW, MOD, SHR, SHL, NOT, AND, OR and XOR.The reserved implicit operands include the symbols A, AB, C, DPTR, PC, R0, R1, R2, R3, R4, R5, R6, R7, AR0, AR1, AR2, AR3, AR4, AR5, AR6 and AR7. These symbols are used primarily as instruction operands. Except for AB, C, DPTR or PC, these symbols can also be used to define other symbols (see EQU directive inChapter 5).The following are examples of illegal symbols with an explanation of why they are illegal: 1ST_VARIABLE (Symbols can not start with a number.)ALPHA# (Illegal character "#" in symbol.)MOV (8051 instruction mnemonic)LOW (Assembly operator)DATA (Assembly directive)2.3. LabelsLabels are special cases of symbols. Labels are used only before statements that have physical addresses associated with them. Examples of such statements are assembly language instructions, data storage directives (DB and DW), and data reservation directives (DS and DBIT). Labels must follow all the rules of symbol creation with the additional requirement that they be followed by a colon. The following are legal examples of label uses:TABLE_OF_CONTROL_CONSTANTS:DB 0,1,2,3,4,5 (Data storage)MESSAGE: DB 'HELP' (Data storage)START: MOV A,#23 (Assembly language instruction)2.4. Assembler ControlsAssembler controls are used to control where the Cross Assembler gets its input source file, where it puts the object file, and how it formats the listing file.Table 2-1 summarizes the assembler controls available. Refer to C hapter 6 for a detailed explanation of the controls.$DATE(date) Places date in page header $EJECT Places a form feed in listing $INCLUDE(file) Inserts file in source program $LIST Allows listing to be output $NOLIST Stops outputting the listing $MOD51 Uses 8051 predefined symbols $MOD52 Uses 8052 predefined symbols $MOD44 Uses 8044 predefined symbols $NOMOD No predefined symbols used $OBJECT(file) Places object output in file $NOOBJECT No object file is generated $PAGING Break output listing into pages $NOPAGING Print listing w/o page breaks $PAGELENGTH(n) No. of lines on a listing page $PAGEWIDTH(n) No. of columns on a listing page $PRINT(file) Places listing output in file $NOPRINT Listing will not be output $SYMBOLS Append symbol table to listing $NOSYMBOLS Symbol table will not be output $TITLE(string) Places string in page header Table 2-1: Summary of Cross Assembler ControlsAs can be seen in Table 2-1, all assembler controls are prefaced with a dollar sign ($). No spaces or tabs are allowed between the dollar sign and the body of the control. Also, only one control per line is permitted. However, comments can be on the same line as a control. The following are examples of assembler controls:$TITLE(8051 Program Ver. 1.0)$LIST$PAGEWIDTH(132)2.5. Assembler DirectivesAssembler directives are used to define symbols, reserve memory space, store values in program memory and switch between different memory spaces. There are also directives that set the location counter for the active segment and identify the end of the source file. Table 2-2 summarizes the assembler directivesavailable. These directives are fully explained in Chapter 5.EQU Define symbolDATA Define internal memory symbolIDATA Define indirectly addressed internal XDATA Define external memory symbolBIT Define internal bit memory symbol CODE Define program memory symbolDS Reserve bytes of data memoryDBIT Reserve bits of bit memoryDB Store byte values in program memory DW Store word values in program memory ORG Set segment location counterEND End of assembly language source file CSEG Select program memory spaceDSEG Select internal memory data space XSEG Select external memory data spaceISEG Select indirectly addressed internal BSEG Select bit addressable memory space USING Select register bankIF Begin conditional assembly blockELSE Alternative conditional assembly block ENDIF End conditional assembly blockTable 2-2: Summary of Cross Assembler DirectivesOnly one directive per line is allowed, however comments may be included. The following are examples of assembler directives:TEN EQU 10 RESET CODE 0 ORG 40962.6. 8051 Instruction MnemonicsThe standard 8051 Assembly Language Instruction mnemonics plus the generic C ALL and JMP instructions are recognized by the C ross Assembler and are summarized in Table 2-3. See hapter 4 for the operation of the individual instructions.ACALL Absolute callADD AddADDC Add with carryAJMP Absolute jumpANL Logical andCJNE Compare & jump if not equal CLR ClearCPL ComplementDA Decimal adjustDEC DecrementDIV DivideDJNZ Decrement&jump if not zero INC IncrementJB Jump if bit setJBC Jump & clear bit if bit set JC Jump if carry setJMP JumpJNB Jump if bit not setJNC Jump if carry not setJNZ Jump if accum. not zeroJZ Jump if accumulator zero LCALL Long callLJMP Long jump MOV MoveMOVC Move codeMOVX Move externalMUL MultiplyNOP No operationORL Inclusive orPOP Pop stackPUSH Push stackRET ReturnRETI Return from interrupt RL Rotate leftRLC Rotate left thru carry RR Rotate rightRRC Rotate right thru carry SETB Set bitSJMP Short jumpSUBB Subtract with borrow SWAP Swap nibblesXCH Exchange bytesXCHD Exchange digitsXRL Exclusive orCALL Generic callTable 2-3: 8051 Instructions and MnemonicsWhen the C ross Assembler sees a generic C ALL or JMP instruction, it will try to translate the instruction into its most byte efficient form. The Cross Assembler will translate a C ALL into one of two instructions (AC ALL or LC ALL) and it will translate a generic JMP into one of three instructions (SJMP, AJMP or LJMP). The choice of instructions is based on which one is most byte efficient. The generic CALL or JMP instructions saves the programmer the trouble of determining which form is best.However, generic C ALLs and JMPs do have their limitations. While the byte efficiency algorithm works well for previously defined locations, when the target location of the C ALL or JMP is a forward location (a location later on in the program), the assembler has no way of determining the best form of the instruction. In this case the C ross Assembler simply puts in the long version (LC ALL or LJMP) of the instruction, which may not be the most byte efficient. NOTE that the generic C ALLs and JMPs must not be used for the 751/752 device as LC ALL and LJMP are not legal instructions for those devices. Instead use ACALL and AJMP explicitly.For instructions that have operands, the operands must be separated from the mnemonic by at least one space or tab. For instructions that have multiple operands, each operand must be separated from the others by a comma.Two addressing modes require the operands to be preceded by special symbols to designate the addressing mode. The AT sign (@) is used to designate the indirect addressing mode. It is used primarily with Register 0 and Register 1 (R0, R1), but is can also be used with the DPTR in the MOVX and the Accumulator in MOVC and JMP @A+DPTR instructions. The POUND sign (#) is used to designate an immediate operand. It can be used to preface either a number or a symbol representing a number.A third symbol used with the operands actually specifies an operation. The SLASH (/) is used to specify that the contents of a particular bit address is to be complemented before the instruction operation. This is used with the ANL and ORL bit instructions.Only one assembly language instruction is allowed per line. Comments are allowed on the same line as an instruction, but only after all operands have been specified. The following are examples of instruction statements:START: LJMP INITMOV @R0,Serial_Port_BufferCJNE R0 , #TEN, INC_TENANL C,/START_FLAGCALL GET_BYTERET2.7. Bit AddressingThe period (.) has special meaning to the Cross Assembler when used in a symbol. It is used to explicitly specify a bit in a bit-addressable symbol. For example, it you wanted to specify the most significant bit in the Accumulator, you could write AC C.7, where AC C was previously defined as the Accumulator address. The same bit can also be selected using the physical address of the byte it's in.For example, the Accumulator's physical address is 224. The most significant bit of the Accumulator can be selected by specifying 224.7. If the symbol ONwas defined to be equal to the value 7, you could also specify the same bit by either ACC.ON or 224.ON.2.8. ASCII LiteralsPrintable characters from the ASCII characterset can be used directly as an immediate operand, or they can used to define symbols or store ASCII bytes in Program Memory. Such use of the ASCII character set is called ASCII literals. ASCII literals are identifiedby the apostrophe (') delimiter. The apostrophe itself can be used as an ASCII literal. In this case, use two apostrophes in a row. Below are examples of using ASCII literals.MOV A,#'m' ;Load A with 06DH (ASCII m)QUOTE EQU '''' ;QUOTE defined as 27H (ASCII single quote)DB '8051' ;Store in Program Memory2.9. CommentsComments are user defined character stringsthat are not processed by the C ross Assembler. A comment begins with a semicolon ( ; ) and ends at the carriage return/line feed pair that terminates theline. A comment can appear anywhere in a line, but it has to be the last field. The following are examples of comment lines:; Begin initialization routine here$TITLE(8051 Program Vers. 1.0) ;Place version number here TEN EQU 10 ;Constant2.10. The Location CounterThe C ross Assembler keeps a locationcounter for each of the five segments (code, internal data, external data, indirect internal data and bit data). Each location counter is initialized to zero and can be modified using Assembler Directives described in Chapter 5.The dollar sign ($) can be used to specify thecurrent value of the location counter of the active segment. The following are examples of how this can be used:JNB FLAG,$ ;Jump on self until flag is reset CPYRGHT: DB 'Copyright, 1983'CPYRGHT_LENGTH EQU $-CPYRGHT-1 ;Calculate length of copyright message2.11. Syntax SummarySince the Cross Assembler essentiallytranslates the source file on a line by line basis,certain rules must be followed to ensure the translation process is done correctly. First of all,since the C ross Assembler's line buffer is 256characters deep, there must always be a carriage return/line feed pair within the first 256 columns of the line.A legal source file line must begin with either acontrol, a symbol, a label, an instruction mnemonic, a directive, a comment or it can be null (just thecarriage return/line feed pair). Any other beginning to a line will be flagged as an error.While a legal source file line must begin withone of the above items, the item doesn't have to begin in the first column of the line. It only must be the first field of the line. Any number (including zero)of spaces or tabs, up to the maximum line size, may precede it.C omments can be placed anywhere, but theymust be the last field in any line.2.12. Numbers and OperatorsThe Cross Assembler accepts numbers in anyone of four radices: binary, octal, decimal and hexadecimal. To specify a number in a specific radix,the number must use the correct digits for the particular radix and immediately following the number with its radix designator. Decimal is the default radixand the use of its designator is optional. An hexadecimal number that would begin with a letter digit must be preceded by a 0 (zero) to distinguish it from a symbol. The internal representation of numbers is 16-bits, which limits the maximum number possible. Table 2-4 summarizes the radices available.Radix DesignatorLegal DigitsMax. Legal Number Binary B 0,11111111111111111BOctal O, Q0,1,2,3,4,5177777Q Decimal D, (default)0,1,2,3,4,5,6,7,8,965535D Hexadecimal H 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F 0FFFFHTable 2-4: Cross Assembler RadicesNo spaces or tabs are allowed between thenumber and the radix designator. The letter digits and radix designators can be in upper or lower case.The following examples list the decimal number 2957in each of the available radices:101110001101B (Binary)5615o or 5615Q (Octal)2957 or 2957D (Decimal)0B8DH, 0b8dh (Hexadecimal)When using radices with explicit bit symbols,the radix designator follows the byte portion of the address as shown in the following examples:0E0H.7 Bit seven of hexadecimal address 0E0200Q.ON Bit ON of octal address 200The C ross Assembler also allows assemblytime evaluation of arithmetic expressions up to thirty-two levels of embedded parentheses. All calculationsuse integer numbers and are done in sixteen bit precision.+ Addition Unary positive- Subtraction Unary negation (2's complement)* Multiplication/ Integer division (no remainder)MOD Modulus (remainder of integer division)SHR Shift right SHL Shift leftNOT Logical negation (1's complement)AND Logical and OR Inclusive or XOR Exclusive orLOW Low order 8-bits HIGH High order 8-bits EQ, = Relational equalNE, <> Relational not equal GT, > Relational greater thanGE, >= Relational greater than or equal LT, < Relational less thanLE, <= Relational less than or equal ( ) Parenthetical statementTable 2-5: Assembly Time OperationsThe relational operators test the specifiedvalues and return either a True or False. False is represented by a zero value, True is represented by a non zero value (the True condition actually returns a 16-bit value with every bit set; i.e., 0FFFFH). The relational operators are used primarily with theC onditional Assembly capability of the Cross Assembler.Table 2-5 lists the operations available whileTable 2-6 lists the operations precedence in descending order. Operations with higher precedence are done first. Operations with equal precedence are evaluated from left to right.(,)HIGH,LOW*,/,MOD,SHR,SHL +,-EQ,LT,GT,LE,GE,NE,=,<,>,<=,>=,<>NOT AND OR,XORTable 2-6: Operators Precedence2.13. Source File ListingThe source file listing displays the results of the C ross Assembler translation. Every line of the listing includes a copy of the original source line as well as a line number and the C ross Assembler translation. For example, in translating the following line taken from the middle of a source file:TRANS: MOV R7,#32 ;Set up pointer 002F 7920 152 TRANS: MOV R1,#32 ;Set up pointerThe '002F' is the current value of the location counter in hexadecimal. The '7920' is the translated instruction, also in hexadecimal. The '152' is the decimal line number of the current assembly. After the line number is a copy of the source file line that was translated.Another example of a line in the listing file is as follows:015B 13 =1 267 +2 RRC AHere we see two additional fields. The '=1' before the line number gives the current nesting of include files. The '+2' after the line number gives the current macro nesting. This line essentially says that this line comes from a second level nesting of a macro that is part of an include file.Another line format that is used in the listing is that of symbol definition. In this case the location counter value and translated instruction fields described above are replaced with the definition of the symbol. The following are examples of this:00FF 67 MAX_NUM EQU 255 REG 68 COUNTER EQU R7The '00FF' is the hexadecimal value of the symbol MAX_NUM. Again, '67'is the decimal line number of the source file and the remainder of the first line is a copy of the source file. In the second line above, the 'REG' shows that the symbol C OUNTER was defined to be a general purpose register.Optionally, a listing can have a page header that includes the name of the file being assembled, title of program, date and page number. The header and its fields are controlled by specific Assembler Controls (see Chapter 6).The default case is for a listing to be output as a file on the default drive with the same name as the entered source file and an extension of .LST. For example, if the source file name was PROGRAM.ASM, the listing file would be called PROGRAM.LST. Or if the source file was called MODULE1, the listing file would be stored as MODULE1.LST. The default can be changed using the $NOPRINT and $PRINT() Assembler C ontrols (see Chapter 6).2.14. Object FileThe 8051 C ross Assembler also creates a machine language object file. The format of the object file is standard Intel Hexadecimal. This Hexadecimal file can be used to either program EPROM’s using standard PROM Programmers for prototyping, or used to pattern masked ROMs for production.The default case is for the object file to be output on the default drive with the same name as the first source file and an extension of .HEX. For example, if the source file name was PROGRAM.ASM, the object file would be called PROGRAM.HEX. Or if the source file was called MODULE1, the object file would be stored as MODULE1.HEX. The default can be changed using the $NOOBJECT and $OBJECT() Assembler Controls (see Chapter 6).。
8051 Microcontroller Instruction Set
Notes on Data Addressing ModesRn - Working register R0-R7direct - 128 internal RAM locations, any l/O port, control or status register@Ri - Indirect internal or external RAM location addressed by register R0 or R1#data - 8-bit constant included in instruction#data 16 - 16-bit constant included as bytes 2 and 3 of instructionbit - 128 software flags, any bitaddressable l/O pin, control or status bitA - AccumulatorNotes on Program Addressing Modesaddr16 - Destination address for LCALL and LJMP may be anywhere within the 64-Kbyte program memory address space.addr11 - Destination address for ACALL and AJMP will be within the same 2-Kbyte page of program memory as the first byte of the following instruction.rel - SJMP and all conditional jumps include an 8 bit offset byte. Range is +127/–128 bytes relative to the first byte of the following instruction.All mnemonics copyrighted: © Intel Corporation 1980ACALL addr11Function: Absolute callDescription: ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the followinginstruction, then pushes the 16-bit result onto the stack (low-order byte first) andincrements the stack pointer twice. The destination address is obtained bysuccessively concatenating the five high-order bits of the incremented PC, op codebits 7-5, and the second byte of the instruction. The subroutine called musttherefore start within the same 2K block of program memory as the first byte of theinstruction following ACALL. No flags are affected.Example: Initially SP equals 07H. The label ”SUBRTN” is at program memory location 0345H.After executing the instructionACALL SUBRTNat location 0123H, SP will contain 09H, internal RAM location 08H and 09H willcontain 25H and 01H, respectively, and the PC will contain 0345H.Operation: ACALL(PC) ← (PC) + 2(SP) ← (SP) + 1((SP)) ← (PC7-0)(SP) ← (SP) + 1((SP)) ← (PC15-8)(PC10-0) ← page addressEncoding: a10 a9 a8 1 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0Bytes: 2Cycles: 2ADD A, <src-byte>Function: AddDescription: ADD adds the byte variable indicated to the accumulator, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively, if there is acarry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers,the carry flag indicates an overflow occurred.OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 butnot out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicatesa negative number produced as the sum of two positive operands, or a positive sumfrom two negative operands.Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.Example: The accumulator holds 0C3H (11000011B) and register 0 holds 0AA H (10101010B).The instructionADD A,R0will leave 6D H (01101101B) in the accumulator with the AC flag cleared and boththe carry flag and OV set to 1.ADD A,RnOperation: ADD(A) ← (A) + (Rn)Encoding: 0 0 1 0 1 r r rBytes: 1Cycles: 1ADD A,directOperation: ADD(A) ← (A) + (direct)Encoding: 0 0 1 0 0 1 0 1 direct addressBytes: 2Cycles: 1ADD A, @RiOperation: ADD(A) ← (A) + ((Ri))Encoding: 0 0 1 0 0 1 1 iBytes: 1Cycles: 1ADD A, #dataOperation: ADD(A) ← (A) + #dataEncoding: 0 0 1 0 0 1 0 0 immediate data Bytes: 2Cycles: 1ADDC A, < src-byte>Function: Add with carryDescription: ADDC simultaneously adds the byte variable indicated, the carry flag and the accumulator contents, leaving the result in the accumulator. The carry and auxiliarycarry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and clearedotherwise. When adding unsigned integers, the carry flag indicates an overflowoccurred.OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 butnot out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicatesa negative number produced as the sum of two positive operands or a positive sumfrom two negative operands.Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.Example: The accumulator holds 0C3H (11000011B) and register 0 holds 0AA H (10101010B) with the carry flag set. The instructionADDC A,R0will leave 6E H (01101110B) in the accumulator with AC cleared and both the carryflag and OV set to 1.ADDC A,RnOperation: ADDC(A) ← (A) + (C) + (Rn)Encoding: 0 0 1 1 1 r r rBytes: 1Cycles: 1ADDC A,directOperation: ADDC(A) ← (A) + (C) + (direct)Encoding: 0 0 1 1 0 1 0 1 direct addressBytes: 2Cycles: 1ADDC A, @RiOperation: ADDC(A) ← (A) + (C) + ((Ri))Encoding: 0 0 1 1 0 1 1 iBytes: 1Cycles: 1ADDC A, #dataOperation: ADDC(A) ← (A) + (C) + #dataEncoding: 0 0 1 1 0 1 0 0 immediate data Bytes: 2Cycles: 1AJMP addr11Function: Absolute jumpDescription: AJMP transfers program execution to the indicated address, which is formed at run-time by concatenating the high-order five bits of the PC (after incrementing the PCtwice), op code bits 7-5, and the second byte of the instruction. The destination musttherefore be within the same 2K block of program memory as the first byte of theinstruction following AJMP.Example: The label ”JMPADR” is at program memory location 0123H. The instruction AJMP JMPADRis at location 0345H and will load the PC with 0123H.Operation: AJM P(PC) ← (PC) + 2(PC10-0) ← page addressEncoding: a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0Bytes: 2Cycles: 2ANL <dest-byte>, <src-byte>Function: Logical AND for byte variablesDescription: ANL performs the bitwise logical AND operation between the variables indicated and stores the results in the destination variable. No flags are affected.The two operands allow six addressing mode combinations. When the destinationis a accumulator, the source can use register, direct, register-indirect, or immediateaddressing; when the destination is a direct address, the source can be theaccumulator or immediate data.Note:When this instruction is used to modify an output port, the value used as the originalport data will be read from the output data latch, not the input pins.Example: If the accumulator holds 0C3H (11000011B) and register 0 holds 0AA H(10101010B) then the instructionANL A,R0will leave 81H (10000001B) in the accumulator.When the destination is a directly addressed byte, this instruction will clearcombinations of bits in any RAM location or hardware register. The mask bytedetermining the pattern of bits to be cleared would either be a constant containedin the instruction or a value computed in the accumulator at run-time.The instructionANL P1, #01110011Bwill clear bits 7, 3, and 2 of output port 1.ANL A,RnOperation: ANL(A) ← (A) ∧ (Rn)Encoding: 0 1 0 1 1 r r rBytes: 1Cycles: 1ANL A,directOperation: ANL(A) ← (A) ∧ (direct)Encoding: 0 1 0 1 0 1 0 1 direct address Bytes: 2Cycles: 1ANL A, @RiOperation: ANL(A) ← (A) ∧ ((Ri))Encoding: 0 1 0 1 0 1 1 iBytes: 1Cycles: 1ANL A, #dataOperation: ANL(A) ← (A) ∧ #dataEncoding: 0 1 0 1 0 1 0 0 immediate data Bytes: 2Cycles: 1ANL direct,AOperation: ANL(direct) ← (direct) ∧ (A)Encoding: 0 1 0 1 0 1 0 1 direct address Bytes: 2Cycles: 1ANL direct, #dataOperation: ANL(direct) ← (direct) ∧ #dataEncoding: 0 1 0 1 0 0 1 1 direct address immediate data Bytes: 3Cycles: 2ANL C, <src-bit>Function: Logical AND for bit variablesDescription: If the Boolean value of the source bit is a logic 0 then clear the carry flag; otherwise leave the carry flag in its current state. A slash (”/” preceding the operand in theassembly language indicates that the logical complement of the addressed bit isused as the source value, but the source bit itself is not affected. No other flags areaffected.Only direct bit addressing is allowed for the source operand.Example: Set the carry flag if, and only if, P1.0 = 1, ACC.7 = 1, and OV = 0:MOV C,P1.0 ; Load carry with input pin stateANL C,ACC.7 ; AND carry with accumulator bit 7ANL C,/OV ; AND with inverse of overflow flagANL C,bitOperation: ANL(C) ← (C) ∧ (bit)Encoding: 1 0 0 0 0 0 1 0 bit addressBytes: 2Cycles: 2ANL C,/bitOperation: ANL(C) ← (C) ∧ ¬ (bit)Encoding: 1 0 1 1 0 0 0 0 bit addressBytes: 2Cycles: 2CJNE <dest-byte >, < src-byte >, relFunction: Compare and jump if not equalDescription: CJNE compares the magnitudes of the tirst two operands, and branches if their values are not equal. The branch destination is computed by adding the signedrelative displacement in the last instruction byte to the PC, after incrementing thePC to the start of the next instruction. The carry flag is set if the unsigned integervalue of <dest-byte> is less than the unsigned integer value of <src-byte>;otherwise, the carry is cleared. Neither operand is affected.The first two operands allow four addressing mode combinations: the accumulatormay be compared with any directly addressed byte or immediate data, and anyindirect RAM location or working register can be compared with an immediateconstant.Example: The accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequenceCJNE R7, # 60H, NOT_EQ; . . . . . . . . ; R7 = 60HNOT_EQ JC REQ_LOW ; If R7 < 60H; . . . . . . . . ; R7 > 60Hsets the carry flag and branches to the instruction at label NOT_EQ. By testing thecarry flag, this instruction determines whether R7 is greater or less than 60H.If the data being presented to port 1 is also 34H, then the instructionWAIT: CJNE A,P1,WAITclears the carry flag and continues with the next instruction in sequence, since theaccumulator does equal the data read from P1. (If some other value was input onP1, the program will loop at this point until the P1 data changes to 34H).CJNE A,direct,relOperation: (PC) ← (PC) + 3if (A) < > (direct)then (PC) ← (PC) + relative offsetif (A) < (direct)then (C) ←1else (C) ← 0Encoding: 1 0 1 1 0 1 0 1 direct address rel. address Bytes: 3Cycles: 2CJNE A, #data,relOperation: (PC) ← (PC) + 3if (A) < > datathen (PC) ← (PC) + relative offsetif (A) ← datathen (C) ←1else (C) ← 0Encoding: 1 0 1 1 0 1 0 0 immediate data rel. address Bytes: 3Cycles: 2CJNE RN, #data, relOperation: (PC) ← (PC) + 3if (Rn) < > datathen (PC) ← (PC) + relative offsetif (Rn) < datathen (C) ← 1else (C) ← 0Encoding: 1 0 1 1 1 r r r immediate data rel. address Bytes: 3Cycles: 2CJNE @Ri, #data,relOperation: (PC) ← (PC) + 3if ((Ri)) < > datathen (PC) ← (PC) + relative offsetif ((Ri)) < datathen (C) ← 1else (C) ← 0Encoding: 1 0 1 1 0 1 1 i immediate data rel. address Bytes: 3Cycles: 2CLR AFunction: Clear accumulatorDescription: The accumulator is cleared (all bits set to zero). No flags are affected. Example: The accumulator contains 5C H (01011100B). The instructionCLR Awill leave the accumulator set to 00H (00000000B).Operation: CLR(A) ← 0Encoding: 1 1 1 0 0 1 0 0Bytes: 1Cycles: 1CLR bitFunction: Clear bitDescription: The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the carry flag or any directly addressable bit.Example: Port 1 has previously been written with 5D H (01011101B). The instruction CLR P1.2will leave the port set to 59H (01011001B).CLR COperation: CLR(C) ← 0Encoding: 1 1 0 0 0 0 1 1Bytes: 1Cycles: 1CLR bitOperation: CLR(bit) ← 0Encoding: 1 1 0 0 0 0 1 0 bit addressBytes: 2Cycles: 1CPL AFunction: Complement accumulatorDescription: Each bit of the accumulator is logically complemented (one’s complement). Bits which previously contained a one are changed to zero and vice versa. No flags areaffected.Example: The accumulator contains 5C H (01011100B). The instructionCPL Awill leave the accumulator set to 0A3H (10100011 B).Operation: CPL(A) ←¬ (A)Encoding: 1 1 1 1 0 1 0 0Bytes: 1Cycles: 1CPL bitFunction: Complement bitDescription: The bit variable specified is complemented. A bit which had been a one is changed to zero and vice versa. No other flags are affected. CPL can operate on the carry orany directly addressable bit.Note:When this instruction is used to modify an output pin, the value used as the originaldata will be read from the output data latch, not the input pin.Example: Port 1 has previously been written with 5D H (01011101B). The instruction sequence CPL P1.1CPL P1.2will leave the port set to 5B H (01011011B).CPL COperation: CPL(C) ←¬ (C)Encoding: 1 0 1 1 0 0 1 1Bytes: 1Cycles: 1CPL bitOperation: CPL(bit) ←¬ (bit)Encoding: 1 0 1 1 0 0 1 0 bit addressBytes: 2Cycles: 1DA AFunction: Decimal adjust accumulator for additionDescription: DA A adjusts the eight-bit value in the accumulator resulting from the earlier addition of two variables (each in packed BCD format), producing two four-bit digits.Any ADD or ADDC instruction may have been used to perform the addition.If accumulator bits 3-0 are greater than nine (xxxx1010-xxxx1111), or if the AC flagis one, six is added to the accumulator producing the proper BCD digit in the low-order nibble. This internal addition would set the carry flag if a carry-out of the low-order four-bit field propagated through all high-order bits, but it would not clear thecarry flag otherwise.If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxxx-1111xxxx), these high-order bits are incremented by six, producing the proper BCDdigit in the high-order nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but wouldn’t clear the carry. The carry flag thus indicatesif the sum of the original two BCD variables is greater than 100, allowing multipleprecision decimal addition. OV is not affected.All of this occurs during the one instruction cycle. Essentially; this instructionperforms the decimal conversion by adding 00H, 06H, 60H, or 66H to theaccumulator, depending on initial accumulator and PSW conditions.Note:DA A cannot simply convert a hexadecimal number in the accumulator to BCDnotation, nor does DA A apply to decimal subtraction.Example: The accumulator holds the value 56H (01010110B) representing the packed BCD digits of the decimal number 56. Register 3 contains the value 67H (01100111B)representing the packed BCD digits of the decimal number 67. The carry flag is set.The instruction sequenceADDC A,R3DA Awill first perform a standard two’s-complement binary addition, resulting in the value0BE H (10111110B) in the accumulator. The carry and auxiliary carry flags will becleared.The decimal adjust instruction will then alter the accumulator to the value 24H(00100100B), indicating the packed BCD digits of the decimal number 24, the low-order two digits of the decimal sum of 56, 67, and the carry-in. The carry flag will beset by the decimal adjust instruction, indicating that a decimal overflow occurred.The true sum 56, 67, and 1 is 124.BCD variables can be incremented or decremented by adding 01H or 99H. If theaccumulator initially holds 30H (representing the digits of 30 decimal), then theinstruction sequenceADD A, #99HDA Awill leave the carry set and 29H in the accumulator, since 30 + 99 = 129. The low-order byte of the sum can be interpreted to mean 30 – 1 = 29.Operation: DAcontents of accumulator are BCDif [[(A3-0) > 9] ∨ [(AC) = 1]]then (A3-0) ← (A3-0) + 6andif [[(A7-4) > 9] ∨ [(C) = 1]]then (A7-4) ← (A7-4) + 6Encoding: 1 1 0 1 0 1 0 0Bytes: 1Cycles: 1DEC byteFunction: DecrementDescription: The variable indicated is decremented by 1. An original value of 00H will underflow to 0FF H. No flags are affected. Four operand addressing modes are allowed:accumulator, register, direct, or register-indirect.Note:When this instruction is used to modify an output port, the value used as the originalport data will be read from the output data latch, not the input pins.Example: Register 0 contains 7F H (01111111B). Internal RAM locations 7E H and 7F H contain 00H and 40H, respectively. The instruction sequenceDEC @R0DEC R0DEC @R0will leave register 0 set to 7E H and internal RAM locations 7E H and 7F H set to0FF H and 3F H.DEC AOperation: DEC(A) ← (A) – 1Encoding: 0 0 0 1 0 1 0 0Bytes: 1Cycles: 1DEC RnOperation: DEC(Rn) ← (Rn) – 1Encoding: 0 0 0 1 1 r r rBytes: 1Cycles: 1DEC directOperation: DEC(direct) ← (direct) – 1Encoding: 0 0 0 1 0 1 0 1 direct address Bytes: 2Cycles: 1DEC @RiOperation: DEC((Ri)) ← ((Ri)) – 1Encoding: 0 0 0 1 0 1 1 iBytes: 1Cycles: 1DIV ABFunction: DivideDescription: DIV AB divides the unsigned eight-bit integer in the accumulator by the unsignedeight-bit integer in register B. The accumulator receives the integer part of thequotient; register B receives the integer remainder. The carry and OV flags will becleared.Exception: If B had originally contained 00H , the values returned in the accumulatorand B register will be undefined and the overflow flag will be set. The carry flag iscleared in any case.Example: The accumulator contains 251 (0FB H or 11111011B) and B contains 18 (12H or00010010B). The instructionDIV ABwill leave 13 in the accumulator (0D H or 00001101 B) and the value 17 (11H or00010001B) in B, since 251 = (13x18) + 17. Carry and OV will both be cleared.Operation: DIV(A15-8)(B7-0) Bytes: 1Cycles: 4Encoding: 1 0 0 0 0 1 0 0← (A) / (B)DJNZ <byte>, < rel-addr>Function: Decrement and jump if not zeroDescription: DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original valueof 00H will underflow to 0FF H. No flags are affected. The branch destination wouldbe computed by adding the signed relative-displacement value in the last instructionbyte to the PC, after incrementing the PC to the first byte of the following instruction.The location decremented may be a register or directly addressed byte.Note:When this instruction is used to modify an output port, the value used as the originalport data will be read from the output data latch, not the input pins.Example: Internal RAM locations 40H, 50H, and 60H contain the values, 01H, 70H, and 15H, respectively. The instruction sequenceDJNZ 40H,LABEL_1DJNZ 50H,LABEL_2DJNZ 60H,LABEL_3will cause a jump to the instruction at label LABEL_2 with the values 00H, 6F H, and15H in the three RAM locations. The first jump was not taken because the result waszero.This instruction provides a simple way of executing a program loop a given numberof times, or for adding a moderate time delay (from 2 to 512 machine cycles) with asingle instruction. The instruction sequenceMOV R2, #8TOGGLE:CPL P1.7DJNZ R2,TOGGLEwill toggle P1.7 eight times, causing four output pulses to appear at bit 7 of outputport 1. Each pulse will last three machine cycles; two for DJNZ and one to alter thepin.DJNZ Rn,relOperation: DJNZ(PC) ← (PC) + 2(Rn) ← (Rn) – 1if (Rn) > 0 or (Rn) < 0then (PC) ← (PC) + relEncoding: 1 1 0 1 1 r r r rel. addressBytes: 2Cycles: 2DJNZ direct,relOperation: DJNZ(PC) ← (PC) + 2(direct) ← (direct) – 1if (direct) > 0 or (direct) < 0then (PC) ← (PC) + relEncoding: 1 1 0 1 0 1 0 1 direct address rel. address Bytes: 3Cycles: 2INC <byte>Function: IncrementDescription: INC increments the indicated variable by 1. An original value of 0FF H will overflow to 00H. No flags are affected. Three addressing modes are allowed: register, direct,or register-indirect.Note:When this instruction is used to modify an output port, the value used as the originalport data will be read from the output data latch, not the input pins.Example: Register 0 contains 7E H (01111110B). Internal RAM locations 7E H and 7F H contain 0FF H and 40H, respectively. The instruction sequenceINC @R0INC R0INC @R0will leave register 0 set to 7F H and internal RAM locations 7E H and 7F H holding(respectively) 00H and 41H.INC AOperation: INC(A) ← (A) + 1Encoding: 0 0 0 0 0 1 0 0Bytes: 1Cycles: 1INC RnOperation: INC(Rn) ← (Rn) + 1Encoding: 0 0 0 0 1 r r rBytes: 1Cycles: 1INC directOperation: INC(direct) ← (direct) + 1Encoding: 0 0 0 0 0 1 0 1 direct address Bytes: 2Cycles: 1INC @RiOperation: INC((Ri)) ← ((Ri)) + 1Encoding: 0 0 0 0 0 1 1 iBytes: 1Cycles: 1INC DPTRFunction: Increment data pointerDescription: Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 216) is performed;an overflow of the low-order byte of the data pointer (DPL) from 0FF H to 00H willincrement the high-order byte (DPH). No flags are affected.This is the only 16-bit register which can be incremented.Example: Registers DPH and DPL contain 12H and 0FE H, respectively. The instruction sequenceINC DPTRINC DPTRINC DPTRwill change DPH and DPL to 13H and 01H.Operation: INC(DPTR) ← (DPTR) + 1Encoding: 1 0 1 0 0 0 1 1Bytes: 1Cycles: 2JB bit,relFunction: Jump if bit is setDescription: If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signedrelative-displacement in the third instruction byte to the PC, after incrementing thePC to the first byte of the next instruction. The bit tested is not modified. No flagsare affected.Example: The data present at input port 1 is 11001010B. The accumulator holds 56 (01010110B). The instruction sequenceJB P1.2,LABEL1JB ACC.2,LABEL2will cause program execution to branch to the instruction at label LABEL2. Operation: JB(PC) ← (PC) + 3if (bit) = 1then (PC) ← (PC) + relEncoding: 0 0 1 0 0 0 0 0 bit address rel. addressBytes: 3Cycles: 2JBC bit,relFunction: Jump if bit is set and clear bitDescription: If the indicated bit is one, branch to the address indicated; otherwise proceed with the next instruction. In either case, clear the designated bit. The branch destinationis computed by adding the signed relative displacement in the third instruction byteto the PC, after incrementing the PC to the first byte of the next instruction. No flagsare affected.Note:When this instruction is used to test an output pin, the value used as the originaldata will be read from the output data latch, not the input pin.Example: The accumulator holds 56H (01010110B). The instruction sequenceJBC ACC.3,LABEL1JBC ACC.2,LABEL2will cause program execution to continue at the instruction identified by the labelLABEL2, with the accumulator modified to 52H (01010010B).Operation: JBC(PC) ← (PC) + 3if (bit) = 1then (bit) ← 0(PC) ← (PC) + relEncoding: 0 0 0 1 0 0 0 0 bit address rel. addressBytes: 3Cycles: 2JC relFunction: Jump if carry is setDescription: If the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PCtwice. No flags are affected.Example: The carry flag is cleared. The instruction sequenceJC LABEL1CPL CJC LABEL2will set the carry and cause program execution to continue at the instructionidentified by the label LABEL2.Operation: JC(PC) ← (PC) + 2if (C) = 1then (PC) ← (PC) + relEncoding: 0 1 0 0 0 0 0 0 rel. addressBytes: 2Cycles: 2JMP @A + DPTRFunction: Jump indirectDescription: Add the eight-bit unsigned contents of the accumulator with the sixteen-bit data pointer, and load the resulting sum to the program counter. This will be the addressfor subsequent instruction fetches. Sixteen-bit addition is performed (modulo 216): acarry-out from the low-order eight bits propagates through the higher-order bits.Neither the accumulator nor the data pointer is altered. No flags are affected. Example: An even number from 0 to 6 is in the accumulator. The following sequence of instructions will branch to one of four AJMP instructions in a jump table starting atJMP_TBL:MOV DPTR, #JMP_TBLJMP @A + DPTRJMP_TBL:AJMP LABEL0AJMP LABEL1AJMP LABEL2AJMP LABEL3If the accumulator equals 04H when starting this sequence, execution will jump tolabel LABEL2. Remember that AJMP is a two-byte instruction, so the jumpinstructions start at every other address.Operation: JMP(PC) ← (A) + (DPTR)Encoding: 0 1 1 1 0 0 1 1Bytes: 1Cycles: 2JNB bit,relFunction: Jump if bit is not setDescription: If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signedrelative-displacement in the third instruction byte to the PC, after incrementing thePC to the first byte of the next instruction. The bit tested is not modified. No flagsare affected.Example: The data present at input port 1 is 11001010B. The accumulator holds 56H (01010110B). The instruction sequenceJNB P1.3,LABEL1JNB ACC.3,LABEL2will cause program execution to continue at the instruction at label LABEL2. Operation: JNB(PC) ← (PC) + 3if (bit) = 0then (PC) ← (PC) + rel.Encoding: 0 0 1 1 0 0 0 0 bit address rel. addressBytes: 3Cycles: 2JNC relFunction: Jump if carry is not setDescription: If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signedrelative-displacement in the second instruction byte to the PC, after incrementingthe PC twice to point to the next instruction. The carry flag is not modified. Example: The carry flag is set. The instruction sequenceJNC LABEL1CPL CJNC LABEL2will clear the carry and cause program execution to continue at the instructionidentified by the label LABEL2.Operation: JNC(PC) ← (PC) + 2if (C) = 0then (PC) ← (PC) + relEncoding: 0 1 0 1 0 0 0 0 rel. addressBytes: 2Cycles: 2JNZ relFunction: Jump if accumulator is not zeroDescription: If any bit of the accumulator is a one, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding thesigned relative-displacement in the second instruction byte to the PC, afterincrementing the PC twice. The accumulator is not modified. No flags are affected. Example: The accumulator originally holds 00H. The instruction sequenceJNZ LABEL1INC AJNZ LABEL2will set the accumulator to 01H and continue at label LABEL2.Operation: JNZ(PC) ← (PC) + 2if (A) ≠ 0then (PC) ← (PC) + rel.Encoding: 0 1 1 1 0 0 0 0 rel. addressBytes: 2Cycles: 2。
8051_Instruction_Set
As you can see from this chart the number of SFRs has grown significantly over the original 8051. The SFRs are used as the configuration registers for peripherals within the device as well as control functions for the core. For example, the P0MDIN is a special function register responsible for I/O pin control. The PSW is the Program Status Word and controls register banking and arithmetic bits like carry and overflow. All SFRs are accessed via the direct addressing mode. Indirect addressing to these memory locations access the upper RAM portion. In C, abbreviated SFR names are defined in the family specific header files. For example, the F900 SFRs are in the “C8051F930_defs.h” and “compiler_defs.h” header files.
* Related to program branching instructions
8
There are 8 addressing modes. The addressing mode determines how the operand byte is selected. The direct and indirect addressing modes are used to distinguish between the SFR space and data memory space. The relative instructions are based on the value of the program counter. The absolute instructions operate in the same manner. Indexed instructions use a calculation to generate the address used as part of the instruction.
单片机全面介绍(8051,avr,pic,msp430,arm,dsp)
1、内部 ROM 读取时，PSEN 不动作； 2、外部 ROM 读取时，在每个机器周期会动作两次； 3、外部 RAM 读取时，两个 PSEN 脉冲被跳过不会输出； 4、外接 ROM 时，与 ROM 的 OE 脚相接。 参见图 2—（8051 扩展 2KB EEPROM 电路，在图中 PSEN 与扩展 ROM 的 OE 脚相 接） EA/VPP 访问和序存储器控制信号 1、接高电平时： CPU 读取内部程序存储器（ROM） 扩展外部 ROM：当读取内部程序存储器超过 0FFFH（8051）1FFFH（8052）时自动 读取外部 ROM。 2、接低电平时：CPU 读取外部程序存储器（ROM）。 在前面的学习中我们已知道， 8031 单片机内部是没有 ROM 的，那么在应用 8031 单片机时，这个脚是一直接低电平的。 3、8751 烧写内部 EPROM 时，利用此脚输入 21V 的烧写电压。
ALE/PROG 地址锁存控制信号：在系统扩展时，ALE 用于控制把 P0 口的输出低 8 位 地址送锁存器锁存起来，以实现低位地址和数据的隔离。（在后面关于扩展的课程中我们就 会看到 8051 扩展 EEPROM 电路，在图中 ALE 与 74LS373 锁存器的 G 相连接，当 CPU 对外部进行存取时，用以锁住地址的低位地址，即 P0 口输出。ALE 有可能是高电平也有可 能是低电平，当 ALE 是高电平时，允许地址锁存信号，当访问外部存储器时，ALE 信号负 跳变（即由正变负）将 P0 口上低 8 位地址信号送入锁存器。当 ALE 是低电平时，P0 口上 的内容和锁存器输出一致。关于锁存器的内容，我们稍后也会介绍。
8051单片机的引脚及结构
P2 P1 P2
P1
P2 P1
P2
P1 P2 P1
P2 P1
P2
P1
P2 P1
P2 P1
P2 P1
P2
(OSC)
振荡周期
时钟周期
MCS-51单片机各种周期的相互关系
1．振荡周期：为单片机提供时钟信号的振荡源 的周期。
2．时钟周期：是振荡源信号经二分频后形成的 时钟脉冲信号。
3．机器周期：通常将完成一个基本操作所需的 时间称为机器周期。
片外RAM： 最大范围：0000H～FFFFH，
64KB；用指令MOVX访问。 片内RAM：
最大范围：00H～FFH， 256B；用指令MOV访问。又分 为两部分：低128B（00～7FH） 为真正的RAM区，高128B （80～FFH）为特殊功能寄存器 （SFR）区。如右图所示。
3．特殊功能寄存器（SFR）
1、复位方式
系统开始运行和重新启动靠复位电路来实现，这种工作 方式为复位方式。
单片机在开机时都需要复位，以便CPU及其他功能部件 都处于一种确定的初始状态，并从这个状态开始工作。
MCS-51单片机在RST引脚产生两个机器周期（即24个 时钟周期）以上的高电平即可实现复位。
复位电路有两种：上电自动复位和上电/按键手动复位， 如下图所示。
1．HMOS单片机的掉电保护
当VCC突然掉电时，单片机通过中断将必须保护的数据送 入内部RAM，备用电源VPD可以维持内部RAM中的数据不丢失。
2．CHMOS单片机的节电方式
CHMOS 型 单 片 机 是 一 种 低 功 耗 器 件 ， 正 常 工 作 时 电 流 为 11～22mA，空闲状态时为1.7～5mA，掉电方式为5～50A。因 此，CHMOS型单片机特别适用于低功耗应用场合，它的空闲方 式和掉电方式都是由电源控制寄存器PCON中相应的位来控制。
经典：7种寻址方式
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的确，这两条指令执行的结果是完全相同的， 都是将00H单元中的内容送到A中去，但是执行的过 程不同，执行第一条指令需要2个机器周期，而第二 条则只需要1个机器周期，第一条指令变成最终的目 标码要两个字节（E5H 00H），而第二条则只要一个 字节（E8H）就可以了。
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3.2.3 寄存器寻址
Register Addressing
对选定的工作寄存器R0～R7、累加器A、通用寄存器B、 地址寄存器DPTR中的数进行操作。 例：MOV A，R0；将R0工作寄存器中的数据送到累加器A中去。
MOV AL，BL （8086CPU的寄存器寻址方式）
提一个问题：我们知道，工作寄存器就是内存单元 的一部分，如果我们选择工作寄存器组0，则R0就 是RAM的00H单元，那么这样一来，MOV A，00H 和 MOV A，R0不就没什么区别了吗？
寄存器间接寻址
变址寻址 相对寻址
位寻址
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寻址空间（操作数存放空间） 程序存储器
片内RAM低128字节、SFR 工作寄存器R0～R7,A,B,DPTR 片内RAM:@R0,@R1,SP 片外RAM:@R0 ,@R1,@DPTR 程序存储器:@A+PC,@A+DPTR 程序存储器256字节范围内:PC+偏移量 片内RAM的位寻址区(20H～2FH字节地址) 某些可位寻址的SFR
第三章 MCS-51指令系统 Instruction Set
§3.1 概述
7种寻址方式，111条指令
字节数
单字节指令：49条 双字节指令：45条 三字节指令：17条
运算速度
单片机红外遥控外文翻译
Infrared Remote And Chips Are IntroducedPeople's eyes can see the visible wavelength from long to short according to the arrangement, in order to red, orange, yellow, green, green, blue, violet. One of the red wavelengths for 0.62 ~ 0.76 mount, Purple is 0.38 wavelength range ~ mount. Purple is shorter than the wavelength of light called ultraviolet ray, red wavelengths of light is longer than that of infrared light. Infrared remote control is to use wavelength for 0.76 ~ 1.5 mount between the near infrared to transfer control signal.Commonly used infrared remote control system of general points transmit and receive two parts. The main component part for the launch of infrared light emitting diode. It is actually a special light emitting diode, due to its internal material differs from ordinary light emitting diode, resulting in its ends on certain voltage, it is a rather infrared light. Use of infrared light emitting diode the infrared wavelengths, for 940nm appearance and ordinary, just the same light emitting diode five different colors. Infrared light emitting diode generally have black and blue, transparent three colors. Judgment of infrared light emitting diode and judgment method, using a millimeter to ordinary diode electric block measure of infrared light emitting diode, reverse resistance. The infrared light emitting diode luminescence efficiency to use special instrument to measure precise, and use only spare conditions to pull away from roughly judgment. Receiving partof infrared receiving tube is a photosensitive diode.In actual application of it receiving diode to reverse bias, it can work normally, i.e., the infrared receiving circuit application in diode is used to reverse, higher sensitivity. Infrared receiving diode usually have two round and rectangular. Due to the power of infrared light emitting diode (or less commonly 100mW), so ir receiving diode received signals is weak, so will increase high-gain ones.the amplifier circuit.In common CX20106A, etc. PC1373H moon infrared receiving special amplifier circuit. In recent years both amateur or formal products, mostly using infrared receiving head finished. The head of infrared receiving product packages generally has two kinds: one kind USES sheet shielding, A kind of plastic packaging. There are three pin, namely the power is (VDD), power negative (GND) and data output (VO or OUT). Infrared receiving head foot arrangement for types varied, manufacturer's instructions. Finished the advantages of infrared receiving head is not in need of sophisticated debugging and shell screen, use rise as a transistor, very convenient. But when used in the infrared receiving attention finished first carrier frequency.Infrared remote common carrier frequency for 38kHz, this is transmitted by using 455kHz Tao Zhen to decide. At the launch of crystals were integer frequency, frequency coefficients, so commonly 12, so 455kHz ÷ 12 hundredth kHz 38kHz hundredth 379,000. Some remote control system adopts 36kHz, 56kHz, etc. general 40kHz launched by the crystals of oscillation frequency to decide.Infrared remote characteristic is not influence the surrounding environment and does not interfere with other electric equipment. Due to its cannot penetrate walls, so the room can use common household appliance of remote control without mutual interference, Circuit testing is simple, as long as given circuit connection, generally does not need any commissioning can work, Decoding easily, can undertake multiple remote control. Because each manufacturer produces a great deal of infrared remote application-specific integrated circuit, when need press diagram so jip. Therefore, the infrared remote now in household appliances, indoor close (less than 10 meters) in the remote control is widely used.Multiple infrared remote control system of infrared emission control buttons, there are many parts general representative of different control function. When pressed a button, correspondingly in the receiver with different output.Receiving the output state can be roughly divided into pulse, level, self-locking and interlock, data five forms. "The pulse output is according to launch" when the button, the receiver output terminals output corresponding "effective", a pulse width 100ms in general. "Level" refers to the output launch press button, the receiver output corresponding output level ", "effective transmit to loosen the receiver" level "disappears. This "effective pulse" and "effective", may be of high level is low, and may also depend on the output corresponding static state, such as feet for low, static "high" for effective, As for the static, "low" high effective. In most cases, "high" for effective. "Since the lock" refersto launch the output of each time you press the button, a receiver output corresponding change, namely originally a state for high level into a low level, originally for low level into high level. The output power switch and mute as control etc. Sometimes also called the output form for "invert". "The interlock" refers to multiple outputs each output, at the same time only one output. The TV sets of this case is selected, the other is like the light and sound input speed, etc."Data" refers to launch the output some key, use a few output form a binary number, to represent different keystroke.Normally, the receiver except a few data output, but also a "valid" output data, so the timely to collect data. This output form with single-chip microcomputer or are commonly used interface. In addition to the above output form outside, still have a "latch" and "temporary" two forms. The so-called "latch" refers to launch the output signal of each hair, the receiver output corresponding ", "new store until you receive signals. "Temporary" output and the introduction of "level" output is similar.Remote distance (Remote Control effect of RF Remote Control distance) are the major factors as follows:unched in power transmission power: while distance, but great power consumption, easy to generate interference.2.and receiving the receiver sensitivity, receiving, remote distance increased sensitivity to improve, but easy to cause disturbance maloperation or abuse.3.antenna, using linear antenna, and parallel, remote distance, but occupies a large space, in use the antenna spin, pull can increase the remote distance.4.and the higher height: antenna, remote farther, but by objective conditions.5.and stop: current use of wireless remote use of UHF band stipulated by the state, the propagation characteristics of approximate linear transmission, light, small, transmitters and receivers diffraction between such as walls are blocking will greatly discounted remote distance, if is reinforced concrete walls, due to the absorption effect conductor, radio waves.Considering the design of hardware volume small to be embedded in the remote control, so we chose 20 foot single-chip chip AT89C2051. Below is the introduction of the function.（1）AT89C2051 internal structure and performanceAT89C2051 is a byte flash 2K with programmable read-only memory can be erased EEPROM (low voltage, high performance of eight CMOS microcomputer. It adopts ATMEL of high-density non-volatile storage technology manufacturing and industrial standard MCS - 51 instruction set and lead. Through the combination of single chip in general CPL1 and flash memory, is a strong ATMEL AT89C2051 microcomputer, its application in many embedded control provides a highly flexible and low cost solutions. The compatible with 8051 AT89C2051 is CHMOS micro controller, the Flash memory capacity for 2KB. And CHMOS 80C51 process, have two kinds of leisure and power saving operation mode. The performance is as follows.5.CUP, 2KB Flash memory,Working voltage range 2.7-6V, 128KB data storage.The static working way: 0-24MHz, 15 root input/output line.A programmable serial, 2 a 16-bit timing/counters.Thereis a slice of inside precision simulation comparator, 5 the interrupt sources, 2 priority.Programmable serial UART channel, Directly LED driver output,The internal structure of AT89C2051 is shown in figure 1.Figure 1 AT89C2051 interior structure（2）AT89C2051 chip pin and functionIn order to adapt to the requirement of intelligent instrument, embedded in the chip foot AT89C2051 simplified configuration, as shown in figure b. The major changes to: (1) the lead foot from 20 to 40 wires, (2) increased a simulated comparator.=Diagram b AT89C2051 foot figure.AT89C2051 pin function:1.the VCC: voltage.2. to GND.3.P1 mouth: P1 mouth is an 8-bit two-way I/O port. P1.2 ~ P1.7 mouth pin the internal resistance provides. P1.0 and P1.1 requirements on the external pull-up resistors. P1.0 and P1.1 also separately as piece inside precision simulation comparator with input (AIN0) and reversed-phase input (AIN1). Output buffer can absorb the P1 mouth 20mA current and can directly LED display driver. When P1 mouth pin into a "1", can make its input. When the pin P1.2 ~ P1.7 as input and external down, they will be for the internal resistance and flow current (IIL). In flash P1 mouth during the procedure and program code data receiving calibration.4.P3: the P3.0 ~ P3.5 P3, P3.7 is the internal resistance with seven two-way I / 0 lead. P3.6 for fixed inputs piece inside the comparator output signal and it as a general I/Ofoot and inaccessible. P3 mouth buffer can absorb 20mA current. When P3 mouth pin into "1", they are the internal resistance can push and input. As input, and the low external P3 mouth pin pull-up resistors and will use current (IIL) outflow. P3 mouth still used to implement the various functions, such as AT89C2051 shown in table P3 mouth still receive some for flash memory programming and calibration of program control signals.5.RST: reset input. RST once, all into high level I/O foot will reset to "1". When the oscillator is running, continuous gives RST pin two machine cycle of high level can finish reset. Each machine cycle to 12 oscillator or clock cycle.6.XTAL1: as the oscillator amplifier input and inverse internal clock generator input.7.XTAL2: as the oscillator reversed-phase the amplifier's output.P3 mouth function as is shown in table 1.（3）the software and hardware constraints. AT89C2051Due to the foot of the chip AT89C2051, no set limits of external storage interface, so, for external memory read/write instructions as MOVX etc.Due to 2KB ROM, so, the space to jump instruction should pay attention to the destination address range (transfer 000H - 7FFH), beyond the range of addresses, will not meet wrong results. The scope of data storage is 00H (7FH -- when stack manipulation), also should be noticed.The input signal is simulated by the original P3.6 foot into the microcontroller, so the original P3.6 foot.Unable to external use. Simulation comparator can compare two simulation, if the size of the voltage external A D/A converter and its output as A comparator analog input, and by simulating the comparator another input voltage to be measured, through the introduction of the software method can realize the A/D conversion.8.the Flash memory AT89C2051)Provide a 2KB of single-chip AT89C2051 in Flash memory chips, which allows the online program to modify or use special programming programming.(1)Flash memory encryptionAT89C2051 SCM has 2 encryption, can programming (P) or programming (U) to obtain different encryption functionality. Encryption functionality table as shown in table 1-1.Encrypt a content erased only through chips to erase operation.(2)Flash memory programming and procedures，the piece inside chip AT89C2051 Flash memory programming.Note:1.the counters RESET at an EPROM inside the rising edge, and 000H RESET to XTAL1 by foot is executed, pulse count.2.pieces of 10ms to erase PROG pulse.3.during the programming P3.1 pulled low RDY/BSY instructions.(3).A T89C2051 SCM in Flash memory chips programming steps are as follows:1.in the sequence is the VCC GND pin, add working voltage, XTAL1 pin RESET, receiving GND pin, other than the above time, waiting for 10ms.2.In P3.2 pin RESET, heightening level.3.In P3.3, P3.4, P3.5, P3.7 pin; add model multilevel.4.P1.0 P1.7 -- for the 000H unit add data bytes.5.RESET to increase the 12V activation programming.6.P3.2 jump to a one byte programming or encryption.7.calibration has been programming, data from 12V to RESET logic level "H" and set P3.3 P3.7 -- for the correct level, and can output data in P1 mouth.8.For the next addresses) in the unit XTAL1 byte programming, a pulse, make address counter add 1, in mouth add programming data.9.programming and calibration circuit figure c, d.Figurec programming circuit Figured calibration circuit Explanation:(1) P3.1 during programming instructions to be low RDY/BSY,(2) single erasing the PROG 10ms need,(3) internal EEPROM address counter on the rising edge RESET, and 000H RESET to XTAL1 by foot pulses are executed.Along with the rapid development of science and technology, human society has undergone earth-shaking changes. Make our life more colorful. In these changes, the remote control technology has been widely permeates TV, aerospace, military, sports and other production, all aspects of life. From the broad sense, all equipped with electric locomotive facility or electrical switches, if feel some necessary, can consider to improve existing with remote control device, the operation fixed switch to realize the remote operation of the original equipment, stop, the variable, etc. Function.switch, for example, can be used to control the electric control switch the light switch, We design the infrared remote control system to realize the opponent switch quantity control. Infrared remote characteristic is not influence the surrounding environment and does not interfere with other electric equipment. Due to its cannot penetrate walls, so the room can use common household appliance of remote control without mutual interference, Circuit testing is simple, aslong as given circuit connection, generally does not need any commissioning can work, Decoding easily, can undertake multiple remote control.红外遥控人的眼睛能看到的可见光按波长从长到短排列，依次为红、橙、黄、绿、青、蓝、紫。
8051 Instruction sets 指令集
Instruction Set Summary of 8051 8051 Software Architecture:y Data memory: lower iRAM(00-7F), upper iRAM(80-FF), bit-addresable RAM (00-7F), SFR (80-FF),xRAM(0000-FFFF).y Code memory: iROM(0000-1FFF), xROM.y Registers: SFR, PC,y8 Addressing modes: register, direct, indirect,immediate, relative, absolute, long, indexed.y Instruction set: 139 1-byte, 92 2-byte, 24 3-byteinstructions (total 255 for 8-bit opcode)y Instruction types: arithmetic, logical, data transfer,boolean, program branching.2010/11/271Memory OrganizationSeparate memory space for program (64KB) and data (64KB).Internal memory:y On-chip ROM (4K/8K for 51/52)y On-chip RAM (128/256 for 31,51/32,52):General purpose storage(30-7F/FF)Bit-addressable storage(20-2F, some SFR)4 Register banks (00-1F)Special function registers (SFR 80-FF)2010/11/272MCS51 Memory Structure2010/11/273Internal Data RAMMOV A,5FH MOV A,FFH MOV Ri,#9FH (i=0 or 1)MOV A,@Ri2010/11/274Lower 128 Bytes of Internal RAM30H-7FH: General purpose RAM (can be accessed through direct orindirect addressing)2010/11/275Upper 128 Bytes of Internal RAMAvailable only in 8052. Can be accessed by indirect addressing only(via @R0 or @R1). Can be used as stack area by setting SP to 7FH.2010/11/2762010/11/277Alternate Pin Functions forPort PinsTimer/counter 2 capture/load91HT2EXP1.1Timer/counter 2 external input 90H T2P1.0External data memory read strobe B7H /RD P3.7External data memory write strobe B6H /WR P3.6Timer/counter 1 external input B5H T1P3.5Timer/counter 0 external input B4H T0P3.4External interrupt 1B3H /INT1P3.3External interrupt 0B2H /INT0P3.2Transmit data for serial port B1H TxD P3.1Receive data for serial port B0H RxD P3.0ALTERNATE FUNCTION BIT ADDRESS NAME BITSFR (occupy 80H-FFH)21Special Function Registers (8051) (26for 8052). Accessible by direct addressing only.Each SFR can be addressed by its byte addressor register name.SFRs with byte address X0H or X8H are also bit-addressable with starting bit address coincide with its byte address. (82BITS), THEREFORE, TOTAL BIT-ADDRESSABLE BIT ARE 210 (128+82).Other SFRs are not bit-addressable.2010/11/2782010/11/279P0808182838485868780SP Not bit addressable81DPL Not bit addressable 82DPH Not bit addressable 83PCON87TCON 88898A8B8C8D8E8F88TMODNot bit addressable89TL0Not bit addressable 8A TL1Not bit addressable 8B TH0Not bit addressable 8C TH1Not bit addressable 8D P1909192939495969790SCON 98999A 9B 9C 9D 9E 9F 98SBUF Not bit addressable99Address2010/11/2710TH2Not bit addressable CD TL2Not bit addressable CC RCAP2H Not bit addressable CB RCAP2LNot bit addressable CA T2CON C8C9CA CB CC CD CE CF C8A8A9AA AB AC --B0B1B2B3B4B5B6D0-D2D3D4D5D6E0E1E2E3E4E5E6F0F1F2F3F4F5F6P2A0A1A2A3A4A5A6A7A0IE AF A8P3B7B0IP B8B9BA BB BC ---B8PSW D7D0 A or ACC E7E0B F7F02010/11/2711SFR Memory Map2010/11/2712Program Status Word2010/11/2713Addressing ModesRegister addressing: MOV A,R7Direct addressing: MOV P1,AIndirect addressing: MOV A,@R1Immediate addressing:MOV A,#20HRelative addressing: SJMP relativeAbsolute addressing: AJMP addr11Long addressing: LJMP addr16Indexed addressing: MOVC A,@A+PC2010/11/2714Register AddressingAccess 8 “working registers”R0-R7 (3-bit). ASM use Rn, n=0,..,7, to representregister addressing.Register addressing instruction is 1-byte,first 5 bits for opcode and the last 3 bitsfor register n (LSb).e.g., ADD A,R5 MOV R5,AOpcode n2010/11/2715Direct AddressingAccess any on-chip variables orhardware registers, i.e., lower 128 bytesiRAM, SFR.Need an additional byte after theopcode for specifying the location.MOV SCON,#55H MOV direct,#dataMOV P1,A ADD A,55HOpcode Direct address2010/11/2716Indirect AddressingUse R0, R1as pointers to iRAM(lower& upper 128), DPTR or Ri for xRAM.Suitable for table, multiple-precisionnumbers, char string, etc.MOV A,@Ri(I=0,1) ADD A,@R0MOVX A,@DPTR MOVX @DPTR,AMOVX A,@Ri MOVX @Ri,AOpcode i2010/11/2717Indirect Addressing ExampleClear internal RAM from address 60H to7FH:MOV R0,#60HLOOP:MOV@R0,#0INC R0CJNE R0,#80H,LOOP(continue)2010/11/2718Immediate AddressingFor specifying constant source operand.Can be 8-bit or 16-bit constants.MOV A,#12 MOV DPTR,#1200HADD A,#data 8 MOV DPTR,#data16 Opcode Immediate data 8Opcode Imm. data 16 low Imm. data 16 high 2010/11/2719Relative AddressingUsed only with certain jump instructions.A 8-bit signed integer relative address(offset, -128 ~ 127) is added to PC toform the address of the next instruction.SJMP label (ASM will compute the relative offset)SJMP AHEADOpcode Relative Offset2010/11/2720010A 0109 0108 0107 0106 0105 0104 0103 0102 01010100 00FF 8005SJMP 0107H54321Relative offsetfrom address0102H is “5”Code Memory (80H is opcode)SJMP Example2010/11/27212043 2042 20412040 203F 203E 203D 203C 203B 203A 2039 203880F6SJMP 2038H-1-2-3-4-5-6-7-8-9-10Relative offsetfrom address2042H is“-10”i.e., F6HCode MemorySJMP Example2010/11/2722Absolute AddressingUsed only with ACALL and AJMP 2-byteinstruction.Allow branching within current 2K page(11 bits). (64K = 32 pages)AJMP THERE:y xxx00001 --1st byte (A10-A8 + opcode)y xxxxxxxx--2nd byte (A7-A0)y A15-A11 in PC does not change and is usedto determine the current page.2010/11/2723e.g., the instruction in 0900H and0901H is AJMP THERE where labelTHERE represent an instruction ataddress 0F46H. The ASM willy0900H11100001y0901H01000110y0F46H00001111 0100 0110The upper 5 bits determine the current2K page (copied from PC)The lower 11 bits determine the addresswithin the page (supplied in theinstruction)2010/11/2724e.g., An ACALL instruction is in 1024Hand 1025H. The subroutine begins inaddress 17A6H. The machine code is:y1024H1111 0001 (10001--ACALL)y1025H1010 0110y1024H0001 0000 0010 0100y17A6H00010111 1010 0110The machine code in 1024H is F1H and1025H is A6H.2010/11/2725Long AddressingOnly used with LCALL and LJMP 3-byteinstructions. A full 16-bit long address isspecified in the 2nd and 3rd byte of theinstruction.Can address any location in the 64Kbyte range but instructions are 3 byteslong and position-dependent (notrelative, therefore not relocatable).LCALL 8AF2H, LJMP 7F4EH2010/11/2726Indexed AddressingUse a base register (PC or DPTR)andan offset (ACC)in forming the effectiveaddress for a JMP or MOVC instruction.Jump tables or look-up tables are easilycreated using indexed addressing.MOVC A, @A+DPTR (opcode: 93H)MOVC A, @A+PC (opcode: 83H)JMP @A+DPTR (opcode: 73H)2010/11/2727Instruction TypesArithmeticLogicalData transferBoolean variableProgram branchingPoints to notes: addressing mode? # ofbytes? # of M cycles? what operations?flags affected? Applications?2010/11/2728Instructions that Affect FlagSettingsInstruction Flag Instruction FlagC OV AC C OV ACADD X X X CLR C0ADDC X X X CPL C XSUBB X X X ANL C,bit XMUL0 X ANL C,/bit XDIV 0 X ORL C,bit XDA X ORL C,/bit XRRC X MOV C,bit XRLC X CJNE XSETB C 12010/11/2729LegendRn register addressing using R0-R7direct8-bit internal address (00H-FFH)@Ri indirect addressing using R0 or R1source any of [Rn, direct, @Ri]dest any of [Rn, direct, @Ri]#data8-bit constant included in instruction#data1616-bit constantbit8-bit direct address of bitrel signed 8-bit offset in relative addressingaddr1111-bit absolute address in current 2K page addr1616-bit address2010/11/2730ADD A,source add source to AADD A,#data add data to AADDC A,source add with carryADDC A,#dataSUBB A,source subtract from Aborrow SUBB A,#data withINC A increment AINC source2010/11/2731DEC A decrement ADEC sourceINC DPTR (2)increment DPTRMUL AB (4)multiply A & BDIV AB (4)divide A by BDA A decimal adjust AAll arithmetic instructions execute onemachine cycle, except INC DPTR (2 M cycles)and MUL AB, DIV AB(4 M cycles).2010/11/2732DEC DPTR?No instruction for decrement DPTR. Need program:DEC DPLMOV R7,DPLCJNE R7,#0FFH,skipDEC DPHskip:(continue)2010/11/2733Addition of 2 4-digit BCDMOV A,43H;num1 in 40,41HADD A,41H;num2 in 42,43HDA A;result in 40,41HMOV41H,AMOV A,42HADDC A,40HDA AMOV40H,A2010/11/27342010/11/2735Arithmetic InstructionsANL A,source logical ANDANL A,#dataANL direct,AANL direct,#data (2)ORL A,source logical ORORL A,#dataORL direct,AORL direct,#data (2)2010/11/2736XRL A,source logical XORXRL A,#dataXRL direct,AXRL direct,#data (2)CLR A clear ACPL A complement A2010/11/2737Rotate A 3 positions leftRL A;rotate left onceRL A;RL A;SWAP A;swap A nibblesRR A;rotate right once2010/11/2738Reverse bits of AMOV R7,#8Loop:RLC AXCH A,0F0HRRC AXCH A,0F0HDJNZ R7,LOOPXCH A,0F0H2010/11/2739Binary to BCDA contains a binary < 100, convert A intoBCD:MOV B,#10DIV ABSWAP AADD A,B2010/11/2740Logical OperationsRL A rotate A leftRL C A rotate A left through CRR A rotate A rightRRC A rotate A right through CSWAP A swap nibbles of A2010/11/2741Logical Instructions2010/11/2742Data TransferMOV A,source;move sourceMOV A,#data;to destinationMOV dest,AMOV dest,#data(2)MOV DPTR,#data16(2)MOVC A,@A+DPTR (2)MOVC A,@A+PC (2)2010/11/2743Data TransferMOVX A,@Ri;move fromMOVX A,@DPTR;data memoryMOVX@Ri,AMOVX@DPTR,APUSH directPOP directXCH A,source;exchange bytes XCHD A,@Ri;exchange low-order digits2010/11/2744What are A & B after prog?MOV0F0H,#12H;B=12HMOV R0,#0F0H;MOV A,#34H;A=34HXCH A,0F0H;A=12H, B=34H XCHD A,@R0;A=14H, B=32H2010/11/2745Read 10F4H & 10F5H into R6,R7MOV DPTR,#10F4HMOVX A,@DPTRMOV R6,AINC DPTRMOVX A,@DPTRMOV R7,A2010/11/2746Look-up TablesMOV A,ENTRY_#CALLLOOK_UP..LOOK_UP:INC AMOVC A,@A+PCRETTABLE:DB data,data,data,... 2010/11/27472010/11/2748Data Transfer Instructions2010/11/2749Boolean Variable ManipulationCLR C;clear bitCLR bitSETB C;set bitSETB bitCPL C;complement bitCPL bitANL C,bit;AND bit with CANL C,/bit;And NOT bit with C 2010/11/2750。
dw8051
DesignWare LibraryDW8051 MacroCellData SheetOverviewThe DesignWare®DW8051™MacroCell is a high-performance, configurable, fully synthesizable 8051 core that is binary compatible with the industry standard 803x/805x microcontrollers. The DW8051 core is technology-independent and has been fabricated in both ASIC and FPGA technologies. Designed for ease of use, the DW8051 includes the coreConsultant™tool, a user-friendly wizard, which guides users through configuration, simulation and synthesis.The DesignWare DW8051 MacroCell solution includes the DW8051 MacroCell, a reference design, and Synopsys’ extensive verification environment. The high-performance architecture of the DW8051 provides up to three times performance improvement over the standard 8051 when operating at the same clock rate.Proven Quality, Complete SolutionTo ensure quality, the DW8051 was developed according to Synopsys’ strict design-for-reuse methodology. It has undergone extensive testing during the design process and has been proven in many different technologies. It has also been tested with a variety of third-party 8051 development tools and 8051 evaluation boards.The DW8051’s high-performance, config-urable, synthesizable architecture, combined with the development environment, provides a total solution for building low-cost, high-performance embedded control systems for a wide range of applications.Automated Design Flow with Synopsys coreConsultantThe DW8051 MacroCell solution includes the Synopsys coreConsultant tool, which provides the following services:I Activity checklist that guides usersthrough DW8051 design activities inthe correct orderI Automatic, error-free DW8051configuration,including parametercross-dependency checkingI Automatic configuration and operationof the DW8051 verification environment I Automatic, high-quality synthesis withusers’ technology library and installedversion of Design Compiler™I Automatic design checking and synthesisresults analysisUsers can operate coreConsultant in its GUI mode (Figure 1) or in batch mode through its command line interface.Technical Advantages of the DW8051I 4 clocks/instruction cycle versus 12 instandard 8051- Up to three times faster execution onaverage versus standard 8051I Stretch memory cycle- Allows application software to adjust todifferent external RAM speeds- MOVX in as little as eight clock cycles I Dual data pointers- Improves efficiency when moving largeblocks of dataI Internal/external peripheral interface- Special function register (SFR) bus inDW8051 supports both internal andexternal peripherals vs. internal only instandard 8051I Two optional full-duplex serial portsI Seven additional interruptsI SFR bus for adding custom peripherals803x/805x CompatibilityThe DW8051 is compatible with the standard 8051 instruction set and can be configured to a wide range of industry standard 803x/805x architectures. Control signals for standard 803x/805x I/O ports are included. Optional full-duplex serial ports and third timer are selectable through parameters.High-Performance ArchitectureThe DW8051 is a fully static and synchronousdesign. Eliminating wasted bus cycles andproviding dual data pointers for moving largedata blocks achieve greater efficiency andperformance. The DW8051 MacroCelltypically contains ~10k-13k gates, dependingon the configuration and technology in whichit is implemented. It runs at greater than 300megahertz in 90-nm process technology.Lower performance applications also benefitby being able to run at lower clock rates toget the same performance as a standard 12clocks/instruction 8051. Lower clock rateslead to lower power consumption and lowerelectro-magnetic interference (EMI).Adding Custom Designed PeripheralsA typical 8051 allows peripheral interfaceonly through port logic. In addition to theports, the DW8051 also provides directaccess to peripherals through the memoryand SFR buses (Figure 2).I Users can interface additional peripheralsdirectly to the DW8051’s memory bus.This method allows them to make use ofthe “stretch” memory cycle feature tointerface slow peripherals.I Users can also directly attach customdesigned peripherals to the efficient SFRbus, the same bus used for interfacing thestandard DW8051 internal peripherals.SFR addresses that are not used for theDW8051 internal SFRs are available forconnecting external peripherals. Addingperipherals to the SFR bus offers thefollowing advantages:- Faster read, write accesses; 1 clockvs. 2 clocks using mem_bus- Direct addressing- Takes advantage of bitmanipulation instructions- Efficient, compact codeThird-Party Development Tools SupportSynopsys has an active program in placeto support third-party tools. Many industrystandard compilers, assemblers, ROMmonitors, and in-circuit emulators have beentested for compatibility with the DW8051.This allows integration of these tools into adesign environment and provides a completedevelopment solution for DW8051-basedembedded systems on a chip. NohauCorporation and Hitex Development Toolsprovide in-circuit emulation support.Figure 1. Example coreConsultant dialogs for DW8051DW8051 Configurable Architecture Figure 3 illustrates the hardware architecture of the DW8051 core. The name of thetop-level module is DW8051_core. The internal RAM and ROM modules are located outside DW8051_core to facilitate simulation and insertion of technology-specificRAM/ROM modules. The followingsub-modules and interfaces are selectable through parameter settings:I DW8051_core can address either 128or 256 bytes of internal RAMI The internal ROM address range is deter-mined by a parameter (rom_addr_size)I Timer 2 (DW8051_timer2) is optionalI0,1, or 2 serial ports (DW8051_serial)can be implementedI The interrupt unit is either DW8051_intr_0(6-source) or DW8051_intr_1 (13-source) The coreConsultant tool automatically generates the selected DW8051 configuration so that no HDL source code editing is needed.803X/805X Feature ComparisonThrough parameter settings, user scanconfigure the DW8051 hardware to befunctionally compatible with a variety of803x/805x configurations. For example,users can implement two 16-bit timers forcompatibility with the Intel 8051, or theycan implement three 16-bit timers forcompatibility with the Intel 80C32 (Table 1).Performance OverviewThe DW8051 processor core offers increasedperformance by executing instructions in a4-clock bus cycle, as opposed to the 12-clockbus cycle in the standard 8051 (Figure 4).The shortened bus timing improves theinstruction execution rate for most instructionsby a factor of three over the standard 8051architectures.Some instructions require a different numberof instruction cycles on the DW8051 thanthe standard 8051. In the standard 8051,all instructions except for MUL and DIV takeone or two instruction cycles to complete. Inthe DW8051 architecture, instructions cantake between one and five instruction cyclesto complete. The average speed improvementfor the entire instruction set is approximatelytwo-and-a-half times (Table 2).DW8051 Development EnvironmentThe DW8051 MacroCell solution is devel-oped and packaged for use with Synopsys’coreConsultant tool. The complete DW8051MacroCell solution coreKit includes:I The DW8051 MacroCellI Multiple-simulator support (e.g., VCS, MTIModelSim, Verilog-XL and NC-Verilog)I An example 8032-compatible design- This design uses the DW8051_coreand illustrates how to build andconnect 8051-compatible port modulesfor designs where it is preferable touse standard 8051 port modulesinstead of the 16-bit address memoryinterfaceI Extensive verification environment- HDL testbench that instantiates theDW8051_core, models internal ROMand RAM, and emulates 64-kilobytesof external RAM and 64-kilobytes ofexternal ROM- Processes that trace the programcounter and write accesses toexternal RAM(1) Internal ROM and RAM are located outside of DW8051_core.Figure 3. DW8051_core Table 1. Feature summary of DW8051 and common803x/805x configurations- A collection of 8051 assemblerprograms that test all of the instructionset opcodes, plus miscellaneous testsfor internal hardware- A set of expected results(golden log files)- Automatic testbench configuration,simulation, and results checkingthrough coreConsultantI Example scan insertion script forSynopsys DFT Compiler™I Example TSMC .18µm LibraryI Complete documentation- DW8051 data book in on-line format(PDF), integrated into thecoreConsultant on-line helpI Support for third-party development tools- Industry standard compilers,assemblers, debuggers, ROMmonitors, in-circuit emulators fromNohau and Hitex.- Keil 8051 software development tools I Comprehensive worldwide technicalsupport About DesignWare IPSynopsys’ DesignWare IP enables designersto cost effectively create and verify complexSoCs, ASICs and FPGAs. The broad IPportfolio includes industry leading connec-tivity IP Cores and Verification IP (e.g., USB1.1,2.0, OTG and PHYs, PCI, PCI-X®,PCIExpress™, PCI Express PHY, Ethernet,1394, I2C), AMBA™on-chip bus (logic,peripherals, verification IP) complete memo-ry solution (e.g., memory controllers, BISTand models), high-speed datapath compo-nents, microcontrollers (8051, 6811)andStar IP processors and DSP core (e.g.,IBM PowerPC®440, Infineon C166™S andTriCore®1, MIPS32™4KE™, NEC V850E™,Philips CoolFlux™DSP). When combinedwith our robust IP development methodology,extensive investment in quality and comprehen-sive worldwide technical support, DesignWareIP gives designers a faster, more pre-dictable and lower-risk path to chip success.The DesignWare 8051 MacroCell is availablein encrypted form in the DesignWare Library.The Source RTL of the DW8051 can also belicensed individually, on a per-use basisFor a complete directory of Synopsys IPvisit: /ipdirectoryFor more information on DesignWare IP,visit: or call1-877-4BEST-IPFigure 4. Instruction cycle timing comparison700 East Middlefield Road, Mountain View, CA 94043 Synopsys, the Synopsys logo, DesignWare and VCS are registered trademarks and coreConsultant, DW8051, Design Compiler and DFT Compiler, aretrademarks of Synopsys, Inc. PCI, PCI-X and PCI Express are trademarks of PCI-SIG. AMBA is a trademark of ARM Limited. All other products or service namesmentioned herein are trademarks of their respective holders and should be treated as such. Printed in the U.S.A.©2004 Synopsys, Inc. 12/04.PS.WO.04-12879。
C8051F2xx 开发板用户指南说明书
Rev. 0.6 9/06Copyright © 2006 by Silicon LaboratoriesC8051F2xx-DKXX EVELOPMENT IT SER S UIDE1. Kit ContentsThe C8051F2xx Development Kits contain the following items:•C8051F206 or C8051F226 Target Board•C8051Fxxx Development Kit Quick-Start Guide•Silicon Laboratories IDE and Product Information CD-ROM. CD content includes:•Silicon Laboratories Integrated Development Environment (IDE)•Keil Software 8051 Development Tools (macro assembler, linker, evaluation ‘C’ compiler)•Source code examples and register definition files •Documentation•C8051F2xx Development Kit User’s Guide (this document)•AC to DC Power Adapter•USB Debug Adapter (USB to Debug Interface)•USB Cable2. Hardware Setup using a USB Debug AdapterThe target board is connected to a PC running the Silicon Laboratories IDE via the USB Debug Adapter as shown in Figure 1.1.Connect the USB Debug Adapter to the JTAG connector on the target board with the 10-pin ribbon cable.2.Connect one end of the USB cable to the USB connector on the USB Debug Adapter.3.Connect the other end of the USB cable to a USB Port on the PC.4.Connect the ac/dc power adapter to power jack P1 on the target board.Notes:•Use the Reset button in the IDE to reset the target when connected using a USB Debug Adapter.•Remove power from the target board and the USB Debug Adapter before connecting or disconnecting the ribbon cable from the target board. Connecting or disconnecting the cable when the devices have power can damage the device and/or the USB Debug Adapter.Figure 1. Hardware Setup using a USB Debug AdapterPWRP1.6C8051F2xx-DK3. Software SetupThe included CD-ROM contains the Silicon Laboratories Integrated Development Environment (IDE), Keil software 8051 tools and additional documentation. Insert the CD-ROM into your PC’s CD-ROM drive. An installer will auto-matically launch, allowing you to install the IDE software or read documentation by clicking buttons on the Installa-tion Panel. If the installer does not automatically start when you insert the CD-ROM, run autorun.exe found in the root directory of the CD-ROM. Refer to the readme.txt file on the CD-ROM for the latest information regarding known IDE problems and restrictions.4. Silicon Laboratories Integrated Development EnvironmentThe Silicon Laboratories IDE integrates a source-code editor, source-level debugger and in-system Flash program-mer. The use of third-party compilers and assemblers is also supported. This development kit includes the Keil Software A51 macro assembler, BL51 linker and evaluation version C51 ‘C’ compiler. These tools can be used from within the Silicon Laboratories IDE.4.1. System RequirementsThe Silicon Laboratories IDE requirements:•Pentium-class host PC running Microsoft Windows 98SE or later.•One available COM or USB port.•64 MB RAM and 40MB free HD space recommended.4.2. Assembler and LinkerA full-version Keil A51 macro assembler and BL51 banking linker are included with the development kit and are installed during IDE installation. The complete assembler and linker reference manual can be found under the Help menu in the IDE or in the “SiLabs\MCU\hlp” directory (A51.pdf).4.3. Evaluation C51 ‘C’ CompilerAn evaluation version of the Keil C51 ‘C’ compiler is included with the development kit and is installed during IDE installation. The evaluation version of the C51 compiler is the same as the full professional version except code size is limited to 4kB and the floating point library is not included. The C51 compiler reference manual can be found under the Help menu in the IDE or in the “SiLabs\MCU\hlp” directory (C51.pdf).4.4. Using the Keil Software 8051 Tools with the Silicon Laboratories IDETo perform source-level debugging with the IDE, you must configure the Keil 8051 tools to generate an absolute object file in the OMF-51 format with object extensions and debug records enabled. You may build the OMF-51 absolute object file by calling the Keil 8051 tools at the command line (e.g. batch file or make file) or by using the project manager built into the IDE. The default configuration when using the Silicon Laboratories IDE project manager enables object extension and debug record generation. Refer to Applications Note AN104 - Integrating Keil 8051 Tools Into the Silicon Labs IDE in the “SiLabs\MCU\Documentation\Appnotes” directory on the CD-ROM for additional information on using the Keil 8051 tools with the Silicon Laboratories IDE.To build an absolute object file using the Silicon Laboratories IDE project manager, you must first create a project.A project consists of a set of files, IDE configuration, debug views, and a target build configuration (list of files and tool configurations used as input to the assembler, compiler, and linker when building an output object file).The following sections illustrate the steps necessary to manually create a project with one or more source files, build a program and download the program to the target in preparation for debugging. (The IDE will automatically create a single-file project using the currently open and active source file if you select Build/Make Project before a project is defined.)C8051F2xx-DK4.4.1. Creating a New Project1.Select Project→New Project to open a new project and reset all configuration settings to default.2.Select File→New File to open an editor window. Create your source file(s) and save the file(s) with a rec-ognized extension, such as .c, .h, or .asm, to enable color syntax highlighting.3.Right-click on “New Project” in the Project Window. Select Add files to project. Select files in the filebrowser and click Open. Continue adding files until all project files have been added.4.For each of the files in the Project Window that you want assembled, compiled and linked into the targetbuild, right-click on the file name and select Add file to build. Each file will be assembled or compiled as appropriate (based on file extension) and linked into the build of the absolute object file.Note: If a project contains a large number of files, the “Group” feature of the IDE can be used to organize.Right-click on “New Project” in the Project Window. Select Add Groups to project. Add pre-definedgroups or add customized groups. Right-click on the group name and choose Add file to group. Select files to be added. Continue adding files until all project files have been added.4.4.2. Building and Downloading the Program for Debugging1.Once all source files have been added to the target build, build the project by clicking on the Build/MakeProject button in the toolbar or selecting Project→Build/Make Project from the menu.Note: After the project has been built the first time, the Build/Make Project command will only build the files that have been changed since the previous build. To rebuild all files and project dependencies, click on the Rebuild All button in the toolbar or select Project→Rebuild All from the menu.2.Before connecting to the target device, several connection options may need to be set. Open theConnection Options window by selecting Options→Connection Options... in the IDE menu. First, select the appropriate adapter in the “Serial Adapter” section. Next, the correct “Debug Interface” must be selected.C8051F2xx family devices use the JTAG debug interface. Once all the selections are made, click the OK button to close the window.3.Click the Connect button in the toolbar or select Debug→Connect from the menu to connect to the device.4.Download the project to the target by clicking the Download Code button in the toolbar.Note: To enable automatic downloading if the program build is successful select Enable automatic con-nect/download after build in the Project→Target Build Configuration dialog. If errors occur during the build process, the IDE will not attempt the download.5.Save the project when finished with the debug session to preserve the current target build configuration,editor settings and the location of all open debug views. To save the project, select Project->Save Project As... from the menu. Create a new name for the project and click on Save.C8051F2xx-DK5. Example Source CodeExample source code and register definition files are provided in the “SiLabs\MCU\Examples\C8051F2xx”directory during IDE installation. These files may be used as a template for code development. Example applications include a blinking LED example which configures the green LED on the target board to blink at a fixed rate.5.1. Register Definition FilesRegister definition files C8051F200.inc and C8051F200.h define all SFR registers and bit-addressable control/status bits. They are installed into the “SiLabs\MCU\Examples\C8051F2xx” directory during IDE installation. The register and bit names are identical to those used in the C8051F2xx data sheet. Both register definition files are also installed in the default search path used by the Keil Software 8051 tools. Therefore, when using the Keil 8051 tools included with the development kit (A51, C51), it is not necessary to copy a register definition file to each project’s file directory.5.2. Blinking LED ExampleThe example source files blink.asm and blinky.c show examples of several basic C8051F2xx functions. These include; disabling the watchdog timer (WDT), configuring the Port I/O crossbar, configuring a timer for an interrupt routine, initializing the system clock, and configuring a GPIO port. When compiled/assembled and linked this program flashes the green LED on the target board about five times a second using the interrupt handler with a timer.C8051F2xx-DK 6. Target BoardThe C8051F2xx Development Kit includes a target board with a C8051F206/26 device pre-installed for evaluation and preliminary software development. Numerous input/output (I/O) connections are provided to facilitate prototyping using the target board. Refer to Figure2 for the locations of the various I/O connectors.P1Power connector (accepts input from 7 to 15 VDC unregulated power adapter)J1VDDMonEn, Ties MONEN to +3VD2 or GND to enable/disable the VDD monitorJ264-pin I/O connector providing access to all I/O signalsP2.5Connects SW2 to port pin P2.5LED Connects LED D2 to port pin P2.4PWMIN Connects PWM low-pass filter to port pin P2.7J4JTAG connector for Debug Adapter interfaceJ5Connects P3.0 to analog signal from J6J6Analog I/O configuration connectorJ7Connects P3.1 to analog signal from J6X1Analog I/O terminal blockFigure 2. C8051F206 and C8051F226 Target BoardsC8051F2xx-DK6.1. System Clock SourcesThe C8051F2xx device installed on the target board features a internal oscillator which is enabled as the system clock source on reset. After reset, the internal oscillator operates at a frequency of 2MHz (+/-2%) by default but may be configured by software to operate at other frequencies. Therefore, in many applications an external oscillator is not required. However, an external crystal may be installed on the target board for additional applications. The target board is designed to facilitate the installation of an external crystal at the pads marked Q1. Refer to the C8051F2xx datasheet for more information on configuring the system clock source. Following are a few part numbers of suitable crystals:Freq(MHz)Digikey P/N ECS P/N22.1184X063-ND ECS-221-20-1 (20pF loading capacitance)18.432X146-ND ECS-184-20-1 (20pF loading capacitance)11.0592X089-ND ECS-110.5-20-1 (20pF loading capacitance)6.2. Switches and LEDsTwo switches are provided on the target board. Switch SW1 is connected to the RESET pin of the C8051F2xx device on the target board. Pressing SW1 puts the device into its hardware-reset state. The device will leave the reset state after SW1 is released. Switch SW2 is connected to the device’s general purpose I/O (GPIO) pin through headers. Pressing SW2 generates a logic low signal on the port pin. Remove the shorting block from the header to disconnect SW2 from the port pins. The port pin signal is also routed to a pin on the J2 I/O connector. See Table1 for the port pins and headers corresponding to each switch.Two LEDs are also provided on the target board. The red LED labeled PWR is used to indicate a power connection to the target board. The green LED labeled with a port pin name is connected to the device’s GPIO pin through headers. Remove the shorting block from the header to disconnect the LED from the port pin. The port pin signal is also routed to a pin on the J2 I/O connector. See Table1 for the port pins and headers corresponding to each LED.Table 1. Target Board I/O DescriptionsDescription I/O HeaderSW1Reset noneSW2P2.5P2.5Green LED P2.4LEDRed LED PWR none6.3. Target Board JTAG Interface (J4)The JTAG connector (J4) provides access to the JTAG pins of the C8051F2xx. It is used to connect the Serial Adapter or the USB Debug Adapter to the target board for in-circuit debugging and Flash programming. Table2 shows the JTAG pin definitions.Table 2. JTAG Connector Pin DescriptionsPin #Description1+3VD (+3.3VDC)2, 3, 9GND (Ground)4TCK5TMS6TDO7TDI8, 10Not ConnectedC8051F2xx-DK6.4. Analog I/O (J5, J6, J7, Terminal Block)An Analog I/O Configuration connector (J6) provides the ability to route analog I/O signals from the C8051F2xx to a terminal block in addition to connector J2 by installing shorting blocks on J6. Additionally, if shorting blocks are installed on J5 and J7, the analog signals routed through J6 can be inputs to the C8051F2xx at port pins P3.0 and/or P3.1. The port pins can then be configured as inputs to the on-chip ADC for evaluation. J6 also allows the user to route analog signals from the terminal block to port pins P1.3 and P1.4. These port pin can then be configured as inputs to Comparator 1. The PWM signal from the low-pass filter is also routed to J6 to provide a user controlled analog voltage level. This signal can then be used to evaluate the on-chip ADC by placing a shorting block on J6 (provided the J5 or J7 header is shorted). Refer to Figure3 to determine the shorting block installation positions required to create the desired analog signal paths. Refer to Table3 for terminal block connections and Table4 for J6 pin definitions.Figure 3. J6 Analog I/O Configuration ConnectorTable 3. Terminal Block Pin DescriptionsPin #Description1VREF2GND7AIN28AIN1Table 4. J6 Connector Pin DescriptionsPin #Description1P1.4/CP1-2, 9, 10NC3AIN24P3.0AIN5P1.3/CP1+6PWM7AIN18P3.1AIN6.5. VDD Monitor Disable (J1)The VDD Monitor of the C8051F2xx may be disabled by moving the shorting block on J1 from pins 1-2 to pins 2-3, as shown in Figure4.Figure 4. VDD Monitor Hardware SetupC8051F2xx-DK6.6. Low-pass Filter (PWMIN)The C8051F2xx target board features a low-pass filter that may be connected to port pin P2.7. Install a shorting block on connector “PWMIN” to connect the P2.7 pin of the target device to the low-pass filter input. The output of the low-pass filter is routed to the PWM signal at J6[6]. To route the PWM signal to the ADC on the target device, a shorting block should be placed on “PWMIN”, and a shorting block placed on connector “P3.0AIN” (J5) or “P3.1AIN” (J7). Connector J6 is used to connect the PWM voltage to the P3.0AIN or P3.1AIN signal routed to the corresponding port pins (See Figure3). These port pins are then configured for use by the ADC.The C8051F2xx may be programmed to generate a PWM (Pulse-Width Modulated) waveform which is then input to the low-pass filter to implement a user-controlled PWM digital-to-analog converter. Refer to Applications Note AN110 - Implementing 16-Bit PWM Using an On-Chip Timer in the “Documentation” directory on the CD-ROM for a discussion on generating a programmable dc voltage level with a PWM waveform and low-pass filter.6.7. Expansion I/O Connector (J2)The target board provides access to all C8051F2xx signals (except the four JTAG signals: TCK, TMS, TDO and TDI used to connect the Emulation Cartridge – these are accessed using test points in place near the J4 header) via the 64-pin connector J2. A small through-hole prototyping area is also provided. All I/O signals routed to connector J2 are also routed to through-hole connection points between J2 and the prototyping area (see Figure2). The signal layout pattern of these connection points is identical to the adjacent J2 connector pins. Table5 shows the pin-out of the J2 connector.Table 5. J2 Pin DescriptionsPin Description Pin Description1,46,64+3VD2 (voltage supply)21P2.42XTAL122P2.53P1.623P2.24P1.724P2.35P1.425P2.06P1.526P2.17P1.227P3.68P1.328P3.79P1.029P3.410P1.130P3.511P0.631P3.212P0.732P3.313P0.433P3.014P0.534P3.115P0.236/RST16P0.339,41,42,45,47,63GND17P0.048,50PWM (pulse-width modulator) 18P0.153VREF19P2.662VDDMONEN20P2.7C8051F2xx-DK 7. SchematicC8051F2xx-DKD OCUMENT C HANGE L ISTRevision 0.4 to Revision 0.5⏹Section 1, added USB Debug Adapter and USB Cable.⏹Section 2, changed name from "Hardware Setup" to "Hardware Setup using an EC2 Serial Adapter".⏹Section 2, added 2 Notes bullets.⏹Section 2, removed Note from bottom of page.⏹Added Section 3, "Hardware Setup using a USB Debug Adapter".⏹Section 5.4.2, changed step 2 to include new instructions.⏹Section 7, J4, changed "Serial Adapter" to "Debug Adapter".⏹Target Board DEBUG Interface Section, added USB Debug Adapter.⏹DEBUG Connector Pin Descriptions Table, changed pin 4 to C2D.⏹Changed "jumper" to "header".⏹EC2 Serial Adapter section, added EC2 to the section title, table title and figure title.⏹EC2 Serial Adapter section, changed "JTAG" to "DEBUG".⏹Added "USB Debug Adapter" section.Revision 0.5 to Revision 0.6⏹Removed EC2 Serial Adapter from Kit Contents.⏹Removed Section 2. Hardware Setup using an EC2 Serial Adapter. See RS232 Serial Adapter (EC2) User's Guide.⏹Removed Section 8. EC2 Serial Adapter. See RS232 Serial Adapter (EC2) User's Guide.⏹Removed Section 9. USB Debug Adapter. See USB Debug Adapter User's Guide.DisclaimerSilicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. 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c51 指令二进制
c51 指令二进制## English Answer:C51 Instruction Set.The C51 instruction set is a set of instructions used by the 8051 microcontroller. It is a reduced instruction set computer (RISC) architecture, which means that it has a small number of instructions that are designed to be executed quickly. The C51 instruction set is divided into three types:Data manipulation instructions These instructions are used to perform operations on data, such as adding, subtracting, multiplying, and dividing.Control flow instructions These instructions are used to control the flow of execution of a program, such as branching, looping, and returning from a subroutine.Input/output instructions These instructions are used to transfer data between the microcontroller and the outside world, such as reading from a port or writing to a display.The C51 instruction set is a powerful set of instructions that can be used to implement a wide variety of applications. It is a popular choice for embedded systems because of its small size, low power consumption, and high performance.Instruction Format.The C51 instructions are all 8 bits wide. The first 4 bits of an instruction specify the opcode, which is the operation that the instruction will perform. The remaining 4 bits of an instruction specify the operands, which are the data that the instruction will operate on.Addressing Modes.The C51 instruction set supports a variety ofaddressing modes, which allow instructions to access datain different ways. The most common addressing modes are:Register addressing This addressing mode allows instructions to access data in the microcontroller's registers.Immediate addressing This addressing mode allows instructions to access data that is specified in the instruction itself.Direct addressing This addressing mode allows instructions to access data in the microcontroller's memory.Indirect addressing This addressing mode allows instructions to access data in the microcontroller's memory through a pointer.Example Instructions.The following are some examples of C51 instructions:MOV A, R0 This instruction moves the contents of register R0 to register A.ADD A, #5 This instruction adds the value 5 to the contents of register A.JMP 0x1000 This instruction jumps to the address0x1000.MOVX @DPTR, A This instruction moves the contents of register A to the memory location pointed to by the DPTR register.Conclusion.The C51 instruction set is a powerful set of instructions that can be used to implement a wide variety of applications. It is a popular choice for embedded systems because of its small size, low power consumption, and high performance.## 中文回答：C51 指令集。
8051单片机 Microcontroller Instruction__
Atmel 8051 Microcontrollers Hardware10509C–8051–07/06Section 18051 Microcontroller Instruction SetFor interrupt response time information, refer to the hardware description chapter.Note:1.Operations on SFR byte address 208 or bit addresses 209-215 (that is, the PSW or bits in the PSW) also affect flag settings.(1)Table 1-1. Instruction Set SummaryNote:Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle20509C–8051–07/0630509C–8051–07/06Table 1-2. Instruction Set Summary (Continued)Note:Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle8051 Microcontroller Instruction Set0509C–8051–07/06Table 1-3. AT89 Instruction Set Summary (1)Note: 1.All mnemonics copyrighted © Intel Corp., 1980.8051 Microcontroller Instruction Set8051 Microcontroller Instruction Set0509C–8051–07/068051 Microcontroller Instruction SetTable 1-4. Instruction Opcodes in Hexadecimal Order8051 Microcontroller Instruction Set0509C–8051–07/068051 Microcontroller Instruction Set8051 Microcontroller Instruction Set0509C–8051–07/06110509C–8051–07/061.1Instruction DefinitionsACALL addr11Function:Absolute CallDescription:ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PCtwice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice. The destination address is obtained by successivelyconcatenating the five high-order bits of the incremented PC, opcode bits 7 through 5, and the second byte of the instruction. The subroutine called must therefore start within the same 2 K block of the program memory as the first byte of the instruction following ACALL. No flags are affected.Example:Initially SP equals 07H. The label SUBRTN is at program memory location 0345 H. After executing the followinginstruction,ACALL SUBRTNat location 0123H, SP contains 09H, internal RAM locations 08H and 09H will contain 25H and 01H, respectively, and the PC contains 0345H.Bytes:2Cycles:2Encoding:a10a9a811a7a6a5a4a3a2a1a0Operation:ACALL(PC) ← (PC) + 2(SP) ← (SP) + 1((SP)) ← (PC 7-0)(SP) ← (SP) + 1((SP)) ← (PC 15-8)(PC 10-0) ← page addressFunction:AddDescription:ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. Whenadding unsigned integers, the carry flag indicates an overflow occurred.OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6; otherwise, OV iscleared. When adding signed integers, OV indicates a negative number produced as the sum of two positiveoperands, or a positive sum from two negative operands.Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.Example:The Accumulator holds 0C3H (1100001lB), and register 0 holds 0AAH (10101010B). The following instruction, ADD A,R0leaves 6DH (01101101B) in the Accumulator with the AC flag cleared and both the carry flag and OV set to 1. ADD A,R nBytes:1Cycles:1Encoding:00101r r rOperation:ADD(A) ← (A) + (R n)ADD A,directBytes:2Cycles:1Encoding:00100101direct addressOperation:ADD(A) ← (A) + (direct)ADD A,@R iBytes:1Cycles:1Encoding:0010011iOperation:ADD(A) ← (A) + ((R i))ADD A,#dataBytes:2Cycles:1Encoding:00100100immediate dataOperation:ADD(A) ← (A) + #data120509C–8051–07/06130509C–8051–07/06Function:Add with CarryDescription:ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator contents, leaving theresult in the Accumulator. The carry and auxiliary-carry flags are set respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands.Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.Example:The Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B) with the carry flag set. Thefollowing instruction,ADDC A,R0leaves 6EH (01101110B) in the Accumulator with AC cleared and both the Carry flag and OV set to 1.ADDC A,R nBytes:1Cycles:1Encoding:111rrrOperation:ADDC(A) ← (A) + (C) + (R n )ADDC A,directBytes:2Cycles:1Encoding:1111direct addressOperation:ADDC(A) ← (A) + (C) + (direct)ADDC A,@R iBytes:1Cycles:1Encoding:1111iOperation:ADDC(A) ← (A) + (C) + ((R i ))ADDC A,#dataBytes:2Cycles:1Encoding:111immediate dataOperation:ADDC(A) ← (A) + (C) + #dataAJMP addr11Function:Absolute JumpDescription:AJMP transfers program execution to the indicated address, which is formed at run-time by concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7 through 5, and the second byte ofthe instruction. The destination must therfore be within the same 2 K block of program memory as the first byteof the instruction following AJMP.Example:The label JMPADR is at program memory location 0123H. The following instruction,AJMP JMPADRis at location 0345H and loads the PC with 0123H.Bytes:2Cycles:2Operation:ANL(A) ← (A) ∧ (R n)140509C–8051–07/06150509C–8051–07/06ANL A,directBytes:2Cycles:1Encoding:1111direct addressOperation:ANL(A) ← (A)∧ (direct)ANL A,@R iBytes:1Cycles:1Encoding:1111iOperation:ANL(A) ← (A)∧ ((R i ))ANL A,#dataBytes:2Cycles:1Encoding:111immediate dataOperation:ANL(A) ← (A)∧ #dataANL direct,ABytes:2Cycles:1Encoding:111direct addressOperation:ANL(direct) ← (direct)∧ (A)ANL direct,#dataBytes:3Cycles:2Encoding:1111direct addressimmediate dataOperation:ANL(direct) ← (direct)∧ #dataANL C,<src-bit>Function:Logical-AND for bit variablesDescription:If the Boolean value of the source bit is a logical 0, then ANL C clears the carry flag; otherwise, this instruction leaves the carry flag in its current state. A slash ( / ) preceding the operand in the assembly language indicatesthat the logical complement of the addressed bit is used as the source value, but the source bit itself is notaffected. No other flags are affected.Only direct addressing is allowed for the source operand.Example:Set the carry flag if, and only if, P1.0 = 1, ACC.7 = 1, and OV = 0:MOV C,P1.0;LOAD CARRY WITH INPUT PIN STATEANL C,ACC.7;AND CARRY WITH ACCUM. BIT 7ANL C,/OV;AND WITH INVERSE OF OVERFLOW FLAGANL C,bitBytes:2Cycles:2Encoding:10000010bit addressOperation:ANL(C) ← (C) ∧ (bit)ANL C,/bitBytes:2Cycles:2Encoding:10110000bit addressOperation:ANL(C) ← (C) ∧ (bit)160509C–8051–07/06170509C–8051–07/06CJNE <dest-byte>,<src-byte>, relFunction:Compare and Jump if Not Equal.Description:CJNE compares the magnitudes of the first two operands and branches if their values are not equal. The branchdestination is computed by adding the signed relative-displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of <dest-byte> is less than the unsigned integer value of <src-byte>; otherwise, the carry is cleared. Neither operand is affected.The first two operands allow four addressing mode combinations: the Accumulator may be compared with any directly addressed byte or immediate data, and any indirect RAM location or working register can be compared with an immediate constant.Example:The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence,CJNER7, # 60H, NOT_EQ ;. . . . . . . . ;R7 = 60H.NOT_EQ: JC REQ_LOW ;IF R7 < 60H.;. . .. . . . .;R7 > 60H.sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag, this instruction determines whether R7 is greater or less than 60H.If the data being presented to Port 1 is also 34H, then the following instruction,WAIT :CJNE A, P1,WAITclears the carry flag and continues with the next instruction in sequence, since the Accumulator does equal thedata read from P1. (If some other value was being input on P1, the program loops at this point until the P1 data changes to 34H.)CJNE A,direct,relBytes:3Cycles:2Encoding:11111direct addressrel. addressOperation:(PC) ← (PC) + 3IF (A) < > (direct )THEN(PC) ← (PC) + relative offset IF (A) < (direct )THEN(C) ← 1ELSE(C) ← 0CJNE A,#data,relBytes:3Cycles:2Encoding:10110100immediate data rel.addressOperation:(PC) ← (PC) + 3IF (A) < > dataTHEN(PC) ← (PC) + relative offsetIF (A) < dataTHEN(C) ← 1ELSE(C) ← 0CJNE R n,#data,relBytes:3Cycles:2Encoding:10111r r r immediate data rel. addressOperation:(PC) ← (PC) + 3IF (R n) < > dataTHEN(PC) ← (PC) + relative offsetIF (R n) < dataTHEN(C) ← 1ELSE(C) ← 0CJNE @R i,data,relBytes:3Cycles:2Encoding:1011011i immediate data rel.addressOperation:(PC) ← (PC) + 3IF ((R i)) < > dataTHEN(PC) ← (PC) + relative offsetIF ((R i)) < dataTHEN(C) ← 1ELSE(C) ← 0180509C–8051–07/06190509C–8051–07/06Function:Clear AccumulatorDescription:CLR A clears the Accumulator (all bits set to 0). No flags are affectedExample:The Accumulator contains 5CH (01011100B). The following instruction,CLR Aleaves the Accumulator set to 00H(00000000B).Bytes:1Cycles:1Operation:CLR(bit) ← 0Function:Complement AccumulatorDescription:CPLA logically complements each bit of the Accumulator (one’s complement). Bits which previously contained a1 are changed to a 0 and vice-versa. No flags are affected.Example:The Accumulator contains 5CH (01011100B). The following instruction,CPL Aleaves the Accumulator set to 0A3H (10100011B).Bytes:1Cycles:1Operation:CPL(bit) ← (bit)200509C–8051–07/06210509C–8051–07/06DA AFunction:Decimal-adjust Accumulator for AdditionDescription:DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two variables (each inpacked-BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used toperform the addition.If Accumulator bits 3 through 0 are greater than nine (xxxx1010-xxxx1111), or if the AC flag is one, six is added tothe Accumulator producing the proper BCD digit in the low-order nibble. This internal addition sets the carry flagif a carry-out of the low-order four-bit field propagates through all high-order bits, but it does not clear the carryflag otherwise.If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxxx-1111xxxx), these high-orderbits are incremented by six, producing the proper BCD digit in the high-order nibble. Again, this sets the carryflag if there is a carry-out of the high-order bits, but does not clear the carry. The carry flag thus indicates if thesum of the original two BCD variables is greater than 100, allowing multiple precision decimal addition. OV is notaffected.All of this occurs during the one instruction cycle. Essentially, this instruction performs the decimal conversion byadding 00H, 06H, 60H, or 66H to the Accumulator, depending on initial Accumulator and PSW conditions.Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation, nor does DAAapply to decimal subtraction.Example:The Accumulator holds the value 56H (01010110B), representing the packed BCD digits of the decimal number56. Register 3 contains the value 67H (01100111B), representing the packed BCD digits of the decimal number67. The carry flag is set. The following instruction sequenceADDCA,R3 DA Afirst performs a standard two’s-complement binary addition, resulting in the value 0BEH (10111110) in theAccumulator. The carry and auxiliary carry flags are cleared.The Decimal Adjust instruction then alters the Accumulator to the value 24H (00100100B), indicating the packedBCD digits of the decimal number 24, the low-order two digits of the decimal sum of 56, 67, and the carry-in. Thecarry flag is set by the Decimal Adjust instruction, indicating that a decimal overflow occurred. The true sum of56, 67, and 1 is 124.BCD variables can be incremented or decremented by adding 01H or 99H. If the Accumulator initially holds 30H(representing the digits of 30 decimal), then the following instruction sequence,ADD A, # 99HDA Aleaves the carry set and 29H in the Accumulator, since 30 + 99 = 129. The low-order byte of the sum can beinterpreted to mean 30 - 1 = 29.Bytes:1Cycles:1Encoding:11010100Operation:DA-contents of Accumulator are BCDIF [[(A 3-0) > 9] ∨ [(AC) = 1]]THEN (A 3-0) ← (A 3-0) + 6ANDIF [[(A 7-4) > 9] ∨[(C) = 1]]THEN (A 7-4) ← (A 7-4) + 6DEC byteFunction:DecrementDescription:DEC byte decrements the variable indicated by 1. An original value of 00H underflows to 0FFH. No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect.Note: When this instruction is used to modify an output port, the value used as the original port data will be readfrom the output data latch, not the input pins.Example:Register 0 contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain 00H and 40H, respectively.The following instruction sequence,DEC@R0DEC R0DEC@R0leaves register 0 set to 7EH and internal RAM locations 7EH and 7FH set to 0FFH and 3FH.DEC ABytes:1Cycles:1Encoding:00010100Operation:DEC(A) ← (A) - 1DEC R nBytes:1Cycles:1Encoding:00011r r rOperation:DEC(R n) ← (R n) - 1DEC directBytes:2Cycles:1Encoding:00010101direct addressOperation:DEC(direct) ← (direct) - 1DEC @R iBytes:1Cycles:1Encoding:0001011iOperation:DEC((R i)) ← ((R i)) - 1220509C–8051–07/06230509C–8051–07/06DIV ABFunction:DivideDescription:DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit integer in register B.The Accumulator receives the integer part of the quotient; register B receives the integer remainder. The carryand OV flags are cleared.Exception : if B had originally contained 00H, the values returned in the Accumulator and B-register areundefined and the overflow flag are set. The carry flag is cleared in any case.Example:The Accumulator contains 251 (0FBH or 11111011B) and B contains 18 (12H or 00010010B). The followinginstruction,DIV ABleaves 13 in the Accumulator (0DH or 00001101B) and the value 17 (11H or 00010001B) in B, since251 = (13 x 18) + 17. Carry and OV are both cleared.Bytes:1Cycles:4Encoding:10000100Operation:DIV(A)15-8 ← (A)/(B)(B)7-0DJNZ<byte>,<rel-addr>Function:Decrement and Jump if Not ZeroDescription:DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00H underflows to 0FFH. No flags are affected. The branchdestination is computed by adding the signed relative-displacement value in the last instruction byte to the PC,after incrementing the PC to the first byte of the following instruction.The location decremented may be a register or directly addressed byte.Note: When this instruction is used to modify an output port, the value used as the original port data will be readfrom the output data latch, not the input pins.Example:Internal RAM locations 40H, 50H, and 60H contain the values 01H, 70H, and 15H, respectively. The following instruction sequence,DJNZ40H,LABEL_1DJNZ50H,LABEL_2DJNZ60H,LABEL_3causes a jump to the instruction at label LABEL_2 with the values 00H, 6FH, and 15H in the three RAMlocations. The first jump was not taken because the result was zero.This instruction provides a simple way to execute a program loop a given number of times or for adding amoderate time delay (from 2 to 512 machine cycles) with a single instruction. The following instruction sequence,MOV R2, # 8TOGGLE: CPL P1.7DJNZ R2,TOGGLEtoggles P1.7 eight times, causing four output pulses to appear at bit 7 of output Port 1. Each pulse lasts threemachine cycles; two for DJNZ and one to alter the pin.DJNZ R n,relBytes:2Cycles:2Encoding:11011r r r rel. addressOperation:DJNZ(PC) ← (PC) + 2(R n) ← (R n) - 1IF (R n) > 0 or (R n) < 0THEN(PC) ← (PC) + relDJNZ direct,relBytes:3Cycles:2Encoding:11010101direct address rel.addressOperation:DJNZ(PC) ← (PC) + 2(direct) ← (direct) - 1IF (direct) > 0 or (direct) < 0THEN(PC) ← (PC) + rel240509C–8051–07/06250509C–8051–07/06INC <byte>Function:IncrementDescription:INC increments the indicated variable by 1. An original value of 0FFH overflows to 00H. No flags are affected.Three addressing modes are allowed: register, direct, or register-indirect.Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.Example:Register 0 contains 7EH (011111110B). Internal RAM locations 7EH and 7FH contain 0FFH and 40H,respectively. The following instruction sequence,INC @R0INC R0INC @R0leaves register 0 set to 7FH and internal RAM locations 7EH and 7FH holding 00H and 41H, respectively.INC ABytes:1Cycles:1Encoding:00000100Operation:INC(A) ← (A) + 1INC R nBytes:1Cycles:1Encoding:00001r r rOperation:INC(R n ) ← (R n ) + 1INC directBytes:2Cycles:1Encoding:00000101direct addressOperation:INC(direct) ← (direct) + 1INC @R iBytes:1Cycles:1Encoding:0000011iOperation:INC((R i )) ← ((R i )) + 1INC DPTRFunction:Increment Data PointerDescription:INC DPTR increments the 16-bit data pointer by 1. A 16-bit increment (modulo 216) is performed, and an overflow of the low-order byte of the data pointer (DPL) from 0FFH to 00H increments the high-order byte (DPH).No flags are affected.This is the only 16-bit register which can be incremented.Example:Registers DPH and DPL contain 12H and 0FEH, respectively. The following instruction sequence,INC DPTRINC DPTRINC DPTRchanges DPH and DPL to 13H and 01H.Bytes:1Cycles:2Operation:JB(PC) ← (PC) + 3IF (bit) = 1THEN(PC) ← (PC) + rel260509C–8051–07/06270509C–8051–07/06JBC bit,relFunction:Jump if Bit is set and Clear bitDescription:If the indicated bit is one, JBC branches to the address indicated; otherwise, it proceeds with the next instruction.The bit will not be cleared if it is already a zero . The branch destination is computed by adding the signedrelative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the nextinstruction. No flags are affected.Note: When this instruction is used to test an output pin, the value used as the original data will be read from theoutput data latch, not the input pin.Example:The Accumulator holds 56H (01010110B). The following instruction sequence,JBCACC.3,LABEL1 JBC ACC.2,LABEL2causes program execution to continue at the instruction identified by the label LABEL2, with the Accumulatormodified to 52H (01010010B).Bytes:3Cycles:2Operation:JC(PC) ← (PC) + 2IF (C) = 1THEN(PC) ← (PC) + relJMP @A+DPTRFunction:Jump indirectDescription:JMP @A+DPTR adds the eight-bit unsigned contents of the Accumulator with the 16-bit data pointer and loads the resulting sum to the program counter. This is the address for subsequent instruction fetches. Sixteen-bitaddition is performed (modulo 216): a carry-out from the low-order eight bits propagates through the higher-orderbits. Neither the Accumulator nor the Data Pointer is altered. No flags are affected.Example:An even number from 0 to 6 is in the Accumulator. The following sequence of instructions branches to one of four AJMP instructions in a jump table starting at JMP_TBL.MOV DPTR, # JMP_TBLJMP@A + DPTRJMP_TBL:AJMP LABEL0AJMP LABEL1AJMP LABEL2AJMP LABEL3If the Accumulator equals 04H when starting this sequence, execution jumps to label LABEL2. Because AJMP isa 2-byte instruction, the jump instructions start at every other address.Bytes:1Cycles:2Encoding:01110011Operation:JMP(PC) ← (A) + (DPTR)280509C–8051–07/06290509C–8051–07/06Function:Jump if Bit Not setDescription:If the indicated bit is a 0, JNB branches to the indicated address; otherwise, it proceeds with the next instruction.The branch destination is computed by adding the signed relative-displacement in the third instruction byte to thePC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified . No flags areaffected.Example:The data present at input port 1 is 11001010B. The Accumulator holds 56H (01010110B). The followinginstruction sequence,JNBP1.3,LABEL1JNB ACC.3,LABEL2causes program execution to continue at the instruction at label LABEL2.Bytes:3Cycles:2Operation:JNC(PC) ← (PC) + 2IF (C) = 0THEN (PC) ← (PC) + relFunction:Jump if Accumulator Not ZeroDescription:If any bit of the Accumulator is a one, JNZ branches to the indicated address; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the secondinstruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags areaffected.Example:The Accumulator originally holds 00H. The following instruction sequence,JNZ LABEL1INC AJNZ LABEL2sets the Accumulator to 01H and continues at label LABEL2.Bytes:2Cycles:2Operation:JZ(PC) ← (PC) + 2IF (A) = 0THEN (PC) ← (PC) + rel300509C–8051–07/06310509C–8051–07/06LCALL addr16Function:Long callDescription:LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter togenerate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first),incrementing the Stack Pointer by two. The high-order and low-order bytes of the PC are then loaded,respectively, with the second and third bytes of the LCALL instruction. Program execution continues with theinstruction at this address. The subroutine may therefore begin anywhere in the full 64K byte program memoryaddress space. No flags are affected.Example:Initially the Stack Pointer equals 07H. The label SUBRTN is assigned to program memory location 1234H. Afterexecuting the instruction,LCALL SUBRTNat location 0123H, the Stack Pointer will contain 09H, internal RAM locations 08H and 09H will contain 26H and 01H, and the PC will contain 1234H.Bytes:3Cycles:2Operation:LJMP(PC) ← addr 15-0MOV <dest-byte>,<src-byte>Function:Move byte variableDescription:The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected.This is by far the most flexible operation. Fifteen combinations of source and destination addressing modes areallowed.Example:Internal RAM location 30H holds 40H. The value of RAM location 40H is 10H. The data present at input port 1 is 11001010B (0CAH).MOV R0,#30H;R0 < = 30HMOV A,@R0;A < = 40HMOV R1,A;R1 < = 40HMOV B,@R1;B < = 10HMOV@R1,P1;RAM (40H) < = 0CAHMOV P2,P1;P2 #0CAHleaves the value 30H in register 0, 40H in both the Accumulator and register 1, 10H in register B, and 0CAH(11001010B) both in RAM location 40H and output on port 2.MOV A,R nBytes:1Cycles:1Encoding:11101r r rOperation:MOV(A) ← (R n)*MOV A,directBytes:2Cycles:1Encoding:11100101direct addressOperation:MOV(A) ← (direct)* MOV A,ACC is not a valid Instruction.MOV A,@R iBytes:1Cycles:1Encoding:1110011iOperation:MOV(A) ← ((R i))320509C–8051–07/06330509C–8051–07/06MOV A,#dataBytes:2Cycles:1Encoding:01110100immediate data Operation:MOV(A) ← #dataMOV R n ,ABytes:1Cycles:1Encoding:11111r r rOperation:MOV(R n ) ← (A)MOV R n ,directBytes:2Cycles:2Encoding:10101r r rdirect addr.Operation:MOV(R n ) ← (direct)MOV R n ,#dataBytes:2Cycles:1Encoding:01111r r rimmediate data Operation:MOV(R n ) ← #dataMOV direct,ABytes:2Cycles:1Encoding:11110101direct address Operation:MOV(direct) ← (A)MOV direct,R nBytes:2Cycles:2Encoding:10001r r rdirect address Operation:MOV(direct) ← (R n )MOV direct,directBytes:3Cycles:2Encoding:10000101dir. addr. (dest) dir. addr. (scr)Operation:MOV(direct) ← (direct)MOV direct,@R iBytes:2Cycles:2Encoding:1000011i direct addr.Operation:MOV(direct) ← ((R i))MOV direct,#dataBytes:3Cycles:2Encoding:01110101direct address immediate dataOperation:MOV(direct) ← #dataMOV @R i,ABytes:1Cycles:1Encoding:1111011iOperation:MOV((R i)) ← (A)MOV @R i,directBytes:2Cycles:2Encoding:1010011i direct addr.Operation:MOV((R i)) ← (direct)MOV @R i,#dataBytes:2Cycles:1Encoding:0111011i immediate dataOperation:MOV((R i)) ← #data340509C–8051–07/06350509C–8051–07/06MOV <dest-bit>,<src-bit>Function:Move bit dataDescription:MOV <dest-bit>,<src-bit> copies the Boolean variable indicated by the second operand into the locationspecified by the first operand. One of the operands must be the carry flag; the other may be any directlyaddressable bit. No other register or flag is affected.Example:The carry flag is originally set. The data present at input Port 3 is 11000101B. The data previously written tooutput Port 1 is 35H (00110101B).MOVP1.3,C MOVC,P3.3MOV P1.2,Cleaves the carry cleared and changes Port 1 to 39H (00111001B).MOV C,bitBytes:2Cycles:1Operation:MOV(DPTR) ← #data 15-0DPH ← DPL ← #data 15-8 ← #data 7-0。
8051 Instruction Set
8051 Instruction SetAlphabetical List of Instructions∙ACALL - Absolute Call∙ADD, ADDC - Add Accumulator (With Carry)∙AJMP - Absolute Jump∙ANL - Bitwise AND∙CJNE - Compare and Jump if Not Equal∙CLR - Clear Register∙CPL - Complement Register∙DA - Decimal Adjust∙DEC - Decrement Register∙DIV - Divide Accumulator by B∙DJNZ - Decrement Register and Jump if Not Zero ∙INC - Increment Register∙JB - Jump if Bit Set∙JBC - Jump if Bit Set and Clear Bit∙JC - Jump if Carry Set∙JMP - Jump to Address∙JNB - Jump if Bit Not Set∙JNC - Jump if Carry Not Set∙JNZ - Jump if Accumulator Not Zero∙JZ - Jump if Accumulator Zero∙LCALL - Long Call∙LJMP - Long Jump∙MOV - Move Memory∙MOVC - Move Code Memory∙MOVX - Move Extended Memory∙MUL - Multiply Accumulator by B∙NOP - No Operation∙ORL - Bitwise OR∙POP - Pop Value From Stack∙PUSH - Push Value Onto Stack∙RET - Return From Subroutine∙RETI - Return From Interrupt∙RL - Rotate Accumulator Left∙RLC - Rotate Accumulator Left Through Carry∙RR - Rotate Accumulator Right∙RRC - Rotate Accumulator Right Through Carry ∙SETB - Set Bit∙SJMP - Short Jump∙SUBB - Subtract From Accumulator With Borrow ∙SWAP - Swap Accumulator Nibbles∙XCH - Exchange Bytes∙XCHD - Exchange Digits∙XRL - Bitwise Exclusive OR∙Undefined - Undefined Instruction8051 Instruction Set: ACALLOperation:ACALLFunction:Absolute Call Within 2K BlockSyntax:ACALL code addressDescription: ACALL unconditionally calls a subroutine at the indicated code address. ACALL pushes the address of the instruction that follows ACALL onto the stack, least-significant-byte first, most-significant-byte second. The Program Counter is then updated so that program execution continues at the indicated address.The new value for the Program Counter is calculated by replacing the least-significant-byte of the Program Counter with the second byte of the ACALL instruction, and replacing bits 0-2 of the most-significant-byte of the Program Counter with 3 bits that indicate the page. Bits 3-7 of the most-significant-byte of the Program Counter remain unchaged.Since only 11 bits of the Program Counter are affected by ACALL, calls may only be made to routines located within the same 2k block as the first byte that follows ACALL.See Also: LCALL, RET8051 Instruction Set: ADDOperation:ADD, ADDCFunction:Add Accumulator, Add Accumulator With CarrySyntax:ADD A,operandADDC A,operandDescription: Description: ADD and ADDC both add the value operand to the value of the Accumulator, leaving the resulting value in the Accumulator. The value operand is not affected.ADD and ADDC function identically except that ADDC adds the value of operand as well as the value of the Carry flag whereas ADD does not add the Carry flag to the result.The Carry bit (C) is set if there is a carry-out of bit 7. In other words, if the unsigned summed value of the Accumulator, operand and (in the case of ADDC) the Carry flag exceeds 255 Carry is set. Otherwise, the Carry bit is cleared.The Auxillary Carry (AC) bit is set if there is a carry-out of bit 3. In other words, if the unsigned summed value of the low nibble of the Accumulator,operand and (in the case of ADDC) the Carry flag exceeds 15 the Auxillary Carry flag is set. Otherwise, the Auxillary Carry flag is cleared.The Overflow (OV) bit is set if there is a carry-out of bit 6 or out of bit 7, but not both. In other words, if the addition of the Accumulator, operand and (in the case of ADDC) the Carry flag treated as signed values results in a value that is out of the range of a signed byte (-128 through +127) the Overflow flag is set. Otherwise, the Overflow flag is cleared.See Also:SUBB, DA, INC, DEC8051 Instruction Set: AJMPOperation:AJMPFunction:Absolute Jump Within 2K BlockSyntax:AJMP code addressDescription: AJMP unconditionally jumps to the indicated code address. The new value for the Program Counter is calculated by replacing the least-significant-byte of the Program Counter with the second byte of the AJMP instruction, and replacing bits 0-2 of the most-significant-byte of the Program Counter with 3 bits that indicate the page of the byte following the AJMP instruction. Bits 3-7 of the most-significant-byte of the Program Counter remain unchaged.Since only 11 bits of the Program Counter are affected by AJMP, jumps may only be made to code located within the same 2k block as the first byte that follows AJMP.See Also: LJMP, SJMP8051 Instruction Set: ANLOperation:ANLFunction:Bitwise ANDSyntax:ANL operand1, operand2Description: ANL does a bitwise "AND" operation between operand1 and operand2, leaving the resulting value in operand1. The value of operand2 is not affected. A logical "AND" compares the bits of each operand and sets the corresponding bit in the resulting byte only if the bit was set in both of the original operands, otherwise the resulting bit is cleared.See Also:ORL, XRL8051 Instruction Set: CJNEOperation:CJNEFunction:Compare and Jump If Not EqualSyntax:CJNE operand1,operand2,reladdrDescription: CJNE compares the value of operand1 and operand2 and branches to the indicated relative address if operand1 and operand2 are not equal. If the two operands are equal program flow continues with the instruction following the CJNE instruction.The Carry bit (C) is set if operand1 is less than operand2, otherwise it is cleared.See Also:DJNZ8051 Instruction Set: CLROperation:CLRFunction:Clear RegisterSyntax:CLR registerDescription: CLR clears (sets to 0) all the bit(s) of the indicated register. If the register is a bit (including the carry bit), only the specified bit is affected. Clearing the Accumulator sets the Accumulator's value to 0.See Also:SETB8051 Instruction Set: CPLOperation:CPLFunction:Complement RegisterSyntax:CPL operandDescription: CPL complements operand, leaving the result in operand. If operand is a single bit then the state of the bit will be reversed. If operand is the Accumulator then all the bits in the Accumulator will be reversed. This can be thought of as "Accumulator Logical Exclusive OR 255" or as "255-Accumulator." If the operand refers to a bit of an output Port, the value that will be complemented is based on the last value written to that bit, not the last value read from it. See Also: CLR, SETB8051 Instruction Set: DAOperation:DAFunction:Decimal Adjust AccumulatorSyntax:DA ADescription: DA adjusts the contents of the Accumulator to correspond to a BCD (Binary Coded Decimal) number after two BCD numbers have been added by the ADD or ADDC instruction. If the carry bit is set or if the value of bits 0-3 exceed 9, 0x06 is added to theaccumulator. If the carry bit was set when the instruction began, or if 0x06 was added to the accumulator in the first step, 0x60 is added to the accumulator.The Carry bit (C) is set if the resulting value is greater than 0x99, otherwise it is cleared. See Also:ADD, ADDC8051 Instruction Set: DECOperation:DECFunction:Decrement RegisterSyntax:DEC registerDescription: DEC decrements the value of register by 1. If the initial value of register is 0, decrementing the value will cause it to reset to 255 (0xFF Hex). Note: The Carry Flag is NOT set when the value "rolls over" from 0 to 255.See Also:INC, SUBB8051 Instruction Set: DIVOperation:DIVFunction:Divide Accumulator by BSyntax:DIV ABDescription: Divides the unsigned value of the Accumulator by the unsigned value of the "B" register. The resulting quotient is placed in the Accumulator and the remainder is placed in the "B" register.The Carry flag (C) is always cleared.The Overflow flag (OV) is set if division by 0 was attempted, otherwise it is cleared.See Also:MUL AB8051 Instruction Set: DJNZOperation:DJNZFunction:Decrement and Jump if Not ZeroSyntax:DJNZ register,reladdrDescription: DJNZ decrements the value of register by 1. If the initial value of register is 0, decrementing the value will cause it to reset to 255 (0xFF Hex). If the new value of register is not 0 the program will branch to the address indicated by relative addr. If the new valueof register is 0 program flow continues with the instruction following the DJNZ instruction. See Also:DEC, JZ, JNZ8051 Instruction Set: INCOperation:INCFunction:Increment RegisterSyntax:INC registerDescription: INC increments the value of register by 1. If the initial value of register is 255 (0xFF Hex), incrementing the value will cause it to reset to 0. Note: The Carry Flag is NOT set when the value "rolls over" from 255 to 0.In the case of "INC DPTR", the value two-byte unsigned integer value of DPTR is incremented. If the initial value of DPTR is 65535 (0xFFFF Hex), incrementing the value will cause it to reset to 0. Again, the Carry Flag is NOT set when the value of DPTR "rolls over" from 65535 to 0. See Also:ADD, ADDC, DEC8051 Instruction Set: JBOperation:JBFunction:Jump if Bit SetSyntax:JB bit addr, reladdrDescription: JB branches to the address indicated by reladdr if the bit indicated by bit addr is set. If the bit is not set program execution continues with the instruction following the JB instruction.See Also:JBC, JNB8051 Instruction Set: JBCOperation:JBCFunction:Jump if Bit Set and Clear BitSyntax:JB bit addr, reladdrDescription: JBC will branch to the address indicated by reladdr if the bit indicated by bit addr is set. Before branching to reladdr the instruction will clear the indicated bit. If the bit is not set program execution continues with the instruction following the JBC instruction.See Also:JB, JNB8051 Instruction Set: JCOperation:JCFunction:Jump if Carry SetSyntax:JC reladdrDescription: JC will branch to the address indicated by reladdr if the Carry Bit is set. If the Carry Bit is not set program execution continues with the instruction following the JC instruction.See Also:JNC8051 Instruction Set: JMPOperation:JMPFunction:Jump to Data Pointer + AccumulatorSyntax:JMP @A+DPTRDescription: JMP jumps unconditionally to the address represented by the sum of the value of DPTR and the value of the Accumulator.See Also:LJMP, AJMP, SJMP8051 Instruction Set: JNBOperation:JNBFunction:Jump if Bit Not SetSyntax:JNB bit addr,reladdrDescription: JNB will branch to the address indicated by reladdress if the indicated bit is not set. If the bit is set program execution continues with the instruction following the JNB instruction.See Also:JB, JBC8051 Instruction Set: JNCOperation:JNCFunction:Jump if Carry Not SetSyntax:JNC reladdrDescription: JNC branches to the address indicated by reladdr if the carry bit is not set. If the carry bit is set program execution continues with the instruction following the JNB instruction.See Also:JC8051 Instruction Set: JNZOperation:JNZFunction:Jump if Accumulator Not ZeroSyntax:JNZ reladdrDescription: JNZ will branch to the address indicated by reladdr if the Accumulator contains any value except 0. If the value of the Accumulator is zero program execution continues with the instruction following the JNZ instruction.See Also:JZ8051 Instruction Set: JZOperation:JZFunction:Jump if Accumulator ZeroSyntax:JNZ reladdrDescription: JZ branches to the address indicated by reladdr if the Accumulator contains the value 0. If the value of the Accumulator is non-zero program execution continues with the instruction following the JNZ instruction.See Also:JNZ8051 Instruction Set: LCALLOperation:LCALLFunction:Long CallSyntax:LCALL code addrDescription: LCALL calls a program subroutine. LCALL increments the program counter by 3 (to point to the instruction following LCALL) and pushes that value onto the stack (low byte first, high byte second). The Program Counter is then set to the 16-bit value which follows the LCALL opcode, causing program execution to continue at that address.See Also:ACALL, RET8051 Instruction Set: LJMPOperation:LJMPFunction:Long JumpSyntax:LJMP code addrDescription: LJMP jumps unconditionally to the specified code addr.See Also:AJMP, SJMP, JMP8051 Instruction Set: MOVOperation:MOVFunction:Move MemorySyntax:MOV operand1,operand2Description: MOV copies the value of operand2 into operand1. The value of operand2 is not affected. Both operand1 and operand2 must be in Internal RAM. No flags are affected unless the instruction is moving the value of a bit into the carry bit in which case the carry bit is affected or unless the instruction is moving a value into the PSW register (which contains all the program flags).** Note: In the case of "MOV iram addr,iram addr", the operand bytes of the instruction are stored in reverse order. That is, the instruction consisting of the bytes 0x85, 0x20, 0x50 means "Move the contents of Internal RAM location 0x20 to Internal RAM location 0x50" whereas the opposite would be generally presumed.See Also:MOVC, MOVX, XCH, XCHD, PUSH, POP8051 Instruction Set: MOVCOperation:MOVCFunction:Move Code Byte to AccumulatorSyntax:MOVC A,@A+registerDescription: MOVC moves a byte from Code Memory into the Accumulator. The Code Memory address from which the byte will be moved is calculated by summing the value of the Accumulator with either DPTR or the Program Counter (PC). In the case of the Program Counter, PC is first incremented by 1 before being summed with the Accumulator.See Also:MOV, MOVX8051 Instruction Set: MOVXOperation:MOVXFunction:Move Data To/From External Memory (XRAM)Syntax:MOVX operand1,operand2Description: MOVX moves a byte to or from External Memory into or from the Accumulator.If operand1 is @DPTR, the Accumulator is moved to the 16-bit External Memory address indicated by DPTR. This instruction uses both P0 (port 0) and P2 (port 2) to output the 16-bit address and data. If operand2 is DPTR then the byte is moved from External Memory into the Accumulator.If operand1 is @R0 or @R1, the Accumulator is moved to the 8-bit External Memory address indicated by the specified Register. This instruction uses only P0 (port 0) to output the 8-bit address and data. P2 (port 2) is not affected. If operand2 is @R0 or @R1 then the byte is moved from External Memory into the Accumulator.See Also:MOV, MOVC8051 Instruction Set: MULOperation:MULFunction:Multiply Accumulator by BSyntax:MUL ABDescription: Multiples the unsigned value of the Accumulator by the unsigned value of the "B" register. The least significant byte of the result is placed in the Accumulator and themost-significant-byte is placed in the "B" register.The Carry Flag (C) is always cleared.The Overflow Flag (OV) is set if the result is greater than 255 (if the most-significant byte is not zero), otherwise it is cleared.See Also:DIV8051 Instruction Set: NOPOperation:NOPFunction:None, waste timeSyntax:No OperationDescription: NOP, as it's name suggests, causes No Operation to take place for one machine cycle. NOP is generally used only for timing purposes. Absolutely no flags or registers are affected.8051 Instruction Set: ORLOperation:ORLFunction:Bitwise ORSyntax:ORL operand1,operand2Description: ORL does a bitwise "OR" operation between operand1 and operand2, leaving the resulting value in operand1. The value of operand2 is not affected. A logical "OR" compares the bits of each operand and sets the corresponding bit in the resulting byte if the bit was set in either of the original operands, otherwise the resulting bit is cleared.See Also:ANL, XRL8051 Instruction Set: POPOperation:POPFunction:Pop Value From StackSyntax:POPDescription: POP "pops" the last value placed on the stack into the iram addr specified. In other words, POP will load iram addr with the value of the Internal RAM address pointed to by the current Stack Pointer. The stack pointer is then decremented by 1.See Also:PUSH8051 Instruction Set: PUSHOperation:PUSHFunction:Push Value Onto StackSyntax:PUSHDescription: PUSH "pushes" the value of the specified iram addr onto the stack. PUSH first increments the value of the Stack Pointer by 1, then takes the value stored in iram addr and stores it in Internal RAM at the location pointed to by the incremented Stack Pointer.See Also:POP8051 Instruction Set: RETOperation:RETFunction:Return From SubroutineSyntax:RETDescription: RET is used to return from a subroutine previously called by LCALL or ACALL. Program execution continues at the address that is calculated by popping the topmost 2 bytes off the stack. The most-significant-byte is popped off the stack first, followed by theleast-significant-byte.See Also:LCALL, ACALL, RETI8051 Instruction Set: RETIOperation:RETIFunction:Return From InterruptSyntax:RETIDescription: RETI is used to return from an interrupt service routine. RETI first enables interrupts of equal and lower priorities to the interrupt that is terminating. Program execution continues at the address that is calculated by popping the topmost 2 bytes off the stack. The most-significant-byte is popped off the stack first, followed by the least-significant-byte.RETI functions identically to RET if it is executed outside of an interrupt service routine.See Also:RET8051 Instruction Set: RLOperation:RLFunction:Rotate Accumulator LeftSyntax:RL ADescription: Shifts the bits of the Accumulator to the left. The left-most bit (bit 7) of the Accumulator is loaded into bit 0.See Also:RLC, RR, RRC8051 Instruction Set: RLCOperation:RLCFunction:Rotate Accumulator Left Through CarrySyntax:RLC ADescription: Shifts the bits of the Accumulator to the left. The left-most bit (bit 7) of the Accumulator is loaded into the Carry Flag, and the original Carry Flag is loaded into bit 0 of the Accumulator. This function can be used to quickly multiply a byte by 2.See Also:RL, RR, RRC8051 Instruction Set: RROperation:RRFunction:Rotate Accumulator RightSyntax:RR ADescription: Shifts the bits of the Accumulator to the right. The right-most bit (bit 0) of the Accumulator is loaded into bit 7.See Also:RL, RLC, RRC8051 Instruction Set: RRCOperation:RRCFunction:Rotate Accumulator Right Through CarrySyntax:RRC ADescription: Shifts the bits of the Accumulator to the right. The right-most bit (bit 0) of the Accumulator is loaded into the Carry Flag, and the original Carry Flag is loaded into bit 7. This function can be used to quickly divide a byte by 2.See Also:RL, RLC, RR8051 Instruction Set: SETBOperation:SETBFunction:Set BitSyntax:SETB bit addrDescription: Sets the specified bit.See Also:CLR8051 Instruction Set: SJMPOperation:SJMPFunction:Short JumpSyntax:SJMP reladdrDescription: SJMP jumps unconditionally to the address specified reladdr. Reladdr must be within -128 or +127 bytes of the instruction that follows the SJMP instruction.See Also:LJMP, AJMP8051 Instruction Set: SUBBOperation:SUBBFunction:Subtract from Accumulator With BorrowSyntax:SUBB A,operandDescription: SUBB subtract the value of operand from the value of the Accumulator, leaving the resulting value in the Accumulator. The value operand is not affected.The Carry Bit (C) is set if a borrow was required for bit 7, otherwise it is cleared. In other words, if the unsigned value being subtracted is greater than the Accumulator the Carry Flag is set.The Auxillary Carry (AC) bit is set if a borrow was required for bit 3, otherwise it is cleared. In other words, the bit is set if the low nibble of the value being subtracted was greater than the low nibble of the Accumulator.The Overflow (OV) bit is set if a borrow was required for bit 6 or for bit 7, but not both. In other words, the subtraction of two signed bytes resulted in a value outside the range of a signed byte (-128 to 127). Otherwise it is cleared.See Also:ADD, ADDC, DEC8051 Instruction Set: SWAPOperation:SWAPFunction:Swap Accumulator NibblesSyntax:SWAP ADescription: SWAP swaps bits 0-3 of the Accumulator with bits 4-7 of the Accumulator. This instruction is identical to executing "RR A" or "RL A" four times.See Also:RL, RLC, RR, RRC8051 Instruction Set: Undefined InstructionOperation:Undefined InstructionFunction:UndefinedSyntax:???Description: The "Undefined" instruction is, as the name suggests, not a documented instruction. The 8051 supports 255 instructions and OpCode 0xA5 is the single OpCode that is not used by any documented function. Since it is not documented nor defined it is not recommended that it be executed. However, based on my research, executing this undefined instruction takes 1 machine cycle and appears to have no effect on the system except that the Carry Bit always seems to be set.Note: We received input from an user that the undefined instruction really has a format of Undefined bit1,bit2 and effectively copies the value of bit2 to bit1. In this case, it would be a three-byte instruction. We haven't had an opportunity to verify or disprove this report, so we present it to the world as "additional information."Note: It has been reported that Philips 8051 model P89C669 uses instruction prefix 0xA5 to let the user access a different (extended) SFR area.8051 Instruction Set: XCHOperation:XCHFunction:Exchange BytesSyntax:XCH A,registerDescription: Exchanges the value of the Accumulator with the value contained in register. See Also:MOV8051 Instruction Set: XCHDOperation:XCHDFunction:Exchange DigitSyntax:XCHD A,[@R0/@R1]Description: Exchanges bits 0-3 of the Accumulator with bits 0-3 of the Internal RAM address pointed to indirectly by R0 or R1. Bits 4-7 of each register are unaffected.See Also:DA8051 Instruction Set: XRLOperation:XRLFunction:Bitwise Exclusive ORSyntax:XRL operand1,operand2Description: XRL does a bitwise "EXCLUSIVE OR" operationbetween operand1 and operand2, leaving the resulting value in operand1. The value of operand2 is not affected. A logical "EXCLUSIVE OR" compares the bits of each operand and sets the corresponding bit in the resulting byte if the bit was set in either (but not both) of the original operands, otherwise the bit is cleared.See Also:ANL, ORL。
8051指令总结
8051指令总结第一篇：8051指令总结指令总结共性：（1）立即数不能用作目的操作数。
（2）以累加器A为目的操作数的指令影响P标志位。
（3）Rn与Rn、Rn 与@Ri、@Ri与@Ri不能同时出现在指令的源、目的操作数中。
操作数的表现形式：内部RAM：A、Rn、@Ri、direct、#data 外部RAM：@DPTR、@Ri 外部ROM：@A+DPTR、@A+PC一、数据传送指令（5种/29条）对标志位的影响：除以累加器A为目的操作数的数据传送指令对P标志位有影响外，其余数据传送指令均不影响标志位。
格式：MOV , ；←（一）内部RAM数据传送指令 1.指令操作码：MOV 2.源、目的操作数均在片内RAM、SFR中。
3.操作数A、Rn、@Ri、direct、#data之间，除Rn之间、Rn 与@Ri之间、@Ri之间不能直接传送外，其余均可直接传送。
4.源和目的操作数同为一种寻址方式只有直接地址direct。
（二）外部RAM数据传送指令1.指令操作码：MOVX 2.源、目的操作数均在片外RAM中，其中有一个必须是A。
3.操作数为@DPTR、@Ri，只能通过累加器A，采用寄存器间接寻址方式。
@Ri：片外RAM的低256个单元，@ DPTR：片外RAM的全部64KB的空间。
（三）程序存储器（ROM）数据传送指令 1.指令操作码：MOVC，主要用于查表。
2.源操作数在片外ROM中，目的操作数在A中。
3.操作数为@A+DPTR、@A+PC，只能读入累加器A中。
@A+DPTR ：远程查表表可以放在64KB ROM的任何地址。
@A+PC：近程查表，表只能在查表指令后的256B ROM的地址空间中。
4.偏移量A的计算方法:@A+DPTR：A=欲查数值距离表首地址的值@A+PC： A=表首地址－当前指令的PC值－1（四）数据交换指令 1.半字节交换SWAP A;（A）3～0←→（A）7～4XCHD A , @Ri;（A）3～0←→（（Ri））3～0 2.字节交换XCH A ,包括Rn、@Ri、direct。
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8051 Instruction Set SummaryRn Register R7-R0 of the currently selected Register Bank.Data8-bit internal data location’s address. This could be an internal Data RAM location (0-127) or a SFR [i.e. I/O port, control register, status register, etc. (128-255)].@Ri 8-bit Internal Data RAM location (0-255) addressed indirectly throughregister R1 or R0.#data 8-bit constant included in instruction. #data16 16-bit constant included in instruction.addr16 16-bit destination address. Used by LCALL and LJMP. A branch can beanywhere within the 64k byte Program Memory address space.addr11 11-bit destination address. Used by ACALL and AJMP. The branch willbe within the same 2k byte page of Program Memory as the first byte of the following instruction.rel Signed (two’s component) 8-bit offset byte. Used by SJMP and allconditional jumps. Range is –128 to +127 bytes relative to first byte of the following instruction.bit Direct Addressed bit in Internal Data RAM or Special Function Register.Flag Flag InstructionC OV AC Instruction C OV AC ADDX X X CLR C O ADDCX X X CPL C X SUBB X X X ANL C,bit X MULO X ANL C,/bit X DIV O X ORL C,bit X DAX ORL C,/bit X RRCX MOV C,bit X RLCX CJNE X SETB C 1 Note that operations on SFR byte address 206 or bit addresses 209-215 (i.e. the PSW or bitsin the PSW) will also affect flag settings.Mnemonic Description Byte Cycle Arithmetic operationsADDA,Rn Add register to accumulator 1 1 ADD A,direct Add direct byte to accumulator 2 1 ADD A,@Ri Add indirect RAM to accumulator 1 1 ADDA,#dataAdd immediate data to accumulator 2 1 ADDCA,Rn Add register to accumulator with carry flag 1 1 ADDC A,direct Add direct byte to A with carry flag 2 1 ADDC A,@Ri Add indirect RAM to A with carry flag 1 1 ADDC A,#dataAdd immediate data to A with carry flag 2 1 SUBB A,RnSubtract register to accumulator with borrow 1 1 SUBBA,direct Subtract direct byte to A with carry borrow 2 1 SUBB A,@Ri Subtract indirect RAM to A with carry borrow 1 1 SUBB A,#dataSubtract immediate data to A with carry borrow 2 1 INC A Increment accumulator 1 1INC Rn Increment register 11INC direct Increment direct byte 21INC@RiIncrement indirect RAM 1 1 DEC A Decrement accumulator 11DEC Rn Decrement register 1 1DEC direct Decrement direct byte 21DEC @Ri Decrement indirect RAM 1 1 INC DPTRIncrement data pointer 1 2MUL AB Multiply A and B -> [B hi]:[A lo] 1 4 Mnemonic Description Byte Cycle CPL A Complement accumulator 11RL A Rotate accumulator left1 1 RLC A Rotate accumulator left through carry 1 1 RR A Rotate accumulator right1 1 RRCARotate accumulator right through carry 1 1 SWAP A Swap nibbles within the accumulator 1 1 Logic operationsANLA,Rn AND register to accumulator 1 1 ANL A,direct AND direct byte to accumulator 2 1 ANL A,@Ri AND indirect RAM to accumulator 1 1 ANLA,#data AND immediate data to accumulator 2 1 ANL direct,A AND accumulator to direct byte 2 1 ANL direct,#dataAND immediate data to direct byte3 2 ORL A,Rn OR register to accumulator 1 1 ORLA,direct OR direct byte to accumulator 2 1 ORL A,@Ri OR indirect RAM to accumulator 1 1 ORL A,#data OR immediate data to accumulator 2 1 ORL direct,A OR accumulator to direct byte2 1 ORL direct,#data OR immediate data to direct byte3 2 XRL A,Rn Exclusive OR register to accumulator 1 1 XRL A,direct Exclusive OR direct byte to accumulator 2 1 XRL A,@Ri Exclusive OR indirect RAM to accumulator 1 1 XRLA,#data Exclusive OR immediate data to accumulator2 1 XRL direct,A Exclusive OR accumulator to direct byte 2 1 XRL direct,#data Exclusive OR immediate data to direct byte3 2 Boolean variable manipulationCLR C Clear carry flag 1 1 CLR bitClear direct bit 2 1 SETB CSet carry flag 1 1 SETB bitSet direct bit 2 1CPL C Complement carry flag 1 1 CPL bitComplement direct bit 21ANL C,bit AND direct bit to carry flag2 2 ANL C,/bit AND complement of direct bit to carry 2 2 ORL C,bit OR direct bit to carry flag2 2 ORLC,/bitOR complement of direct bit to carry 2 2 MOV C,bit Move direct bit to carry flag 2 1 MOV bit,C Move carry flag to direct bit 2 2 Program and machine controlACALL addr11 Absolute subroutine call 2 2 LCALL addr16Long subroutine call32RET Return from subroutine1 2RETI Return from interrupt 1 2AJMP addr11 Absolute jump2 2 LJMP addr16 Long jump3 2SJMP rel Short jump (relative address) 2 2 JMP @A+DPTR Jump indirect relative to the DPTR 1 2 JZ rel Jump if accumulator is zero 2 2 JNZ rel Jump if accumulator is not zero 2 2 JC rel Jump if carry flag is set 2 2 JNC rel Jump if carry flag is not set 2 2 JB bit,rel Jump if bit is set 3 2 Mnemonic Description Byte Cycle CJNE A,#data,rel Compare immediate to A and jump if not equal 3 2 CJNE Rn,#data,rel Compare immed. to reg. and jump if not equal 3 2 CJNE @Rn,#data,rel Compare immed. to ind. and jump if not equal 3 2 DJNZ Rn,rel Decrement register and jump in not zero 2 2 DJNZ direct,rel Decrement direct byte and jump in not zero32NOP No operation1 1 Data transfer MOV A,RnMove register to accumulator 1 1 MOVA,direct*) Move direct byte to accumulator 2 1 MOV A,@Ri Move indirect RAM to accumulator 1 1 MOVA,#dataMove immediate data to accumulator 2 1 MOV Rn,A Move accumulator to register 1 1 MOV Rn,direct Move direct byte to register 2 2 MOV Rn,#data Move immediate data to register 2 1 MOV direct,A Move accumulator to direct byte 2 1 MOV direct,Rn Move register to direct byte 2 2 MOV direct,direct Move direct byte to direct byte 3 2 MOV direct,@Ri Move indirect RAM to direct byte 2 2 MOV direct,#data Move immediate data to direct byte 3 2 MOV @Ri,A Move accumulator to indirect RAM 1 1 MOV @Ri,direct Move direct byte to indirect RAM 2 2 MOV @Ri,#data Move immediate data to indirect RAM2 1 MOV DPTR,#data16 Load data pointer with a 16-bit constant3 2 MOVC A,@A+DPTR Move code byte relative to DPTR to accumulator 12 MOVC A,@A+PC Move code byte relative to PC to accumulator 1 2 MOVX A,@Ri Move external RAM (8-bit addr.) to A 1 2 MOVX A,@DPTR Move external RAM (16-bit addr.) to A 1 2 MOVX @Ri,A Move A to external RAM (8-bit addr.) 1 2 MOVX @DPTR,A Move A to external RAM (16-bit addr.) 1 2 PUSH direct Push direct byte onto stack 2 2 POP direct Pop direct byte from stack 2 2 XCH A,Rn Exchange register to accumulator 1 1 XCH A,direct Exchange direct byte to accumulator 2 1 XCHA,@RiExchange indirect RAM to accumulator 1 1 XCHD A,@RiExchange low-order nibble indir. RAM with A11*) MOV A,ACC is not a valid instructionjne A,#data,@ (jump if A ! = data) cjne A,#data,@ je A, #data,@(jump if A == data)add A,#low(−data) or cjne A,#(data),ne jz @ jmp @ne: ...ja, jnbe A,#data,@(jump if A > data) add A,#low(−data −1) or cjne A,#(data+1),ne jc @ ne: jnc @ jae, jnb A,#data,@ (jump if A >= data) add A,#low(−data) or cjne A,#(data),ne jc @ ne: jnc @ jb, jnae A,#data,@(jump if A < data) add A,#low,(−data) or cjne A,#(data),ne jnc @ne: jc @jbe, jna A,#data,@ (jump if A <= data) add A,#low(−data −1) or cjne A,#(data+1),nejnc @ ne: jc @ switch A <,==,> #data (no A modification)cjne A,#data,ne ...; execute code if A==data ne: jc is_below ; jump if A<datajnc is_above; jump if A>data or exec. codeI N CD E CA D D A D D C O R L A N L X R LM O V M O V S U B B M O V C J N E X C H D J N Z M O V VI N CD E CA D D A D D C O R L A N L X R LM O V M O V S U B B M O V C J N E X C H D J N Z M O V V。