3216YASQM4G05T中文资料
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Pin Assignment
Pin#Front Side Pin#Front Side Pin#Back Side Pin#Back Side 1Vss 26Vss 51Vss 76Vss 2DQ027CKE052DQ877CKE13DQ128WE*53DQ978NC 4DQ229S0*54DQ1079S1*5DQ330NC 55DQ1180NC 6Vcc 31Vcc 56Vcc 81Vcc 7DQ432NC 57DQ1282NC 8DQ533NC 58DQ1383NC 9DQ634NC 59DQ1484NC 10DQ735NC 60DQ1585NC 11DQMB036Vss 61DQMB186Vss 12Vss 37DQMB262Vss 87DQMB313A038DQ1663A188DQ2414A239DQ1764A389DQ2515A440DQ1865A590DQ2616A641DQ1966A791DQ2717A842Vcc 67A992Vcc 18A1043DQ2068BA093DQ2819BA144DQ2169A1194DQ2920NC 45DQ2270NC 95DQ3021Vcc 46DQ2371Vcc 96DQ3122NC 47Vss 72RAS*97Vss 23RFU 48SDA 73CAS*98SA024RFU 49SCL 74RFU 99SA125CK050Vcc 75CK1100SA2 * Active Low
100 PIN SYNCHRONOUS DRAM DIMM
3216YASQM4G05T 100 Pin 16Mx32 SDRAM DIMM Unbuffered, 4k Refresh, 3.3V with SPD
Features
• JEDEC-Standard 100-pin Dual Inline Memory
Module (DIMM)• Unbuffered
• Based on 8Mx16 JEDEC SDRAM Components • Power Supply: 3.3V ± 0.3V • 64ms, 4096-cycle refresh • Serial Presence Detect (SPD)
• LVTTL Compatible Inputs and Outputs • Two External Banks • Four Internal Banks
• Pure Power and Ground Planes • Gold PCB connector
General Description
The 3216YASQM4G05T is a 16Mx32 bit, 5 chip,100 Pin DIMM module consisting of (4) 2Mx16x4(TSOP) SDRAM and (1) 256x8 EEPROM for serial presence detect. The module conforms to JEDEC specifications, is unbuffered, and has byte data masks.
Valid Part Numbers
Part Number
Bus Speed CAS Latency
Organization 3216YASQM4G05T
66Mhz
CL2
8Mx16
Block Diagram
Pin Descriptions
Pin Name Function
CLK#System Clock All input signals are sampled on the rising edge of clock.
S#Chip Select Enables and disables the command decoder. All commands are disabled
when S# is high.
CKE Clock Enable Masks system clock to freeze current operation on the next clock cycle,
also provides access to standby mode (see truth table).
A#Address Lines Input lines for Row/Column address.
BA#Bank Select Lines Selects the internal bank to be accessed during a row or column address
latch.
RAS Row Address Strobe Latches the row address on the rising edge of clock when asserted. CAS Column Address Strobe Latches the column address on the rising edge of clock when asserted. WE Write Enable Enables write operation and row precharge.
DQMB#Data Masks Provides a byte mask for write operations and a byte enable for read
operations.
DQ#Data Lines Data input/output lines.
Vdd Power Supply Power Supply 3.3V±0.3V
Vss Ground Ground
SDA, SCL SPD Data/Clock Lines Serial Presence Detect (SPD) EEPROM bus lines. These line provides
bi-directional data transfer over an I2C bus.
SA#SPD Address Lines Serial Presence Detect (SPD) EEPROM address lines. These lines are
used to configure the SPD.
NC No Connection Line is not connected in DIMM.