8490中文资料
C0940中文资料
ElectronicsComputer CableProduct Construction:Conductor:• 28 and 24 AWG fully annealed strandedtinned copper per ASTM B-33Insulation:• Premium-grade, coIor-coded S-R PVCper UL 1061• Color Code: See charts belowShield:• 100% Flexfoil®aluminum/polyesterwith 25% overlap, minimum, foil facing out• Stranded tinned copper drain wire(28 AWG only)• 65% tinned copper braidJacket:• PVC, gray• Temperature Range: –20˚C to +80˚CApplications:• Computers• Industrial equipment• Data transmission• Control circuits• Suitable for EIA RS-232 applications• Suggested voltage rating: 300 voltsFeatures:• Braid shield provides good flexibility• Superior shielding where noise rejectionis critical• Assists system designers in meeting FCCDocket 20780 demandsCompliances:• NEC Article 725 Type CL2 - 28 AWG(UL: 75˚C)• NEC Article 800 Type CM - 24 AWG(UL: 75˚C)• UL Style 2464 (UL: 80°C, 300V)• CSA CMG (CSA: 60˚C)• Designed to meet UL 70,000 BTU VerticalTray Flame Test• Passes CSA CMG Flame TestPackaging:• Please contact Customer Service forpackaging and color options Multi-Conductor, Foil/Braid ShieldUL 2464, NEC Type CL2 or CM (UL) c(UL), CSA CMG**B - Capacitance between one conductor and other conductors connected to shield*Color Code Chart 1. Remaining items Color Code Chart 2元器件交易网41Computer Cable Electronics Multi-Conductor, Foil/Braid ShieldUL 2464, NEC Type CM (UL) c(UL), CSA CMGProduct Construction:Conductor:• 22 AWG fully annealed stranded tinnedcopper per ASTM B-33Insulation:• Premium-grade, coIor-coded S-R PVCper UL 1061• Color Code: See chart belowShield:• 100% Flexfoil®aluminum/polyesterwith 25% overlap, minimum, foil facing out• 65% tinned copper braidJacket:• PVC, gray• Temperature Range: –20°C to +80˚CApplications:• Computers• Industrial equipment• Data transmission• Control circuits• Suitable for EIA RS-232 applications• Suggested voltage rating: 300 voltsFeatures:• Braid shield provides good flexibility• Superior shielding where noise rejectionis critical• Assists system designers in meeting FCCDocket 20780 demandsCompliances:• NEC Article 800 Type CM (UL: 75˚C)• UL Style 2464 (UL: 80°C, 300V)• CSA CMG (CSA: 60˚C)• Designed to meet UL 70,000 BTU VerticalTray Flame Test• Passes CSA CMG Flame TestPackaging:• Please contact Customer Service forpackaging and color options*B - Capacitance between one conductor and other conductors connected to shield 元器件交易网42。
SATO打印引擎技术手册_中文版
电源要求
100-115 伏特(±10%)
电压
220 伏特(±10%)
50-60 赫兹(±1%)
功耗
空闲状态 50 瓦 工作状态 700 瓦
环境
工作温度
41 到 104 华氏度(5 到 40 摄氏度)
存放温度
0 到 104 华氏度(零下 20 到零上 40 摄氏度)
工作湿度
15-85%RH,无结露状态
“S”系列条码标签打印引擎
操作员及技术参考手册
适用于 M-8459S、M-8460S、M-8485S、M-8490S 机型
规格
规格
M-8485S
M-8460S
M-8490S
打印
方式
直热或热转印
每秒 4 到 10 英寸 每秒 4 到 8 英寸 每秒 4 到 8 英寸
速度(用户选择) 每秒 100 到 250 每秒 100 到 200 每秒 100 到 200
4.4 英寸 112 毫米 896 点
49.2 英寸 1249 毫米
1.0 英寸(25 毫 米)
0.25 英寸(6 毫 米)
5.25 英寸 134 毫米
无 无 无
(1) 打印速度高于 6 英寸每秒时的最小标签长度为 1 英寸。
规格 控制和信号
联机状态 电源 标签
碳带(M-8459S 机型不适用) 错误
(24 点高×24 点宽)Univers Condensed Bold
OA 字体
(22 点高×15 点宽)OCR-A (33 点高×22 点宽)OCR A
OB 字体
(24 点高×20 点宽)OCR-B (36 点高×30 点宽)OCR B
自动平滑字体
WB
中国政法大学学院路校区号码
学院路校区管委会办公室办公室——————8032——————8033——————8034 校友办——————8022 会议室——————8035——————8036 收发室——————8037组织部办公室—————8573统战部办公室—————8461 民主党派—————8038纪委、监察处办公室—————8093宣传部办公室——————8540 广播台——————8039 LED屏播放室——8577离退休干部管理处处长办——————8041 分党委——————8098 副处长办—————8042 离休办——————8043 退休办——————8045 活动室——————8044 老年人权益保障研究中心—————8046 公关委——————8097科研处办公室——————8051 传真——————8052人事处办公室——————8550研究生院院长办——————8056 副院长办—————8057—————8058 办公室——————8059——————8060 博士后办—————8063培养办——————8066——————8067——————8076学位办——————8068——————8390招生办——————8070——————8071招生传真—————8074招生机要—————8073教室调度—————8078研究生法学编辑部—8527发展规划与学科建设处处长办—————8053副处长办—————8062—————8471综合科—————8061传真——————8054开放教育管理办公室主任办——————8161副主任——————8542办公室——————8454——————8064——————8065会议室——————8554国际合作与交流处长办——————8080副处长——————8365综合科——————8082——————8083交流科——————8085——————8086专家科——————8049传真——————8081——————8084学生工作部就业中心办————8090研究生工作办———8091心理健康咨询———8389综合办—————8511学生工作办————8510就业咨询————8512财务处处长办——————8095——————8547结算中心—————8096会计结算二科———8578审计跟踪审计—————8152—————8509保卫处处长办——————8100办公室——————8101治安二科—————8102综合二科—————8103总值班室—————8104—————8110监控室—————8543东门——————8105北门——————8106南门——————8107保安队——————8108政法家委会————8109塔楼家委会————8111明光楼家委会———811218#楼传达室———834215#楼传达室———8314人口普查办———8576资产管理处房产科——————8116传真——————8117后勤工作委员会办公室办公室——————8118基建处处长办——————8119办公室——————8120——————8546拆迁建设办公室办公室——————8371团委办公室——————8137研究生会—————8002法律援助中心———8411研究生工作办——8253工会办公室——————8138校医院保健科——————8139急诊室——————8140内科(一)————8350内科(二)————8351护士办——————8352药房——————8353口腔科——————8354挂号室——————8355化验室——————8356饮食服务中心主任办——————8142办公室——————8143值班室/门岗————8144法学餐厅—————8145回民餐厅—————8146正文园商店————8172————8173运输服务中心办公室——————8150——————8419休息室——————8151学生公寓管理服务中心办公室——————8157——————81582#公寓门卫————8162新1#公寓门卫———8160家政服务部———8161培训公寓办公室——8153培训公寓接待室——8337培训公寓值班———8437物业管理服务中心副主任办—————8163办公室——————8164——————8174经理室——————8155保洁部——————8156绿化环保部————8154预算室——————8169房产维修—————8165水暖维修—————8166热力供应—————8167电卡充值—————8168 电器维修—————8170 配电室—————8171 新1#公寓浴池——8364 新1#保洁值班——8528电信服务中心主任办——————8008 机线维护部————8006 电信营业厅————8503司法考试学院院长办——————8122——————8123 网络部——————8375 教学研究部————8127——————8128——————8126——————8133 教学研究部————8129——————8376——————8377——————8131法学院办公室——————8178——————8177 研究生工作办———8175——————8176——————8381——————8382 就业办——————8395 培训部——————8179——————8180——————8181——————8182——————8183——————8185民商经济法学院办公室——————8186——————8187——————8188——————8366 研究生工作办———8189——————9357 博士点——————8190——————8191 江平办——————8192 网站——————8404国际法学院院长办——————8548办公室——————8195——————8196博导办公室————8197研究生工作办———8198——————8199——————8336——————8383外事办——————8384辅导员办—————8360研究生教研办———8361在职教育培训办——8200出国留学培训办——8558——————8585刑事司法学院院长办——————8209研究生工作办———8201——————8202——————8372传真——————8203侦查学实验室———8204政治与公共管理学院院长办——————8205——————8378MPA教育办———8206————8380研究生工作办———8207——————8519博导办——————8518国际化与国际问题—8000———8497政治文化与政治文明研究所——————8520培训部——————8208商学院办公室——————8210——————8211研究生办—————8212—————8214培训部——————8213商学院(一)———8448商学院(二)———8449研究所—————8534MBA教育办———8536———8537MBA综合服务办———8587人文学院李德顺办—————8391办公室——————8216研究生办—————8217外国语学院办公室——————8220研究生外语教务办——————8221——————8222研究生外语教研室——————8223无线发射台————8224研工办——————8387——————8397英语语言文学研究所——————8541继续教育学院副院长——————8472——————8125分党委——————8473财务室——————8475院务办——————8476——————8477——————8478——————8479律师学院—————8484—————8487招生与学籍办———8489—————8490函授站管理办———8491教务考务办————8493—————8494司法职业教育中心—————8481海外留学教育中心—————8480—————8482—————8486政府与企业管理教育中心—————8225对外拓展部————8483研发中心—————8438—————8226—————8485成人学历教育中心————8227夜大学——————8228——————8229——————8495——————8496—————8492研究室——————8230教材部——————8231高级政法管理干部进修中心办公室—————8464—————8469副主任办—————8465常务副主任————8467教学部—————8468会议室—————8470新闻与传播学院办公室——————8115教务办——————8474文化产业导报编辑室—————8580—————8581国际教育学院院长办——————8234院长传真—————8235副院长办—————8236——————8238院办——————8233——————8338院办传真—————8339国际合作部————8237港澳台侨办————8239——————8240外国留学生————8241汉语言专业————8340暑期学校办————8341法硕学院院办/党总支———8517————8552教学科研办————8075————8553中欧法学院办公室—————8092社会学院院长办——————8024 研工办——————8014 心理学教研室———8531 社会学教研室———8532马克思主义学院院长办——————8218 研究生办—————8219国际儒学院办公室——————8001中德法学院办公室——————8242——————8243 图书馆——————8244中美法学院办公室——————8246——————8247 传真——————8245卡特政府学院办公室——————8385——————8386体育教学部办公室——————8250新1#公寓体育馆办公室——————8048 新1#公寓体育馆门卫——————8446科学技术教学部办公室——————8252比较法学研究中心所长办——————8256 办公室——————8257 编辑部——————8258 法学文挡—————8248 教学科研办————8549诉讼法学研究院主任办——————8260名誉主任—————8261顾问室——————8262副主任室—————8263办公室——————8270——————8370——————8388刑诉法学研究室——8264民诉法学研究室——8265行政诉讼研究室——8266证据法学研究室——8267编辑室——————8268图书资料—————8269电子阅览—————8259中文资料室————8394法律史学研究中心主任办——————8271——————8374名誉主任—————8373副主任办—————8272办公室——————8273——————8274破产法与企业重组研究中心办公室——————8278欧盟法研究中心办公室——————8358法学教育研究与评估中心主任办——————8159副主任办—————8149办公室——————8079传真——————8047评估所——————8099研究所——————8255刑事法律研究中心陈光中办—————8379中国法律信息中心主任办——————8113副主任办—————8114—————8582顾问室——————8193办公室——————8147法律信息部————8134监控室——————8194网络机房—————8533法制政府研究院主任室——————8215办公室——————8232——————8003研究室(一)———8040研究室(二)———8303《行政法学》编辑部——————8184证据科学研究院副院长——————8028办公室——————8029教学培训部————8031编辑部——————8121编辑部办公室———8141证据法研究所———8251长江学者艾伦办公室—————8249对外培训部————8431————8432法律古籍整理研究所办公室——————8275——————8463人权与人道主义研究所办公室——————8276——————8277——————8428法和经济研究所办公室——————8077宪政研究所办公室——————8346全国专利保护重点联系基地办公室—————8148《政法论坛》编辑部主编室——————8280办公室——————8281传真——————8279学报办公室——————8005——————8444中关村法大科技园办公室——————8009——————8557传真——————8007出版社社长办——————8282副社长办—————8283总编室——————8284——————8285——————8286——————8287策划编辑室————8288综合编辑部————8289照排室——————8290校对室——————8291文字编辑室————8292美编室——————8293版权部——————8583出版部——————8294教材编辑室————8295实用读物编辑室——8524财务室——————8296社长办公室————8297——————8298前台——————8299读者服务部————8300——————8301网络室——————8302发行部——————8325——————8326储运部——————8335分工会——————8004资料室——————8575图书馆馆长办——————8304副馆长办—————8305办公室——————8306会计室——————8307文献资源—————8308——————8309——————8555电子阅览室————8310信息咨询部————8311现刊阅览室————8312 过刊阅览室————8313 系统部——————8315 外文阅览室————8316 文史书库—————8317 法律书库—————8318 中文阅览室————8319 传达室——————8320 古籍库——————8321信息化建设办公室(现代教育技术中心)网络部——————8451 卡务部——————8452 制作部——————8322 教学服务部————8324其它18#楼电梯值班——8348 15#楼电梯值班——8349 13#楼电梯————8343————8254 15#楼电梯————8344 18#楼电梯————8345。
国民经济行业分类及代码
8330 8320 8310 8300
8290
8224
8223
8222 8221 8220
8210
广告业
指专门为客户的商品、业务 和其他委托的事项进行文字 、图案、模型、影片等的设 计、绘制、装置等宣传广告 活动,广告代理活动也包括 在内。
8200 8100
信息、咨 询服务业 包括卡拉OK歌舞厅、电子 娱乐服务 游戏厅(室)、游乐园 业 (场)、夜总会等活动。 包括经营旅游业务的各种旅 行社和旅行公司等的活动。 旅游业 不包括接待旅游业务的饭 店,公园等的活动。 包括提供机械电子设备、交 租 赁 服 务 通工具、办公用品、家庭生 业 活用品、文化体育用品等租 赁活动。 包括宾馆、旅馆及招持所、 旅馆业 大车店等。 包括刻字、印名片、收费停 (存)车场、机械描图、晒 其他居民 图社、复印、誊印、劳务介 服务业 绍所、婚姻介绍所等的活动 。 包括埋葬、火化及与此有关 的葬礼服务。墓地出租或出 殡葬业 售,墓地或陵地保护和维 护,列士陵园的管理等活动 。 包括各种直接受家庭雇用人 员进行的活动。如:保姆、 厨师、洗衣工、园丁、门卫 家 务 服 务 、司机、看护、教师、私人 业 秘书等。不包括劳务介绍所 、保姆介绍所等活动,这些 介绍所应列入其他居民服务 业。 包括修理工厂以外的各类修 理店(铺)进行的日用品修 日 用 品 修 理活动,如照相机、钟表、 理业 自行车、缝纫机、收音机、 电视机、黑白铁及其他杂品 修理等。 托儿所 摄 影 及 扩 包括从事摄影和彩色扩印活 动。 印业 包括洗染店(部)、干洗店 洗染业 、洗衣房等的活动。 包括浴池、沐浴室、桑那浴 沐浴业 等的活动。
国民经济行业分类与代码表 行业代码 行业名称 行业说明 其 他 未 包 以上各行业未包括的行业。 9990 括的行业 包括主要行使行政管理职能 企业管理 9910 、执行行政事业单位会计制 机构 度的行政性公司。 9900 其他行业 村民委员 9720 包括各类村民委员会。 会 居民委员 9710 包括各类居民委员会。 会 基层群众 9700 自治组织 包括各级工会、共青团、妇 联、文联、残联、工商联及 各类协会,中国红十字会、 9600 社会团体 中国福利会、中国保护儿童 委员会,各类学术团体和宗 教团体等。 包括中国共产党各级机关和 所属办事机构,各民主党派 9500 政党机关 各级机关办事机构和各级政 治协商会议。 包括各级国家权力机关和各 级行政机关。即各级人大常 委会及其所属办事机构;各 级人民政府及其所属各工作 9400 国家机关 部门;各级法院和检察院。 以及区、乡、镇、街道人民 政府的权力机构和行政办事 机构。人民解放军、武警部 队也包括在此类。 其他综合 包括专利审批活动、产品设 9390 技术服务 计等活动。 业 工 程 设 计 包括各行业的工程设计活动 9380 业 。 技术推广 9370 和科技交 流服务业 包括环境保护、监测等活动 9360 环境保护 。 包括海洋调查、监测等活动 9350 海洋环境 。 包括技术监督、检定、质量 9340 技术监督 监督、标准制定以及计量活 动。
PIC下载地址
PIC18F87J10系列(128K字节Flash)中文数据手册:
/downloads/en/DeviceDoc/39663b_cn.pdf
PIC16F627A/628A/648A中文数据手册:
/downloads/en/DeviceDoc/40044d_cn.pdf
Section 17. 10-Bit A/D Converter
/downloads/en/DeviceDoc/39705a_cn.pdf
Section 19. Comparator Module
/downloads/en/DeviceDoc/39710a_cn.pdf
电池电量管理芯片PS810中文数据手册:
/downloads/en/DeviceDoc/21904b_cn.pdf
PIC24系列参考手册部分章节中文翻译
Section 7. Reset
/downloads/en/DeviceDoc/39712a_cn.pdf
PIC18F45J10系列中文数据手册
/downloads/en/devicedoc/39682a_cn.pdf
PICKIT2 在线编程器中文使用说明书
/downloads/en/DeviceDoc/51553a_cn.pdf
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MC-4R512FKE6D-840资料
GND LDQA8 GND LDQA6 GND LDQA4 GND LDQA2 GND LDQA0 GND LCTMN GND LCTM GND NC GND LROW1 GND LCOL4 GND LCOL2 GND LCOL0 GND LDQB1 GND LDQB3 GND LDQB5 GND LDQB7 GND LSCK VCMOS SOUT VCMOS NC GND NC VDD VDD NC NC NC NC
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46
NC NC NC NC VREF GND SA0 VDD SA1 SVDD SA2 VDD RCMD GND RDQB8 GND RDQB6 GND RDQB4 GND RDQB2 GND RDQB0 GND RCOL1 GND RCOL3 GND RROW0 GND RROW2 GND NC GND RCFMN GND RCFM GND RDQA1 GND RDQA3 GND RDQA5 GND RDQA7 GND
NC NC NC NC VREF GND SCL VDD SDA SVDD SWP VDD RSCK GND RDQB7 GND RDQB5 GND RDQB3 GND RDQB1 GND RCOL0 GND RCOL2 GND RCOL4 GND RROW1 GND NC GND RCTM GND RCTMN GND RDQA0 GND RDQA2 GND RDQA4 GND RDQA6 GND RDQA8 GND
PIC中文资料下载
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MCP6001/2/4 1MHz低功率运算放大器
PC849中文资料
Response time ( µ s)
500
VCE = 2V
200
100
IC = 2mA
50
Ta = 25˚C
20 10
tr tf
5
2
td
1
ts
0.5
0.2
0.1
0.1
1
10
Load resistance RL ( k Ω )
Fig.11 Frequency Response
V CE = 5V
0
0.5TYP. 3.0 ± 0.5 3.5 ± 0.5
s Applications 1. Telephone exchangers 2. Computer terminals 3. System appliances, measuring instruments 4. Signal transmission between circuits of
200
Collector power dissipation PC ( mW )
Forward current IF ( mA )
50 150
40
30
100
20
10
0 - 25 0
25 50 75 100 125
Ambient temperature T a (˚C)
Fig. 3 Peak Forward Current vs. Duty Ratio
25˚C
20 10 5
2 1
0 0.5 1.0 1.5 2.0 2.5 3.0
Forward voltage V F (V)
Fig. 5 Current Transfer Ratio vs.
Forward Current
LT1185中文资料
Dropout Voltage
TJ = 25°C TJ = 125°C
TJ = –55°C
1
2
3
4
LOAD CURRENT (A)
LT1185 • TA02
1
元器件交易网
LT1185
U WU
U WW W
ABSOLUTE AXI U RATI GS
(Note 1)
Input Voltage .......................................................... 35V Input-Output Differential ......................................... 30V FB Voltage ................................................................ 7V REF Voltage .............................................................. 7V Output Voltage ........................................................ 30V Output Reverse Voltage ............................................ 2V Operating Ambient Temperature Range
LT1185C ............................................... 0°C to 70°C LT1185M ......................................... – 55°C to 125°C Operating Junction Temperature Range* Control Section LT1185C ............................................. 0°C to 125°C LT1185I .......................................... – 40°C to 125°C LT1185M ........................................ – 55°C to 150°C Power Transistor Section LT1185C ............................................. 0°C to 150°C LT1185I .......................................... – 40°C to 150°C LT1185M ........................................ – 55°C to 175°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................ 300°C
SP9840资料
SPECIFICATIONS
(VDD = +5V, All VINX= 0V, VREFL = 1.625V, TA = 25° C for commercial–grade parts; TMIN ≤ TA = TMAX for industrial–grade parts; specifications apply to all DAC's unless noted otherwise.)
PARAMETER SIGNAL INPUTS Input Voltage Range Input Resistance SP9840 SP9843 Input Capacitance SP9840 SP9843 VREFL Resistance VREFL Capacitance DIGITAL INPUTS Logic High Logic Low Input Current Input Capacitance Input Coding STATIC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Half-Scale Output Voltage Minimum Output Voltage Output Voltage Drift DYNAMIC PERFORMANCE Multiplying Gain Bandwidth Slew Rate Positive Negative Total Harmonic Distortion Output Settling Time Crosstalk Digital Feedthrough Wideband Noise SINAD Digital Crosstalk
元器件交易网
COPCJ840资料
COP820CJ/COP840CJ Family8-Bit CMOS ROM Based Microcontrollers with 1k or 2k Memory,Comparator and Brown Out DetectorGeneral DescriptionThe COP820CJ/840CJ Family ROM based microcontrollers are integrated COP8™Base core devices with 1k or 2k memory,an Analog comparator and Brownout detection.These single-chip CMOS devices are suited for lower-functionality applications where power and voltage fluctua-tions are a consideration.Pin and software compatible (no Brownout;different Vcc range)4k/32k OTP versions are available (COP87LxxCJ/RJ Family)for pre-production,and for use with a range of COP8software and hardware devel-opment tools.Family features include an 8-bit memory mapped architec-ture,10MHz CKI with 1us instruction cycle,one multi-function 16-bit timer/counter,MICROWIRE/PLUS ™serial I/O,one analog comparator,power saving HALT mode,MIWU,on-chip R/C oscillator capacitor (COP840CJ),high current outputs,software selectable I/O options,WATCH-DOG ™timer,modulator/timer,Brownout detector,Power on Reset,2.5v-6.0v operation,and 16/20/28pin packages.In this datasheet,the term COP820CJ refers to packages in-cluding the COP820CJ,COP822CJ,and COP823CJ;and COP840CJ refers to COP840CJ,COP842CJ,COP940CJ,and COP942CJ.Devices included in this data sheet are:Device Memory (bytes)RAM (bytes)I/O Pins Packages Temperature CommentsCOP820CJ 1k ROM 642428DIP/SOIC -40to +85˚C COP822CJ 1k ROM 541620DIP/SOIC -40to +85˚C COP823CJ 1k ROM 641216SOIC -40to +85˚C COP840CJ 2k ROM 1282428DIP/SOIC -40to +85˚C Low EMICOP940CJ 2k ROM 1282428DIP/SOIC -0to +70˚C 2.5V-4.5V,CJH =4V-6VCOP842CJ 2k ROM 1281620DIP/SOIC -40to +85˚C COP942CJ2k ROM1281620DIP/SOIC-0to +70˚C2.5V-4.5V,CJH =4V-6V Key Featuresn Multi-Input Wake Up (on the 8-bit Port L)n Brown out detector n Analog comparatorn Modulator/timer (High speed PWM for IR transmission)n16-bit multi-function timer supporting —PWM mode—External event counter mode —Input capture moden 1024or 2048bytes of ROM n 64or 128bytes of RAMn Quiet design (low radiated emissions)nIntegrated capacitor for the R/C oscillator for COP840CJI/O Featuresn Software selectable I/O options (TRI-STATE ®output,push-pull output,weak pull-up input,high impedance input)n High current outputs (8pins)n Packages—16SO with 12I/O pins for COP820CJ —20DIP/SO with 16I/O pins —28DIP/SO with 24I/O pinsn Schmitt trigger inputs on Port G n MICROWIRE/PLUS serial I/OCPU/Instruction Set Featuren 1µs instruction cycle timen Three multi-source vectored interrupts servicing —External interrupt with selectable edge —Timer interrupt —Software interruptn 8-bit Stack Pointer (SP)—stack in RAMn Two 8-bit register indirect data memory pointers (B,X)Fully Static CMOSn Low current drain (typically <1µA)n Single supply operation:2.5V to 6.0Vn Temperature ranges:−0˚C to +70˚C and −40˚C to +85˚CDevelopment Supportn Emulation and OTP devicesn Real time emulation and full program debug offered by MetaLink Development SystemTRI-STATE ®is a registered trademark of National Semiconductor Corporation.COP8™,MICROWIRE ™,MICROWIRE/PLUS ™and WATCHDOG ™are trademarks of National Semiconductor Corporation.iceMASTER ®is a registered trademark of MetaLink Corporation.September 1999COP820CJ/COP840CJ Family,8-Bit CMOS ROM Based Microcontrollers with 1k or 2k Memory,Comparator and Brown Out Detector©2000National Semiconductor Corporation Block DiagramConnection DiagramsDS011208-12k ROM and 128Bytes RAM for COP840CJFIGURE 1.Block DiagramDS011208-3Top ViewOrder Number COPCJ820-XXX/N orCOPCJ820-XXX/M,Order Number COPCJ840-XXX/N orCOPCJ840-XXX/M,Order Number COPCJ940-XXX/N orCOPCJ940-XXX/MSee NS Package Number N28B orM28BDS011208-4Top ViewOrder Number COPCJ822-XXX/N orCOPCJ822-XXX/MOrder Number COPCJ842-XXX/N orCOPCJ842-XXX/MOrder Number COPCJ942-XXX/N orCOPCJ942-XXX/MSee NS Package Number N20A orM20B 2Connection Diagrams(Continued)COP820CJ/COP840CJ Pin AssignmentPort Pin Typ.ALT Function16-Pin20-Pin28-Pin L0I/O MIWU/CMPOUT5711 L1I/O MIWU/CMPIN−6812 L2I/O MIWU/CMPIN+7913 L3I/O MIWU81014 L4I/O MIWU91115 L5I/O MIWU101216 L6I/O MIWU111317 L7I/O MIWU/MODOUT121418 G0I/O INTR1725 G1I/O1826 G2I/O1927 G3I/O TIO152028 G4I/O SO11 G5I/O SK1622 G6I SI133 G7I CKO244 I0I7 I1I8 I2I9 I3I10 D0O19 D1O20 D2O21 D3O22 VCC466 GND131523 CKI355 RESET141624COP820CJ/COP840CJ Family 3Absolute Maximum Ratings (Note 1)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage (V CC )7.0V Voltage at any Pin−0.3V to V CC+0.3VTotal Current into V CC pin (Source)80mA Total Current out of GND pin (sink)80mAStorage Temperature Range −65˚C to +150˚CNote 1:Absolute maximum ratings indicate limits beyond which damage to the device may occur.DC and AC electrical specifications are not ensured when operating the de-vice at absolute maximum ratings.DC Electrical Characteristics−0˚C ≤T A ≤+70˚C for COP94x and −40˚C ≤T A ≤+85˚C for all othersParameterConditionsMin TypMax Units Operating Voltage Brown Out Disabled 2.5 6.0V COP94xCJ Brown Out Disabled 2.5 4.5V COP94xCJHBrown Out Disabled 4.56.0V Power Supply Ripple 1(Note 2)Peak to Peak0.1V CCVSupply Current (Note 3)CKI =10MHz V CC =6V,tc =1µs 6.0mA CKI =4MHz V CC =6V,tc =2.5µs 3.5mA CKI =4MHz V CC =4.0V,tc =2.5µs 2.0mA CKI =1MHzV CC =4.0V,tc =10µs 1.5mA HALT Current with Brown Out Disabled (Note 4)V CC =6V,CKI =0MHz <110µA HALT Current with Brown Out EnabledV CC =6V,CKI =0MHz<50110µACOP840CJ Supply Current (Note 3)CKI =10MHz,R =2.2k V CC =6V,tc =1µs 8.0mA CKI =4MHz,R =4.7k V CC =6V,tc =2.5µs 6.0mA CKI =4MHz,R =4.7k V CC =4.5V,tc =2.5µs 2.5mA CKI =1MHz,R =20k V CC =4.5V,tc =10µs 1.5mA HALT Current with Brown Out DisabledV CC =6V,CKI =0MHz <2.28µA HALT Current with Brown Out EnabledV CC =6V,CKI =0MHz<50100µA Brown Out Trip Level (Brown Out Enabled)1.8 3.1 4.2V COP840CJ Brown Out Trip Level (Brown Out Enabled) 1.93.13.9VINPUT LEVELS (V IH ,V IL )Reset,CKI:Logic High 0.8V CCV Logic Low 0.2V CCVAll Other Inputs Logic High 0.7V CCV Logic Low 0.2V CCV Hi-Z Input Leakage V CC =6.0V−2+2µA Input Pullup CurrentV CC =6.0V,V IN =0V−40−250µA L-and G-Port Hysteresis (Note 6)COP840CJ 0.05V CC0.35V CCVC O P 820C J /C O P 840C J F a m i l y 4DC Electrical Characteristics(Continued)−0˚C≤T A≤+70˚C for COP94x and−40˚C≤T A≤+85˚C for all othersParameter Conditions Min Typ Max Units Output Current LevelsD Outputs:Source V CC=4.5V,V OH=3.8V−0.4mAV CC=2.5V,V OH=1.8V−0.2mA Sink V CC=4.5V,V OL=1.0V10mAV CC=2.5V,V OH=0.4V2mA L4–L7Output Sink V CC=4.5V,V OL=2.5V15mA All OthersSource(Weak Pull-up Mode)V CC=4.5V,V OH=3.2V−10−110µAV CC=2.5V,V OH=1.8V−2.5−33µA Source(Push-pull Mode)V CC=4.5V,V OH=3.8V−0.4mAV CC=2.5V,V OH=1.8V−0.2mA Sink(Push-pull Mode)V CC=4.5V,V OL=0.4V 1.6mAV CC=2.5V,V OL=0.4V0.7mA TRI-STATE Leakage−2.0+2.0µA Allowable Sink/SourceCurrent Per PinD Outputs15mA L4–L7(Sink)20mA All Others3mA Maximum Input Current Room Temperature±100mA without Latchup(Note5)RAM Retention Voltage,V r500ns Rise and 2.0VFall Time(Min)Input Capacitance7pF Load Capacitance on D21000pF Note2:Rate of voltage change must be less than10V/mS.Note3:Supply current is measured after running2000cycles with a square wave CKI input,CKO open,inputs at rails and outputs open.Note4:The HALT mode will stop CKI from oscillating in the RC and crystal configurations.HALT test conditions:L,and G0..G5ports configured as outputs and set high.The D port set to zero.All inputs tied to V CC.The comparator and the Brown Out circuits are disabled.Note5:Pins G6and RESET are designed with a high voltage input network.These pins allow input voltages greater than V CC and the pins will have sink current to V CC when biased at voltages greater than V CC(the pins do not have source current when biased at a voltage below V CC).The effective resistance to V CC is750Ω(typical).These two pins will not latch up.The voltage at the pins must be limited to less than14V.COP820CJ/COP840CJ Family 5AC Electrical Characteristics−40˚C ≤T A ≤+85˚C unless otherwise specifiedParameterConditions Min Typ Max Units Instruction Cycle Time (tc)Crystal/Resonator 4.5V ≤V CC ≤6.0V 1DC µs 2.5V ≤V CC ≤4.5V 2.5DC µs R/C Oscillator4.5V ≤V CC ≤6.0V 3DC µs COP840CJ 2DC µs 2.5V ≤V CC ≤4.5V 7.5DC µs COP840CJ5DCµs V CC Rise Time when Using Brown OutV CC =0V to 6V50µsFrequency at Brown Out Reset 4MHz CKI Frequency For Modular Output 4MHz CKI Clock Duty Cycle (Note 6)fr =Max4060%Rise Time (Note 6)fr =10MHz ext.Clock 12ns Fall Time (Note 6)fr =10MHz ext.Clock 8ns Inputs t Setup 4.5V ≤V CC ≤6.0V 200ns 2.5V ≤V CC ≤4.5V 500ns t Hold4.5V ≤V CC ≤6.0V 60ns 2.5V ≤V CC ≤4.5V 150nsOutput Propagation Delay R L =2.2k,CL =100pF t PD1,t PD0SO,SK 4.5V ≤V CC ≤6.0V 0.7µs 2.5V ≤V CC ≤4.5V 1.75µs All Others 4.5V ≤V CC ≤6.0V 1µs 2.5V ≤V CC ≤4.5V5µs Input Pulse Width Interrupt Input High Time 1tc Interrupt Input Low Time 1tc Timer Input High Time 1tc Timer Input Low Time1tc MICROWIRE Setup Time (t µWS )20ns MICROWIRE Hold Time (t µWH )56ns MICROWIRE Output 220ns Propagation Delay (t µPD )Reset Pulse Width1.0µsNote 6:Parameter characterized but not production tested.DS011208-2FIGURE 3.MICROWIRE/PLUS TimingC O P 820C J /C O P 840C J F a m i l y 6Comparator DC and AC Characteristics4V≤V CC≤6V,−40˚C≤T A≤+85˚C(Note7)Parameters Conditions Min Type Max Units Input Offset Voltage0.4V<V IN<V CC−1.5V±10±25mV Input Common Mode Voltage Range0.4V CC−1.5V Voltage Gain300k V/V DC Supply Current(when enabled)V CC=6.0V250µA Response Time100mV Overdrive60100140ns500mV Overdrive80125165ns1000mV Overdrive135215300ns Note7:For comparator output current characteristics see L-Port specs.Typical Performance Characteristics for COP820CJDynamic—I DD vs V CC(Crystal Clock Option)DS011208-32Halt—I DD vs V CC(Brown Out Disabled)DS011208-33Halt—I DD vs V CC(Brown Out Enabled)DS011208-34Ports L/G WeakPull-Up Source CurrentDS011208-35Ports L/G Push-PullSource CurrentDS011208-36Ports L/G Push-PullSink CurrentDS011208-37COP820CJ/COP840CJFamily7Typical Performance Characteristics for COP820CJ(Continued)Typical Performance Characteristics for COP840CJPorts L4–L7Sink CurrentDS011208-38Port D Source CurrentDS011208-39Port D Sink CurrentDS011208-40Brown Out Voltage vs TemperatureDS011208-41Port D Sink currentDS011208-42Halt Current with Brown Out DisabledDS011208-43Halt Current with Brown Out EnabledDS011208-44C O P 820C J /C O P 840C J F a m i l y 8Typical Performance Characteristics for COP840CJ(Continued)Halt Current with Comparator EnabledDS011208-45Ports L/G Push-Pull Source CurrentDS011208-46Ports L/G Push-Pull Sink CurrentDS011208-47Port D Source Current DS011208-48Port D Sink CurrentDS011208-49Brown Out Voltage vs TemperatureDS011208-50COP820CJ/COP840CJ Family9Pin DescriptionV CC and GND are the power supply pins.CKI is the clock input.This can come from an external source,a R/C generated oscillator or a crystal (in conjunc-tion with CKO).See Oscillator description.RESET is the master reset input.See Reset description.PORT I is a 4-bit Hi-Z input port.PORT L is an 8-bit I/O port.There are two registers associated with the L port:a data register and a configuration register.Therefore,each L I/O bit can be individually configured under software control as shown below:Port L Port L Port L Config.Data Setup00Hi-Z Input (TRI-STATE)01Input with Weak Pull-up 10Push-pull Zero Output 11Push-pull One OutputThree data memory address locations are allocated for this port,one each for data register [00D0],configuration register [00D1]and the input pins [00D2].Port L has the following alternate features:L7MIWU or MODOUT (high sink current capability)L6MIWU (high sink current capability)L5MIWU (high sink current capability)L4MIWU (high sink current capability)L3MIWUL2MIWU or CMPIN+L1MIWU or CMPIN−L0MIWU or CMPOUTThe selection of alternate Port L functions is done through registers WKEN [00C9]to enable MIWU and CNTRL2[00CC]to enable comparator and modulator.All eight L-pins have Schmitt Triggers on their inputs.PORT G is an 8-bit port with 6I/O pins (G0–G5)and 2input pins (G6,G7).All eight G-pins have Schmitt Triggers on the inputs.There are two registers associated with the G port:a data register and a configuration register.Therefore each G port bit can be individually configured under software control as shown below:Port G Port G Port G Config.Data Setup00Hi-Z Input (TRI-STATE)01Input with Weak Pull-up 10Push-pull Zero Output 11Push-pull One OutputThree data memory address locations are allocated for this port,one for data register [00D4],one for configuration reg-ister [00D5]and one for the input pins [00D6].Since G6and G7are Hi-Z input only pins,any attempt by the user to con-figure them as outputs by writing a one to the configuration register will be disregarded.Reading the G6and G7configu-ration bits will return zeros.Note that the device will be placed in the Halt mode by writing a “1”to the G7data bit.Six pins of Port G have alternate features:G7CKO crystal oscillator output (selected by mask option)or HALT restart input/general purpose input (if clock option is R/C or external clock)G6SI (MICROWIRE serial data input)G5SK (MICROWIRE clock I/O)G4SO (MICROWIRE serial data output)G3TIO (timer/counter input/output)G0INTR (an external interrupt)Pins G2and G1currently do not have any alternate func-tions.The selection of alternate Port G functions are done through registers PSW [00EF]to enable external interrupt and CN-TRL1[00EE]to select TIO and MICROWIRE operations.PORT D is a four bit output port that is preset when RESET goes low.One data memory address location is allocated for the data register [00DC].Note:Care must be exercised with the D2pin operation.At RESET,the ex-ternal loads on this pin must ensure that the output voltages stay above 0.8V CC to prevent the chip from entering special modes.Also keep the external loading on D2to less than 1000pF.Functional DescriptionThe internal architecture is shown in the block diagram.Data paths are illustrated in simplified form to depict how the vari-ous logic elements communicate with each other in imple-menting the instruction set of the device.ALU and CPU RegistersThe ALU can do an 8-bit addition,subtraction,logical or shift operations in one cycle time.There are five CPU registers:A is the 8-bit Accumulator registerPC is the 15-bit Program Counter registerPU is the upper 7bits of the program counter (PC)PL is the lower 8bits of the program counter (PC)B is the 8-bit address register and can be auto incre-mented or decremented.X is the 8-bit alternate address register and can be autoincremented or decremented.SP is the 8-bit stack pointer which points to the subroutinestack (in RAM).B,X and SP registers are mapped into the on chip RAM.The B and X registers are used to address the on chip RAM.The SP register is used to address the stack in RAM during sub-routine calls and returns.The SP must be preset by software upon initialization.MemoryThe memory is separated into two memory spaces:program and data.PROGRAM MEMORYProgram memory consists of 1024x 8ROM or 2048x 8ROM.These bytes of ROM may be instructions or constant data.The memory is addressed by the 15-bit program counter (PC).ROM can be indirectly read by the LAID in-struction for table lookup.DATA MEMORYThe data memory address space includes on chip RAM,I/O and registers.Data memory is addressed directly by the in-struction or indirectly through B,X and SP registers.The de-vice has 64or 128bytes of RAM.Sixteen bytes of RAM areC O P 820C J /C O P 840C J F a m i l y10Memory(Continued)mapped as“registers”,these can be loaded immediately, decremented and tested.Three specific registers:X,B,and SP are mapped into this space,the other registers are avail-able for general usage.Any bit of data memory can be directly set,reset or tested. All I/O and registers(except A and PC)are memory mapped; therefore,I/O bits and register bits can be directly and indi-vidually set,reset and tested,except the write once only bit (WDREN,WATCHDOG Reset Enable),and the unused and read only bits in CNTRL2and WDREG registers.Note:RAM contents are undefined upon power-up.ResetEXTERNAL RESETThe RESET input pin when pulled low initializes the micro-controller.The user must insure that the RESET pin is held low until V CC is within the specified voltage range and the clock is stabilized.An R/C circuit with a delay5x greater than the power supply rise time is recommended(Figure4). The device immediately goes into reset state when the RE-SET input goes low.When the RESET pin goes high the de-vice comes out of reset state synchronously.The device will be running within two instruction cycles of the RESET pin go-ing high.The following actions occur upon reset:Port L TRI-STATEPort G TRI-STATEPort D HIGHPC CLEAREDRAM Contents RANDOM with Power-On-ResetUNAFFECTED with externalReset(power already applied) B,X,SP Same as RAMPSW,CNTRL1,CNTRL2and WDREG Reg.CLEAREDMulti-Input WakeupReg.WKEDG,WKEN CLEAREDWKPND UNKNOWNData and ConfigurationRegisters for L&G CLEAREDWATCHDOG Timer Prescaler/Counter eachloaded with FFThe device comes out of the HALT mode when the RESET pin is pulled low.In this case,the user has to ensure that the RESET signal is low long enough to allow the oscillator to re-start.An internal256t c delay is normally used in conjunction with the two pin crystal oscillator.When the device comes out of the HALT mode through Multi-Input Wakeup,this de-lay allows the oscillator to stabilize.The following additional actions occur after the device comes out of the HALT mode through the RESET pin.If a two pin crystal/resonator oscillator is being used:RAM Contents UNCHANGEDTimer T1and A Contents UNKNOWN WATCHDOG Timer Prescaler/Counter ALTEREDIf the external or RC Clock option is being used:RAM Contents UNCHANGEDTimer T1and A Contents UNCHANGED WATCHDOG Timer Prescaler/Counter ALTEREDThe external RESET takes priority over the Brown Out Re-set.Note:If the RESET pin is pulled low while Brown Out occurs(Brown Out cir-cuit has detected Brown Out condition),the external reset will not oc-cur until the Brown Out condition is removed.External reset has prior-ity only if V CC is greater than the Brown Out voltage.WATCHDOG RESETWith WATCHDOG enabled,the WATCHDOG logic resetsthe device if the user program does not service the WATCH-DOG timer within the selected service window.The WATCH-DOG reset does not disable the WATCHDOG.Upon WATCHDOG reset,the WATCHDOG Prescaler and Counterare each initialized with FF Hex.The following actions occur upon WATCHDOG reset that are different from external reset.WDREN WATCHDOG Reset Enable bit UNCHANGED WDUDFWATCHDOG Underflow bitUNCHANGEDAdditional initialization actions that occur as a result of WATCHDOG reset are as follows:Port L TRI-STATEPort G TRI-STATEPort D HIGHPC CLEAREDRAM Contents UNCHANGED/RANDOMB,X,SP UNCHANGEDPSW,CNTRL1andCNTRL2(except WDUDFBit)RegistersCLEAREDMulti-Input WakeupRegistersWKEDG,WKEN CLEAREDWKPND UNKNOWNData and ConfigurationRegisters for L&G CLEAREDWATCHDOG Timer Prescalar/Countereach loaded with FFDS011208-51RC>5x Power Supply Rise TimeFIGURE4.Recommended Reset CircuitCOP820CJ/COP840CJFamilyReset(Continued)BROWN OUT RESETThe on-board Brown Out protection circuit resets the device when the operating voltage (V CC )is lower than the Brown Out voltage.The device is held in reset when V CC stays be-low the Brown Out Voltage.The device will remain in RESET as long as V CC is below the Brown Out Voltage.The Device will resume execution if V CC rises above the Brown Out Volt-age.If a two pin crystal/resonator clock option is selected,the Brown Out reset will trigger a 256tc delay.This delay al-lows the oscillator to stabilize before the device exits the re-set state.The delay is not used if the clock option is either R/C or external clock.The contents of data registers and RAM are unknown following a Brown Out reset.The external reset takes priority over Brown Out Reset and will deactivate the 256t c cycles delay if in progress.The Brown Out reset takes priority over the WATCHDOG reset.The following actions occur as a result of Brown Out reset:Port L TRI-STATE Port G TRI-STATE Port D HIGH PCCLEARED RAM Contents RANDOM B,X,SPUNKNOWNPSW,CNTRL1,CNTRL2and WDREG Registers CLEARED Multi-Input Wakeup Registers WKEDG,WKEN CLEARED WKPNDUNKNOWN Data and Configuration Registers for L &G CLEAREDWATCHDOG Timer Prescalar/Counter each loaded with FFTimer T1and AccumulatorUnknown data after coming out of the HALT (through Brown Out Reset)with any Clock option Note 8:The development system will detect the BROWN OUT RESET ex-ternally and will force the RESET pin low.The Development System does not emulate the 256tc delay.Brown Out DetectionAn on-board detection circuit monitors the operating voltage (V CC )and compares it with the minimum operating voltage specified.The Brown Out circuit is designed to reset the de-vice if the operating voltage is below the Brown Out voltage (between 1.8V to 4.2V at −40˚C to +85˚C).The Minimum op-erating voltage for the device is 2.5V with Brown Out dis-abled,but with BROWN OUT enabled the device is guaran-teed to operate properly down to minimum Brown Outvoltage (Max frequency 4MHz),For temperature range of 0˚C to 70˚C the Brown Out voltage is expected to be be-tween 1.9V to 3.9V.The circuit can be enabled or disabled by Brown Out mask option.If the device is intended to oper-ate at lower V CC (lower than Brown Out voltage VBO max),the Brown Out circuit should be disabled by the mask option.The Brown Out circuit may be used as a power-up reset pro-vided the power supply rise time is slower than 50µs (0V to 6.0V).Brown Out should not be used at frequencies over 4MHz (COP840CJ).Note:Brown Out Circuit is active in HALT mode (with the Brown Out maskoption selected).Oscillator CircuitsEXTERNAL OSCILLATORCKI can be driven by an external clock signal provided it meets the specified duty cycle,rise and fall times,and input levels.G7/CKO is available as a general purpose input G7and/or Halt control.CRYSTAL OSCILLATORBy selecting G7/CKO as a clock output,CKI and G7/CKO can be connected to create a crystal controlled oscillator.Table 1shows the component values required for various standard crystal values.R/C OSCILLATOR (COP820CJ)For COP820CJ,selecting CKI as a single pin oscillator,CKI can make a R/C oscillator.G7/CKO is available as a general purpose input and/or HALT control.Table 2shows variation in the oscillator frequencies as functions of the component (R and C)values.TABLE 1.Crystal Oscillator ConfigurationR1R2C1C2CKI Freq.Conditions (k Ω)(M Ω)(pF)(pF)(MHz)013030–3610V CC =5V 013030–364V CC =5V 5.61100/200100–1560.455V CC =5VDS011208-7FIGURE 5.Clock Oscillator ConfigurationsC O P 820C J /C O P 840C J F a m i l yReset(Continued)TABLE2.R/C Oscillator Configuration(Part-To-Part Variation)R C CK1Freq.Instr.CycleConditions (kΩ)(pF)(MHz)(µs)3.382 2.2to2.7 3.7to4.6V CC=5V5.6100 1.1to1.37.4to9.0V CC=5V6.81000.9to1.18.8to10.8V CC=5VR/C OSCILLATOR(COP840CJ)For COP840CJ,selecting the R/C oscillator option makes a R/C oscillator when connecting a resistor from the CKI pin to V.The capacitor is on-chip.The G7/CKO pin is available as a general purpose input G7and/or Halt control.Adding an external capacitor will jeopardize the clock frequency toler-ance and increase EMI emissions.Table3shows the clock frequency for the different resistor values.TABLE3.RC Oscillator Configuration(Part-To-Part Variation)R(kΩ)CK1Freq.(MHz)Temperature V CC2.27.0±15%-40˚C to+85˚C 4.5V to5.5V4.7 4.2±10%-40˚C to+85˚C 4.5V to5.5V20.07.1±10%-40˚C to+85˚C 4.5V to5.5VNote9:The resistance level is calculated with a total of5.3pF capacitance added from the printed circuit board.It is important to take this into account when figuring the clock frequency.HALT ModeThe device is a fully static device.The device enters the HALT mode by writing a one to the G7bit of the G data reg-ister.Once in the HALT mode,the internal circuitry does not receive any clock signal and is therefore frozen in the exact state it was in when halted.In this mode,the chip will only draw leakage current(output current and DC current due to the Brown Out circuit if Brown Out is enabled).The device supports four different methods of exiting the HALT mode.The first method is with a low to high transition on the CKO(G7)pin.This method precludes the use of the crystal clock configuration(since CKO is a dedicated out-put).It may be used either with an RC clock configuration or an external clock configuration.The second method of exit-ing the HALT mode is with the multi-Input Wakeup feature on the L port.The third method of exiting the HALT mode is by pulling the RESET input low.The fourth method is with the operating voltage going below Brown Out voltage(if Brown Out is enabled by mask option).If the two pin crystal/resonator oscillator is being used and Multi-Input Wakeup or Brown Out causes the device to exit the HALT mode,the WAKEUP signal does not allow the chip to start running immediately since crystal oscillators have a delayed start up time to reach full amplitude and freuqency stability.The WATCHDOG timer(consisting of an8-bit pres-caler followed by an8-bit counter)is used to generate a fixed delay of256tc to ensure that the oscillator has indeed stabi-lized before allowing instruction execution.In this case,upon detecting a valid WAKEUP signal only the oscillator circuitry is enabled.The WATCHDOG Counter and Prescaler are each loaded with a value of FF Hex.The WATCHDOG pres-caler is clocked with the t c instruction cycle.(The t c clock is derived by dividing the oscillator clock down by a factor of 10).The Schmitt trigger following the CKI inverter on the chip ensures that the WATCHDOG timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specs.This Schmitt trigger is not part of the oscillator closed loop.The start-up timeout from the WATCH-DOG timer enables the clock signals to be routed to the rest of the chip.The delay is not activated when the device comes out of HALT mode through RESET pin.Also,if the clock option is either RC or External clock,the delay is notused,but the WATCHDOG Prescaler/Counter contents are changed.The Development System will not emulate the256tc delay.The RESET pin or Brown Out will cause the device to resetand start executing from address X’0000.A low to high tran-sition on the G7pin(if single pin oscillator is used)orMulti-Input Wakeup will cause the device to start executingfrom the address following the HALT instruction.When RESET pin is used to exit the device from the HALTmode and the two pin crystal/resonator(CKI/CKO)clock op-tion is selected,the contents of the Accumulator and theTimer T1are undetermined following the reset.All other in-formation except the WATCHDOG Prescaler/Counter con-tents is retained until continuing.If the device comes out ofthe HALT mode through Brown Out reset,the contents ofdata registers and RAM are unknown following the reset.All information except the WATCHDOG Prescaler/Counter con-tents is retained if the device exits the HALT mode throughG7pin or Multi-Input Wakeup.G7is the HALT-restart pin,but it can still be used as an input.If the device is not halted,G7can be used as a general pur-pose input.If the Brown Out Enable mask option is selected,the BrownOut circuit remains active during the HALT mode causing ad-ditional current to be drawn.Note:To allow clock resynchronization,it is necessary to program two NOP’s immediately after the device comes out of the HALT mode.The usermust program two NOP’s following the“enter HALT mode”(set G7data bit)instruction.MICROWIRE/PLUSMICROWIRE/PLUS is a serial synchronous bidirectional communications interface.The MICROWIRE/PLUS capabil-ity enables the device to interface with any of National Semi-conductor’s MICROWIRE peripherals(i.e.A/D converters,display drivers,EEPROMS,etc.)and with other microcon-trollers which support the MICROWIRE/PLUS interface.It consists of an8-bit serial shift register(SIO)with serial dataCOP820CJ/COP840CJFamily。
S849T-GS08资料
S849T / S849TRDocument Number 85051Rev. 1.4, 02-May-05Vishay Semiconductors1MOSMIC ® for TV-Tuner Prestage with 12 V Supply VoltageCommentsMOSMIC - MOS M onolithic I ntegrated C ircuitFeatures•Integrated gate protection diodes •Low noise figure•High gain•Biasing network on chip•Improved cross modulation at gain reduction •High AGC-range •SMD package•Lead (Pb)-free component•Component in accordance to RoHS 2002/95/EC and WEEE 2002/96/ECApplicationsL ow noise gain controlled input stages in UHF-and VHF- tuner with 12 V supply voltage.Mechanical DataTyp: S849TCase: SOT-143 Plastic case Weight: approx. 8.0 mgPinning: 1 = Source, 2 = Drain,3 = Gate 2, 4 = Gate 1Typ: S849TRCase: SOT-143R Plastic case Weight: approx. 8.0 mgPinning: 1 = Source, 2 = Drain,3 = Gate 2, 4 = Gate 1Parts TablePartMarkingPackageS849T 849SOT -143S849TR49RSOT -143R 2Document Number 85051Rev. 1.4, 02-May-05S849T / S849TRVishay Semiconductors Absolute Maximum RatingsT amb = 25°C, unless otherwise specifiedMaximum Thermal Resistance1) on glass fibre printed board (25 x 20 x 1.5) mm 3 plated with 35 μm CuElectrical DC CharacteristicsT amb = 25°C, unless otherwise specifiedParameterTest conditionSymbol Value Unit Drain - source voltage V DS 16V Drain currentI D 30mA Gate 1/Gate 2 - source peak current± I G1/G2SM 10mA Gate 1/Gate 2 - source voltage ± V G1/G2SM7.5V Total power dissipation T amb ≤ 60°CP tot 200mW Channel temperature T Ch 150°C Storage temperature rangeT stg- 55 to + 150°CParameterTest condition Symbol Value Unit Channel ambient1)R thChA450K/WParameterTest conditionSymbolMin Typ.Max Unit Gate 1 - source breakdown voltage± I G1S = 10 mA, V G2S = V DS = 0± V (BR)G1SS 812V Gate 2 - source breakdown voltage± I G2S = 10 mA, V G1S = V DS = 0± V (BR)G2SS812V Gate 1 - source leakage current + V G1S = 6 V , V G2S = V DS = 0+ I G1SS 60μA - V G1S = 6 V, V G2S = V DS = 0- I G1SS 120μA Gate 2 - source leakage current ± V G2S = 6 V , V G1S = V DS = 0± I G2SS 20nA Drain currentV DS = 12 V , V G1S = 0, V G2S = 6 V I DSS 50500μA Self-biased operating current V DS = 12 V , V G1S = nc, V G2S = 6 VI DSP 81216mA Gate 2 - source cut-off voltageV DS = 12 V , V G1S = nc, I D = 200 μAV G2S(OFF)1.0VS849T / S849TRDocument Number 85051Rev. 1.4, 02-May-05Vishay Semiconductors3Electrical AC CharacteristicsT amb = 25°C, unless otherwise specified V DS = 12 V, V G2S = 6 V, f = 1 MHzCaution for Gate 1 switch-off mode:No external DC-voltage on Gate 1 in active mode!Switch-off at Gate 1 with V G1S < 0.7 V is feasible.Using open collector switching transistor (inside of PLL), insert 10 k Ω collector resistor.Common Emitter S-ParametersParameterT est conditionSymbol Min T yp.Max Unit Forward transadmittance |y 21s |202428mS Gate 1 input capacitance C issg1 2.1 2.5pF Feedback capacitance C rss 20fF Output capacitance C oss 0.9pF Power gainG S = 2 mS, G L = 0.5 mS, f = 200 MHzG ps 26dB G S = 3,3 mS, G L = 1 mS, f = 800 MHzG ps 16.520dB AGC range V DS = 12 V, V G2S = 1 to 6 V , f = 800 MHzΔG ps 40dB Noise figureG S = 2 mS, G L = 0.5 mS, f = 200 MHzF 1dBG S = 3.3 mS, G L = 1 mS, f = 800 MHzF1.3dBf/MHzS11S21S12S22LOG MAGANG LOG MAGANG LOG MAGANG LOG MAGANG deg deg deg deg 50-0.01-3.97.46175.0-61.6487.7-0.17-1.7100-0.04-7.67.37169.3-55.5885.2-0.20-3.3150-0.11-11.57.30163.4-52.0582.0-0.22-5.0200-0.16-15.17.21157.8-49.7879.5-0.25-6.6250-0.28-19.17.09151.8-48.1576.4-0.26-8.4300-0.39-22.4 6.98146.8-46.7975.0-0.31-9.8350-0.51-26.0 6.79141.2-45.9272.6-0.34-11.3400-0.65-29.4 6.66136.0-45.1570.9-0.38-12.8450-0.79-32.7 6.47131.0-44.6669.5-0.44-14.3500-0.95-35.8 6.29125.8-44.2867.8-0.48-15.9550-1.09-39.0 6.13121.0-44.1367.3-0.53-17.4600-1.26-42.2 5.91116.0-44.0468.0-0.59-18.8650-1.41-45.1 5.76111.8-43.8468.6-0.63-20.2700-1.56-48.3 5.55106.9-43.9769.2-0.65-21.6750-1.71-50.9 5.40102.6-44.1870.4-0.72-23.1800-1.89-53.6 5.2298.0-44.5473.2-0.76-24.4850-2.02-56.7 5.0893.8-44.8177.0-0.80-25.9900-2.15-59.5 4.8989.4-45.0383.4-0.85-27.6950-2.28-62.3 4.7585.2-44.8790.8-0.90-29.01000-2.45-65.1 4.5580.9-44.5995.7-0.96-30.21050-2.59-67.8 4.3876.2-44.59100.2-1.07-31.61100-2.75-70.5 4.2072.2-44.54108.4-1.11-33.01150-2.81-73.34.1467.9-44.05116.7-1.13-34.7 4Document Number 85051Rev. 1.4, 02-May-05S849T / S849TRVishay SemiconductorsTypical Characteristics (Tamb = 25 °C unless otherwise specified)1200-2.96-75.7 4.0264.3-43.33125.5-1.15-36.21250-3.07-78.7 3.9060.1-42.41133.5-1.18-37.61300-3.18-81.43.7355.6-41.13139.3-1.26-39.1f/MHzS11S21S12S22LOG MAGANG LOG MAGANG LOG MAGANG LOG MAGANG degdeg deg deg Figure 1. Total Power Dissipation vs. Ambient Temperature Figure 2. Drain Current vs. Drain Source Voltage 0255075100050100150200250P -T o t a l P o w e r D i s s i p a t i o n (m W )t o t T amb –AmbientTemperature (°C )15095107591252468048I –D r a i n C u r r e n t (m A )D V DS –Drain Source Voltage (V )12951076010Figure 3. Drain Current vs. Gate 2 Source VoltageFigure4. Forward Transadmittance vs. Gate 2 Source Voltage1234048121620I -D r a i n C u r r e n t (m A )D V G2S -Gate 2Source Voltage (V )695107615095107641234V G2S -Gate 2Source Voltage (V )65y -F o r w a r d T r a n s a d m i t t a n c e (m S )21sS849T / S849TRDocument Number 85051Rev. 1.4, 02-May-05Vishay Semiconductors5Figure 5. Gate 1 Input Capacitance vs. Gate 2 Source Voltage Figure 6. Output Capacitance vs. Drain Source VoltageFigure 7. Transducer Gain vs. Gate 2 Source VoltageC -G a t e 1I n p u t C a p a c i t a n c e (p F )i s s g 19510762012341234V G2S –Gate 2Source Voltage (V )650.00.51.01.52.068101214V DS -Drain Source Voltage (V )15967C -O u t p u t C a p a c i t a n c e (p F )o ss -60-40-20S -T r a n s d u c e r G a i n (d B )295107631234V G2S –Gate 2Source Voltage (V )6521Figure 8. Cross Modulation vs. Gate 2 Source VoltageC M –C r o s s M o d u l a t i o n ( d B )95 1113802040608023456V G2S – Gate 2 Source V oltage ( V ) 6Document Number 85051 Rev. 1.4, 02-May-05S849T / S849TR Vishay SemiconductorsV DS = 10 V, I D = 10 mA, Z0 = 50 ΩS11 S21S12S22Figure9. Input Reflection CoefficientFigure10. Forward Transmission Coefficientj∞0°12950Figure11. Reverse Transmission CoefficientFigure12. Output Reflection Coefficient0°18012949jı∞S849T / S849TRDocument Number 85051Rev. 1.4, 02-May-05Vishay Semiconductors7Package Dimensions in mmPackage Dimensions in mm 8Document Number 85051 Rev. 1.4, 02-May-05S849T / S849TRVishay SemiconductorsOzone Depleting Substances Policy StatementIt is the policy of Vishay Semiconductor GmbH to1.Meet all present and future national and international statutory requirements.2.Regularly and continuously improve the performance of our products, processes, distribution and operatingsystems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment.It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs).The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances.Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents.1.Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendmentsrespectively2.Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the EnvironmentalProtection Agency (EPA) in the USA3.Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.We reserve the right to make changes to improve technical designand may do so without further notice.Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. 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