K8D1716UTC-PI08中文资料

FLASH MEMORY K8D1716UTC / K8D1716UBCDocument Title16M Bit (2M x8/1M x16) Dual Bank NOR Flash MemoryRevision HistoryRevision No.0.00.10.21.0RemarkAdvancePreliminaryPreliminary HistoryInitial DraftSupport 48TSOP1 Lead Free PackageSupport 48FBGA Leaded/Lead Free PackageSpecification finalizedDraft DateJuly 25, 2004Sep 16, 2004Nov 29, 2004Dec 16, 2004FLASH MEMORYK8D1716UTC / K8D1716UBC16M Bit (2M x8/1M x16) Dual Bank NOR Flash MemoryThe K8D1716U featuring single 3.0V power supply, is a 16Mbit NOR-type Flash Memory organized as 2Mx8 or 1M x16. The memory architecture of the device is designed to divide its memory arrays into 39 blocks to be protected by the block group. This block architecture provides highly flexible erase and program capability. The K8D1716U NOR Flash consists of two banks. This device is capable of reading data from one bank while programming or erasing in the other bank. Access times of 70ns, 80ns and 90ns are available for the device. The device ′s fast access times allow high speed microprocessors to operate without wait states. The device performs a program operation in units of 8 bits (Byte) or 16 bits (Word) and erases in units of a block. Single or multiple blocks can be erased. The block erase operation is completed within typically 0.7 sec. The device requires 15mA as program/erase current in the standard and industrial temperature ranges.The K8D1716U NOR Flash Memory is created by using Sam-sung's advanced CMOS process technology. This device is available in 48 pin TSOP1 and 48 ball FBGA package. The device is compatible with EPROM applications to require high-density and cost-effective nonvolatile read/write storage solu-tions.FEATURES• Single Voltage, 2.7V to 3.6V for Read and Write operations • Organization1,048,576 x 16 bit (Word mode)• Fast Read Access Time : 70ns• Read While Program/Erase Operation • Dual Bank architecturesBank 1 / Bank 2 : 8Mb / 8Mb• Secode(Security Code) Block : Extra 64K Byte block • Power Consumption (typical value @5MHz) - Read Current : 14mA- Program/Erase Current : 15mA- Read While Program or Read While Erase Current : 25mA - Standby Mode/Auto Sleep Mode : 5µA • WP/ACC input pin- Allows special protection of two outermost boot blocks at V IL , regardless of block protect status- Removes special protection of two outermost boot block at V IH, the two blocks return to normal block protect status - Program time at V HH : 9µs/word • Erase Suspend/Resume • Unlock Bypass Program • Hardware RESET Pin• Command Register Operation• Block Group Protection / Unprotection• Supports Common Flash Memory Interface • Industrial Temperature : -40°C to 85°C• Endurance : 100,000 Program/Erase Cycles Minimum • Data Retention : 10 years• Package : 48 Pin TSOP1 : 12 x 20 mm / 0.5 mm Pin pitch 48 Ball FBGA : 6 x 8.5 mm / 0.8 mm Ball pitchGENERAL DESCRIPTIONSAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.PIN DESCRIPTIONPin Name Pin FunctionA0 - A19Address Inputs DQ0 - DQ14Data Inputs / Outputs DQ15/A-1DQ15 Data Input / Output A-1 LSB Address BYTE Word / Byte Selection CE Chip Enable OE Output Enable RESET Hardware Reset Pin RY/BY Ready/Busy Output WE Write EnableWP/ACCHardware Write Protection/Program Acceleration Vcc Power Supply V SS Ground N.CNo ConnectionPIN CONFIGURATION48-pin TSOP1Standard Type 12mm x 20mm123456789101112131415161718192021222324484746454443424140393837363534333231302928272625A15A14A13A12A11A10A9A8A19N.C WE RESETN.C WP/ACC RY/BY A18A17A7A6A5A4A3A2A1A16BYTE VssDQ15/A-1DQ7DQ14DQ6DQ13DQ5DQ12DQ4Vcc DQ11DQ3DQ10DQ2DQ9DQ1DQ8DQ0OE Vss CE A0Note :Please refer to the package dimension.FLASH MEMORY K8D1716UTC / K8D1716UBCFUNCTIONAL BLOCK DIAGRAMVccVssCEOEWEBYTERESETRY/BYA0~A19 DQ0~DQ14I/OInterface&BankControlXDecY Dec Latch &ControlLatch &ControlDecXY DecEraseControlProgramControlHighVoltageGen.Bank2Cell ArrayBank1AddressBank2AddressBank1 Data-In/OutBank2 Data-In/OutBank1Cell ArrayWP/ACC DQ15/A-1A3A7A9A13A4A17RESETRY/BYA8A12A2A6A18N.C A10A14DQ15/A5N.C A19A11A0DQ0DQ2DQ5DQ7A16CE DQ8DQ10DQ12DQ14BYTEDQ9DQ11V CC DQ13V SS DQ1DQ3DQ4DQ6V SSA-123456CDEFGHWEWP/A1A15OEACC48 Ball FBGA TOP VIEW (BALL DOWN)1ABFLASH MEMORYK8D1716UTC / K8D1716UBCORDERING INFORMATIONK 8 D 17 1 6 U T C - Y I 0 7SamsungNOR Flash Memory Device TypeDual Bank Boot BlockOperating Temperature RangeC = Commercial Temp. (0 °C to 70 °C) I = Industrial Temp. (-40 °C to 85 °C)Block Architecture T = Top Boot Block B = Bottom Boot BlockVersion ionAccess Time 07 = 70 ns 08 = 80 ns 09 = 90 nsOperating Voltage Range 2.7V to 3.6VOrganization x16Table 1. PRODUCT LINE-UPPart No.- 7-8-9Vcc2.7V~3.6V Max. Address Access Time (ns)70ns 80ns 90ns Max. CE Access Time (ns)70ns 80ns 90ns Max. OE Access Time (ns)25ns 25ns35ns Table 2. K8D1716U DEVICE BANK DIVISIONSDevice Part Number Bank 1Bank 2Mbit Block Sizes Mbit Block Sizes K8D1716U8 MbitEight 8 Kbyte/4 Kword,fifteen 64 Kbyte/32 Kword8 MbitSixteen64 Kbyte/32 KwordBank Division17 = 8Mbits + 8Mbits PackageP = 48TSOP1(Lead-Free) Y = 48 TSOP1 D : FBGA(Lead Free) F : FBGAFLASH MEMORY K8D1716UTC / K8D1716UBCTable 3. Top Boot Block Address(K8D1716UT)K8D1716UT Block A19A18A17A16A15A14A13A12 Block Size(KW/KB)Address RangeWord Mode Byte ModeBank1BA38111111114/8FF000H-FFFFFH1FE000H-1FFFFFH BA37111111104/8FE000H-FEFFFH1FC000H-1FDFFFH BA36111111014/8FD000H-FDFFFH1FA000H-1FBFFFH BA35111111004/8FC000H-FCFFFH1F8000H-1F9FFFH BA34111110114/8FB000H-FBFFFH1F6000H-1F7FFFH BA33111110104/8FA000H-FAFFFH1F4000H-1F5FFFH BA32111110014/8F9000H-F9FFFH1F2000H-1F3FFFH BA31111110004/8F8000H-F8FFFH1F0000H-1F1FFFH BA3011110X X X32/64F0000H-F7FFFH1E0000H-1EFFFFH BA2911101X X X32/64E8000H-EFFFFH1D0000H-1DFFFFH BA2811100X X X32/64E0000H-E7FFFH1C0000H-1CFFFFH BA2711011X X X32/64D8000H-DFFFFH1B0000H-1BFFFFH BA2611010X X X32/64D0000H-D7FFFH1A0000H-1AFFFFH BA2511001X X X32/64C8000H-CFFFFH190000H-19FFFFH BA2411000X X X32/64C0000H-C7FFFH180000H-18FFFFH BA2310111X X X32/64B8000H-BFFFFH170000H-17FFFFH BA2210110X X X32/64B0000H-B7FFFH160000H-16FFFFH BA2110101X X X32/64A8000H-AFFFFH150000H-15FFFFH BA2010100X X X32/64A0000H-A7FFFH140000H-14FFFFH BA1910011X X X32/6498000H-9FFFFH130000H-13FFFFH BA1810010X X X32/6490000H-97FFFH120000H-12FFFFH BA1710001X X X32/6488000H-8FFFFH110000H-11FFFFH BA1610000X X X32/6480000H-87FFFH100000H-10FFFFHBank2BA1501111X X X32/6478000H-7FFFFH0F0000H-0FFFFFH BA1401110X X X32/6470000H-77FFFH0E0000H-0EFFFFH BA1301101X X X32/6468000H-6FFFFH0D0000H-0DFFFFH BA1201100X X X32/6460000H-67FFFH0C0000H-0CFFFFH BA1101011X X X32/6458000H-5FFFFH0B0000H-0BFFFFH BA1001010X X X32/6450000H-57FFFH0A0000H-0AFFFFH BA901001X X X32/6448000H-4FFFFH090000H-09FFFFH BA801000X X X32/6440000H-47FFFH080000H-08FFFFH BA700111X X X32/6438000H-3FFFFH070000H-07FFFFH BA600110X X X32/6430000H-37FFFH060000H-06FFFFH BA500101X X X32/6428000H-2FFFFH050000H-05FFFFH BA400100X X X32/6420000H-27FFFH040000H-04FFFFH BA300011X X X32/6418000H-1FFFFH030000H-03FFFFH BA200010X X X32/6410000H-17FFFH020000H-02FFFFH BA100001X X X32/6408000H-0FFFFH010000H-01FFFFH BA000000X X X32/6400000H-07FFFH000000H-00FFFFHDeviceBlock AddressA19-A12BlockSize(X8)Address Range(X16)Address RangeK8D1716UT11111xxx64/321F0000H-1FFFFFH F8000H-FFFFFHTable 4. Secode Block Addresses for Top Boot DevicesFLASH MEMORY K8D1716UTC / K8D1716UBCTable 5. Bottom Boot Block Address(K8D1716UB)K8D1716UT Block A19A18A17A16A15A14A13A12 Block Size(KW/KB)Address RangeWord Mode Byte ModeBank2BA3811111X X X32/64F8000H-FFFFFH1F0000H-1FFFFFH BA3711110X X X32/64F0000H-F7FFFH1E0000H-1EFFFFH BA3611101X X X32/64E8000H-EFFFFH1D0000H-1DFFFFH BA3511100X X X32/64E0000H-E7FFFH1C0000H-1CFFFFH BA3411011X X X32/64D8000H-DFFFFH1B0000H-1BFFFFH BA3311010X X X32/64D0000H-D7FFFH1A0000H-1AFFFFH BA3211001X X X32/64C8000H-CFFFFH190000H-19FFFFH BA3111000X X X32/64C0000H-C7FFFH180000H-18FFFFH BA3010111X X X32/64B8000H-BFFFFH170000H-17FFFFH BA2910110X X X32/64B0000H-B7FFFH160000H-16FFFFH BA2810101X X X32/64A8000H-AFFFFH150000H-15FFFFH BA2710100X X X32/64A0000H-A7FFFH140000H-14FFFFH BA2610011X X X32/6498000H-9FFFFH130000H-13FFFFH BA2510010X X X32/6490000H-97FFFH120000H-12FFFFH BA2410001X X X32/6488000H-8FFFFH110000H-11FFFFH BA2310000X X X32/6480000H-87FFFH100000H-10FFFFHBank1BA2201111X X X32/6478000H-7FFFFH0F0000H-0FFFFFH BA2101110X X X32/6470000H-77FFFH0E0000H-0EFFFFH BA2001101X X X32/6468000H-6FFFFH0D0000H-0DFFFFH BA1901100X X X32/6460000H-67FFFH0C0000H-0CFFFFH BA1801011X X X32/6458000H-5FFFFH0B0000H-0BFFFFH BA1701010X X X32/6450000H-57FFFH0A0000H-0AFFFFH BA1601001X X X32/6448000H-4FFFFH090000H-09FFFFH BA1501000X X X32/6440000H-47FFFH080000H-08FFFFH BA1400111X X X32/6438000H-3FFFFH070000H-07FFFFH BA1300110X X X32/6430000H-37FFFH060000H-06FFFFH BA1200101X X X32/6428000H-2FFFFH050000H-05FFFFH BA1100100X X X32/6420000H-27FFFH040000H-04FFFFH BA1000011X X X32/6418000H-1FFFFH030000H-03FFFFH BA900010X X X32/6410000H-17FFFH020000H-02FFFFH BA800001X X X32/6408000H-0FFFFH010000H-01FFFFH BA7000001114/807000H-07FFFH00E000H-00FFFFH BA6000001104/806000H-06FFFH00C000H-00DFFFH BA5000001014/805000H-05FFFH00A000H-00BFFFH BA4000001004/804000H-04FFFH008000H-009FFFH BA3000000114/803000H-03FFFH006000H-007FFFH BA2000000104/802000H-02FFFH004000H-005FFFH BA1000000014/801000H-01FFFH002000H-003FFFH BA0000000004/800000H-00FFFH000000H-001FFFHDeviceBlock AddressA19-A12BlockSize(X8)Address Range(X16)Address Range K8D1716UB00000xxx64/32000000H-00FFFFH00000H-07FFFHTable 6. Secode Block Addresses for Bottom Boot DevicesFLASH MEMORYK8D1716UTC / K8D1716UBCPRODUCT INTRODUCTIONTable 7. Operations TableOperation CEOE WE BYTE WP/ACC A9A6A1A0DQ15/A-1DQ8/DQ14DQ0/DQ7RESET Read word L L H H L/H A9A6A1A0DQ15D OUT D OUT H byteL L H L A9A6A1A0A-1High-Z D OUT H Stand-by Vcc ±0.3V X X X (2)X X X X High-Z High-Z High-Z (2)Output Disable L H H X L/H X X X X High-Z High-Z High-Z H Reset X X X X L/H X X X X High-Z High-Z High-Z L Writeword L H L H (4)A9A6A1A0D IN D IN D IN H byteL H L L A9A6A1A0A-1High-Z D IN H Enable Block Group Protect (3)L H L X L/H X L H L X X D IN V ID Enable Block Group Unprotect (3)L H L X (4)X H H L X X D IN V ID Temporary Block GroupX X X X (4)X X X X X X X V ID Auto SelectManufacturer ID (5)L L H X L/H V ID L L L X X Code (SeeTable 9)H Auto SelectDevice Code (5)LLHXL/HV IDLLHXXCode (SeeTable 9)HNotes :1. L = V IL (Low), H = V IH (High), V ID = 8.5V~12.5V, D IN = Data in, D OUT = Data out, X = Don't care. 2. WP/ACC and RESET pin are asserted at Vcc ±0.3 V or Vss ±0.3 V in the Stand-by mode.3. Addresses must be composed of the Block address (A12 - A19).The Block Protect and Unprotect operations may be implemented via programming equipment too. Refer to the "Block Group Protection and Unprotection".4. If WP/ACC =V IL, the two outermost boot blocks is protected. If WP/ACC =V IH, the two outermost boot block protection depends on whether those blocks were last protected or unprotected using the method described in "Block Group Protection and Unprotection". If WP/ACC =V HH , all blocks will be temporarily unprotected.5. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 9.The K8D1716U is a 16Mbit (16,777,216 bits) NOR-type Flash memory. The device features single voltage power supply operating within the range of 2.7V to 3.6V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flex-ible erase and program capability, the device adapts a block memory architecture that divides its memory array into 39 blocks (64-Kbyte x 31 , 8-Kbyte x 8). Programming is done in units of 8 bits (Byte) or 16 bits (Word). All bits of data in one or multiple blocks can be erased simultaneously when the device executes the erase operation. To prevent the device from accidental erasing or over-writ-ing the programmed data, 39 memory blocks can be hardware protected by the block group. Byte/Word modes are available for read operation. These modes can be selected via BYTE pin. The device provides read access times of 70ns, 80ns and 90ns supporting high speed microprocessors to operate without any wait states.The command set of K8D1716U is fully compatible with standard Flash devices. The device is controlled by chip enable (CE), output enable (OE) and write enable (WE). Device operations are executed by selective command codes. The command codes to be com-bined wih addresses and data are sequentially written to the command registers using microprocessor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase circuitry. Register contents also internally latch addresses and data necessary to execute the program and erase operations. The K8D1716U is implemented with Internal Program/Erase Algorithms to execute the program/erase operations. The Internal Program/Erase Algorithms are invoked by program/erase command sequences. The Internal Program Algorithm automatically programs and verifies data at specified addresses. The Internal Erase Algorithm automatically pre-programs the memory cell which is not programmed and then executes the erase operation. The K8D1716U has means to indicate the status of completion of program/erase operations. The status can be indicated via the RY/BY pin, Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to the read mode. The device requires only 14 mA as active read current and 15 mA for program/erase operations.FLASH MEMORY K8D1716UTC / K8D1716UBCCOMMAND DEFINITIONSThe K8D1716U operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a certain mode, a proper command with specific address and data sequences must be written into the command reg-ister. Writing incorrect information which include address and data or writing an improper command will reset the device to the read mode. The defined valid register command sequences are stated in Table 8. Note that Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Block Erase Operation is in progress.Table 8. Command SequencesCommand Sequence Cycle1st Cycle2nd Cycle3rd Cycle4th Cycle5th Cycle6th Cycle Word Byte Word Byte Word Byte Word Byte Word Byte Word ByteRead Addr1RA Data RDReset Addr1XXXH Data F0HAutoselect Manufacturer ID (2,3) Addr4555H AAAH2AAH555HDA/555HDA/AAAHDA/X00HDA/X00H Data AAH 55H90H ECHAutoselect Device Code (2,3) Addr4555H AAAH2AAH555HDA/555HDA/AAAHDA/X01HDA/X02HData AAH 55H90H(SeeTable9)Autoselect Block Group Protect Verify (2,3) Addr4555H AAAH2AAH555HDA/555HDA/AAAHBA /X02HBA/X04H Data AAH 55H90H(See Table 9)Auto Select Secode Block Factory Protect Verify (2,3) Addr4555H AAAH2AAH555HDA/555HDA/AAAHDA /X03HDA/X06H Data AAH 55H90H(See Table 9)Enter Secode Block Region Addr3555H AAAH2AAH555H 555H AAAH Data AAH 55H88HExit Secode Block Region Addr4555H AAAH2AAH555H 555H AAAH XXXH Data AAH 55H90H00HProgram Addr4555H AAAH2AAH555H 555H AAAH PA Data AAH55H A0H PDUnlock Bypass Addr3555H AAAH2AAH555H 555H AAAH Data AAH55H20HUnlock Bypass Program Addr2XXXH PA Data A0H PDUnlock Bypass Reset Addr2XXXH XXXH Data90H00HChip Erase Addr6555H AAAH2AAH555H 555H AAAH 555H AAAH 2AAH555H555H AAAH Data AAH55H80H AAH55H10HBlock Erase Addr6555H AAAH2AAH555H 555H AAAH 555H AAAH 2AAH555H BA Data AAH55H80H AAH55H30HBlock Erase Suspend (4, 5)Addr1XXXH Data B0HBlock Erase Resume Addr1XXXH Data30HCFI Query (6)Addr155H AAH Data98HFLASH MEMORY K8D1716UTC / K8D1716UBCNotes : 1. RA : Read Address, PA : Program Address, RD : Read Data, PD : Program DataDA : Dual Bank Address, BA : Block Address (A12 - A19), X = Don’t care .2. To terminate the Autoselect Mode, it is necessary to write Reset command to the register.3. The 4th cycle data of Autoselect mode is output data.The 3rd and 4th cycle bank addresses of Autoselect mode must be same.4. The Read / Program operations at non-erasing blocks and the autoselect mode are allowed in the Erase Suspend mode.5. The Erase Suspend command is applicable only to the Block Erase operation.6. Command is valid when the device is in read mode or Autoselect mode.7. DQ8 - DQ15 are don’t care in command sequence, but RD and PD is excluded.8. A11 - A19 are also don’t care, except for the case of special notice.Description CE OE WE A19toA12A11toA10A9A8toA7A6A5toA2A1A0DQ8 to DQ15DQ7toDQ0BYTE=V IHBYTE=V ILManufacturer ID L L H DA X V ID X L X L L X X ECH Device Code K8D1716UT(Top Boot Block)L L H DA X V ID X L X L H22H X75HDevice Code K8D1716UB(Bottom Boot Block)L L H DA X V ID X L X L H22H X77HBlock Protection Verification L L H BA X V ID X L X H L X X01H (Protected),00H (Unprotected)Secode Block (2) Indicator Bit (DQ7)L L H DA X V ID X L X H H X X80H (Factory locked),00H (Not factory locked)Table 9. K8D1716U Autoselect Codes, (High Voltage Method)Notes : 1. L=Logic Low=V IL, H=Logic High=V IH, DA=Dual Bank Address, BA=Block Address, X=Don’t care.2. Secode Block : Security Code Block.FLASH MEMORYK8D1716UTC / K8D1716UBCDEVICE OPERATION Byte/Word ModeIf the BYTE pin is set at logical "1" , the device is in word mode, DQ0-DQ15 are active. Otherwise the BYTE pin is set at logical "0" ,the device is in byte mode, DQ0-DQ7 are active. DQ8-DQ14 are in the High-Z state and DQ15 pin is used as an input for the LSB (A-1) address pin.Read ModeThe K8D1716U is controlled by Chip Enable (CE), Output Enable (OE) and Write Enable (WE). When CE and OE are low and WE is high, the data stored at the specified address location,will be the output of the device. The outputs are in high impedance state whenever CE or OE is high.Standby ModeThe K8D1716U features Stand-by Mode to reduce power consumption. This mode puts the device on hold when the device is dese-lected by making CE high (CE = V IH ). Refer to the DC characteristics for more details on stand-by modes.Output DisableThe device outputs are disabled when OE is High (OE = V IH ). The output pins are in high impedance state.Automatic Sleep ModeK8D1716U features Automatic Sleep Mode to minimize the device power consumption. Since the device typically draws 5µA of the current in Automatic Sleep Mode, this feature plays an extremely important role in battery-powered applications. When addresses remain steady for t AA +50ns, the device automatically activates the Automatic Sleep Mode. In the sleep mode, output data is latched and always available to the system. When addresses are changed, the device provides new data without wait time.Data Outputst AA + 50nsDataAuto Sleep ModeAddressData Data Data DataFigure 1. Auto Sleep Mode OperationAutoselect ModeThe K8D1716U offers the Autoselect Mode to identify manufacturer and device type by reading a binary code. The Autoselect Mode allows programming equipment to automatically match the device to be programmed with its corresponding programming algorithm.In addition, this mode allows the verification of the status of write protected blocks. This mode is used by two method. The one is high voltage method to be required V ID (8.5V~12.5V) on address pin A9. When A9 is held at V ID and the bank address or block address is asserted, the device outputs the valid data via DQ pins(see Table 9 and Figure 2). The rest of addresses except A0, A1 and A6 are Don ′t Care. The other is autoselect command method that the autoselect code is accessible by the commamd sequence without V ID.The manufacturer and device code may also be read via the command register. The Command Sequence is shown in Table 8 and Figure 3. The autoselect operation of block protect verification is initiated by first writing two unlock cycle. The third cycle must con-tain the bank address and autoselect command (90H). If Block address while (A6, A1, A0) = (0,1,0) is finally asserted on the address pin, it will produce a logical "1" at the device output DQ0 to indicate a write protected block or a logical "0" at the device output DQ0to indicate a write unprotected block. To terminate the autoselect operation, write Reset command (F0H) into the command register.FLASH MEMORYK8D1716UTC / K8D1716UBCFigure 3. Autoselect Operation ( by command sequence method )WE555H/AAAH 2AAH/555H 555H/AAAH AAH 55H 90H 00H/01H/ECHManufacturerCode Device Code A19∼A0(x16)/*DQ15∼DQ0F0HReturn to Read ModeWrite (Program/Erase) ModeThe K8D1716U executes its program/erase operations by writing commands into the command register. In order to write the com-mands to the register, CE and WE must be low and OE must be high. Addresses are latched on the falling edge of CE or WE (which-ever occurs last) and the data are latched on the rising edge of CE or WE (whichever occurs first). The device uses standard microprocessor write timing.ProgramThe K8D1716U can be programmed in units of a word or a byte. Programming is writing 0's into the memory array by executing the Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the mem-ory location and the data to be programmed at that location are written. The device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not required to provide further controls or timings.During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program operation will cause data corruption at the corresponding location.Figure 4. Program Command SequenceWE555H/AAAH2AAH/555H555H/AAAHAAH55HA0HProgram Program Program StartDQ15-DQ0AddressDataRY/BYA9V ID00H01HECH2275H or 2277H Manufacturer CodeDevice Code A6,A1,A0*DQ15-DQ0Figure 2. Autoselect Operation ( by high voltage method )Return to Read ModeV = V IH or V IL2275H or 2277H Note : The addresses other than A0 , A1 and A6 are Don ′t care. Please refer to Table 9 for device code.Note : The 3rd Cycle and 4th Cycle address must include the same bank address. Please refer to Table 9 for device code.(K8D1716U )(K8D1716U)A19∼A-1(x8)A19∼A0(x16)/A19∼A-1(x8)00H 02HFLASH MEMORYK8D1716UTC / K8D1716UBCUnlock BypassThe K8D1716U provides the unlock bypass mode to save its program time for program operation. The mode is invoked by the unlock bypass command sequence. Then, the unlock bypass program command sequence is required to program the device.Unlike the standard program command sequence that contains four bus cycles, the unlock bypass program command sequence comprises only two bus cycles.The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writ-ing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypass mode, the unlock bypass program command sequence is necessary to program in this mode. The unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the pro-gram address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode.The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data (00H). Then, the device returns to the read mode.Chip EraseTo erase a chip is to write 1′s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE or CE pulse in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode.Figure 5. Chip Erase Command SequenceWE555H/AAAH2AAH/555H555H/AAAHAAH55H80H555H Chip Erase StartDQ15-DQ0AAAH2AAH/555HAAH55H10HRY/BY555H/AAAHA19∼A0(x16)/A19∼A-1(x8)Block EraseTo erase a block is to write 1′s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six bus cycles to write the command sequence shown in Table 8. After the first two "unlock" cycles, the erase setup command (80H) is written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the falling edge of WE or CE, while the Block Erase command is latched on the rising edge of WE or CE.Multiple blocks can be erased sequentially by writing the six bus-cycle operation in Figure 6. Upon completion of the last cycle for the Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. An 50µs (typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the 50µs "time window", otherwise the Block Erase command will be ignored. The 50µs "time window" is reset when the falling edge of the WE occurs within the 50µs of "time window" to latch the Block Erase command. During the 50µs of "time window", any command other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50µs of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend command during Block Erase operation.。