STM704TDS6E中文资料

1/31September 2004STM690, STM704, STM795STM802, STM804, STM805, STM8063V Supervisor with Battery Switchover* Contact local ST sales office for availability.FEATURES SUMMARY■■NVRAM SUPERVISOR FOR EXTERNAL LPSRAM■CHIP-ENABLE GATING (STM795 only) FOR EXTERNAL LPSRAM (7ns max PROP DELAY)■MANUAL (PUSH-BUTTON) RESET INPUT ■200ms (TYP) t rec■WATCHDOG TIMER - 1.6sec (TYP)■AUTOMATIC BATTERY SWITCHOVER■LOW BATTERY SUPPLY CURRENT - 0.4µA (TYP)■POWER-FAIL COMPARATOR (PFI/PFO)■LOW SUPPLY CURRENT - 40µA (TYP)■GUARANTEED RST (RST) ASSERTION DOWN TO V CC = 1.0V■OPERATING TEMPERATURE:–40°C to 85°C (Industrial Grade)Table 1. Device OptionsNote: 1.2.Open drain output.Watchdog InputActive- Low RST (1)Active- High RSTManual Reset Input Battery Switch-overPower-fail Compar-atorChip-Enable GatingSTM690T/S/R ✔✔✔✔STM704T/S/R ✔✔✔✔STM795T/S/R ✔(2)✔✔STM802T/S/R ✔✔✔✔STM804T/S/R ✔✔(2)✔✔STM805T/S/R ✔✔(2)✔✔STM806T/S/R✔✔✔✔STM690/704/795/802/804/805/806TABLE OF CONTENTSFEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1.Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 1.Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2.Logic Diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure 3.Logic Diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure 4.Logic Diagram (STM795). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Table 2.Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure 5.STM690/802/804/805 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure 6.STM704/806 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure 7.STM795 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 3.Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Figure 8.Block Diagram (STM690/802/804/805). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 9.Block Diagram (STM704/806). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 10.Block Diagram (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 11.Hardware Hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Push-button Reset Input (STM704/806). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Watchdog Input (NOT available on STM704/795/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Back-up Battery Switchover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 4.I/O Status in Battery Back-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..9 Chip-Enable Gating (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Chip Enable Input (STM795 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Chip Enable Output (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Figure 12.Chip-Enable Gating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Figure 13.Chip Enable Waveform (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Power-fail Input/Output (NOT available on STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Figure 14.Power-fail Comparator Waveform (STM690/704/802/804/805/806). . . . . . . . . . . . . . . .11 Using a SuperCap™ as a Backup Power Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Figure ing a SuperCap™. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Negative-Going V CC Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Figure 16.V BAT-to-V OUT On-Resistance vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Figure 17.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Figure 18.V PFI Threshold vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 19.Reset Comparator Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 20.Power-up t rec vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142/31STM690/704/795/802/804/805/806Figure 21.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 22.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 CON On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 24.PFI to PFO Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 25.RST Output Voltage vs. Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 26.RST Output Voltage vs. Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Figure 27.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Figure 28.RESET Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Figure 29.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Figure 30.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . .19 Figure 31.V CC to Reset Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Figure 32.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . .20CON Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 5.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 6.Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Figure 34.E to ECON Propagation Delay Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 35.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 36.MR Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 37.Watchdog Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 7.DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Figure 38.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing. . . .26 Table 8.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . .26 Figure 39.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . .27 Table 9.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data. . . .27PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 10.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 11.Marking Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Table 12.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303/31STM690/704/795/802/804/805/8064/31SUMMARY DESCRIPTIONThe STM690/704/795/802/804/805/806 Supervi-sors are self-contained devices which provide mi-croprocessor supervisory functions with the ability to non-volatize and write-protect external LPSRAM. A precision voltage reference and com-parator monitors the V CC input for an out-of-toler-ance condition. When an invalid V CC condition high in the case of RST). These devices also offer a watchdog timer (except for STM704/795/806) as well as a power-fail comparator (except for STM795) to provide the system with an early warning of impending power failure.These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin TSSOP package.Note: 1.For STM804/805, reset output is active-high and opendrain.Table 2. Signal NamesNote: 1.Open drain for STM804/805 only.2.STM795MR Push-button Reset Input WDIWatchdog InputRST Active-Low Reset Output RST (1)Active-High Reset Output E (2)Chip Enable InputE CON (2)Conditioned Chip Enable Output Vccsw (2)V CC Switch Output V OUTSupply Voltage Output V CC Supply Voltage V BAT Back-up Supply Voltage PFI Power-fail Input PFO Power-fail Output V SSGroundSTM690/704/795/802/804/805/806drain.5/31STM690/704/795/802/804/805/8066/31Pin DescriptionsA logic low on /MR asserts the reset output.Reset remains asserted as long as MR is low and for t rec after MR returns high. This active-low inputhas an internal pull-up. It can be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if unused.WDI.If WDI remains high or low for 1.6sec, the in-ternal watchdog timer runs out and reset is trig-gered. The internal watchdog timer clears while reset is asserted or when WDI sees a rising or fall-ing edge.The watchdog function cannot be disabled by al-lowing the WDI pin to float.Pulses low for t rec when triggered, and stayslow whenever V CC is below the reset threshold or when MR is a logic low. It remains low for t rec after either V CC rises above the reset threshold, the watchdog triggers a reset, or MR goes from low tohigh.RST (Open Drain).Pulses high for t rec when trig-gered, and stays high whenever V CC is above the reset threshold or when MR is a logic high. It re-mains high for t rec after either V CC falls below thereset threshold, the watchdog triggers a reset, orMR goes from high to low.PFI.When PFI is less than V PFI or when V CC falls below V SW remains high. Connect to ground if unused.When PFI is less than V PFI , or V CC falls be-low V SW high. Leave open if unused.V OUT .When V CC is above the switchover voltage(V SO ), V OUT is connected to V CC through a P-channel MOSFET switch. When V CC falls belowV SO , V BAT connects to V OUT . Connect to V CC if no battery is used.When V OUT switches to battery, Vccsw ishigh. When V OUT switches back to V CC low. It can be used to drive gate of external PMOS transistor for I OUT requirements exceeding 75mA.The input to the chip-enable gating circuit. Con-nect to ground if unused.CON .CON goes low only when E is low and re-set is not asserted. If E CON is low when reset is as-CON goes high, whichever occurs first. In the disabled CON is pulled up to V OUT .V BAT .When V CC falls below V SO , V OUT switchesfrom V CC to V BAT . When V CC rises above V SO +hysteresis, V OUT reconnects to V CC . V BAT may ex-ceed V CC . Connect to V CC if no battery is used.Table 3. Pin DescriptionPinNameFunctionSTM795STM690STM802STM704STM806STM804STM805––6–MR Push-button Reset Input –6–6WDI Watchdog Input777–RST Active-Low Reset Output –––7RST Active-High Reset Output –444PFI PFI Power-fail Input –555PFO PFO Power-fail Output1111V OUT Supply Output for External LPSRAM 2222V CC Supply Voltage 3–––Vccsw V CC Switch Output 4333V SS Ground5–––E Chip Enable Input6–––E CON Conditioned Chip Enable Output 8888V BATBackup-Battery InputSTM690/704/795/802/804/805/806Note: 1.For STM804/805, reset output is active-high and open drain.7/31STM690/704/795/802/804/805/806Note: 1.For STM690/802/804/805.2.For STM795 only.3.Not available on STM795.4.For STM704/806.8/31STM690/704/795/802/804/805/806 OPERATIONReset OutputThe STM690/704/795/802/804/805/806 Supervi-sor asserts a reset signal to the MCU whenever V CC goes below the reset threshold (V RST), a watchdog time-out occurs, or when the Push-but-ton Reset Input (MR) is taken low. RST is guaran-teed to be a logic low (logic high for STM804/805) for 0V < V CC < V RST if V BAT is greater than 1V. Without a back-up battery, RST is guaranteed val-id down to V CC =1V.During power-up, once V CC exceeds the reset threshold an internal timer keeps RST low for the reset time-out period, t rec. After this interval RST returns high.If V CC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays low for at least the reset time-out period (t rec). Any time V CC goes below the reset threshold the internal timer clears. The reset timer starts when V CC returns above the reset threshold.Push-button Reset Input (STM704/806)A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t rec (see Figure 36.,page22) after it returns high. The MR input has an internal 40kΩ pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/ collector outputs. Connect a normally open mo-ual reset function; external debounce circuitry is the device is used in a noisy environment, connect a 0.1µF capacitor from MR to GND to provide ad-V CC when not used.Watchdog Input (NOT available on STM704/ 795/806)The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not toggle the Watchdog Input (WDI) within t WD (1.6sec typ), the reset is asserted. The internal watchdog timer is cleared by either:1. a reset pulse, or2.by toggling WDI (high-to-low or low-to-high),which can detect pulses as short as 50ns. If WDI is tied high or low, a reset pulse istriggered every 1.8sec (t WD + t rec).The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is re-leased, the timer starts counting (see Figure 37.,page23).Note: Input frequency greater than 20ns (50MHz) will be filtered.Back-up Battery SwitchoverIn the event of a power failure, it may be necessary to preserve the contents of external SRAM through V OUT. With a backup battery installed with voltage V BAT, the devices automatically switch the SRAM to the back-up supply when V CC falls. Note: If back-up battery is not used, connect both V BAT and V OUT to V CC.This family of Supervisors does not always con-nect V BAT to V OUT when V BAT is greater than V CC. V BAT connects to V OUT (through a 100Ω switch) when V CC is below V SW (2.4V) or V BAT (whichever is lower). This is done to allow the back-up battery (e.g., a 3.6V lithium cell) to have a higher voltage than V CC.Assuming that V BAT > 2.0V, switchover at V SO en-sures that battery back-up mode is entered before V OUT gets too close to the 2.0V minimum required to reliably retain data in most external SRAMs. When V CC recovers, hysteresis is used to avoid oscillation around the V SO point. V OUT is connect-ed to V CC through a 3Ω PMOS power switch. Note: The back-up battery may be removed while V CC is valid, assuming V BAT is adequately decou-pled (0.1µF typ), without danger of triggering a re-set.Table 4. I/O Status in Battery Back-up Pin StatusV OUT Connected to V BAT through internal switchV CC Disconnected from V OUTPFI DisabledPFO Logic LowE High impedanceE CON Logic HighWDI Watchdog timer is disabledMR DisabledRST Logic LowRST Logic HighV BAT Connected to V OUTVccsw Logic High (STM795)9/31STM690/704/795/802/804/805/80610/31Chip-Enable Gating (STM795 only)vents erroneous data from corrupting the external CMOS RAM in the event of an undervoltage con-dition. The STM795 uses a series transmission gate from E to E CON (see Figure 12). During nor-mal operation (reset not asserted), the E transmis-sion gate is enabled and passes all E transitions.When reset is asserted, this path becomes dis-abled, preventing erroneous data from corrupting the CMOS RAM. The short E propagation delay from E to E CON enables the STM795 to be used with most µPs. If E is low when reset asserts,CON remains low for typically 10µs to permit the current WRITE cycle to complete.Chip Enable Input (STM795 only)The chip-enable transmission gate is disabled and E is high impedance (disabled mode) while reset is asserted. During a power-down sequence when V CC passes the reset threshold, the chip-enable transmission gate disables and E immediately be-comes high impedance if the voltage at E is high.transmission gate will disable 10µs after reset as-serts (see Figure 13). This permits the current WRITE cycle to complete during power-down.Any time a reset is generated, the chip-enable transmission gate remains disabled and E remains high impedance (regardless of E activity) for the first half of the reset time-out period (t rec /2). When the chip enable transmission gate is enabled, the impedance of E appears as a 40Ω resistor in se-ries with the load at E CON . The propagation delay through the chip-enable transmission gate de-pends on V CC , the source impedance of the drive connected to E, and the loading on E CON . The chip enable propagation delay is production tested from the 50% point on E to the 50% point on E CON using a 50Ω driver and a 50pF load capacitance (see Figure 35.,page 22). For minimum propaga-CON and use a low-output impedance driver.Chip Enable Output (STM795 only)When the chip-enable transmission gate is en-CON is equivalent to a 40Ω resistor in series with the source driving E. In the disabled mode, the transmission gate is off CON to V OUT (see Figure 12). This pull-up turns off when the trans-mission gate is enabled.Power-fail Input/Output (NOT available on STM795)The Power-fail Input (PFI) is compared to an inter-nal reference voltage (independent from the V RST comparator). If PFI is less than the power-fail threshold (V PFI), the Power-Fail Output (PFO) will go low. This function is intended for use as an un-dervoltage detector to signal a failing power sup-ply. Typically PFI is connected through an external voltage divider (see Figure 11.,page8) to either the unregulated DC input (if it is available) or the regulated output of the V CC regulator. The voltage divider can be set up such that the voltage at PFI falls below V PFI several milliseconds before the regulated V CC input to the STM690/704/795/802/ 804/805/806 or the microprocessor drops below the minimum operating voltage.During battery back-up, the power-fail comparator Figure 14.,page11). This occurs after V CC drops below V SW (2.4V). When power returns, the pow-er-fail comparator is enabled and PFO follows PFI. If the comparator is unused, PFI should be con-nected to V SS and PFO left unconnected. PFO may be connected to MR on the STM704/806 so that a low voltage on PFI will generate a reset out-put.Applications InformationThese Supervisor circuits are not short-circuit pro-tected. Shorting V OUT to ground - excluding pow-er-up transients such as charging a decoupling capacitor - destroys the device. Decouple both V CC and V BAT pins to ground by placing 0.1µF ca-pacitors as close to the device as possible.11/31Using a SuperCap™ as a Backup Power SourceSuperCaps™ are capacitors with extremely high capacitance values (e.g., order of 0.47F) for their size. Figure 15 shows how to use a SuperCap as a back-up power source. The SuperCap may be connected through a diode to the V CC supply. Since V BAT can exceed V CC while V CC is above the reset threshold, there are no special precau-tions when using these supervisors with a Super-Cap.Negative-Going V CC TransientsThe STM690/704/795/802/804/805/806 Supervi-sors are relatively immune to negative-going V CC transients (glitches). Figure 32.,page20 was gen-erated using a negative pulse applied to V CC, starting at V RST + 0.3V and ending below the reset threshold by the magnitude indicated (comparator overdrive). The graph indicates the maximum pulse width a negative V CC transient can have without causing a reset pulse. As the magnitude of the transient increases (further below the thresh-old), the maximum allowable pulse width decreas-es. Any combination of duration and overdrive which lies under the curve will NOT generate a re-set signal. Typically, a V CC transient that goes 100mV below the reset threshold and lasts 40µs or less will not cause a reset pulse. A 0.1µF bypass capacitor mounted as close as possible to the V CC pin provides additional transient immunity.12/31TYPICAL OPERATING CHARACTERISTICSNote: Typical values are at T A = 25°C.13/3114/3115/31Figure 24. PFI to PFO Propagation Delay vs. TemperatureFigure 25. RST Output Voltage vs. Supply Voltage16/31Figure 27. RST Response Time (Assertion)17/3118/3119/31Figure 33. E to E20/3121/31MAXIMUM RATINGStressing the device above the rating listed in the Absolute Maximum Ratings” table may cause per-manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im-plied. Exposure to Absolute Maximum Rating con-ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu-ments.Table 5. Absolute Maximum RatingsNote: 1.Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C for between 90 to 150seconds).DC AND AC PARAMETERSThis section summarizes the operating measure-ment conditions, and the DC and AC characteris-tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the MeasurementConditions summarized in Table 6, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.Table 6. Operating and AC Measurement ConditionsSymbol ParameterValue Unit T STG Storage Temperature (V CC Off)–55 to 150°C T SLD (1)Lead Solder Temperature for 10 seconds 260°C V IO Input or Output Voltage –0.3 to V CC +0.3V V CC /V BATSupply Voltage –0.3 to 6.0V I O Output Current 20mA P DPower Dissipation320mWParameterSTM690/704/795/802/804/805/806Unit V CC /V BAT Supply Voltage1.0 to 5.5V Ambient Operating Temperature (T A )–40 to 85°C Input Rise and Fall Times ≤5ns Input Pulse Voltages0.2 to 0.8V CC V Input and Output Timing Ref. Voltages0.3 to 0.7V CCVFigure 34. E to ENote: 1.C L includes load capacitance and scope probe capacitance.Figure 36. MR Timing WaveformNote: 1.RST for STM805.22/31Table 7. DC and AC CharacteristicsSym Alter-nativeDescription Test Condition(1)Min Typ Max UnitV CC,V BAT(2)Operating Voltage T A = –40 to +85°C 1.1(3) 5.5VI CC V CC Supply CurrentExcluding I OUT (V CC < 5.5V)4060µAExcluding I OUT (V CC < 3.6V)3550µAV CC Supply Current inBattery Back-up ModeExcluding I OUT(V BAT = 2.3V,V CC = 2.0V, MR = V CC)2535µAI BAT(4)V BAT Supply Current inBattery Back-up ModeExcluding I OUT(V BAT = 3.6V)0.4 1.0µAV OUT1V OUT Voltage (Active)I OUT1 = 5mA(5)V CC –0.03V CC –0.015V I OUT1 = 75mAV CC –0.3V CC –0.15V I OUT1 = 250µA,V CC > 2.5V(5)V CC –0.0015V CC –0.0006VV OUT2V OUT Voltage (BatteryBack-up)I OUT2 = 250µA, V BAT = 2.3VV BAT –0.1V BAT –0.034VI OUT2 = 1mA, V BAT = 2.3VV BAT –0.14V V CC to V OUT On-resistance34ΩV BAT to V OUT On-resistance100ΩI LI Input Leakage Current (MR)STM704/806 only;MR = 0V; V CC = 3V2075350µA Input Leakage Current (PFI)0V = V IN = V CC–252+25nA Input Leakage Current (WDI)0V = V IN = V CC–1+1µAI LO Output Leakage Current STM804/805/795;0V = V IN = V CC(6)–1+1µAV IH Input High Voltage (MR, WDI)V RST (max) < V CC < 5.5V0.7V CC VV IL Input Low Voltage (MR, WDI)V RST (max) < V CC < 5.5V0.3V CC V23/31V OL Output Low Voltage (PFO,RST, RST, Vccsw)V CC = V RST (max),I SINK = 3.2mA0.3V Output Low Voltage (E CON)V CC = V RST (max),I OUT = 1.6mA, E = 0V0.2V CC VV OL Output Low Voltage (RST)I OL = 40µA; V CC = 1.0V;V BAT = V CC;T A = 0°C to 85°C0.3VI OL = 200µA;V CC = 1.2V; V BAT = V CC0.3VV OH Output High Voltage (RST,RST)(7)I SOURCE = 1mA,V CC = V RST (max)2.4V Output High Voltage (E CON)V CC = V RST (max),I OUT = 1.6mA, E = V CC0.8V CC V Output High Voltage (PFO)I SOURCE = 75µA,V CC = V RST (max)0.8V CC VV OHB V OH Battery Back-up (E CON,Vccsw, RST)I SOURCE = 100µA,0.8V BA T VPower-fail Comparator (NOT available on STM795)V PFI PFI Input ThresholdPFI Falling(V CC < 3.6V)STM802/804/8061.212 1.237 1.262VSTM690/704/8051.187 1.237 1.287VPFI Hysteresis PFI Rising (V CC < 3.6V)1020mVt PFD PFI to PFO PropagationDelay2µsI SC PFO Output Short toGND CurrentV CC = 3.6V, PFO = 0V0.10.75 2.0mABattery SwitchoverV SOBattery Back-upSwitchover Voltage (8,9)Power-downV BA T > V SW V SW VV BA T < V SW V BA T VPower-upV BA T > V SW V SW VV BA T < V SW V BA T V V SW 2.4V Hysteresis40mVSym Alter-nativeDescription Test Condition(1)Min Typ Max Unit24/31。