CD74HCT166资料
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For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
D0
D7
DS
8 - REGISTERS
Q7
CP CE
MR
TRUTH TABLE
INPUTS
MASTER RESET
PARALLEL ENABLE
CLOCK ENABLE
CLOCK
SERIAL
PARALLEL D0 D7
INTERNAL Q STATES
Q0
Q1
OUTPUT Q7
L
X
X
X
X
X
L
L
L
H
X
at VCC = 5V • HCT Types
- 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Low Level Input Voltage
High Level Output Voltage CMOS Loads
High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads
Low Level Output Voltage TTL Loads Input Leakage Current
L
L
X
X
Q00
Q10
Q0
H
L
LBaidu Nhomakorabea
↑
X
a...h
a
b
h
H
H
L
↑
H
X
H
Q0n
Q6n
H
H
L
↑
L
X
L
Q0n
Q6n
H
X
H
↑
X
X
Q00
Q10
Q70
NOTES: H = High Voltage Level L = Low Voltage Level X = Don’t Care ↑ = Transition from Low to High Level a...h = The level of steady-state input at inputs D0 thru D7, respectively. Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established. Q0n, Q6n = The level of Q0 or Q6, respectively, before the most recent ↑ transition of the clock.
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC
元器件交易网www.cecb2b.com
Data sheet acquired from Harris Semiconductor SCHS157 February 1998
CD74HC166, CD74HCT166
High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register
Copyright © Harris Corporation 1998
1
File Number 1501.1
元器件交易网www.cecb2b.com Functional Diagram
CD74HC166, CD74HCT166
D0 D1 D2 D3 D4 D5 D6 D7
PE
PARALLEL ENABLE CIRCUIT
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Pinout
CD74HC166, CD74HCT166 (PDIP, SOIC) TOP VIEW
DS 1 D0 2 D1 3 D2 4 D3 5 CE 6 CP 7 GND 8
16 VCC 15 PE 14 D7 13 Q7 12 D6 11 D5 10 D4 9 MR
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC
Ordering Information
PART NUMBER
TEMP. RANGE (oC)
PACKAGE
PKG. NO.
CD74HC166E
-55 to 125
16 Ld PDIP E16.3
CD74HCT166E
-55 to 125
16 Ld PDIP E16.3
CD74HC166M
-55 to 125
[ /Title (CD74 HC166 , CD74 HCT16 6) /Subject (High Speed CMOS Logic 8-Bit ParallelIn/Seri
Features
• Buffered Inputs • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range)
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER HC TYPES High Level Input Voltage
SYMBOL
TEST CONDITIONS
25oC
VI (V) IO (mA) VCC (V) MIN TYP MAX
VIH
-
-
VIL
-
-
VOH VOL
II
VIH or VIL
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
2. Wafer and die is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.
16 Ld SOIC M16.15
CD74HCT166M
-55 to 125
16 Ld SOIC M16.15
CD54HC166W
-55 to 125
Wafer
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
2
元器件交易网www.cecb2b.com
CD74HC166, CD74HCT166
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK
160
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Thermal Information
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
D0
D7
DS
8 - REGISTERS
Q7
CP CE
MR
TRUTH TABLE
INPUTS
MASTER RESET
PARALLEL ENABLE
CLOCK ENABLE
CLOCK
SERIAL
PARALLEL D0 D7
INTERNAL Q STATES
Q0
Q1
OUTPUT Q7
L
X
X
X
X
X
L
L
L
H
X
at VCC = 5V • HCT Types
- 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Low Level Input Voltage
High Level Output Voltage CMOS Loads
High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads
Low Level Output Voltage TTL Loads Input Leakage Current
L
L
X
X
Q00
Q10
Q0
H
L
LBaidu Nhomakorabea
↑
X
a...h
a
b
h
H
H
L
↑
H
X
H
Q0n
Q6n
H
H
L
↑
L
X
L
Q0n
Q6n
H
X
H
↑
X
X
Q00
Q10
Q70
NOTES: H = High Voltage Level L = Low Voltage Level X = Don’t Care ↑ = Transition from Low to High Level a...h = The level of steady-state input at inputs D0 thru D7, respectively. Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established. Q0n, Q6n = The level of Q0 or Q6, respectively, before the most recent ↑ transition of the clock.
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC
元器件交易网www.cecb2b.com
Data sheet acquired from Harris Semiconductor SCHS157 February 1998
CD74HC166, CD74HCT166
High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register
Copyright © Harris Corporation 1998
1
File Number 1501.1
元器件交易网www.cecb2b.com Functional Diagram
CD74HC166, CD74HCT166
D0 D1 D2 D3 D4 D5 D6 D7
PE
PARALLEL ENABLE CIRCUIT
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Pinout
CD74HC166, CD74HCT166 (PDIP, SOIC) TOP VIEW
DS 1 D0 2 D1 3 D2 4 D3 5 CE 6 CP 7 GND 8
16 VCC 15 PE 14 D7 13 Q7 12 D6 11 D5 10 D4 9 MR
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC
Ordering Information
PART NUMBER
TEMP. RANGE (oC)
PACKAGE
PKG. NO.
CD74HC166E
-55 to 125
16 Ld PDIP E16.3
CD74HCT166E
-55 to 125
16 Ld PDIP E16.3
CD74HC166M
-55 to 125
[ /Title (CD74 HC166 , CD74 HCT16 6) /Subject (High Speed CMOS Logic 8-Bit ParallelIn/Seri
Features
• Buffered Inputs • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range)
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER HC TYPES High Level Input Voltage
SYMBOL
TEST CONDITIONS
25oC
VI (V) IO (mA) VCC (V) MIN TYP MAX
VIH
-
-
VIL
-
-
VOH VOL
II
VIH or VIL
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
2. Wafer and die is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.
16 Ld SOIC M16.15
CD74HCT166M
-55 to 125
16 Ld SOIC M16.15
CD54HC166W
-55 to 125
Wafer
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
2
元器件交易网www.cecb2b.com
CD74HC166, CD74HCT166
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK
160
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Thermal Information
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .