FPGA可编程逻辑器件芯片EP3C40F324I7N中文规格书

Configuration & Testing 1An encryption configuration file is the same size as a non-encryption configuration file. When using a serial configuration
scheme such as passive serial (PS) or active serial (AS),
configuration time is the same whether or not the design
security feature is enabled. If the fast passive parallel (FPP)
scheme us used with the design security or decompression
feature, a 4× DCLK is required. This results in a slower
configuration time when compared to the configuration time of
an FPGA that has neither the design security, nor
decompression feature enabled. For more information about
this feature, refer to AN 341: Using the Design Security Feature in
Stratix II Devices. Contact your local Altera sales representative
to request this document.
Device Configuration Data Decompression
Stratix II FPGAs support decompression of configuration data, which saves configuration memory space and time. This feature allows you to store compressed configuration data in configuration devices or other memory, and transmit this compressed bit stream to Stratix II FPGAs. During configuration, the Stratix II FPGA decompresses the bit stream in real time and programs its SRAM cells.
Stratix II FPGAs support decompression in the FPP (when using a MAX II device/microprocessor and flash memory), AS and PS configuration schemes. Decompression is not supported in the PPA configuration scheme nor in JTAG-based configuration.
Remote System Upgrades
Shortened design cycles, evolving standards, and system deployments in remote locations are difficult challenges faced by modern system designers. Stratix II devices can help effectively deal with these challenges with their inherent re-programmability and dedicated circuitry to perform remote system updates. Remote system updates help deliver feature enhancements and bug fixes without costly recalls, reduce time to market, and extend product life.
Stratix II FPGAs feature dedicated remote system upgrade circuitry to facilitate remote system updates. Soft logic (Nios® processor or user logic) implemented in the Stratix II device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides
Stratix II Device Handbook, Volume 1
5.DC & Switching
Characteristics
Operating Conditions Stratix®II devices are offered in both commercial and industrial grades. Industrial devices are offered in -4 speed grades and commercial devices are offered in -3 (fastest), -4, -5 speed grades.
Tables5–1 through 5–32 provide information about absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for Stratix II devices.
Absolute Maximum Ratings
Table5–1 contains the absolute maximum ratings for the Stratix II device family.
Table5–1.Stratix II Device Absolute Maximum Ratings Notes(1), (2),(3)
Symbol Parameter Conditions Minimum Maximum Unit V CCINT Supply voltage With respect to ground–0.5 1.8V
V CCIO Supply voltage With respect to ground–0.5 4.6V
V CCPD Supply voltage With respect to ground–0.5 4.6V
V CCA Analog power supply for
PLLs
With respect to ground–0.5 1.8V
V CCD Digital power supply for PLLs With respect to ground–0.5 1.8V
V I DC input voltage (4)–0.5 4.6V
I OUT DC output current, per pin–2540mA
T STG Storage temperature No bias–65150°C
T J Junction temperature BGA packages under bias–55125°C Notes to Tables5–1
(1)See the Operating Requirements for Altera Devices Data Sheet.
(2)Conditions beyond those listed in Table5–1 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
(3)Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
(4)During transitions, the inputs may overshoot to the voltage shown in Table5–2 based upon the input duty cycle.
The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100mA and periods shorter than 20ns.
Timing Model
Table5–42.M-RAM Block Internal Timing Microparameters(Part 1 of2)Note(1)
Symbol Parameter
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Unit Min
(4)
Max
Min
(4)
Max
Min
(5)
Max
Min
(4)
Max
t M E G A R C Synchronous read cycle
time 1,8662,774 1,8662,9111,777
1,866
3,189 1,777
1,866
3,716 ps
t M E G AW E R E S U Write or read enable
setup time before clock 144 151 165
165
192ps
t M E G AW E R E H Write or read enable
hold time after clock 39 40 44
44
52ps
t M E G A B E S U Byte enable setup time
before clock 50 52 57
57
67ps
t M E G A B E H Byte enable hold time
after clock 39 40 44
44
52ps
t M E G A DATA A S U A port data setup time
before clock 50 52 57
57
67ps
t M E G A DATA A H A port data hold time
after clock 243 255 279
279
325ps
t M E G A A D D R A S U A port address setup
time before clock 589 618 677
677
789ps
t M E G A A D D R A H A port address hold time
after clock 241 253 277
277
322ps
t M E G A DATA B S U B port setup time before
clock 50 52 57
57
67ps
t M E G A DATA B H B port hold time after
clock 243 255 279
279
325ps
t M E G A A D D R B S U B port address setup
time before clock 589 618 677
677
789ps
t M E G A A D D R B H B port address hold time
after clock 241 253 277
277
322ps
t M E G A DATAC O1Clock-to-output delay
when using output
registers 480715 480749457
480
821 480957ps
t M E G A DATAC O2Clock-to-output delay
without output registers 1,9502,899 1,9503,0421,857
1,950
3,332 1,9503,884 ps
t M E G AC L K L Minimum clock low time1,2501,3121,437
1,437
1,675ps
Stratix II Device Handbook, Volume 1
Document Revision History
Altera Corporation Stratix II Device Handbook, Volume 1July 2009
Clock Management
Stratix II Device Handbook, Volume 2
Section I–2。