FPGA可编程逻辑器件芯片5SGSED8N1F45C2L中文规格书

System Overview
The processor core has three ports and can generate up to the following simultaneous off-core accesses per core clock cycle (CCLK):
•One DMA data transfer through the D port
•One L2 or external memory access through the P port
•One MMR register access through the MMR port
The L2 or external memory access through the P port includes normal data or instruction access and cache read or write operation. System Overview
The ADSP-BF54x processor processor system includes a Blackfin proces-sor core, a 128K byte level 2 (L2) memory, the peripheral set (see
Figure2-1 on page2-3), the external memory controller (EBIU, AMC and DDR), the DMA controllers, and bus interfaces.
The external bus interface unit (EBIU) is the primary interface to the chip pins. Detailed information about the EBIU is discussed in “External Bus Interface Unit” on page5-1.
P Port Interface
Figure2-3 shows the interface between the processor core P port and
memory other than L1 through the 64-bit core L2 bus and shows the
interface between processor core P port and the EBIU through the 32-bit EAB bus.
ADSP-BF54x Blackfin Processor Hardware Reference
NFC Programming Examples
P1 = (2048/256)(z);
R3.L = lo(_Buffer);
R3.H = hi(_Buffer);
R4 = (2048/4)(z);
R5 = 0x4(x);
[P4 + (DMA22_START_ADDR - DMA22_CONFIG)] = R3;
w[P4 + lo(DMA22_X_COUNT - DMA22_CONFIG)] = R4;
w[P4 + lo(DMA22_X_MODIFY - DMA22_CONFIG)] = R5;
R7 = 0x89(z);
w[P4] = R7;
LSETUP(_write_data_begin, _write_data_end) LC0 = P1;
_write_data_begin:
P1 = (256/4)(z);
/* Reset the NFC */
R7 = ECC_RST(z);
w[P5 + lo(NFC_RST - NFC_CTL)] = R7;
ssync;
_wait_for_nfc_reset_completion:
R7 = w[P5 + lo(NFC_RST - NFC_CTL)](z);
CC = bittst(R7, bitpos(ECC_RST));
_wait_for_nfc_reset_completion.END:
if CC jump _wait_for_nfc_reset_completion;
R7 = PG_WR_START(x);
w[P5 + lo(NFC_PGCTL - NFC_CTL)] = R7;
ADSP-BF54x Blackfin Processor Hardware Reference。