FPGA可编程逻辑器件芯片5CSXFC5C6U23C7N中文规格书

Symbol
Description
Condition (V)
Resistance Tolerance
–C6
–I7, –C7
–C8, –A7
25-Ω RS
Internal series termination without calibration (25-Ω setting)
VCCIO = 3.0, 2.5
Symbol/Description
Condition
Transceiver Speed Grade 5(30)
Transceiver Speed Grade 6
Min
Typ
Max
Min
Typ
Max
fixedclk clock frequency PCIe Receiver Detect
—
125
—
—
VCCIO = 2.5
±25
±40
±40
Figure 2. Equation for OCT Variation Without Recalibration
Unit
% % % % % % %
The definitions for the equation are as follows: • The ROCT value calculated shows the range of OCT resistance with the variation of temperature and VCCIO. • RSCAL is the OCT resistance value at power-up. • ΔT is the variation of temperature with respect to the temperature at power up.
7)
Unit
MHz MHz
Table 23. Receiver Specifications for Cyclone V GX, GT, SX, and ST Devices
Symbol/Description
Condition
Transceiver Speed Grade 5(30)
Transceiver Speed Grade 6
找FPGA和CPLD可编程逻辑器件，上深圳宇航军工半导体有限公司
Table 10.
OCT Without Calibration Resistance Tolerance Specifications for Cyclone V Devices
This table lists the Cyclone V OCT without calibration resistance tolerance to PVT changes.
Min
Typ
Max
Min
Typ
Max
Supported I/O standards
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Data rate(38)
—
614
—
5000/614
614
—
3125
4(35)
Absolute VMAX for a receiver
—
pin(39)
1.6
Maximum peak-to-peak
—
differential input voltage
VID (diff p-p) after device configuration
—
—
2.2
—
—
2.2
Transceiver Speed Grade 7
Min
Typ
Max
Unit
614 — –0.4 —
(38) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
(39) The device cannot tolerate prolonged operation at this absolute maximum.
—
—
1.2
—
—
1.2
Absolute VMIN for a receiver
—
pin
–0.4
—
—
–0.4
—
—
Maximum peak-to-peak
—
differential input voltage
VID (diff p-p) before device configuration
—
—
1.6
—
—
125
—
Transceiver Reconfiguration
—
Controller IP
(mgmt_clk_clk) clock
frequency
75
—
100/125(3
75
—
100/125(
7)
37)
Transceiver Speed Grade 7
Min
Typ
Max
—
125
—
75
—
100/125(3
Send Feedback
Cyclone V Device Datasheet CV-51002 | 2019.11.27
Send Feedback
Cyclone V Device Datasheet CV-51002 | 2019.11.27
Send Feedback
Symbol/Description VICM (AC coupled) VICM (DC coupled) Transmitter REFCLK phase noise(36)
—
2500
Mbps
—
1.2
V
—
—
V
—
1.6
V
—
—
2.2
V
continued...
(37) The maximum supported clock frequency is 100 MHz if the PCIe hard IP block is enabled or 125 MHz if the PCIe hard IP block is not enabled.
2000
—
±1%
Cyclone V Device Datasheet CV-51002 | 2019.11.27
Transceiver Speed Grade 7
Min
Typ
Max
VCCE_GXBL supply
250
—
550
Unit
V mV
—
—
–50
dBc/Hz
—
—
–80
dBc/Hz
—
—
–110
dBc/Hz
VC
±50
50-Ω RS
Internal series termination without calibration (50-Ω setting)
VCCIO = 3.0, 2.5
±30
±40
±40
50-Ω RS
Internal series termination without calibration (50-Ω setting)
VCCIO = 1.8, 1.5
±30
±40
±40
50-Ω RS
Internal series termination without calibration (50-Ω setting)
VCCIO = 1.2
±35
±50
±50
100-Ω RD
Internal differential termination (100-Ω setting)
Send Feedback
±30
±40
±40
25-Ω RS
Internal series termination without calibration (25-Ω setting)
VCCIO = 1.8, 1.5
±30
±40
±40
25-Ω RS
Internal series termination without calibration (25-Ω setting)
—
—
–120
dBc/Hz
—
—
–120
dBc/Hz
—
—
–130
dBc/Hz
—
2000
—
Ω
±1%
Send Feedback
Cyclone V Device Datasheet CV-51002 | 2019.11.27
Table 22. Transceiver Clocks Specifications for Cyclone V GX, GT, SX, and ST Devices
RREF
Condition
Transceiver Speed Grade 5(30)
Min
Typ
Max
—
HCSL I/O standard for the PCIe reference clock
VCCE_GXBL supply(34)(35)
250
—
550
10 Hz
—
—
–50
100 Hz
—
—
–80
1 KHz
—
—
–110
10 KHz
—
—
–120
100 KHz
—
—
–120
≥1 MHz
—
—
–130
—
—
2000
—
±1%
Transceiver Speed Grade 6
Min
Typ
Max
VCCE_GXBL supply
250
—
550
—
—
–50
—
—
–80
—
—
–110
—
—
–120
—
—
–120
—
—
–130
—