MEMORY存储芯片MT46H128M16LFB7-5中文规格书

36.The refresh period is 64ms when T C is less than or equal to 85°C. This equates to an aver-
age refresh rate of 7.8125μs. However, nine REFRESH commands should be asserted at least once every 70.3μs. When T C is greater than 85°C, but less the 95°C, the refresh peri-od is 32ms. When T C is greater than 95°C, but less the 105°C, the refresh period is 16ms.
37.Although CKE is allowed to be registered LOW after a REFRESH command when
t REFPDEN (MIN) is satisfied, there are cases where additional time such as t XPDLL (MIN)is required.
38.ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to
turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT reference load is shown in Figure 24 (page 63). This output load is used for ODT timings (see Figure 31 (page 75)).Designs that were created prior to JEDEC tightening the maxi-mum limit from 9ns to 8.5ns will be allowed to have a 9ns maximum.
39.Half-clock output parameters must be derated by the actual t ERR10per and t JITdty when
input clock jitter is present. This results in each parameter becoming larger. The parame-ters t ADC (MIN) and t AOF (MIN) are each required to be derated by subtracting both t ERR10per (MAX) and t JITdty (MAX). The parameters t ADC (MAX) and t AOF (MAX) are required to be derated by subtracting both t ERR10per (MAX) and t JITdty (MAX).
40.ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT
turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is shown in Figure 24 (page 63). This output load is used for ODT timings (see Figure 31(page 75)).
41.Pulse width of a input signal is defined as the width between the first crossing of
V REF(DC) and the consecutive crossing of V REF(DC).
42.Should the clock rate be larger than t RFC (MIN), an AUTO REFRESH command should
have at least one NOP command between it and another AUTO REFRESH command. Ad-ditionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should be followed by a PRECHARGE ALL command.
43.DRAM devices should be evenly addressed when being accessed. Disproportionate ac-
cesses to a particular row address may result in a reduction of REFRESH characteristics or product lifetime.
44.When two V IH(AC) values (and two corresponding V IL(AC) values) are listed for a specific
speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one V IH(AC) value may be used for address/command inputs and the other V IH(AC) value may be used for data inputs.
For example, for DDR3-800, two input AC levels are defined: V IH(AC175),min and
V IH(AC150),min (corresponding V IL(AC175),min and V IL(AC150),min ). For DDR3-800, the address/command inputs must use either V IH(AC175),min with t IS(AC175) of 200ps or V IH(AC150),min with t IS(AC150) of 350ps; independently, the data inputs must use either V IH(AC175),min with t DS(AC175) of 75ps or V IH(AC150),min with t DS(AC150) of 125ps.
4Gb: x4, x8, x16 DDR3L SDRAM Electrical Characteristics and AC Operating Conditions
DQS to DQ output timing is shown in Figure 79 (page 170). The DQ transitions between valid data outputs must be within t DQSQ of the crossing point of DQS, DQS#. DQS must also maintain a minimum HIGH and LOW time of t QSH and t QSL. Prior to the READ preamble, the DQ balls will either be floating or terminated, depending on the status of the ODT signal.
Figure 80 (page 171) shows the strobe-to-clock timing during a READ. The crossing point DQS, DQS# must transition within ±t DQSCK of the clock crossing point. The data out has no timing relationship to CK, only to DQS, as shown in Figure 80 (page 171). Figure 80 (page 171) also shows the READ preamble and postamble. Typically, both DQS and DQS# are High-Z to save power (V DDQ). Prior to data output from the DRAM, DQS is driven LOW and DQS# is HIGH for t RPRE. This is known as the READ preamble. The READ postamble, t RPST, is one half clock from the last DQS, DQS# transition. Dur-ing the READ postamble, DQS is driven LOW and DQS# is HIGH. When complete, the DQ is disabled or continues terminating, depending on the state of the ODT signal. Fig-ure 83 (page 173) demonstrates how to measure t RPST.
Asynchronous ODT Mode
Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when
either R TT,nom or R TT(WR) is enabled; however, the DLL is temporarily turned off in pre-
charged power-down standby (via MR0[12]). Additionally, ODT operates asynchronous-
ly when the DLL is synchronizing after being reset. See Power-Down Mode (page 187)
for definition and guidance over power-down details.
In asynchronous ODT timing mode, the internal ODT command is not delayed by AL
relative to the external ODT command. In asynchronous ODT mode, ODT controls R TT
by analog time. The timing parameters t AONPD and t AOFPD replace ODTLon/t AON
and ODTLoff/t AOF, respectively, when ODT operates asynchronously.
The minimum R TT turn-on time (t AONPD [MIN]) is the point at which the device termi-
nation circuit leaves High-Z and ODT resistance begins to turn on. Maximum R TT turn-
on time (t AONPD [MAX]) is the point at which ODT resistance is fully on. t AONPD
(MIN) and t AONPD (MAX) are measured from ODT being sampled HIGH.
The minimum R TT turn-off time (t AOFPD [MIN]) is the point at which the device termi-
nation circuit starts to turn off ODT resistance. Maximum R TT turn-off time (t AOFPD
[MAX]) is the point at which ODT has reached High-Z. t AOFPD (MIN) and t AOFPD
(MAX) are measured from ODT being sampled LOW.。