Xilinx FPGA XC5VLX30T 特殊资源分布示意图概要
嵌入式SATA存储系统的研究
的８ｂ，１０ｂ编码、逗号校准、信道绑定以及时钟校正模块。
以Ｖｉｒｔｅｘ一５ＬＸＴ系列的ＸＣ５ＶＬｘ３０Ｔ为例，它具有四个独立的ＧＴＰ模块，每个模块又分别包含了若干ＧＴＰ驱动电压与参考电压引脚，一对低压差分串行时钟引脚，以及两对ＲｏｃｋｅｔｌＯＴＭ低压差分串行引脚。
３．３．２ＳＡＴＡ接口信号定义ＳＡＴＡ接口数据线由７根信号线组成。
在主机端，ｌ至７号线依次为ＧＮＤ、Ｔｘ＋、Ｔｘ一、ＧＮＤ、Ｒｘ＋、Ｒｘ一和ＧＮＤ。
其中，Ｔｘ＋和Ｔｘ一组成低压差分发送信号对，分别与ＸＣ５ＶＬＸ３０Ｔ的ＭＧｌｌ［ｘＰ和ＭＧＴ．ＴＸＮ引脚相连；Ｒｘ＋和Ｒｘ一组成低压差分接收信号对，分别与ＸＣ５ＶＬｘ３０Ｔ的ＭＧＴＲＸＰ和ＭＧＴＲｘＮ引脚相连。
３．３．３ＳＡ．ｒＡ时钟电路及ＰＣＢ仿真［ｓ－ｓｌ由于ＳＡＴＡ的时钟频率和串行数据传输速率都很高，因此对信号的抗干扰能力的要求很高。
为提高系统可靠性。
需要对布线后的ＰＣＢ板上ＳＡＴＡ时钟信号和数据信号进行反复的仿真实验。
下面以ＳＡＴＡ时钟信号为例，进行ＰＣＢ布线后仿真实验。
ＳＡ’ｒＡ２．５最高支持３．ＯＧｂ，ｓ的传输速度，因此要求所选的晶振具有３００ＭＨｚ以上的低压差分时钟输出能力。
ＩＤＴ公司的ＩＣＳ８４４０７１和ＩＣＳ８４４０３１满足要求，前者的输出频率范围是６２．５ＭＨｚ一１７０ＭＨｚ，后者的输出频率范围是２４５ＭＨｚ一３４０ＭＨｚ。
两者在封装上完全兼容，用户可以根据设计的速度要求来选取。
图３是ＳＡＴＡ时钟接口电路图，其中ＳＡＴＡ—ＣＬＫ和ＳＡｌｒＡ—ＣＬＫ分别与ＸＣ５ＶＬＸ３０Ｔ的Ｇ１１Ｐ专用差分时钟输入引脚ＭＧＴＲＥＦＣＬＫＰ和ＭＧＴＲＥＦ－ＣＬＫＮ相连。
利用８４４０７１—３ｖ３．ｉｂｓ及ｖｉｒｔｅｘ５．ｉｂｓ两个ＩＢＩＳ模型，在Ｈｙｐｅｒｌｙｎｘ７．５环境下对ＳＡＴＡ差分时钟进行ＢｏａｒｄＳｉｍ差分眼图仿真。
图４是在线长１．２ｉｎ、线宽１０ｍｉｌ、差分线距１２ｒａｉｌ、串行连接０．０１斗Ｆ电容以及端接１００１１电阻等条件下，考虑各种过孔、ＰＣＢ板的整体分析等因素后的ＰＲＢＳ位模式仿真眼图。
FPGA可编程逻辑器件芯片XC5VLX330-2FFG1760I中文规格书
Table 1-2:DSP48E Port List and Definitions (Cont’d)Name Direction Bit Width DescriptionBCIN(1)In18Cascaded data input from BCOUT of previous DSP48E slice(muxed with B).PCIN(1)In48Cascaded data input from PCOUT of previous DSP48E slice toadder.CARRYCASCIN(1)In1Cascaded carry input from CARRYCASCOUT of previousDSP48E slice.MULTSIGNIN(1)In1Sign of the multiplied result from the previous DSP48E slice forMACC extension.ACOUT(1)Out30Cascaded data output to ACIN of next DSP48E slice.BCOUT(1)Out18Cascaded data output to BCIN of next DSP48E slice. CARRYCASCOUT(1)Out1Cascaded carry output to CARRYCASCIN of next DSP48E slice.This signal is internally fed back into the CARRYINSELmultiplexer input of the same DSP48E slice. MULTSIGNOUT(1)Out1Sign of the multiplied result cascaded to the next DSP48E slicefor MACC extension.P Out48Data output from second stage adder/subtracter or logicfunction.PATTERNBDETECT Out1Output indicating a match between P[47:0] and pattern bar. PATTERNDETECT Out1Output indicating a match between P[47:0] and pattern. OVERFLOW Out1Output indicating overflow when used with appropriatesetting of the pattern detector.UNDERFLOW Out1Output indicating underflow when used with appropriatesetting of the pattern detector.CARRYOUT Out44-bit CARRYOUT from each 12-bit section of logic unit/adder.Useful for SIMD.CARRYOUT[3] is the carryout of the 48-bit adder (invalidduring multiplies).PCOUT(1)Out48Cascaded data output to PCIN of next DSP48E slice.Notes:1.These signals are dedicated routing paths internal to the DSP48E column. They are not accessible via fabric routing resources.2.All signals are active High.Simplified DSP48E Slice OperationThe math portion of the DSP48E slice consists of a 25-bit by 18-bit, two's complementmultiplier followed by three 48-bit datapath multiplexers (with outputs X, Y, and Z). Thisis followed by a three-input adder/subtracter or two-input logic unit (see Figure1-5).When using two-input logic unit, the multiplier cannot be used.The data and control inputs to the DSP48E slice feed the arithmetic and logic stages. The Aand B data inputs can optionally be registered one or two times to assist the construction ofPipeline RegistersNotesAREG, BREG ACASCREG,BCASCREG(Refer to Figure1-7)Current DSP To Cascade DSP00Direct and cascade paths have no registers.11Direct and cascade paths have one register.21, 2When direct path has two registers, cascade path canhave one or two registers.X, Y, and Z MultiplexerThe OPMODE (Operating Mode) control input contains fields for X, Y, and Z multiplexerselects.The OPMODE input provides a way for the user to dynamically change DSP48Efunctionality from clock cycle to clock cycle (e.g., when altering the internal datapathconfiguration of the DSP48E slice relative to a given calculation sequence).The OPMODE bits can be optionally registered using the OPMODEREG attribute (asnoted in Table1-3).Table1-6, Table1-7, and Table1-8 list the possible values of OPMODE and the resultingfunction at the outputs of the three multiplexers (X, Y, and Z multiplexers). Themultiplexer outputs supply three operands to the following adder/subtracter. Not allpossible combinations for the multiplexer select bits are allowed. Some are marked in thetables as “illegal selection” and give undefined results. If the multiplier output is selected,then both the X and Y multiplexers are used to supply the multiplier partial products to theadder/subtracter.If AREG/BREG = 0 and USE_MULT = MULT_S (this requires MREG=1), the A:B pathshould not be selected via the opmode multiplexer. Since the opmode can be dynamic,switching between the registered multiplier with MREG=1 and the combinatorial A:B pathis not supported. If the multiplier is not being used, USE_MULT should be set to NONE. Table 1-6:OPMODE Control Bits Select X Multiplexer OutputsZ OPMODE [6:4]YOPMODE [3:2]XOPMODE [1:0]XMultiplexerOutputNotesxxx xx000Defaultxxx0101M Must select withOPMODE[3:2]=01 xxx xx10Pxxx xx11A:B 48 bits wide Table 1-7:OPMODE Control Bits Select Y Multiplexer OutputsZ OPMODE[6:4]YOPMODE[3:2]XOPMODE[1:0]YMultiplexerOutputNotesxxx00xx0Defaultxxx0101M Must select withOPMODE[1:0]=01xxx10xx48'ffffffffffff Used mainly for logicunit bitwise operations onX and Z multiplexersxxx11xx CChapter 1:DSP48E Description and SpecificsZ OPMODE[6:4]YOPMODE[3:2]XOPMODE[1:0]ZMultiplexerOutputNotes000xx xx0Default001xx xx PCIN010xx xx P011xx xx C1001000P Use for MACC extendonly101xx xx17-bitShift(PCIN)110xx xx17-bitShift(P)111xx xx xx Illegal selectionSimplified DSP48E Slice OperationAdder/Subtracter or Logic UnitThe adder/subtracter or logic unit output is a function of control and data inputs (see Figure1-15). The data inputs to the adder/subtracter are selected by the OPMODE and the CarryInSel signals. The ALUMODE signals choose the function implemented in theadder/subtracter. Thus, the OPMODE, ALUMODE, and CARRYINSEL signals together determine the functionality of the embedded adder/subtracter/logic unit. When using the logic unit, the multiplier must not be used. The values of OPMODEREG andCARRYINSELREG must be identical.As with the input multiplexers, the OPMODE bits specify a portion of this function. The symbol ± in the table means either add or subtract and is specified by the state of theALUMODE control signal (ALUMODE = 0011 is defined as “subtraction,” used forretargeting designs from Virtex-4 devices). The symbol “:” in the table meansconcatenation. The outputs of the X and Y multiplexer and CIN are always added together.Refer to “ALUMODE Inputs,” page 32.。
FPGA可编程逻辑器件芯片XC5VFX200T-2FFG1738C中文规格书
- 具有零延迟缓冲、频率综合和时钟相移功能的数字时钟管理模 块 (DCM)
- 具备输入抖动滤波、零延迟缓冲、频率综合以及相位匹配时钟 分频功能的 PLL 模块
• 36Kb Block RAM/FIFO
- 真双端口 RAM 模块 - 增强的可选可编程 FIFO 逻辑 - 可编程 - 高达 36 位宽度的真正双端口 - 高达 72 位宽度的简单双端口 - 内置可选纠错电路 - 可选择将每个块配置作为两个独立的18Kb 块
• 将 SSO 感应噪声降低 1/7 • 无铅封装和标准封装
• 片上温度测量（±4℃） • 片上电源测量（±1%） • 简便易用，独立运行
• 65 nm 铜 CMOS 工艺技术 • 1.0V 内核电压 • 可选择标准或无铅的具有高度信号完整性的倒装片封装
DS100 (v5.0) 2009 年 2 月 6 日 产品规范
Virtex-5 系列概述
表 1:Virtex-5 FPGA 系列成员
器件
可配置逻辑模块 (CLB)
Block RAM
3
6 不适用 20 24 840
4
8 不适用 24 27 960
注：
1. Virtex-5 FPGA Slice 的结构与前几代不同。每个 Virtex-5 FPGA Slice 均包含 4 个 LUT 和 4 个触发器（之前为 2 个 LUT 和 2 个触发器。） 2. 每个 DSP48E Slice 内含一个 25x18 乘法器、一个加法器及一个累加器。 3. Block RAM 大小基本为 36 Kb。每个模块还可以作为两个独立的 18 Kb 模块使用。 4. 每个时钟管理模块 (CMT) 内含 2 个 DCM 和一个 PLL。 5. 本表列出了各个器件的以太网 MAC 个数。 6. RocketIO GTP 收发器的运行速率为：100Mb/s 到 3.75Gb/s。RocketIO GTX 收发器的运行速率为：150Mb/s 到 6.5Gb/s。 7. 该数字不包括 RocketIO 收发器。 8. 包含配置 Bank 0。
FPGA可编程逻辑器件芯片XC5VLX30-1FFG324I中文规格书
XTP481 (v3.3) November 18, 2019 FAQ: Implications of XCN18002 SummaryThe purpose of this notification is to communicate FAQs related to substrate material change for Virtex®, Virtex®-II, Virtex®-II Pro, Virtex®-4 and Virtex®-5 FPGA packages.The manufacturer of the current substrate material is discontinuing production of the substrate material. Therefore, Xilinx qualified new substrate material set to continue supply and shipment of Virtex, Virtex-II, Virtex II-Pro, Virtex-4 and Virtex-5 FPGA packages. This enables Xilinx to better support long-term customer demand. There is no change in the fit, form or function with this change. The new substrate core and build up material have been qualified and shipping in many 7 series, ROHS Lead Free and UltraScale™ packages.Xilinx will revise the corresponding material declaration data sheet (MDDS) to reflect the new material change . FAQsQ: What is the change?Substrate material will change.Q: Why is Xilinx making this change?The manufacturer of the current substrate material is discontinuing production of the substrate material. Therefore, Xilinx qualified new substrate material set to continue supply and shipment of Virtex, Virtex-II, Virtex II-Pro, Virtex-4 and Virtex-5 FPGA packages as mentioned in XCN18002. This enables Xilinx to better support long-term customer demand.Q: When will this change take effect?Xilinx will start shipping commercial / industrial “XC” devices 90 days after the PCN release. Estimated cut-over dates for Defense-grade “XQ” devices are listed below. No delay or exceptions will be allowed once the PCN is released.Q: Can customer continue with current core/build up material?No. Substrate material supplier is ending production of current material. There will be no material to continue with current BOM.Q:Is there any change in shelf life?No change.Q: Is there any change in package dimension?No change.FAQ: Substrate Material Change for Virtex, Virtex-II, Virtex-II Pro, Virtex-4 & Virtex-5 FBGA PackagesFAQ: Substrate Material Change for Virtex, Virtex-II, Virtex-II Pro, Virtex-4 & Virtex-5 FBGA Packages Table 1: Virtex-II Pro Devices-PackagesDevice Package-PinEstimatedcrossshippingDevice Package-PinEstimatedcrossshippingXC2VP2 FF(G)672 May 2020 XC2VP50 FF(G)1517 Jul 2018 XC2VP4 FF(G)672 May 2020 XC2VP70 FF(G)1517 Oct 2019 XC2VP7 FF(G)672 Jan 2019 XC2VP100 FF(G)1696 Jul 2018 XC2VP20 FF(G)896 May 2020 XC2VP100 FF(G)1704 Mar 2019 XC2VP30 FF(G)896 Jun 2019 XC2VP70 FF(G)1704 Jun 2019 XC2VP7 FF(G)896 Dec 2019Table 3: Virtex-5 Devices-PackagesDevice Package-PinEstimatedcrossshippingDevice Package-PinEstimatedcrossshippingXC5VTX150T FF(G)1156 Jul 2018 XC5VFX100T FF1738 May 2020 XC5VFX130T FF(G)1738 Jul 2019 XC5VLX110T FF1738 May 2020 XC5VFX200T FF(G)1738 Jan 2019 XC5VLX155T FF1738 Jun 2019 XC5VLX220T FF(G)1738 Nov 2018 XC5VLX110 FF1760 Nov 2019 XC5VLX330T FF(G)1738 Dec 2018 XC5VLX155 FF1760 Jul 2018 XC5VSX240T FF(G)1738 Jun 2019 XC5VLX20T FF323 Jul 2019 XC5VTX150T FF(G)1759 Feb 2019 XC5VLX30T FF323 Feb 2019 XC5VTX240T FF(G)1759 Feb 2019 XC5VLX30 FF324 Jan 2019 XC5VFX100T FF1136 May 2020 XC5VLX50 FF324 Mar 2019 XC5VFX70T FF1136 May 2020 XC5VFX30T FF665 Oct 2019 XC5VLX110T FF1136 Dec 2019 XC5VFX70T FF665 May 2020 XC5VLX155T FF1136 May 2020 XC5VLX30T FF665 Dec 2019 XC5VLX50T FF1136 May 2020 XC5VLX50T FF665 Dec 2019 XC5VLX85T FF1136 Sep 2019 XC5VSX35T FF665 May 2020 XC5VSX50T FF1136 May 2020 XC5VSX50T FF665 Jan 2019 XC5VSX95T FF1136 Apr 2019 XC5VLX110 FF676 Mar 2020 XC5VLX110 FF1153 Jan 2020 XC5VLX30 FF676 Jan 2019 XC5VLX155 FF1153 Feb 2019 XC5VLX50 FF676 Aug 2018 XC5VLX50 FF1153 Aug 2019 XC5VLX85 FF676 Nov 2018 XC5VLX85 FF1153 Feb 2019 XC5VLX220 FF(G)1760 Nov 2019XC5VLX330 FF(G)1760 Nov 2018 Table 4: Virtex-4 EasyPath Devices-PackagesDevice Package-PinEstimatedcrossshippingXCE04L6 FF1148 Nov 2018 XCE04S2 FFG668 Apr 2019 XCE04L10 FF(G)1513 May 2020 XCE04L4 FF(G)1148 Oct 2018 XCE04L8 FFG1148 Oct 2018 XCE04F10 FF(G)1152 Feb 2019Table 8: Virtex-4Q Defense-grade Devices-PackagesDevice Package-PinEstimatedcut-overdate codeDevice Package-PinEstimatedcut-overdate codeXQ4VLX60 EF668 1837 XQL4VFX100 FF1152 1837 XQ4VLX25 FF668 1918 XQL4VFX60 FF1152 2017 XQ4VLX40 FF668 1837 XQ4VFX100 FF(G)1152 2030 XQ4VLX60 FF668 1837 XQ4VFX60 FF(G)1152 1841 XQL4VLX60 FF668 1837 XQL4VLX200 FF(G)1513 1901 XQ4VSX35 FF(G)668 2019 XQ4VFX140 FF1517 2020 XQ4VFX60 EF672 1837 XQL4VFX140 FF(G)1517 1901 XQL4VFX40 FF672 1901 XQ4VLX25 SF363 1837 XQL4VFX60 FF672 1837。
XilinxFPGA介绍
目前FPGA芯片仍是基于查找表技术的，但其概念和性能已经远远超出查找表技术的限制，并且整合了常用功能的硬核模块（如块RAM、时钟管理和DSP）。
图1-1所示为Xilinx公司FPGA的内部结构示意图（由于不同系列的应用场合不同，所以内部结构会有一定的调整），从中可以看出FPGA芯片主要由 6部分组成：可编程输入输出单元、基本可编程逻辑单元、完整的时钟管理、嵌入块式RAM、丰富的布线资源、内嵌的底层功能单元和内嵌专用硬件模块。
图1-1 FPGA芯片的内部结构每个模块的功能如下：1．可编程输入输出单元（IOB）可编程输入/输出单元简称I/O单元，是芯片与外界电路的接口部分，完成不同电气特性下对输入/输出信号的驱动与匹配要求，提供输入缓冲、输出驱动、接口电平转换、阻抗匹配以及延迟控制等功能，其一般示意结构如图1-2所示。
FPGA内的I/O按组分类，每组都能够独立地支持不同的I/O标准。
通过软件的灵活配置，可适配不同的电气标准与I/O物理特性，可以调整驱动电流的大小，可以改变上、下拉电阻。
目前，I/O口的频率也越来越高，一些高端的FPGA 通过DDR寄存器技术可以支持高达2Gbps的数据速率。
外部输入信号可以通过IOB模块的存储单元输入到FPGA的内部，也可以直接输入FPGA 内部。
当外部输入信号经过IOB模块的存储单元输入到FPGA内部时，其保持时间（Hold Time）的要求可以降低，通常默认为0。
为了便于管理和适应多种电器标准，FPGA的IOB被划分为若干个组（bank），每个bank的接口标准由其接口电压VCCO决定，一个bank只能有一种VCCO，但不同bank的VCCO可以不同。
只有相同电气标准的端口才能连接在一起，VCCO 电压相同是接口标准的基本条件。
2．可配置逻辑块（CLB）CLB是FPGA内的基本逻辑单元。
CLB的实际数量和特性会依器件的不同而不同，但是每个CLB都包含一个可配置开关矩阵，此矩阵由4或6个输入、一些选型电路（多路复用器等）和触发器组成。
FPGA可编程逻辑器件芯片XC5VFX200T-1FFG1738C中文规格书
《Virtex-5 FPGA XtremeDSP 设计注意事项》中进一步讨论了 Virtex-5 FPGA DSP48E Slice 的功能。
布线资源
Virtex-5 器件中的所有部件都使用相同的互连方案以及相同的全局布
FPGA 是高可用性/可靠性基础架构的重要构建模块。因此，有必要 更好地监测 FPGA 的片上物理环境及其在系统内紧邻的周边环境。 Virtex-5 系列系统监控器首次为 FPGA 及其外部环境提供了更简单 的监控。Virtex-5 系列的每个成员都包含一个系统监控器模块。系 统监控器是围绕一个 10 位 200kSPS ADC（模数转换器）构建的。
DS100 (v5.0) 2009 年 2 月 6 日 产品规范
Virtex-5 系列概述
全局时钟
配置
CMT 和全局时钟多路复用缓冲器为设计高速时钟网络提供了完善的 Virtex-5 器件的配置方法是用下列模式之一将比特流载入内部配置
解决方案。
存储器：
每个 CMT 包含 2 个 DCM 和一个 PLL。DCM 和 PLL 可独立使用， 也可广泛级联。最多可使用 6 个 CMT 模块，总共可提供 18 个时钟 发生器元件。
为增强 DCM 的功能，Virtex-5 FPGA CMT 还包含一个 PLL。该模 块提供参考时钟抖动滤波和更多频率综合选项。
Virtex-5 器件具有 32 个全局时钟 MUX 缓冲器。时钟树设计为差分 式。差分时钟可帮助减少抖动和占空比失真。
DSP48E Slice
DSP48E Slice 资源包含一个 25x18 补码乘法器和一个 48 位加法器 /减法器/累加器。每个 DSP48E Slice 还含有广泛的级联功能，可 有效实现高速 DSP 算法。
Virtex-5 FPGA 六输入 LUT 架构的优势
白皮书： Virtex-5 FPGAVirtex-5 FPGA 六输入 LUT 架构的优势作者： Andrew Percey新型 Virtex™-5 架构基于具有双 LUT 功能的真正六输入 LUT，与同类架构相比，在资源占用率方面具有显著优势。
本白皮书详述这些优势，重点在 Xilinx 的65nm 高端 FPGA 器件 (Virtex-5FPGA) 与 Altera(Stratix III FPGA) 之间进行比较。
© 2007 Xilinx, Inc. All rights reserved.XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.架构介绍图1 所示为 Xilinx Virtex-5 FPGA 的基本架构：具有相关逻辑的六输入 LUT。
图2 所示为 Altera Stratix III FPGA 的基本架构：自适应逻辑模块（即 ALM）。
图 1：Virtex-5 FPGA 六输入 LUT 架构图 2：Stratix III ALM 架构Xilinx 六输入 LUT 是共有 64位逻辑编程空间和六个独立输入的查找表，能够实现任意六输入功能和一两个较小功能的多种组合。
该六输入 LUT 还包括相关的进位逻辑、MUX 和触发器。
该六输入 LUT 的某些逻辑部分也可用作 64位 RAM 或 32位移位寄存器。
有关更多信息，请见 UG190：《Virtex-5 用户指南》。
Altera ALM 包括两个自适应 LUT (ALUT)，共有 64位逻辑编程空间和八个共用输入，也能实现任意六输入功能和一两个较小功能的多种组合。
FPGA可编程逻辑器件芯片XC5VLX330T-1FFG1738I中文规格书
Pin Cross-Reference for PCB Prototyping with a Commercial PartTo minimize costs during development, the commercial XC5VFX130T Virtex®-5FPGA canbe substituted in place of the XQR5VFX130 Virtex-5QV FPGA, provided the differences in pinassignments are considered in the layout. Table8-1 shows the pin assignments for bothdevices, and provides a super-set footprint that permits either device to be placed on tothis footprint.The keep-out space defined in Figure5-2 must be observed when using the super-setfootprint defined in Table8-1 to accommodate either the commercial XC5VFX130TVirtex-5FPGA or the XQR5VFX130 Virtex-5QV FPGA. All FPGA pins having no connection(listed as UNPOPULATED, UNUSED, or NC in Table8-1) must be connected to GND forspace flight compatibility.•UNPOPULATED pins are defined as pins with no CGA column present at thatspecific pin location.•UNUSED pins are defined as pins with no connection between the package columnsand the die.•NC pins are either UNUSED, or can be treated as UNUSED due to functionality thatmakes them unnecessary to connect.R_FUSE_0 and VFS_0 must also be connected to GND.Table 8-1:Pin Cross-Reference, Virtex-5QV FPGA to Virtex-5 FPGASuper-Set Footprint (FP1760)Virtex-5 FPGA XC5VFX130T (FF1738)Virtex-5QV FPGA XQR5VFX130 (CF/CN1752)Note Pin Bank Name Pin Name Pin NameA2NA GND A2MGTRXP1_124A2UNPOPULATEDA3NA GND A3MGTRXN1_124A3MGTRXN1_124NC A4NA MGTRXN0_124A4MGTRXN0_124A4MGTRXN0_124A5NA MGTRXP0_124A5MGTRXP0_124A5MGTRXP0_124A6NA GND A6UNPOPULATED A6GNDA7NA GND A7UNPOPULATED A7GNDA8NA MGTRXP1_128A8MGTRXP1_128A8MGTRXP1_128A9NA MGTRXN1_128A9MGTRXN1_128A9MGTRXN1_128A10NA MGTRXN0_128A10MGTRXN0_128A10MGTRXN0_128A11NA MGTRXP0_128A11MGTRXP0_128A11MGTRXP0_128A12NA GND A12UNPOPULATED A12GNDChapter 8:Pin Cross-Reference for PCB Prototyping with a Commercial PartTable 8-1:Pin Cross-Reference, Virtex-5QV FPGA to Virtex-5 FPGA (Continued)Super-Set Footprint (FP1760)Virtex-5 FPGA XC5VFX130T (FF1738)Virtex-5QV FPGA XQR5VFX130 (CF/CN1752)Note Pin Bank Name Pin Name Pin NameAG618IO_L13P_18AG6IO_L13P_18AG6IO_L13P_18AG718IO_L13N_18AG7IO_L13N_18AG7IO_L13N_18AG826IO_L9P_CC_26AG8IO_L9P_CC_26AG8IO_L9P_CC_26AG926IO_L3P_26AG9IO_L3P_26AG9IO_L3P_26AG1018VCCO_18AG10VCCO_18AG10VCCO_18AG1126IO_L1N_26AG11IO_L1N_26AG11IO_L1N_26AG1226IO_L1P_26AG12IO_L1P_26AG12IO_L1P_26AG13NA GND AG13GND AG13GNDAG14NA VCCINT AG14VCCINT AG14VCCINTAG15NA GND AG15GND AG15GNDAG16NA VCCINT AG16VCCINT AG16VCCINTAG17NA GND AG17GND AG17GNDAG18NA VCCINT AG18VCCINT AG18VCCINTAG19NA GND AG19GND AG19GNDAG20NA VCCINT AG20VCCINT AG20VCCINTAG21NA GND AG21GND AG21GNDAG22NA VCCINT AG22VCCINT AG22VCCINTAG23NA GND AG23GND AG23GNDAG24NA VCCINT AG24VCCINT AG24VCCINTAG25NA GND AG25GND AG25GNDAG26NA VCCINT AG26VCCINT AG26VCCINTAG27NA GND AG27GND AG27GNDAG28NA VCCINT AG28VCCINT AG28VCCINTAG290TCK_0 AG29TCK_0AG29TCK_0AG300VCCO_0 AG30VCCO_0AG30VCCO_0AG3125IO_L0P_25AG31IO_L0P_25AG31IO_L0P_25AG3225IO_L2N_25AG32IO_L2N_25AG32IO_L2N_25AG3325IO_L1N_25AG33IO_L1N_25AG33IO_L1N_25AG3421IO_L10N_CC_21AG34IO_L10N_CC_21AG34IO_L10N_CC_21AG35NA GND AG35GND AG35GNDAG3621IO_L11N_CC_21AG36IO_L11N_CC_21AG36IO_L11N_CC_21AG3717IO_L7P_17AG37IO_L7P_17AG37IO_L7P_17AG3817IO_L6N_17AG38IO_L6N_17AG38IO_L6N_17AG3917IO_L12P_VRN_17AG39IO_L12P_VRN_17AG39IO_L12P_VRN_17AG4017VCCO_17AG40VCCO_17AG40VCCO_17。
FPGA可编程逻辑器件芯片XQ5VFX130T-1F1138I中文规格书
封装பைடு நூலகம்
FF323 FF324 FFG323 FFG324
FF676 FF1153 FF1760 FF665 FF1136 FF1156 FFG676 FFG1153 FFG1760 FFG665 FFG1136 FFG1156
FF1738 FF1759 FFG1738 FFG1759
尺寸(毫米) 19x19 19x19
- Virtex-5 FXT：主要用于具备高级串行连接功能的高性能嵌 入式系统
• 跨平台兼容性
- LXT、SXT 及 FXT 器件使用可调稳压器，可以在相同封装 内实现引脚兼容
• 最先进的最佳利用率高性能 FPGA 结构
- 真正的 6 输入查找表 (LUT) 技术 - 双 5- LUT 选项 - 改进的布线减少了中间连线 - 64 位分布式 RAM 选项 - SRL32／双 SRL16 选项
Virtex-5 系列概述
Virtex-5 LXT、SXT、TXT 和 FXT 平台特性
本部分简述仅在 LXT、SXT、TXT 和 FXT 器件中使用的模块。
三态 (10/100/1000 Mb/s) 以太网 MAC
PCI Express 集成端点模块
Virtex-5 LXT、SXT、TXT 和 FXT 器件最多包含 8 个嵌入式以太网 Virtex-5 LXT、SXT、TXT 和 FXT 器件最多包含 4 个集成端点模
MAC，每个以太网 MAC 模块有 2 个。这些模块具有以下特点： 块。这些模块实现事务层、数据链路层和物理层功能，在尽量少用
• 符合 IEEE 802.3-2002 规范 • 经过 UNH 一致性测试 • 使用 RocketIO 技术的 GRMII/GMII 接口，或者当与 SelectIO 收
FPGA可编程逻辑器件芯片XC5VLX30T-2FFG665C中文规格书
• Advanced DSP48E slices − 25 x 18, two’s complement, multiplication − Optional adder, subtracter, and accumulator − Optional pipelining − Optional bitwise logical functionality − Dedicated cascade connections
• RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s − LXT and SXT Platforms
• RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s − TXT and FXT Platforms
• PowerPC 440 Microprocessors − FXT Platform only − RISC architecture − 7-stage pipeline − 32-Kbyte instruction and data caches included − Optimized processor interface structure (crossbar)
• Integrated Endpoint blocks for PCI Express Designs − LXT, SXT, TXT, and FXT Platforms − Compliant with the PCI Express Base Specification 1.1 − x1, x4, or x8 lane support per block − Works in conjunction with RocketIO™ transceivers
FPGA可编程逻辑器件芯片XC5VLX330-2FF1760C中文规格书
IntroductionThank you for participating in the Virtex®-6 Engineering Sample Program. As part of this program, we are pleased to provide to you engineering samples of the devices listed in Table 1. Although Xilinx has made every effort to ensure the highest possible quality, these devices are subject to the limitations described in the following errata.DevicesThese errata apply to the devices shown in Table 1.Hardware Errata DetailsThis section provides a detailed description of each hardware issue known at the release time of this document.MMCMRestriction of Frequency Range for Bandwidth = HIGH or OPTIMIZEDWhen the Phase Frequency Detector (PFD) frequency (FIN/D) is lower than 135MHz and the BANDWIDTH attribute of the MMCM is set to HIGH or OPTIMIZED, a phase error between MMCM output clocks can occur, making the output clock signals invalid. This condition can also cause the fractional output counter to fail.The ISE® software v12.4 and later provides appropriate warnings for possible violations of this restriction.The ISE software v12.4 and later correctly handles designs set to OPTIMIZED bandwidth for all valid PFD frequencies.This issue will not be fixed in the devices listed in Table 1.Work-aroundPFD frequencies lower than 135MHz must use LOW bandwidth mode to ensure correct operation.See Answer Record 38132 for more information.EN101 (v1.9) April 11, 2011Errata Notification Table 1:Devices Affected by These Errata Devices XC6VLX760 CES JTAG ID (Revision Code): 0, 2XC6VLX550T CESJT AG ID (Revision Code): 0XC6VLX365T CESJT AG ID (Revision Code): 0XC6VLX240T CESJT AG ID (Revision Code): 2, 4XC6VLX195T CESJT AG ID (Revision Code): 4XC6VLX130T CESJT AG ID (Revision Code): 2, 4XC6VSX475T CESJT AG ID (Revision Code): 2, 4XC6VSX315T CESJT AG ID (Revision Code): 4PackagesAll Speed Grades -1, -2Restriction of Clock Divider ValuesThe input clock divider (DIVCLK_DIVIDE) cannot have a value of 3 or 4 when the input clock frequency (F IN) of the MMCM is above 315MHz.The ISE software v12.4 and later provides appropriate warnings for possible violations of this restriction.This issue will not be fixed in the devices listed in Table1.Work-aroundIn all designs in which F IN is above 315MHz and DIVCLK_DIVIDE is set to 3 or 4, double the CLKFBOUT_MULT_F and DIVCLK_DIVIDE values. See Answer Record 38133 for more information.Block RAMFIFO - First Read after ResetWhen reading from a FIFO after an asynchronous reset or a reset synchronized to WRCLK, the first word read is sometimes incorrect.Work-aroundSynchronize the reset with the RDCLK of the FIFO. See Answer Record 33224.Synchronous Built-in FIFOWhen using the Built-In FIFO as a Synchronous FIFO (EN_SYN=TRUE) with asynchronous reset, correct behavior of the FIFO flags cannot be guaranteed after the first write.All configurations other than EN_SYN=TRUE are not affected by this issue.Work-aroundsTo work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.For more information and additional work-arounds see Answer Record 41099.Dual Port Block RAM Address Overlap in READ_FIRST and Simple Dual Port ModeWhen using the block RAM in True Dual Port (TDP) Read_First mode, Simple Dual Port (SDP) mode, or ECC mode with different clocks on ports A and B, the user must ensure certain addresses do not occur simultaneously on both ports when both ports are enabled and one port is being written to. Failure to observe this restriction can result in read and/or memory array corruption.The description is found in the Conflict Avoidance section in v1.3.1 (or later) of UG363, Virtex-6 FPGA Memory Resources User Guide.This description was originally added in UG363 (v1.1), published 9/16/09. This errata is being provided to highlight this change and ensure that all users are aware of this design restriction. The ISE v12.1 software and later provides appropriate warnings for possible violations of these restrictions.This issue will not be fixed in the devices listed in Table1.Work-aroundThe recommended work-around is to configure the block RAM in WRITE_FIRST mode. WRITE_FIRST mode is available in block RAMs configured in TDP mode in all ISE software versions. WRITE_FIRST mode is available in block RAMs configured in SDP mode from ISE v12.2 and later. See Answer Record 34859.ConfigurationPROGRAM_B Pin Behavior During Power-OnHolding the PROGRAM_B input statically Low prior to the completion of the power-on reset does not hold the FPGA in configuration reset. Instead, the FPGA proceeds with its standard power-on configuration sequence.This issue will not be fixed in the devices listed in Table1.Work-aroundFor systems that need to delay the FPGA configuration sequence at power-on, hold the INIT_B pin Low.See Answer Record 38134 for more information.Speed Grade Minimum PLL Frequency(MHz)Maximum PLL Frequency(MHz)AVCC-11,2002,700 1.0V ±50mV-2(1)1,2002,700 1.0V ±50mV 1,2003,250 1.025V ±25mVNotes:1.For -2 devices, if one of the transceivers sharing the same AVCC power plane has a PLL frequency greater than 2,700MHz, the AVCCvoltage must be within the range of 1.0 to 1.05V.TXOUTCLK and RXRECCLK Static Operating BehaviorThe TXOUTCLK and RXRECCLK output ports might operate at reduced frequency in buffer bypass mode if conditions (1) and (2) persist for more than 15,000 cumulative hours at 65°C T j,2,500 cumulative hours at 85°C T j,or800 cumulative hours at 100°C T j:1.Power has been applied to V CCINT.2.The device is in one of the following states:a.The FPGA is not configuredb.The FPGA is configured, but the transceiver is uninstantiatedc.The transceiver is instantiated, but no reference clock is togglingd.The transceiver is instantiated, but is held in reset or power-downWork-aroundTransceivers Uninstantiated in User Design but are Planned to be Used in the FutureFor transceivers that are not instantiated in the user design but are planned to be used in the future, power must be applied to MGTAVCC, and the user design must be implemented using ISE v12.1 (or later) software for automatic insertion of the work-around circuit.Transceivers Uninstantiated in User Design but are Not Planned to be Used in the FutureAutomatic insertion of the work-around circuit can be disabled for uninstantiated transceivers that will not be used.Transceivers Instantiated in User DesignTransceivers instantiated in user design do not require a work-around circuit if the reference clock is toggling and the transceiver is not held in reset or power-down.。
Xilinx FPGA 引脚功能详细介绍
ＸｉlinｘFＰＧＡ引脚功能详细介绍注：技术交流用,希望对大家有所帮助。
ＩO_LXXＹ_＃用户IO引脚ＸＸ代表某个Bank内唯一得一对引脚，Y=[P|N］代表对上升沿还就是下降沿敏感，＃代表banｋ号2.IO_LXXY＿ZＺZ_＃多功能引脚ＺZZ代表在用户IO得基本上添加一个或多个以下功能。
Dn:I/Ｏ（在ｒeadbａck期间)，在selectMAP或者BPI模式下,D［1５:0]配置为数据口。
在从SelecｔMAP读反馈期间，如果RDWR_B=１，则这些引脚变成输出口。
配置完成后,这些引脚又作为普通用户引脚.Ｄ0_DIN_ＭISO_MＩSO1:Ｉ，在并口模式（SelｅｃtMAP/ＢPI)下，D0就是数据得最低位,在Bit—seｒial模式下，DIＮ就是信号数据得输入;在SPI模式下,MISO就是主输入或者从输出；在SPI*2或者ＳPI＊4模式下,MＩSO１就是ＳPＩ总线得第二位。
D1_MISO２,D2_MISＯ3:Ｉ，在并口模式下，D1与D2就是数据总线得低位;在ＳPI＊4模式下，MISO2与MISO3就是SPI总线得MSBs.Aｎ:O，A［2５:0]为BＰＩ模式得地址位。
配置完成后,变为用户I/Ｏ口。
ＡWAKE:Ｏ,电源保存挂起模式得状态输出引脚。
SUＳPＥND就是一个专用引脚,ＡW A ＫE就是一个多功能引脚。
除非SUSPEND模式被使能，AW AKＥ被用作用户I／O。
ＭOＳＩ_CSI_B_MIＳO0:I/O,在SPI模式下,主输出或者从输入;在SeｌectMAP模式下，ＣＳI_B就是一个低电平有效得片选信号；在SPI＊2或者ＳPＩ*4得模式下,MＩSO０就是SＰＩ总线得第一位数据。
FCS_B:O,BPI flash 得片选信号.FOＥ_B：O,ＢPI flash得输出使能信号FWＥ＿B：O，BPＩｆlａsh 得写使用信号LDC：O,BPＩ模式配置期间为低电平HDC:Ｏ,ＢPI模式配置期间为高电平CSO_Ｂ:O,在并口模式下，工具链片选信号。
Xilinx-v5
I/O 组 总数
13 17 17 23 23 33 12 15 15 20 20 27 12 15 19
最大 用户 I/O 数 (6)
400 560 560 800 800 1,200 360 480 480 680 680 960 360 480 640
Virtex-5 逻辑架构
• 高达 50% 的速度提升
0
R
Virtex-5 系列概述
LX、LXT 和 SXT 平台
DS100 (v3.0) 2007 年 2 月 2 日
0
0
先期产品技术说明
概述
Virtex™-5 系列提供 FPGA 市场中最新最强大的功能。Virtex-5 系列采用第二代 ASMBL™（高级硅片组合模块）列式架构， 包含四种截然不同的平台 （子系列），比此前任何 FPGA 系列提供的选择范围都大。每种平台都包含不同的功能配比，以满 足诸多高级逻辑设计的需求。本概述包含关于 LX、LXT 和 SXT 平台的详细信息。除了最先进的高性能逻辑架构，Virtex-5 FPGA 还包含多种硬 IP 系统级模块，包括强大的 36Kb Block RAM/FIFO、第二代 25 x 18 DSP Slice、带有内置数控阻抗的 SelectIO™ 技术、ChipSync™ 源同步接口模块、系统监视器功能、带有集成 DCM （数字时钟管理器）和锁相环 (PLL) 时钟 发生器的增强型时钟管理模块以及高级配置选项。LXT 和 SXT 器件还包含针对增强型串行连接的电源优化高速串行收发器模 块、一个符合 PCI Express™ 的集成端点模块和三态以太网 MAC （媒体访问控制器） 。这些功能使高级逻辑设计人员能够 在其基于 FPGA 的系统中体现最高档次的性能和功能。Virtex-5 FPGA 以最先进的 65nm 铜工艺技术为基础，是定制 ASIC 技术的可编程替代方案。大多数高级系统设计都需要 FPGA 的可编程能力。Virtex-5 FPGA 以前所未有的逻辑、DSP、软 / 硬微处理器和连接功能提供最佳解决方案，以满足高性能逻辑设计人员、高性能 DSP 设计人员和高性能嵌入式系统设计人员 的需求。Virtex-5 LXT、SXT 和 FXT 平台具有先进的高速串行连接功能和链路 / 事务层功能。
FPGA可编程逻辑器件芯片XC5VLX30-1FFG324C中文规格书
Recommended PCB Design Rules for BGA PackagesXilinx provides the diameter of a land pad on the component side. This information is required prior to the start of the board layout so the board pads can be designed to match the component-side land geometry. The typical values of these land pads are described in Figure 5-1 and summarized in Table 5-1. For Xilinx® BGA packages, Non-Solder Mask Defined (NSMD) pads on the board are suggested to allow a clearance between the land metal (diameter L) and the solder mask opening (diameter M) as shown in Figure 5-1. The space between the NSMD pad and the solder mask as well as the actual signal trace widths depend on the capability of the PCB vendor. The cost of the PCB is higher when the line width and spaces are smaller.Figure 5-1:Suggested Board Layout of Soldered Pads for BGA Packages1.3x 3 matrix is shown for illustration purposes only. One land pad is shown with via connection.Power Management Strategy•Heat Sinking Solutions at the System LevelDepending on the system's physical as well as mechanical constraints, the expectation is that the thermal budget is maintained with custom or OEM heat sink solutions,providing the third prong in the thermal management strategy. At this point, Xilinx has left the heat sink solution to the system-level designers who can tailor the design and solution to the constraints of their systems, being fully aware that the part has certain inherent capabilities for delivering the heat to the surface.Heat sink solutions do exist and can be effective on these low θJB flip-chip platforms.Table 6-3 below illustrates a finned heat sink solution matrix in Network environment (1U and 2U) arrangement for 35mm packages and up for power ranging from 15W to 40W. The AAVID standard finned heat sink offerings are used to illustrate the coverage given thermal budgets of ΔT =35°C and ΔT =45°C scenarios. Other heat sink configurations can be explored similarly.The Virtex-5 FPGA packages can be grouped into medium- and high-performancepackages based on their power handling capabilities. All Virtex-5 FPGA packages can use thermal enhancements, ranging from simple airflow to schemes that can include passive as well as active heat sinks. This is particularly true for the bigger flip-chip BGA packages where system designers have the option to further enhance the packages with bigger and more elaborate heat sinks to handle excesses of 25W with arrangements that consider system –physical constraints as illustrated in Table 6-3.Table 6-3:Finned Heat Sink Solution Matrix for Large Flip-chip BGA in Network Package Power(W)35 x 35 mmFF1136/FF1153/FF115642.5 x 42.5 mmFF1738/FF1759/FF1760ΔT=35°CΔT=45°CΔT=35°CΔT=45°C15W1U (5)Note 1Note 12U (6)Note 1Note 125W1U (5)Note 4Note 2Note 4Note 22U (6)Note 2Note 1Note 2Note 135W1U (5)Note 4Note 3Note 4Note 32U (6)Note 4Note 2Note 4Note 240W1U (5)––Note 4Note 32U (6)Note 3Note 2Notes:1.Solution available at 200 LFM, for example, AAVID finned part number 68520, 72390, 72415.2.Solution available at 400 LFM, for example, AAVID finned part number 68520, 69920.3.Solution available at 600 LFM, for example, AAVID finned part number 72390, 69920, 74590.4.No standard. AAVID finned solution below 600 LFM—custom finned might be required.5.For 1U Height—(max heat sink height = 26mm)6.For 2U Height—(max heat sink height = 64mmChapter 6:Thermal SpecificationsSome Thermal Management OptionsSupport for Compact Thermal Models (CTM)•Designs can be implemented to take advantage of the board's ability to spread heat.The effect of the board is dependent on its size and how it conducts heat. Board size,the level of copper traces, and the number of buried copper planes all lower thejunction-to-ambient thermal resistance for a package mounted on the board. The cold ring junction-to-board thermal data for Virtex-5 FPGA packages are given in Table 6-1. Users need to be aware that a direct heat path to the board from a component also exposes the component to the effect of other heat sources on the board, particularly if the board is not cooled effectively. An otherwise cooler component can be heated by other heat contributing components on the board.Table 6-4:Impact of Mounted Board Characteristics on θJA (FF1148)Xilinx 35 x 35 mmFF1148θJA (°C/W) for Different Board Sizes 4 x 4in 10 x 10in20 x 20inLayer Count of Mounted Board49.1(1)8.3–88.0 5.5 4.9127.5 4.7 4.4167.2 4.5 4.224–4.34.0Notes:1.Base JEDEC Mount ConditionsChapter 6:Thermal Specifications。
Xilinx FPGA 内部结构深入分析
Xilinx FPGA 内部结构深入分析作者：fpga001。
论坛：芯片动力（SocVista）。
网页地址：/bbs/viewthread.php?tid=3443&extra=page%3D2&page=7发表时间：2009.12IOB的结构请大家看到手册的第1页，这是IOB的review部分。
IO block 是高手的领地，一般接触FPGA第一年都不会太关心到这个部分。
注意看，IOB有三个数据通道：输入、输出、三态控制。
每个通道都有一对存储器件，他们可以当做寄存器或者锁存起来使用，视乎你的设置。
输入通道有可编程的延迟模块，可以确保hold time为零。
（这是在什么场合使用？请达人补充！）另外可以看到输入输出通道都有完备的DDR支持，这个在后面可以看到。
所有图都请参考PDF原文，这里就不再粘贴了。
可编程输入延迟看到手册第3页，这个像两根鱼骨似的构造就是输入延迟了。
输入延迟一共16节，每节250ps，所以总共的延迟在0~4ns之间。
这个鱼骨的构造非常巧妙，前面8节直接级联，只有一个输出。
这样8节以内的调整就跳过这根长鱼骨；而超过8节的调整就直接利用第一根鱼骨，然后在后面的8节中进行微调。
调整的输出分别供给IOB中的异步和同步单元，异步就是直接穿过IOB，同步则是经由存储单元流出IOB。
异步单元精度较高，可以单节调整，所以精度为250ps；同步单元精度稍低，两个节为单位调整，所以精度只有500ps。
上述内容看图便知可编程输入延迟的设置输入延迟的设置只能在Image配置的时候建立，在设备工作期间无法改变。
我想有两种方法可以改变输入延迟的设置：1. 通过延迟原语在代码中设置；2. 通过FPGA editor在P&R完成后在ngc文件中修改。
存储单元存储单元可以配置为D触发器，就是我们常说的FF，Xilinx称之为FD；也可以配置为锁存器，Xilinx称之为LD。
输出和三态通路各有一对寄存器外加一个MUX。