IC datasheet pdf-1SS108 pdf datasheet
RS811 Datasheet
Manual Reset
The manual-reset input (MR) allows reset to be triggered by a push button switch. MR has an internal pullup resistor, so it
can be left open when not used.
Pin Configuration
Pin Description
Pin VCC Type Description Supply Voltage. Reset is asserted when VCC drops below the Reset Threshold Voltage (V RST). Reset remains asserted until VCC rises above VRST and keep asserted for the duration of the Reset Timeout Period (tRS) once VCC rises above VRST. Ground Active-Low Reset Output (Push-Pull). It goes low when Vcc is below the reset threshold. It remains low for about 200ms after Vcc rises above the reset threshold (VRST). Manual-Reset: (CMOS). Active low. Pull low to force a reset. Reset remains asserted for the duration of the Reset Timeout Period after MR transitions from low to high. Leave unconnected or connected to VCC if not used.
S108T01;S108T01F;S208T01;中文规格书,Datasheet资料
S108T01 Series S208T01 Series■ FeaturesI T (rms)≤8A, Non-Zero Cross type Low profile SIP 4pin Triac output SSR1. Output current, I T (rms)≤8.0A2. Non-zero crossing functionary3. Slim 4 pin low profile SIP package4. High repetitive peak off-state voltage (V DRM : 600V, S208T01 Series ) (V DRM : 400V, S108T01 Series )5. High isolation voltage between input and output (V iso (rms) : 3.0kV)6. Lead-free terminal components are also available (see Model Line-up section in this datasheet)7. Screw hole for heat sink■ DescriptionS108T01 Series and S208T01 Series Solid State Relays (SSR) are an integration of an infrared emitting diode (IRED), a Phototriac Detector and a main output Triac. These devices are ideally suited for controlling high voltage AC loads with solid state reliability while providing 3.0kV isolation (V iso (rms)) from input to out-put.Notice The content of data sheet is subject to change without prior notice.In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP ■ Agency approvals/Compliance1. Isolated interface between high voltage AC devices and lower voltage DC control circuitry.2. Switching motors, fans, heaters, solenoids, and valves.3. Phase or power control in applications such as light-ing and temperature control equipment.■ Applications1. Package resin : UL flammability grade (94V-0)∗Zero cross type is also available. (S108T02 Series/S208T02 Series)∗ : Do not allow external connection.( ) : Typical dimensions■Internal Connection DiagramOutput (Triac T1)Output (Triac T2)Input (+)Input (−)■ Outline Dimensions(Unit : mm)Date code (2 digit)Rank markThere is no rank mark indicator and currently there are no rank offered for this device.A.D.199019911992199319941995199619971998199920002001MarkABCDEFHJKLMN Mark P R S T U V W X A B C Mark 123456789O N DMonth January February March April May June July August September October November December A.D 20022003200420052006200720082009201020112012······2nd digitMonth of production 1st digitYear of productionCountry of originJapanrepeats in a 20 year cycle■ Electro-optical CharacteristicsParameter Symbol Unit InputOutput (T a =25˚C)Forward voltageReverse currentRepetitive peak OFF-state currentON-state voltageHolding currentCritical rate of rise of OFF-state voltageCritical rate of rise of OFF-state voltage at commutaion Minimum trigger currentIsolation resistanceTurn-on time Turn-off timeThermal resistanceI F =20mA V R =3V V D =V DRM I T (rms)=2A, Resistance load, I F =20mA −V D =2/3•V DRM T j =125˚C , V D =2/3•V DRM , dI T /dt =−4.0A/msV D =12V, R L =30ΩDC500V, 40 to 60%RH V D (rms)=100V, AC50Hz, I F =20mAI T (rms)=2A, Resistance loadV D (rms)=200V, AC50Hz, I F =20mAI T (rms)=2A, Resistance load V D (rms)=100V, AC50Hz, I F =20mAI T (rms)=2A, Resistance loadV D (rms)=200V, AC50Hz, I F =20mAI T (rms)=2A, Resistance loadBetween junction and case Between junction and ambience Conditions MIN.TYP.MAX.Transfer charac-teristicsS108T01S208T01S108T01S208T01V µA µA V mA V/µs V/µs mA Ωmsms˚C /W −−−−−305−1010−−−−−−1.2−−−−−−−−−−−−4.5401.41001001.550−−8−111010−−V F I R I DRM V T (rms)I H dV/dt(dV/dt)c I FT R ISO t ont off R th (j-c)R th (j-a)■ Absolute Maximum RatingsParameter Symbol Rating UnitInputOutput(T a =25˚C)Forward current Reverse voltage RMS ON-state current Peak one cycle surge current Repetitive peak OFF-state voltage Non-Repetitive peak OFF-state voltage Critical rate of rise of ON-state current Operating frequency Isolation voltage Operating temperature Storage temperature Soldering temperature *2*1I FV R I T (rms)I surge V DRMV DSMdI T /dt fV iso (rms)T opr T stg T solmA V A A VVA/µs Hz kV ˚C ˚C ˚C*3*3*45068804006004006005045 to 653.0−25 to +100−30 to +125260*1 40 to 60%RH, AC for 1minute, f =60Hz *2 For 10s*3 Refer to Fig.1, Fig.2*4 f =60Hz sine wave, T j =25˚C startS108T01S208T01S108T01S208T01Soldering areaShipping PackageModel No.Sleeve 25pcs/sleeve S108T01F S208T01FI FT [mA](V D =12V, R L =30Ω)MAX.8400MAX.8600V DRM [V]Please contact a local SHARP sales representative to see the actual status of the production.■ Model Line-up (1) (Lead-free terminal components)■ Model Line-up (2) (Lead solder plating components)Shipping PackageModel No.Sleeve 25pcs/sleeve S108T01S208T01I FT [mA](V D =12V, R L =30Ω)MAX.8400MAX.8600V DRM [V]F o r w a r d c u r r e n t I F (m A )Ambient temperature T a (˚C)060−2502550751001255040302010Fig.1 Forward Current vs. AmbientTemperatureFig.2 RMS ON-state Current vs.Ambient TemperatureR M S O N -s t a t e c u r r e n t I T (r m s )(A )Ambient temperature T a (˚C)0987654321−25100755025125(1)(2)(3)(4)(5)(1)With infinite heat sink(2)With heat sink (200×200×2mm Al plate)(3)With heat sink (100×100×2mm Al plate)(4)With heat sink (50×50×2mm Al plate)(5)Without heat sink(N ote)In natural cooling condition, please locate Al platevertically, spread the thermal conductive silicone grease on the touch surface of the device and tighten up the device in the center of Al plate at the torque of 0.4N•m.F o r w a r d c u r r e n t I F (m A )Forward voltage V F (mA)1010.1100Fig.4 Forward Current vs. Forward VoltageFig.3 RMS ON-state Current vs.Case TemperatureR M S O N -s t a t e c u r r e n t I T (r m s )(A )Case temperature T C (°C) 010−25255075100125987654321Fig.8-b Repetitive Peak OFF-state Current vs.Ambient Temperature (S208T01)Fig.8-a Repetitive Peak OFF-state Current vs.Ambient Temperature (S108T01)R e p e t i t i v e p e a k O F F -s t a t e c u r r e n t I D R M (A )Ambient temperature T a (˚C)10−910−310−410−510−610−710−8R e p e t i t i v e p e a k O F F -s t a t e c u r r e n t I D R M (A )Ambient temperature T a (˚C)10−910−310−410−510−610−710−8Remarks : Please be aware that all data in the graph are just for reference.Fig.5 Surge Current vs. Power-on CycleFig.6 Minimum Trigger Current vs.Ambient TemperatureFig.7 Maximum ON-state Power Dissipationvs. RMS ON-state CurrentM i n i m u m t r i g g e r c u r r e n t I F T (m A )Ambient temperature T a (˚C)0108642S u r g e c u r r e n t I s u r g e (A )Power-on cycle (Times)10080604020120M a x i m u m O N -s t a t e p o w e r d i s s i p a t i o n (W )RMS ON-state current I T (rms)(A)010864297531■ Design ConsiderationsIn order for the SSR to turn off, the triggering current (l F ) must be 0.1mA or less.In phase control applications or where the SSR is being by a pulse signal, please ensure that the pulse width is a minimum of 1ms.When the input current (I F ) is below 0.1mA, the output Triac will be in the open circuit mode. However, if the voltage across the Triac, V D , increases faster than rated dV/dt, the Triac may turn on. To avoid this situation, please incorporate a snubber circuit. Due to the many different types of load that can be driven, we can merely recommend some circuit vales to start with : Cs=0.022µF and Rs=47Ω. The operation of the SSR and snubber circuit should be tested and if unintentional switching occurs, please adjust the snubber circuit component values accordingly.When making the transition from On to Off state, a snubber circuit should be used ensure that sudden drops in current are not accompanied by large instantaneous changes in voltage across the Triac.This fast change in voltage is brought about by the phase difference between current and voltage. Primarily, this is experienced in driving loads which are inductive such as motors and solenoids. Following the procedure outlined above should provide sufficient results.Any snubber or Varistor used for the above mentioned scenarios should be located as close to the main out-put triac as possible.The load current should be within the bounds of derating curve. (Refer to Fig.2) Also, please use the optional heat sink when necessary.In case the optional heat sink is used and the isolation voltage between the device and the optional heat sink is needed, please locate the insulation sheet between the device and the heat sink.When the optional heat sink is equipped, please set up the M3 screw-fastening torque at 0.3 to 0.5N•m.In order to dissipate the heat generated from the inside of device effectively, please follow the below sugges-tions.(a) Make sure there are no warps or bumps on the heat sink, insulation sheet and device surface.(b) Make sure there are no metal dusts or burrs attached onto the heat sink, insulation sheet and device sur-face.(c) Make sure silicone grease is evenly spread out on the heat sink, insulation sheet and device surface.● Design guide● Recommended Operating ConditionsParameterS108T01S208T01Symbol Unit InputOutputInput signal current at ON state Input signal current at OFF state Load supply voltage Load supply currentFrequencyOperating temperatureI F (ON)I F (OFF)V OUT (rms)I OUT (rms)f T oprmA mA V mA Hz ˚C−−−Locate snubber circuit between output terminals(Cs =0.022µF, Rs =47Ω)−−Conditions(∗) See Fig.2 about derating curve (I T (rms) vs. ambient temperature).16080800.147−20240.1120240I T (rms)×80%(∗)6380MIN.MAX.✩ For additional design assistance, please review our corresponding Optoelectronic Application Notes.● Standard CircuitV 1+V CCS108T01● DegradationIn general, the emission of the IRED used in SSR will degrade over time.In the case where long term operation and / or constant extreme temperature fluctuations will be applied to the devices, please allow for a worst case scenario of 50% degradation over 5years.Therefore in order to maintain proper operation, a design implementing these SSRs should provide at least twice the minimum required triggering current from initial operation.Silicone grease to be used is as follows;1) There is no aged deterioration within the operating temperature ranges.2) Base oil of grease is hardly separated and is hardly permeated in the device.3) Even if base oil is separated and permeated in the device, it should not degrade the function of a device. Recommended grease : G-746 (Shin-Etsu Chemical Co., Ltd.): G-747 (Shin-Etsu Chemical Co., Ltd.): SC102 (Dow Corning Toray Silicone Co., Ltd.) In case the optional heat sink is screwed up, please solder after screwed.In case of the lead frame bending, please keep the following minimum distance and avoid any mechanical stress between the base of terminals and the molding resin.Some of AC electromagnetic counters or solenoids have built-in rectifier such as the diode.In this case, please use the device carefully since the load current waveform becomes similar with rectangu-lar waveform and this results may not make a device turn off.■ Manufacturing Guidelines● Soldering MethodFlow Soldering (No solder bathing)Flow soldering should be completed below 260˚C and within 10s.Preheating is within the bounds of 100 to 150˚C and 30 to 80s.Please solder within one time.Other noticesPlease test the soldering method in actual condition and make sure the soldering works fine, since the impact on the junction between the device and PCB varies depending on the tooling and soldering conditions.分销商库存信息:SHARP-MICROELECTRONICSS108T01S108T01F S208T01。
IC datasheet pdf-ADS7846,pdf(Touch-Screen Controller)
"
"
"
"
"
"
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI web site at .
US Patent No. 6246394 QSPI and SPI are registered trademarks of Motorola.
+VCC
X+ X–
Temperature Sensor
SAR
Y+ Y–
ADS7846
DOUT BUSY
Comparator 6-Channel MUX CDAC Serial Data Out CS
ADS7846
ADS 7846
AD S784 6
®
AD
S784
6
SBAS125H – SEPTEMBER 1999 – REVISED JANUARY 2005
TOUCH SCREEN CONTROLLER
FEATURES
q SAME PATION q INTERNAL 2.5V REFERENCE q q q q DIRECT BATTERY MEASUREMENT (0V to 6V) ON-CHIP TEMPERATURE MEASUREMENT TOUCH-PRESSURE MEASUREMENT QSPITM/SPITM 3-WIRE INTERFACE
PENIRQ
IC datasheet pdf-ADC12C080,pdf datasheet (12-Bit, 65_80 MSPS A_D Converter)
August 2007 ADC12C08012-Bit, 65/80 MSPS A/D ConverterGeneral DescriptionThe ADC12C080 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at rates up to 80 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sam-ple-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC12C080 may be oper-ated from a single +3.0V power supply and consumes low power. A separate +2.5V supply may be used for the digital output interface which allows lower power operation with re-duced noise. A power-down feature reduces the power con-sumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC12C080 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains perfor-mance over a wide range of clock duty cycles.The ADC12C080 is available in a 32-lead LLP package and operates over the industrial temperature range of −40°C to +85°C.Features■ 1 GHz Full Power Bandwidth■Internal reference and sample-and-hold circuit■Low power consumption■Data Ready output clock■Clock Duty Cycle Stabilizer■Single +3.0V supply operation■Power-down mode■32-pin LLP package, (5x5x0.8mm, 0.5mm pin-pitch) Key Specifications■Resolution12 Bits ■Conversion Rate80 MSPS ■SNR (f IN = 170 MHz)68 dBFS (typ)■SFDR (f IN = 170 MHz)86 dBFS (typ)■Full Power Bandwidth 1 GHz (typ)■Power Consumption300 mW (typ) Applications■High IF Sampling Receivers■Wireless Base Station Receivers■Test and Measurement Equipment■Communications Instrumentation■Portable InstrumentationConnection Diagram20211101© 2007 National Semiconductor ADC12C080 12-Bit, 65/80 MSPS A/D Converter 电子发烧友 电子技术论坛Block Diagram20211102Ordering InformationIndustrial (−40°C ≤ T A ≤ +85°C)Package ADC12C080CISQ 32 Pin LLPADC12C080CISQE 32 Pin LLP,250-Piece Tape and ReelADC12C080EBEvaluation Board 2A D C 12C 080 电子发烧友 电子技术论坛Pin Descriptions and Equivalent CircuitsPin No.SymbolEquivalent CircuitDescriptionANALOG I/O5V IN +Differential analog input pins. The differential full-scale input signal level is 2V P-P with each input pin signal centered on a common mode voltage, V CM .6V IN -2V RP These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 0.1 µF capacitor placed very close to the pin to minimize stray inductance. A 0.1 µF capacitor should be placed between V RP and V RN as close to the pins as possible,and a 1 µF capacitor should be placed in parallel.V RP and V RN should not be loaded. V CMO may be loaded to 1mA for use as a temperature stable 1.5V reference.It is recommended to use V CMO to provide the common mode voltage, V CM , for the differential analog inputs, V IN + and V IN −.32V CMO1V RN31V REFReference Voltage. This device provides an internally developed 1.2V reference. When using the internal reference, V REF should be decoupled to AGND with a 0.1 µFand a 1 µF low equivalent series inductance (ESL) capacitor.This pin may be driven with an external 1.2V reference voltage.This pin should not be used to source or sink current.12OF/DCSThis is a four-state pin controlling the input clock mode and output data format.OF/DCS = V A , output data format is 2's complement without duty cycle stabilization applied to the input clockOF/DCS = AGND, output data format is offset binary, without duty cycle stabilization applied to the input clock.OF/DCS = (2/3)*V A , output data is 2's complement with duty cycle stabilization applied to the input clockOF/DCS = (1/3)*V A , output data is offset binary with duty cycle stabilization applied to the input clock.DIGITAL I/O11CLKThe clock input pin.The analog input is sampled on the rising edge of the clock input.30PDThis is a two-state input controlling Power Down.PD = V A , Power Down is enabled and power dissipation is reduced.PD = AGND, Normal operation.ADC12C080 电子发烧友 电子技术论坛Pin No.Symbol Equivalent Circuit Description15-19,23-29D0–D11Digital data output pins that make up the 12-bit conversion result.D0 (pin 15) is the LSB, while D11 (pin 29) is the MSB of the output word. Output levels are CMOS compatible.21DRDYData Ready Strobe. The data output transition is synchronized with the falling edge of this signal. This signal switches at the same frequency as the CLK input.ANALOG POWER 3, 8, 10V APositive analog supply pins. These pins should be connected to a quiet voltage source and be bypassed to AGND with 0.1 µF capacitors located close to the power pins.4, 7, 9,Exposed Pad AGNDThe ground return for the analog supply.The exposed pad on back of package must be soldered to ground plane to ensure rated performance.DIGITAL POWER20V DRPositive driver supply pin for the output drivers. This pin should be connected to a quiet voltage source and be bypassed to DRGND with a 0.1 µF capacitor located close to the power pin.22DRGNDThe ground return for the digital output driver supply. This pins should be connected to the system digital ground, but not be connected in close proximity to the ADC's AGND pins. 4A D C 12C 080 电子发烧友 电子技术论坛Absolute Maximum Ratings (Notes 1, 3)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage (V A , V DR )−0.3V to 4.2V Voltage on Any Pin (Not to exceed 4.2V)−0.3V to (V A +0.3V)Input Current at Any Pin other than Supply Pins (Note 4)±5 mA Package Input Current (Note 4)±50 mA Max Junction Temp (T J )+150°C Thermal Resistance (θJA )30°C/WESD Rating Human Body Model (Note 6)2500V Machine Model (Note 6)250V Storage Temperature −65°C to +150°C Soldering process must comply with National Semiconductor's Reflow Temperature Profilespecifications. Refer to /packaging.(Note 7)Operating Ratings(Notes 1, 3)Operating Temperature −40°C ≤ T A ≤ +85°CSupply Voltage (V A )+2.7V to +3.6V Output Driver Supply (V DR )+2.4V to V AClock Duty Cycle(DCS Enabled)30/70 %(DCS disabled)45/55 %V CM1.4V to 1.6V|AGND-DRGND|≤100mVADC12C080 Converter Electrical CharacteristicsUnless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V A = +3.0V, V DR = +2.5V, Internal V REF =+1.2V, f CLK = 80 MHz, 50% Duty Cycle, DCS Disabled, V CM = V CMO , C L = 5 pF/pin. Typical values are for T A = 25°C. Boldface limits apply for T MIN ≤ T A ≤ T MAX . All other limits apply for T A = 25°C (Notes 8, 9)SymbolParameterConditionsTypical(Note 10)LimitsUnits (Limits)STATIC CONVERTER CHARACTERISTICSResolution with No Missing Codes 12Bits (min)INL Integral Non Linearity ±0.5 1.2LSB (max)-1.2LSB (min)DNL Differential Non Linearity ±0.350.7LSB (max)-0.6LSB (min)PGE Positive Gain Error 0.25±1.25%FS (max)NGENegative Gain Error0.15±1.25%FS (max)TC PGE Positive Gain Error Tempco −40°C ≤ T A ≤ +85°C -7 ppm/°C TC NGE Negative Gain Error Tempco −40°C ≤ T A ≤ +85°C -6 ppm/°C V OFF Offset Error0.065±0.55%FS (max)TC V OFF Offset Error Tempco−40°C ≤ T A ≤ +85°C 7.5 ppm/°CUnder Range Output Code 00Over Range Output Code40954095 REFERENCE AND ANALOG INPUT CHARACTERISTICS V CMO Common Mode Output Voltage 1.5 1.401.56V (min)V (max)V CM Analog Input Common Mode Voltage1.5 1.41.6V (min)V (max)C IN V IN Input Capacitance (each pin to GND)(Note 11)V IN = 1.5 Vdc ± 0.5 V (CLK LOW)8.5 pF (CLK HIGH)3.5 pF V REFInternal Reference Voltage1.18V TC V REF Internal Reference Voltage Tempco −40°C ≤ T A ≤ +85°C 18 ppm/°C V RPInternal Reference top(Note 13)1.981.892.06V (min)V (max)ADC12C080 电子发烧友 电子技术论坛Symbol ParameterConditionsTypical(Note 10)LimitsUnits (Limits)V RN Internal Reference bottom (Note 13)0.980.891.06V (min)V (max)EXT V REFExternal Reference Voltage(Note 13)1.201.1761.224V (min)V (max)ADC12C080 Dynamic Converter Electrical CharacteristicsUnless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V A = +3.0V, V DR = +2.5V, Internal V REF =+1.2V, f CLK = 80 MHz, 50% Duty Cycle, DCS Disabled, V CM = V CMO , C L = 5 pF/pin, . Typical values are for T A = 25°C. Boldface limits apply for T MIN ≤ T A ≤ T MAX . All other limits apply for T A = 25°C (Notes 8, 9)SymbolParameterConditionsTypical(Note 10)LimitsUnits (Limits)(Note 2)DYNAMIC CONVERTER CHARACTERISTICS, A IN = -1dBFS FPBW Full Power Bandwidth -1 dBFS Input, −3 dB Corner1.0 GHz SNRSignal-to-Noise Ratiof IN = 10 MHz 71.2dBFS f IN = 70 MHz 70.5dBFSf IN = 170 MHz 68.567.8dBFS SFDRSpurious Free Dynamic Rangef IN = 10 MHz90 dBFS f IN = 70 MHz 88dBFS f IN = 170 MHz 8682dBFS ENOBEffective Number of Bitsf IN = 10 MHz11.5 Bits f IN = 70 MHz 11.3Bits f IN = 170 MHz 11.110.9Bits THDTotal Harmonic Disortionf IN = 10 MHz−88 dBFS f IN = 70 MHz −86dBFS f IN = 170 MHz −85-80.5dBFS H2Second Harmonic Distortionf IN = 10 MHz−95 dBFS f IN = 70 MHz −90dBFS f IN = 170 MHz −86-82dBFS H3Third Harmonic Distortionf IN = 10 MHz−90 dBFS f IN = 70 MHz −88dBFS f IN = 170 MHz −86-82dBFS SINAD Signal-to-Noise and Distortion Ratio f IN = 10 MHz71.1 dBFS f IN = 70 MHz 70dBFS f IN = 170 MHz68.567.6dBFS IMDIntermodulation Distortionf IN = 19.5MHz and 20.5MHz, each -7dBFS-82dBFSADC12C080 Logic and Power Supply Electrical CharacteristicsUnless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V A = +3.0V, V DR = +2.5V, Internal V REF =+1.2V, f CLK = 80 MHz, 50% Duty Cycle, DCS Disabled, V CM = V CMO , C L = 5 pF/pin. Typical values are for T A = 25°C. Boldface limits apply for T MIN ≤ T A ≤ T MAX . All other limits apply for T A = 25°C (Notes 8, 9)SymbolParameterConditionsTypical (Note 10)LimitsUnits (Limits)DIGITAL INPUT CHARACTERISTICS (CLK, PD)V IN(1)Logical “1” Input Voltage V D = 3.6V 2.0V (min)V IN(0)Logical “0” Input Voltage V D = 3.0V 0.8V (max)I IN(1)Logical “1” Input Current V IN = 3.3V 10 µA I IN(0)Logical “0” Input Current V IN = 0V −10 µA C INDigital Input Capacitance5pF6A D C 12C 080 电子发烧友 电子技术论坛Symbol Parameter ConditionsTypical (Note 10)LimitsUnits (Limits)DIGITAL OUTPUT CHARACTERISTICS (D0–D11, DRDY)V OUT(1)(1)Logical “1” Output Voltage I OUT = −0.5 mA , V DR = 2.4V 2.0V (min)V OUT(0)(0)Logical “0” Output Voltage I OUT = 1.6 mA, V DR = 2.4V 0.4V (max)+I SC Output Short Circuit Source Current V OUT = 0V −10 mA −I SC Output Short Circuit Sink Current V OUT = V DR 10 mA C OUT Digital Output Capacitance5pFPOWER SUPPLY CHARACTERISTICSI A Analog Supply Current Full Operation100123mA (max)I DRDigital Output Supply Current Full Operation (Note 12)12 mA Power ConsumptionExcludes I DR (Note 12)300369mW (max)Power Down Power ConsumptionClock disabled7mWADC12C080 Timing and AC CharacteristicsUnless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V A = +3.0V, V DR = +2.5V, Internal V REF =+1.2V, f CLK = 80 MHz, 50% Duty Cycle, DCS Disabled, V CM = V CMO , C L = 5 pF/pin. Typical values are for T A = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for T MIN ≤ T A ≤ T MAX . All other limits apply for T A = 25°C (Notes 8, 9)Symb ParameterConditionsTypical (Note 10)Limits Units (Limits) Maximum Clock Frequency 80MHz (max) Minimum Clock Frequency 20MHz (min)t CH Clock High Time 6 ns t CL Clock Low Time 6 ns t CONV Conversion Latency7Clock Cycles t OD Output Delay of CLK to DATA Relative to rising edge of CLK(Note 13) 5.537.3ns (min)ns(max)t SU Data Output Setup Time Relative to DRDY 6.5 5.5ns (min)t H Data Output Hold Time Relative to DRDY 65ns (min)t AD Aperture Delay 0.6 ns t AJAperture Jitter0.1ps rmsADC12C080 电子发烧友 电子技术论坛Dynamic Converter Electrical Characteristics at 65MSPSUnless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V A = +3.0V, V DR = +2.5V, Internal V REF =+1.2V, f CLK = 65 MHz, 50% Duty Cycle, DCS Disabled, V CM = V CMO , C L = 5 pF/pin, . Typical values are for T A = 25°C. Boldface limits apply for T MIN ≤ T A ≤ T MAX . All other limits apply for T A = 25°C (Notes 8, 9)SymbolParameterConditionsTypical (Note 10)LimitsUnits (Limits)(Note 2)DYNAMIC CONVERTER CHARACTERISTICS, A IN = -1dBFSSNRSignal-to-Noise Ratiof IN = 10 MHz71.2dBFS f IN = 70 MHz 70.5dBFS f IN =170 MHz 68.5 dBFS SFDRSpurious Free Dynamic Rangef IN = 10 MHz90 dBFS f IN = 70 MHz 88dBFS f IN = 170 MHz 86 dBFS ENOBEffective Number of Bitsf IN = 10 MHz11.5 Bits f IN = 70 MHz 11.3Bits f IN = 170 MHz 11 Bits THDTotal Harmonic Disortionf IN = 10 MHz−88 dBFS f IN = 70 MHz −85dBFS f IN = 170 MHz −80 dBFS H2Second Harmonic Distortionf IN = 10 MHz-100 dBFS f IN = 70 MHz −95dBFS f IN = 170 MHz −85 dBFS H3Third Harmonic Distortionf IN = 10 MHz−90 dBFS f IN = 70 MHz −88dBFS f IN = 170 MHz −83 dBFS SINADSignal-to-Noise and Distortion Ratiof IN = 10 MHz71.1 dBFS f IN = 70 MHz 69.8dBFS f IN = 170 MHz67.7 dBFS POWER SUPPLY CHARACTERISTICS I A Analog Supply Current Full Operation90mA (max)I DRDigital Output Supply Current Full Operation (Note 12)14.5 mAPower ConsumptionExcludes I DR (Note 12)270mW (max)Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.Note 2:Parameters specified in dBFS indicate the value that would be attained with a full-scale input signal.Note 3:All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.Note 4:When the input voltage at any pin exceeds the power supplies (that is, V IN < AGND, or V IN > V A ), the current at that pin should be limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10.Note 5:The maximum allowable power dissipation is dictated by T J,max , the junction-to-ambient thermal resistance, (θJA ), and the ambient temperature, (T A ), and can be calculated using the formula P D,max = (T J,max - T A )/θJA . The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.Note 6:Human Body Model is 100 pF discharged through a 1.5 k Ω resistor. Machine Model is 220 pF discharged through 0 ΩNote 7:Reflow temperature profiles are different for lead-free and non-lead-free packages.Note 8:The inputs are protected as shown below. Input voltage magnitudes above V A or below GND will not damage this device, provided current is limited per(Note 4). However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section. 8A D C 12C 080 电子发烧友 电子技术论坛20211111Note 9:With a full scale differential input of 2VP-P, the 12-bit LSB is 488 µV.Note 10:Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are notguaranteed.Note 11:The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.Note 12:IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,V DR , and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(Cx f+ C1x f1+....C11x f11) where VDRis the output driver powersupply voltage, Cn is total capacitance on the output pin, and fnis the average frequency at which that pin is toggling.Note 13:This parameter is guaranteed by design and/or characterization and is not tested in production. ADC12C080 电子发烧友 电子技术论坛Specification DefinitionsAPERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for conver-sion.APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output.CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal.COMMON MODE VOLTAGE (V CM ) is the common DC volt-age applied to both input terminals of the ADC.CONVERSION LATENCY is the number of clock cycles be-tween initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is avail-able at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay.DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB.EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion Ratio or SINAD. ENOB is defined as (SINAD -1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits.FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input.GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:Gain Error = Positive Full Scale Error − Negative Full ScaleError It can also be expressed as Positive Gain Error and Negative Gain Error, which are calculated as:PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale ErrorINTEGRAL NON LINEARITY (INL) is a measure of the de-viation of each individual code from a best fit straight line. The deviation of any given code from this straight line is measured from the center of that code value.INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time.It is defined as the ratio of the power in the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-est value or weight of all bits. This value is V FS /2n , where “V FS ” is the full scale input voltage and “n” is the ADC reso-lution in bits.MISSING CODES are those output codes that will never ap-pear at the ADC outputs. The ADC is guaranteed not to have any missing codes.MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of ½ LSB above negative full scale.OFFSET ERROR is the difference between the two input voltages [(V IN +) – (V IN -)] required to cause a transition from code 2047 to 2048.OUTPUT DELAY is the time delay after the falling edge of the clock before the data update is presented at the output pins.PIPELINE DELAY (LATENCY) See CONVERSION LATEN-CY.POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 1½ LSB below positive full scale.POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. PSRR is the ratio of the Full-Scale output of the ADC with the supply at the minimum DC supply limit to the Full-Scale output of the ADC with the supply at the maximum DC supply limit, expressed in dB.SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sam-pling frequency, not including harmonics or DC.SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral com-ponents below half the clock frequency, including harmonics but excluding d.c.SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-ence, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input.TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-pressed in dB, of the rms total of the first six harmonic levels at the output to the level of the fundamental at the output. THD is calculated aswhere f 1 is the RMS power of the fundamental (output) fre-quency and f 2 through f 7 are the RMS power of the first six harmonic frequencies in the output spectrum.SECOND HARMONIC DISTORTION (2ND HARM) is the dif-ference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output.THIRD HARMONIC DISTORTION (3RD HARM) is the dif-ference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output. 10A D C 12C 080 电子发烧友 电子技术论坛Timing Diagram20211109FIGURE 1. Output TimingTransfer Characteristic20211110FIGURE 2. Transfer CharacteristicTypical Performance Characteristics DNL, INL Unless otherwise specified, the followingspecifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR= +2.5V, Internal VREF= +1.2V, fCLK= 80 MHz, 50% Duty Cycle,DCS disabled, VCM = VCMO, CL= 5 pF/pin. TA= 25°C.ADC12C080 电子发烧友 电子技术论坛DNL 20211141INL20211142DNL vs. f CLK 20211143INL vs. f CLK20211144DNL vs. Temperature 20211147INL vs. Temperature20211148A D C 12C 080 电子发烧友 电子技术论坛DNL vs. VA20211149INL vs. VA20211150ADC12C080 电子发烧友 电子技术论坛Typical Performance CharacteristicsUnless otherwise specified, the following specifications apply:AGND = DRGND = 0V, V A = +3.0V, V DR = +2.5V, Internal V REF = +1.2V, f CLK = 80 MHz, 50% Duty Cycle, DCS disabled, V CM =V CMO , f IN = 10 MHz, C L = 5 pF/pin. T A = 25°C.SNR, SINAD, SFDR vs. V A20211151Distortion vs. V A20211152SNR, SINAD, SFDR vs. V DR 20211153Distortion vs. V DR20211154SNR, SINAD, SFDR vs. f CLK 20211155Distortion vs. f CLK20211156A D C 12C 080 电子发烧友 电子技术论坛SNR, SINAD, SFDR vs. Clock Duty Cycle20211157Distortion vs. Clock Duty Cycle20211158SNR, SINAD, SFDR vs. Clock Duty Cycle, DCS Enabled20211159Distortion vs. Clock Duty Cycle, DCS Enabled20211160SNR, SINAD, SFDR vs. fIN20211163Distortion vs. fIN20211164ADC12C080 电子发烧友 电子技术论坛SNR, SINAD, SFDR vs. Temperature 20211165Distortion vs. Temperature20211166Spectral Response @ 10 MHz input 20211168Spectral Response @ 70 MHz input20211169Spectral Response @ 170 MHz input20211170Intermodulation Distortion, f IN 1= 19.5 MHz, f IN 2 = 20.5 MHz20211171A D C 12C 080 电子发烧友 电子技术论坛Power vs. fCLK20211172ADC12C080 电子发烧友 电子技术论坛Functional DescriptionOperating on a single +3.0V supply, the ADC12C080 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The user has the choice of using an internal 1.2V stable reference, or using an external 1.2V reference. Any external reference is buffered on-chip to ease the task of driving that pin.The output word rate is the same as the clock frequency. The analog input is acquired at the rising edge of the clock and the digital data for a given sample is delayed by the pipeline for 7 clock cycles. The digital outputs are CMOS compatible sig-nals that are clocked by a synchronous data ready output signal (DRDY, pin 21) at the same rate as the clock input. Duty cycle stabilization and output data format are selectable using the quad state function OF/DCS pin (pin 12). The output data can be set for offset binary or two's complement.Power-down is selectable using the PD pin (pin 30). A logic high on the PD pin reduces the converter power consumption.For normal operation, the PD pin should be connected to the analog ground (AGND).Applications Information1.0 OPERATING CONDITIONSWe recommend that the following conditions be observed for operation of the ADC12C080: 2.7V ≤ V A ≤ 3.6V 2.4V ≤ V DR ≤ V A20 MHz ≤ f CLK ≤ 80 MHz 1.2V internal referenceV REF = 1.2V (for an external reference) V CM = 1.5V (from V CMO )2.0 ANALOG INPUTS 2.1 Signal Inputs2.1.1 Differential Analog Input PinsThe ADC12C080 has one pair of analog signal input pins,V IN + and V IN −, which form a differential input pair. The input signal, V IN , is defined asV IN = (V IN +) – (V IN −)shows the expected input signal range. Note that the common mode input voltage, V CM , should be 1.5V. Using V CMO (pin 32)for V CM will ensure the proper input common mode level for the analog input signal. The positive peaks of the individual input signals should each never exceed 2.6V. Each analoginput pin of the differential pair should have a maximum peak-to-peak voltage of 1V, be 180° out of phase with each other and be centered around V CM .The peak-to-peak voltage swing at each analog input pin should not exceed the 1V or the out-put data will be clipped.20211115FIGURE 3. Expected Input Signal RangeFor single frequency sine waves the full scale error in LSB can be described as approximatelyE FS = 4096 ( 1 - sin (90° + dev))Where dev is the angular difference in degrees between the two signals having a 180° relative phase relationship to each other (see ). For single frequency inputs, angular errors result in a reduction of the effective full scale input. For complex waveforms, however, angular errors will result in distortion.20211116FIGURE 4. Angular Errors Between the Two Input SignalsWill Reduce the Output Level or Cause Distortion It is recommended to drive the analog inputs with a source impedance less than 100Ω. Matching the source impedance for the differential inputs will improve even ordered harmonic performance (particularly second harmonic).Table 1indicates the input to output relationship of the AD-C12C080.A D C 12C 080 电子发烧友 电子技术论坛。
S108T02;S108T02F;S208T02;中文规格书,Datasheet资料
S108T02 Series S208T02 Series■ FeaturesI T (rms)≤8A, Zero Cross type Low profile SIP 4pin Triac output SSR1. Output current, I T (rms)≤8.0A2. Zero crossing functionary (V OX : MAX. 35V)3. Slim 4 pin low profile SIP package4. High repetitive peak off-state voltage (V DRM : 600V, S208T02 Series ) (V DRM : 400V, S108T02 Series )5. High isolation voltage between input and output (V iso (rms) : 3.0kV)6. Lead-free terminal components are also available (see Model Line-up section in this datasheet)7. Screw hole for heat sink■ DescriptionS108T02 Series and S208T02 Series Solid State Relays (SSR) are an integration of an infrared emitting diode (IRED), a Phototriac Detector and a main output Triac. These devices are ideally suited for controlling high voltage AC loads with solid state reliability while providing 3.0kV isolation (V iso (rms)) from input to out-put.Notice The content of data sheet is subject to change without prior notice.In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP ■ Agency approvals/Compliance1. Isolated interface between high voltage AC devices and lower voltage DC control circuitry.2. Switching motors, fans, heaters, solenoids, and valves.3. Power control in applications such as lighting and temperature control equipment.■ Applications1. Package resin : UL flammability grade (94V-0)∗Non-zero cross type is also available. (S108T01 Series/S208T01 Series)∗ : Do not allow external connection.( ) : Typical dimensions■ Internal Connection Diagram+)−)■ Outline Dimensions(Unit : mm)Date code (2 digit)Rank markThere is no rank mark indicator and currently there are no rank offered for this device.A.D.199019911992199319941995199619971998199920002001MarkABCDEFHJKLMN Mark P R S T U V W X A B C Mark 123456789O N DMonth January February March April May June July August September October November December A.D 20022003200420052006200720082009201020112012······2nd digitMonth of production 1st digitYear of productionCountry of originJapanrepeats in a 20 year cycle■ Electro-optical CharacteristicsParameter Symbol Unit InputOutput (T a =25˚C)Forward voltageReverse currentRepetitive peak OFF-state currentON-state voltageHolding currentCritical rate of rise of OFF-state voltageCritical rate of rise of OFF-state voltage at commutaion Minimum trigger currentZero cross voltageIsolation resistanceTurn-on time Turn-off timeThermal resistanceV F I R I DRM V T (rms)I H dV/dt (dV/dt)c I FT V OX R ISO t ont off R th (j-c)R th (j-a)I F =20mA V R =3V V D =V DRM I T (rms)=2A, Resistance load, I F =20mA −V D =2/3•V DRM T j =125˚C , V D =2/3•V DRM , dI T /dt =−4.0A/msV D =6V, R L =30ΩI F =8mA DC500V, 40 to 60%RH V D (rms)=100V, AC50Hz, I F =20mAI T (rms)=2A, Resistance load V D (rms)=200V, AC50Hz, I F =20mA I T (rms)=2A, Resistance load V D (rms)=100V, AC50Hz, I F =20mAI T (rms)=2A, Resistance loadV D (rms)=200V, AC50Hz, I F =20mAI T (rms)=2A, Resistance loadBetween junction and case Between junction and ambience Conditions MIN.TYP.MAX.Transfer charac-teristics S108T02S208T02S108T02S208T02−−−−−305−−1010−−−−−−1.2−−−−−−−−−−−−−4.5401.41001001.550−−835−10101010−−V µA µA V mA V/µs V/µs mA V Ωmsms˚C /W ■ Absolute Maximum RatingsParameter Symbol Rating UnitInputOutput(T a =25˚C)Forward current Reverse voltage RMS ON-state current Peak one cycle surge current Repetitive peak OFF-state voltage Non-Repetitive peak OFF-state voltage Critical rate of rise of ON-state current Operating frequency Isolation voltage Operating temperature Storage temperature Soldering temperature *2*1I FV R I T (rms)I surge V DRMV DSMdI T /dt fV iso (rms)T opr T stg T solmA V A A VVA/µs Hz kV ˚C ˚C ˚C*3*3*45068804006004006005045 to 653.0−25 to +100−30 to +125260*1 40 to 60%RH, AC for 1minute, f =60Hz *2 For 10s*3 Refer to Fig.1, Fig.2*4 f =60Hz sine wave, T j =25˚C startS108T02S208T02S108T02S208T02Soldering areaShipping PackageModel No.Sleeve 25pcs/sleeve S108T02F S208T02FI FT [mA](V D =6V, R L =30Ω)MAX.8400MAX.8600V DRM [V]Please contact a local SHARP sales representative to see the actual status of the production.■ Model Line-up (1) (Lead-free terminal components)■ Model Line-up (2) (Lead solder plating components)Shipping PackageModel No.Sleeve 25pcs/sleeve S108T02S208T02I FT [mA](V D =6V, R L =30Ω)MAX.8400MAX.8600V DRM [V]F o r w a r d c u r r e n t I F (m A )Ambient temperature T a (˚C)060−2502550751001255040302010Fig.1 Forward Current vs. AmbientTemperatureFig.2 RMS ON-state Current vs.Ambient TemperatureF o r w a r d c u r r e n t I F (m A )Forward voltage V F (mA)1010.1100Fig.4 Forward Current vs. Forward VoltageFig.3 RMS ON-state Current vs.Case TemperatureR M S O N -s t a t e c u r r e n t I T (r m s )(A )Case temperature T C (°C)010−25255075100125987654321R M S O N -s t a t e c u r r e n t I T (r m s )(A )Ambient temperature T a (˚C)0987654321−25100755025125(1)(2)(3)(4)(5)(1)With infinite heat sink(2)With heat sink (200×200×2mm Al plate)(3)With heat sink (100×100×2mm Al plate)(4)With heat sink (50×50×2mm Al plate)(5)Without heat sink(N ote)In natural cooling condition, please locate Al platevertically, spread the thermal conductive silicone grease on the touch surface of the device and tighten up the device in the center of Al plate at the torque of 0.4N•m.Fig.8-b Repetitive Peak OFF-state Current vs.Ambient Temperature (S208T02)Fig.8-a Repetitive Peak OFF-state Current vs.Ambient Temperature (S108T02)R e p e t i t i v e p e a k O F F -s t a t e c u r r e n t I D R M (A )Ambient temperature T a (˚C)10−910−310−410−510−610−710−8R e p e t i t i v e p e a k O F F -s t a t e c u r r e n t I D R M (A )Ambient temperature T a (˚C)10−910−310−410−510−610−710−8Remarks : Please be aware that all data in the graph are just for reference.Fig.5 Surge Current vs. Power-on CycleFig.6 Minimum Trigger Current vs.Ambient TemperatureFig.7 Maximum ON-state Power Dissipationvs. RMS ON-state CurrentM i n i m u m t r i g g e r c u r r e n t I F T (m A )Ambient temperature T a (°C)0108642S u r g e c u r r e n t I s u r g e (A )Power-on cycle (Times)10080604020120M a x i m u m O N -s t a t e p o w e r d i s s i p a t i o n (W )RMS ON-state current I T (rms)(A)010864297531■ Design ConsiderationsIn order for the SSR to turn off, the triggering current (l F ) must be 0.1mA or less.When the input current (I F ) is below 0.1mA, the output Triac will be in the open circuit mode. However, if the voltage across the Triac, V D , increases faster than rated dV/dt, the Triac may turn on. To avoid this situation, please incorporate a snubber circuit. Due to the many different types of load that can be driven, we can merely recommend some circuit vales to start with : Cs=0.022µF and Rs=47Ω. The operation of the SSR and snubber circuit should be tested and if unintentional switching occurs, please adjust the snubber circuit component values accordingly.When making the transition from On to Off state, a snubber circuit should be used ensure that sudden drops in current are not accompanied by large instantaneous changes in voltage across the Triac.This fast change in voltage is brought about by the phase difference between current and voltage. Primarily, this is experienced in driving loads which are inductive such as motors and solenoids. Following the procedure outlined above should provide sufficient results. For over voltage protection, a Varistor may be used.Any snubber or Varistor used for the above mentioned scenarios should be located as close to the main out-put triac as possible.Particular attention needs to be paid when utilizing SSRs that incorporate zero crossing circuitry.If the phase difference between the voltage and the current at the output pins is large enough, zero crossing type SSRs cannot be used. The result, if zero crossing SSRs are used under this condition, is that the SSR may not turn on and off irregardless of the input current. In this case, only a non zero cross type SSR should be used in combination with the above mentioned snubber circuit selection process.The load current should be within the bounds of derating curve. (Refer to Fig.2) Also, please use the optional heat sink when necessary.In case the optional heat sink is used and the isolation voltage between the device and the optional heat sink is needed, please locate the insulation sheet between the device and the heat sink.When the optional heat sink is equipped, please set up the M3 screw-fastening torque at 0.3 to 0.5N•m.In order to dissipate the heat generated from the inside of device effectively, please follow the below sugges-tions.● Design guide● Recommended Operating ConditionsParameterS108T02S208T02Symbol Unit InputOutputInput signal current at ON state Input signal current at OFF state Load supply voltage Load supply currentFrequencyOperating temperatureI F (ON)I F (OFF)V OUT (rms)I OUT (rms)f T oprmA mA V mA Hz ˚C−−−Locate snubber circuit between output terminals(Cs =0.022µF, Rs =47Ω)−−Conditions(∗) See Fig.2 about derating curve (I T (rms) vs. ambient temperature).16080800.147−20240.1120240I T (rms)×80%(∗)6380MIN.MAX.✩ For additional design assistance, please review our corresponding Optoelectronic Application Notes.● Standard CircuitV +V S108T02● DegradationIn general, the emission of the IRED used in SSR will degrade over time.In the case where long term operation and / or constant extreme temperature fluctuations will be applied to the devices, please allow for a worst case scenario of 50% degradation over 5years.Therefore in order to maintain proper operation, a design implementing these SSRs should provide at least twice the minimum required triggering current from initial operation.(a) Make sure there are no warps or bumps on the heat sink, insulation sheet and device surface.(b) Make sure there are no metal dusts or burrs attached onto the heat sink, insulation sheet and device sur-face.(c) Make sure silicone grease is evenly spread out on the heat sink, insulation sheet and device surface.Silicone grease to be used is as follows;1) There is no aged deterioration within the operating temperature ranges.2) Base oil of grease is hardly separated and is hardly permeated in the device.3) Even if base oil is separated and permeated in the device, it should not degrade the function of a device. Recommended grease : G-746 (Shin-Etsu Chemical Co., Ltd.): G-747 (Shin-Etsu Chemical Co., Ltd.): SC102 (Dow Corning Toray Silicone Co., Ltd.) In case the optional heat sink is screwed up, please solder after screwed.In case of the lead frame bending, please keep the following minimum distance and avoid any mechanical stress between the base of terminals and the molding resin.Some of AC electromagnetic counters or solenoids have built-in rectifier such as the diode.In this case, please use the device carefully since the load current waveform becomes similar with rectangu-lar waveform and this results may not make a device turn off.■ Manufacturing Guidelines● Soldering MethodFlow Soldering (No solder bathing)Flow soldering should be completed below 260˚C and within 10s.Preheating is within the bounds of 100 to 150˚C and 30 to 80s.Please solder within one time.Other noticesPlease test the soldering method in actual condition and make sure the soldering works fine, since the impact on the junction between the device and PCB varies depending on the tooling and soldering conditions.分销商库存信息:SHARP-MICROELECTRONICSS108T02S108T02F S208T02。
Schurter PG06 电源入口模块及线滤波器说明书
1IEC Appliance Inlet C14 with Filter, Fuseholder 2-pole, Line Switch 2-poleAluminum Nickel plated steelApprovals and CompliancesC1470° CDescription - Panel Mount :Screw-on mounting from front side - 4 Functions :Appliance Inlet Protection class I , Line Switch 2-pole , Fuseholder for fuse-links 5 x 20 mm 2-pole , Line filter in standard and medical ver-sion- Quick connect terminals 6.3 x 0.8 mmCharacteristics- Compact design with optimal shielding - All single elements are already wired- Plug removal necessary for fuse-link replacement - With EMC-shield- Suitable for use in equipment according to IEC/UL 60950Suitable for use in medical equipment according to IEC/UL 60601-1Other versions on request- Medical version M80Weblinkspdf datasheet , html-datasheet , General Product Information , Distributor-Stock-Check , Accessories , Detailed request for productT echnical DataRatings IEC1 - 10 A @ Ta 40 °C / 250 VAC; 50 Hz Ratings UL/CSA 1 - 10 A @ Ta 40 °C / 125 VAC; 60 Hz Leakage Current standard < 0.25 mA (250 V / 60 Hz) medical < 5 µA (250 V / 60 Hz)Dielectric Strength> 1.7 kVDC between L-N > 2.7 kVDC between L/N-PE Test voltage (2 sec)Allowable Operation Tempe-rature-25 °C to 85 °CClimatic Category 25/085/21 acc. to IEC 60068-1IP-Protection from front side IP 40 acc. to IEC 60529Protection Class Suitable for appliances with protection class I acc. to IEC 61140TerminalQuick connect terminals 6.3 x 0.8 mm Panel Thickness S Screw: max 8 mmMounting screw torque max 0.5 Nm Material: HousingThermoplastic, black, UL 94V-0appliance inlet/-outletC14 acc. to IEC 60320-1,UL 498, CSA C22.2 no. 42 (for cold conditions) pin-temperature 70 °C, 10 A, Protection Class IFuseholder2-pole, Shocksafe category PC2 acc. to IEC 60127-6,for fuse-links 5 x 20 mm Rated Power Acceptance @ Ta 23 °C5 x 20: 1.6 W (2-pole)Power Acceptance @ Ta > 23°C Admissible power acceptance at higher ambient temperature see derating cur-vesLine Switch2-pole, non-illuminated, acc. to IEC 61058-1Technical DetailsLine FilterStandard and Medical Version, IEC 60939, UL 1283, CSA C22.2 no. 8 Technical DetailsMTBF> 1'700'000 h acc. to MIL-HB-217 FApprovals and CompliancesDetailed information on product approvals, code requirements, usage instructions and detailed test conditions can be looked up in Details about ApprovalsApprovalsThe approval mark is used by the testing authorities to certify compliance with the safety requirements placed on electronic products. Approval Reference T ype: FKIApproval LogoCertificates Certification Body DescriptionVDE Approvals VDE Certificate Number: 40004665UL ApprovalsULUL File Number: E72928Product standardsProduct standards that are referencedOrganization Design StandardDescriptionDesigned according to IEC 60320-1Appliance couplers for household and similar general purposesDesigned according to IEC 60939Passive filters for suppressing electromagnetic interferenceDesigned according to IEC 60127-6Miniature fuses. Part 6. Fuse-holders for miniature fuse-linksDesigned according to IEC 61058-1Switches for appliances. Part 1. General requirements Designed according to UL 498Standard for Attachment Plugs and ReceptaclesDesigned according to UL 1283Electromagnetic interference filtersDesigned according to CSA C22.2 no. 42General Use Receptacles, Attachment Plugs, and Similar Wiring DevicesDesigned according to CSA C22.2 no. 8Electromagnetic interference (EMI) filters Application standardsApplication standards where the product can be usedOrganization Design StandardDescriptionDesigned for applications acc.IEC/UL 60950IEC 60950-1 includes the basic requirements for the safety of informationtechnologyequipment.Designed for applications acc.IEC 60601-1Medical electrical equipment - Part 1: General requirements for basicsafety and essential performanceDesigned for applications acc.IEC 60335-1Safety of electrical appliances for household and similar purposes. Meetsthe requirements for appliances in unattended use. This includes the en-hanced requirements of glow wire tests acc. to IEC 60695-2-12 and -13. CompliancesThe product complies with following Guide LinesIdentification Details Initiator DescriptionCE declaration of conformity SCHURTER AG The CE marking declares that the product complies with the applicablerequirements laid down in the harmonisation of Community legislation onits affixing in accordance with EU Regulation 765/2008.RoHS SCHURTER AG EU Directive RoHS 2011/65/EUChina RoHS SCHURTER AG The law SJ / T 11363-2006 (China RoHS) has been in force since 1 March2007. It is similar to the EU directive RoHS.REACH SCHURTER AG On 1 June 2007, Regulation (EC) No 1907/2006 on the Registration,Evaluation, Authorization and Restriction of Chemicals 1 (abbreviated as"REACH") entered into force.Medical Equipment SCHURTER AG Suitable for use in medical equipment according to IEC/UL 60601-1 Dimension [mm]Case 4523Case 50Diagrams Standard versionNLN’PE’L’1)2)R = 1M Ω1) Line2) only FKI 3) LoadMedical version (M5)NPELN’PE’L’1)2)1) Line 2) only FKI 3) Load4Derating Curves 2-poleA d m i s s i b l e p o w e r a c c e p t a n c e i n W a t tAmbient air temperature T a°CAttenuation Loss- - - - 50Ω differential mode _____ 50Ω common modeStandard version1 A2 A 4 A 6 A10 AMedical version (M5)1 A2 A 4 A 6 A10 AAll VariantsPackaging unit 10 Pcs AccessoriesDescriptionAssorted CoversRear Cover0859.0074Mating Outlets/ConnectorsCategory / DescriptionAppliance Outlet Overview completeIEC Appliance Outlet F, Screw-on Mounting, Front Side, Solder Terminal4787IEC Appliance Outlet F, Snap-in Mounting, Front Side, Solder or Quick-connect Terminal4788IEC Appliance Outlet F or H, Screw-on Mounting, Front Side, Solder, PCB or Quick-connect Terminal5091Appliance Outlet further types to FKI5Connector Overview complete4782 Mounting: Power Cord, 3 x 1 mm² / 3 x 18 AWG, Cable, Connector: IEC C1347824022 Mounting: Power Supply Cord, 3 x 1.5 mm², Screw clamps, Connector: IEC C1340224785 Mounting: Power Cord, 3 x 1 mm² / 3 x 18 AWG, Cable, Connector: IEC C1347854300-06 Mounting: Power Cord, 3 x 1 mm² / 3 x 18 AWG, Cable, Connector: IEC C134300-064012 Mounting: Power Supply Cord, 3 x 1.5 mm², Screw clamps, Connector: IEC C134012Connector further types to FKI...The specifications, descriptions and illustrations indicated in this document are based on currentinformation. All content is subject to modifications and amendments. Information furnished is believed2.12.2176。
IC datasheet pdf-CAT3606 pdf,datasheet
CAT36066-Channel Low Noise Charge Pump White LED DriverDescriptionThe CAT3606 controls up to four LEDs for the main display and two LEDs for the sub-display in cellular phones. The device is capable of operating in either 1x (LDO) mode or 1.5x charge pump mode. All LED pin currents are regulated and tightly matched to achieve uniformity of brightness across the LCD backlight. An external resistor (R SET) sets the nominal output current.The device can deliver as much as 20 mA per channel during low voltage operation (3 V), and 30 mA per channel during nominal operation (3.3 V). A constant high-frequency switching scheme (1MHz) provides low noise and allows the use of very small value ceramic capacitors.A “zero” quiescent current mode can be achieved via the chip enable pin EN. The Main and Sub LEDs each have their own dedicated ON/OFF control pins ENM, ENS. Dimming can be achieved using either a DC voltage to control the R SET pin current, or by applying a PWM signal on the ENM and ENS pins.The device is available in a 16−pad TQFN package with a max height of 0.8 mm.Features•Drives up to 4 Main LEDs and 2 Sub LEDs•Separate Control for Main and Sub LEDs •Compatible with Supply V oltage of 3 V to 5.5 V•Power Efficiency up to 90%•Output Current up to 30 mA per LED•High−frequency Operation at 1 MHz•2 Modes of Operation 1x and 1.5x•White LED Detect Circuitry on All Channels •Shutdown Current less than 1 m A•Small Ceramic Capacitors•Soft Start and Current Limiting•Short Circuit Protection•16−pad TQFN Package, 0.8 mm Max Height•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS CompliantApplications•Cell Phone Main and Sub−display Backlight•Navigation •PDAs •Digital CamerasTQFN−16HV4 SUFFIXCASE 510AEPIN CONNECTIONS (Note 1)G366MARKING DIAGRAMSDevice Package ShippingORDERING INFORMATIONCAT3606HV4−T2TQFN−16(Note 2)2,000/Tape & ReelG366 = CAT3606HV4−T2CDBB = CAT3606HV4−GT21.The “exposed pad” under the package must beconnected to the ground plane on the PCB.2.Matte−Tin Plated Finish (RoHS−compliant).3.NiPdAu Plated Finish (RoHS−compliant).LED5LED4LED3LED2LED1C2+C2−C1−LED6ENENMENSRSETVOUTVINC1+1(4 x 4 mm) (Top View)CDBBCAT3606HV4−GT2TQFN−16(Note 3)GNDFigure 1. Typical Application Circuitm FLi −OUT Table 1. PIN DESCRIPTIONPin #Name Function1LED6LED6 cathode terminal2EN Enable/shutdown input, active high3ENM Enable “main” input for LED1 to LED4, active low 4ENS Enable “sub” input for LED5 and LED6, active low5RSET The LED output current is set by the current sourced out of the RSET pin 6VOUT Charge pump output connected to the LED anodes 7VIN Supply voltage8C1+Bucket capacitor 1 terminal 9C1Bucket capacitor 1 terminal 10C2Bucket capacitor 2 terminal 11C2+Bucket capacitor 2 terminal 12LED1LED 1 cathode terminal 13LED2LED 2 cathode terminal 14LED3LED 3 cathode terminal 15LED4LED 4 cathode terminal 16LED5LED 5 cathode terminal PADGNDGround referenceTable 2. ABSOLUTE MAXIMUM RATINGSParameter Rating Unit VIN, VOUT, LEDx voltage−0.3 to 7.0V EN, ENM, ENS voltage−0.3 to VIN V RSET voltage−0.3 to VIN V RSET current±1mA Ambient Temperature Range−40 to +85_C Storage Temperature Range−65 to +160_C Lead Temperature300_C ESD Rating HBM (Human Body Model)2,000V ESD Rating MM (Machine Model) (Note 4)200V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.4.Machine model is with 200 pF capacitor discharged directly into each pin.Table 3. RECOMMENDED OPERATING CONDITIONSParameter Range Unit VIN 3.0 to 5.5V Ambient Temperature Range−40 to +85_C Input/Output/Bucket Capacitors 1 ±20% Typical m FI LED per LED pin0 to 30mAI OUT Total Output Current0 to 150mA Table 4. ELECTRICAL OPERATING CHARACTERISTICS(Limits over recommended operating conditions unless specified otherwise. Typical values at T A = 25°C, V IN = 3.5 V, I RSET = 5 m A.) Symbol Parameter Conditions Min Typ Max UnitI Q Quiescent Current V EN= 0 V1x Mode, No Load1.5x Mode, No Load 0.10.32.6115m AmAmAV RSET RSET Regulated Voltage 1.17 1.2 1.23VI LED Programmed LED Current I RSET = 5 m AI RSET = 37 m AI RSET = 78 m A 2.415.030.0mAI LED LED Current Range with 6 LEDs 3.3 ≤ VIN ≤ 4.5 V3.0 ≤ VIN ≤4.5 V 3020mAI LED LED Current Range with 4 LEDs 3.3 ≤ VIN ≤ 4.5 V30mAI LED−ACC LED Current Accuracy0.5 mA ≤ I LED≤ 3 mA3 mA ≤ I LED≤ 30 mA ±15±5%I LED−DEV LED Channel Matching(I LED – I LEDAVG) / I LEDAVG±3%R OUT Output Resistance(Open Loop)1x Mode,1.5x Mode, I OUT = 100 mA1.46.52.510Wf OSC Charge Pump Frequency0.8 1.0 1.3MHz T DROPOUT1x to 1.5x Mode Transition Dropout Delay0.40.60.9ms I EN−CTR Input Leakage Current On Inputs EN, ENM, ENS1m AV EN−CTR High Detect ThresholdLow Detect Threshold On Inputs EN, ENM, ENS0.40.80.71.3VI SC Input Current Limit VOUT = GND304560mA I LIM Maximum Input Current VOUT > 1 V200400600mABlock DiagramFigure 2. CAT3606 Functional Block Diagramm FVBasic OperationAt power-up, the CA T3606 starts operation in 1x mode. If it is able to drive the programmed LED current, it continues in 1x mode. If the battery voltage drops to a level where the LED current cannot be met, the driver automatically switches into 1.5x mode, to boost the output voltage high enough to achieve the nominal LED current.The above sequence is reinitialized each and every time the chip is powered up or is taken out of shutdown mode (via EN pin). The use of the Main and Sub display enable pins (ENM or ENS) does not affect the mode of operation. LED Current SettingThe LED current is set by the external resistor R SET connected between the RSET pin and ground. Table 5 lists various LED currents and the associated R SET resistor value for standard 1% precision surface mount resistors.Table 5. RSET Resistor SelectionLED Current (mA)R SET (k W)1649228751021049.91532.42023.73015.4The enable lines ENM and ENS allow to turn On or Off a group of LEDs as shown in Table 6.Table 6. LED SelectionControl Lines LED Outputs EN ENM ENSMainLED1 − LED4SubLED5 −LED6 0X X––111––101ON−110−ON100ON ON NOTES:1 = logic high (or VIN)0 = logic low (or GND)– = LED output OFFX = don’t careThe unused LED channels can also be turned off by connecting the respective LED pins to VOUT. In which case, the corresponding LED driver is disabled and the typical LED sink current is only about 0.2 mA. When the following equation is true on any channel, the driver turns off the LED channel:VOUT*V LED v1V(LED channel OFF) Note: The CA T3606 is designed to drive LEDs with forward voltage greater than 1 V and is not compatible with resistive loads.Figure 3. Efficiency vs. Input Voltage(6 LEDs)Figure 4. Efficiency vs. Total LED Current(6 LEDs)INPUT VOLTAGE (V)TOTAL LED CURRENT (mA)405060708090100405060708090100Figure 5. LED Current vs. Input VoltageFigure 6. LED Current Change vs.TemperatureINPUT VOLTAGE (V)TEMPERATURE (°C)−−−0.51.5−−Figure 7. Ground Current vs. Input Voltage(1x Mode)Figure 8. Ground Current vs. Temperature(1x Mode)INPUT VOLTAGE (V)TEMPERATURE (°C)0.10.20.30.40.500.10.20.30.40.5E F F I C I E N C Y (%)E F F I C I E N C Y (%)L E D C U R R E N T C H A N G E (%)L E D C U R R E N T C H A N G E (%)G R O U N D C U R R E N T (m A )G R O U N D C U R R E N T (m A )01.0−−Figure 9. Ground Current vs. Input Voltage(1.5x Mode)Figure 10. Supply Current vs. Input VoltageINPUT VOLTAGE (V)INPUT VOLTAGE (V)134580120140Figure 11. Oscillator Frequency vs. InputVoltageFigure 12. Oscillator Frequency vs.TemperatureINPUT VOLTAGE (V)TEMPERATURE (°C)0.900.951.001.051.100.900.951.001.051.10Figure 13. Output Resistance vs. Input Voltage(1x Mode)Figure 14. Output Resistance vs. Input Voltage(1.5x Mode)INPUT VOLTAGE (V)INPUT VOLTAGE (V)1234246810G R O U N D C U R R E N T (m A )G R O U N D C U R R E N T (m A )C L O C K F R E Q U E N C Y (M H z )C L O C K F R E Q U E N C Y (M H z )O U T P U T R E S I S T A N C E (W )O U T P U T R E S I S T A N C E (W )2100Figure 15. Switching Waveforms in 1.5x Mode Figure 16. Operating Waveforms in 1x Mode400 nsec/div400 nsec/divCurrent Input 50mV/VIN 50mV/divVOUT Input 50mV/div VIN Figure 17. Power Up 6 LEDs at 15 mA,VIN = 3 V (1.5x Mode)Figure 18. Power Up 6 LEDs at 15 mA,VIN = 3.6 V (1x Mode)400 m sec/div400 m sec/div2V/divVOUT 2V/div EN 2V/divVOUT 100mA/divInput 2V/divEN Figure 19. LED Current vs. R SETFigure 20. Line Transient Responsein 1x ModeRSET (k W )200 m sec/div10,000100100.1101002V/div VOUT 5mA/div Input 1V/div3.6V to4.9VVinL E D C U R R E N T (m A )10mA/Input Current 100mA/divAC coupledCurrent 10mA/div AC coupledAC coupledVOUT 50mV/divdiv divCurrent Current 10001(V IN = 3.6 V, EN = V IN , ENM = ENS = GND, C IN = C OUT = 1 m F, T AMB = 25°C, unless otherwise specified.)Figure 21. Foldback Current Limiting OUTPUT CURRENT (mA)5004003002001000012345O U TP U T V O L T A G E (V )1x ModeFigure 22. RSET Pin Voltage vs. Temperature−50−2502550751001251.161.181.201.221.24R S E T P I N V O L T A G E (V )Figure 23. PWM Dimming at 1 kHz on ENM and ENS50mA/divCurrent Tot. LED 1V/divVOUT ENM & ENS5V/div200 m sec/divTEMPERATURE (°C)Recommended LayoutWhen the driver is in the 1.5x charge pump mode, the 1MHz switching frequency operation requires to minimize trace length and impedance to ground on all 4 capacitors. A ground plane should cover the area on the bottom side of the PCB opposite to the IC and the bypass capacitors.Capacitors Cin and Cout require short connection to ground which can be done with multiple vias as shown on Figure 24.A square copper area matches the QFN16 exposed pad (GND) and must be connected to the ground plane underneath. The use of multiple via will improve the heat dissipation.Figure 24. PCB LayoutPACKAGE DIMENSIONSTQFN16, 4x4CASE 510AE−01ISSUE AA3A1SIDE VIEWTOP VIEW BOTTOM VIEWDETAIL AFRONT VIEWNotes:(1) All dimensions are in millimeters.(2) Complies with JEDEC MO-220.SYMBOL MIN NOM MAXA0.700.750.80A10.000.020.05A30.20 REFb0.250.300.35D 3.90 4.00 4.10D2 2.00−−− 2.25E 4.00E2 2.00−−− 2.25e3.900.65 BSC4.10L0.45−−−0.65CAT3606Example of Ordering Information (Note 7)PrefixDevice #Suffix 5.All packages are RoHS −compliant (Lead −free, Halogen −free).6.The standard lead finish is NiPdAu.7.The device used in the above example is a CAT3606HV4−GT2 (TQFN, NiPdAu Plated Finish, Tape & Reel, 2,000/Reel).8.For Matte −Tin package option, please contact your nearest ON Semiconductor Sales office.9.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。
IC datasheet pdf-THS5661A,pdf(12-Bit, 125 MSPS, CommsDAC Digital-to-Analog Converter)
THS5661A 12ĆBIT, 125 MSPS, CommsDAC DIGITALĆTOĆANALOG CONVERTER
D Member of the Pin-Compatible D D D D D D D D D D
CommsDAC Product Family 125 MSPS Update Rate 12-Bit Resolution Spurious Free Dynamic Range (SFDR) to Nyquist at 40 MHz Output: 60 dBc 1 ns Setup/Hold Time Differential Scalable Current Outputs: 2 mA to 20 mA On-Chip 1.2 V Reference 3 V and 5 V CMOS-Compatible Digital Interface Straight Binary or Twos Complement Input Power Dissipation: 175 mW at 5 V, Sleep Mode: 25 mW at 5 V Package: 28-Pin SOIC and TSSOP
Copyright 2002, Texas Instruments Incorporated
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLAS247B − NOVEMBER 1999 REVISED SEPTEMBER 2002
THS5661A 12ĆBIT, 125 MSPS, CommsDAC DIGITALĆTOĆANALOG CONVERTER
AD9608 Datasheet说明书
ADI 中文版数据手册是英文版数据手册的译文，敬请谅解翻译中可能存在的语言组织或翻译错误，ADI 不对翻译中存在的差异或由此产生的错误负责。
如需确认任何词语的准确性，请参考ADI 提供的最新英文版数据手册。
10位、125/105 MSPS 、1.8 V双通道模数转换器(ADC)AD9608Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Speci cations subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.功能框图VIN+A VIN–AVREF SENSE VCM RBIAS VIN–BVIN+BORA D0A D9A DCOA DRVDDORB D9B D0B DCOBSDIO AGNDAVDDSCLK SPIPROGRAMMING DATAM U X O P T I O NPDWN DFS CLK+CLK–MODE CONTROLSDCS DUTY CYCLE STABILIZER SYNC DIVIDE 1TO 8OEBCSBREF SELECTADCC M O S /L VD S O U T P U T B U F FE RADCC M O S /L VD S O U T P U T B U F FE RAD9608NOTES1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES.09977-001图1.1 该产品受美国专利保护。
IC datasheet pdf-ADS8410,pdf (16-Bit, 2-MSPS, LVDS Serial Interface, SAR ADC)(1)
BurrĆBrown Productsfrom TexasInstrumentsFEATURES APPLICATIONSDESCRIPTIONADS8410SLAS493–OCTOBER200516-BIT,2-MSPS,LVDS SERIAL INTERFACE,SAR ANALOG-TO-DIGITAL CONVERTER•Medical Instrumentation•2-MHz Sample Rate•HIgh-Speed Data Acquisiton Systems•16-Bit Resolution•High-Speed Close-Loop Systems•SNR87.5dB at10kHz I/P•Communication•THD–98dB at10kHz I/P•±1LSB Typ,±2.5LSB INL Max•+0.8/–0.5LSB Typ,+1.5/–1LSB DNL MaxThe ADS8410is a16-bit,2-MSPS,analog-to-digital •Unipolar Differential Input Range:0V(A/D)converter with4-V internal reference.The to4V device includes a capacitor based SAR A/D converter •Internal Reference with inherent sample and hold.•Internal Reference Buffer The ADS8410also includes a200-Mbps,LVDS,serial interface.This interface is designed to support •200-Mbps LVDS Serial Interfacedaisy chaining or cascading of multiple devices.A •Optional200-MHz Internal Interface Clockselectable16-/8-bit data frame mode enables the use •16-/8-Bit Data Frame of a single shift register chip(SN65LVDS152)for •Zero Latency at Full Speed converting the data to parallel format.•Power Dissipation:290mW at2MSPS The ADS8410unipolar single-ended input rangesupports a differential input swing of0V to+V ref.•Nap Mode(125mW Power Dissipation)•Power Down(5µW)The nap feature provides substantial power savingwhen used at lower conversion rates.•48-Pin QFN PackageThe ADS8410is available in a48-pin QFN package.High-Speed SAR Converter FamilyType/Speed500kHz~600kHz750kHZ1MHz 1.25MHz2MHz3MHz4MHzADS8383ADS838118-Bit Pseudo-DiffADS8380(S)18-Bit Pseudo-Bipolar,Fully Diff ADS8382(S)ADS841116-Bit Pseudo-Diff ADS8370(S)ADS8371ADS8401/05ADS8410(S-LVDS)ADS841216-Bit Pseudo-Bipolar,Fully Diff ADS8372(S)ADS8402/06ADS8413(S-LVDS)14-Bit Pseudo-Diff ADS7890(S)ADS789112-Bit Pseudo-Diff ADS7881Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2005,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.CSTARTSYNC_O, CLK_O, SDO SYNC_I, CLK_I, SDICONVST BUS BUSY RD BUSY CSLAT_Y/N BYTE,MODE_C/D,CLK_I/E, PD, NAPABSOLUTE MAXIMUM RATINGSADS8410SLAS493–OCTOBER 2005ORDERING INFORMATION (1)MAXIMUM MAXIMUM NO MISSING TRANSPORT INTEGRAL DIFFERENTIAL CODES AT PACKAGE PACKAGE TEMPERATUREORDERING MODELMEDIA LINEARITY LINEARITY RESOLUTIONTYPE DESIGNATORRANGEINFORMATION QUANTITY(LSB)(LSB)(BIT)ADS8410IBRGZT 25048pin –40°C ADS8410lB ±2.51.5/–116RGZQFN to 85°C ADS8410IBRGZR 2000ADS8410IRGZT 25048pin –40°C ADS8410l ±43/–116RGZQFNto 85°CADS8410IRGZR2000(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI website at .over operating free-air temperature range (unless otherwise noted)(1)UNIT+IN to AGND –0.3V to +VA +0.3V -IN to AGND –0.3V to +0.3V +VA to AGND –0.3to 7V +VBD to BDGND–0.3to 7VDigital input voltage to GND –0.3V to (+VBD +0.3V)Digital output to GND –0.3V to (+VBD +0.3V)Operating temperature range –40°C to 85°C Storage temperature range –65°C to 150°CJunction temperature (T J max)150°C Power dissipation (T J Max –T A )/θJAQFN packageθJA Thermal impedance 86°C/W Vapor phase (60sec)215°C Lead temperature,soldering Infrared (15sec)220°C(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.2 SPECIFICATIONSADS8410 SLAS493–OCTOBER2005T A =–40°C to85°C,+VA=5V,+VBD=5V or3.3V,Vref=4.096V,fsample=2MHz(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITANALOG INPUTFull-scale input voltage span(1)+IN–(–IN)0V ref V+IN–0.2V ref+0.2 Absolute input voltage range V–IN–0.2+0.2C i Input capacitance25pFInput leakage current500pA SYSTEM PERFORMANCEResolution16BitsADS8410IB16No missing codes BitsADS8410I16ADS8410IB–2.5±1 2.5INL Integral linearity(2)LSB(3)ADS8410I–4.0±2.5 4.0ADS8410IB–10.8/–0.5 1.5DNL Differential linearity LSB(3)ADS8410I–1.0 1.5/–0.83ADS8410IB–0.75±0.10.75E O Offset error External reference mVADS8410I–1.5±0.75 1.5ADS8410IB–0.05±0.010.05E G Gain error(4)External reference%of FSADS8410I–0.15±0.050.15With common mode input signal=200CMMR Common-mode rejection ratio60dBmV p-p at1MHzPSRR Power supply rejection ratio At FFF0H output code80dB SAMPLING DYNAMICS+VBD=5V360391 Conversion time ns+VBD=3V391+VBD=5V100Acquisition time ns+VBD=3V100Maximum throughput rate with or without latency 2.0MHzAperture delay20nsAperture jitter10psecStep response50nsOvervoltage recovery50ns DYNAMIC CHARACTERISTICSV IN0.5dB below FS at10kHz–98THD Total harmonic distortion(5)dBV IN0.5dB below FS at100kHz–92.5V IN0.5dB below FS at10kHz87.5SNR Signal-to-noise ratio dBV IN0.5dB below FS at100kHz86V IN0.5dB below FS at10kHz87SINAD Signal-to-noise and distortion dBV IN0.5dB below FS at100kHz85V IN0.5dB below FS at10kHz–101SFDR Spurious free dynamic range dBV IN0.5dB below FS at100kHz–93–3dB Small signal bandwidth37.5MHz EXTERNAL REFERENCE INPUTInput voltage range,V REF 3.9 4.096 4.2VResistance(6)To internal reference voltage500kΩ(1)Ideal input span;does not include gain or offset error.(2)This is endpoint INL,not best fit.(3)Least significant bit(4)Measured relative to actual measured reference.(5)Calculated on the first nine harmonics of the input frequency.(6)Can vary±20%3ADS8410SLAS493–OCTOBER 2005SPECIFICATIONS (continued)T=–40°C to 85°C,+VA =5V,+VBD =5V or 3.3V,V =4.096V,f =2MHz (unless otherwise noted)(7)All min max values ensured by design.4TIMING REQUIREMENTSADS8410 SLAS493–OCTOBER2005SPECIFICATIONS(continued)T A =–40°C to85°C,+VA=5V,+VBD=5V or3.3V,Vref=4.096V,fsample=2MHz(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITRECEIVERV ITH+Positive going differential voltage threshold50mV V ITH-Negative going differential voltage threshold–50V IC Common mode input voltage0.2 1.2 2.2V C I Input capacitance5pFT A =–40°C to85°C,+VA=5V,+VBD=5V or3.3V(unless otherwise noted)5ADS8410SLAS493–OCTOBER 2005TIMING REQUIREMENTS (continued)T=–40°C to 85°C,+VA =5V,+VBD =5V or 3.3V (unless otherwise noted)6DEVICE INFORMATION123456789101112131415161718192021222324363534333231302928272625373839404142434445464748A G N DC L K _I +(M 2+) S D I +(M 1 +) S Y N C _I +C S T A R T +A G N D+V A A G N DAGND +VA AGND −IN +IN AGND +VA NC REFOUTREFIN C SC O N V S TB Y T EP DN A PC L K _I /EL A T _Y /NA G N D+V AR E F MR E F MBUS_BUSY RD BUSY BDGND +VBD SDO −+VANC − No internal connection+VA AGNDC S T A R T −(M 1 −) S Y N C _I −(M 2−) S D I −C L K _I −CLK_O −CLK_O +SDO +SYNC_O −SYNC_O +M O D E _C /DADS8410SLAS493–OCTOBER 2005RGZ PACKAGE (TOPVIEW)TERMINAL FUNCTIONSTERMINAL I/ODESCRIPTION ANALOG PINS11,12REFM I Reference ground.Connect to analog ground plane.Reference (positive)input.Decouple with REFM pin using 0.1-µF bypass capacitor and 1-µF storage 13REFIN I capacitor.Internal reference output.Short to REFIN pin when the internal reference is used.Do not connect to 14REFOUT O the REFIN pin when an external reference is used.Always decouple with AGND using a 0.1-µF bypass capacitor.18+IN I Noninverting analog input channel19–INIInverting analog input channel (supports ±0.2V i/p range)LVDS I/O PINS (1)Device sample and convert control input.Device enters sample phase with the rising edge of28,CSTART+ICSTART and the conversion phase starts with the falling edge of CSTART (provided other conditions 29CSTART–are satisfied).Set CSTART =0when the CONVST input is used.(1)All LVDS inputs and outputs are differential with signal+and signal–lines.Whenever only the 'signal'is mentioned it refers to the signal+line and the signal–line is the compliment.For example CLK_O refers to CLK_O+and CLK_O is the compliment.7ADS8410SLAS493–OCTOBER 2005DEVICE INFORMATION (continued)TERMINAL FUNCTIONS (continued)TERMINAL I/O DESCRIPTIONNO.NAME I SYNC_I +Connect to previous device SYNC_O with same polarity,while the device is selected to operate in Dasiy SYNC_I–daisy chain mode.Chain30,31Mode 1(valid in cascade mode only).CLK_O is available while M1=1(LVDS)or M1+is pulled up toM1+I+VBD and M1–is grounded (AGND).CLK_O o/p goes to 3-state when M1=0(LVDS)or M1+isM1–Cascadegrounded (AGND)and M1–is pulled up to +VBD.Do not allow these pins to float.I SDI+Serial data input.Connect to previous device SDO with same polarity,while the device is selected to Daisy SDI–operate in daisy chain mode.Chain32,Mode 2(valid in cascade mode only).Doubles LVDS o/p current while M2=1(LVDS)or M2+is33M2+I pulled up to +VBD and M2–is grounded (AGND).LVDS o/p current is normal (3.4mA typ)when M2M2–Cascade =0(LVDS)or M2+is grounded (AGND)and M2–is pulled up to +VBD.Do not allow these pins tofloat.34,CLK_I+I Serial external clock input.Set CLK_I/E (pin 7)=0to select an external clock source.35CLK_I–38,CLK_O–Serial clock out.Data is latched out on the rising edge of CLK_O and can be captured on the next O 39CLK_O+falling edge.40,SDO–O Serial data out.Data is latched out on the rising edge of CLK_O with MSB first format.41SDO+42,SYNC_O –OSynchronizes the data frame.(2)43SYNC_O +CMOS I/O PINS1CS I Chip select,active low signal.All of the LVDS o/p except CLK_O are 3-state if this pin is high.CMOS equivalent of CSTART input.So functionality is the same as the CSTART input.Set CONVST 2CONVST I =0when the CSTART input is used.Controls the data frame (2)duration.The frame duration is 16CLKs if BYTE =0or 8CLKs if BYTE =3BYTE I 1.4PD I Active low input,acts as device power down.Selects nap mode while high.Device enters the nap state at conversion end and remains so until the 5NAP I next acquisition phase begins.6MODE_C/D I Selects cascade (MODE_C/D =1)or daisy chain mode (MODE_C/D =0).Selects the source of the I/O clock.7CLK_I/E I CLK_I/E =1selects internally generated clock with 200-MHz typ frequency.CLK_I/E =0selects CLK_I as the I/O clock.Controls the data read with latency (LAT_Y/N =1)or without latency ((LAT_Y/N =0).It is essential to 8LAT_Y/N I set LAT_Y/N =0for the first device in daisy chain or cascade.46BUSY O Active high signal,indicates a conversion is in progress.Data read request to the device,also acts as a handshake signal for daisy chain and cascade 47RD I operation.Status output.Indicates that the bus is being used by the device.Connect to RD of the next device 48BUS_BUSYOfor daisy chain or cascade operation.POWER SUPPLY PINS10,16,21,22,+VA–Analog power supply and LVDS input buffer power supply.26,379,17,20,23,24,AGND–Analog ground pins.Short to the analog ground plane below the device.25,27,3644+VBD –Digital power supply for all CMOS digital inputs and CMOS LVDS outputs.45BDGND–Digital ground for all digital inputs and outputs.Short to the analog ground plane below the device.(2)The duration from the first rising edge of SYNC_O to the second rising edge of SYNC_O is one data frame.The data frame duration is 16CLKs if BYTE =0or 8CLKs if BYTE =1.8DETAILED DESCRIPTIONSAMPLE AND CONVERTADS8410SLAS493–OCTOBER 2005DEVICE INFORMATION (continued)TERMINAL FUNCTIONS (continued)TERMINAL I/ODESCRIPTIONNOT CONNECTED PINS15NC–No connection pinsTable 1.Device Configuration for Various Modes of OperationDEVICE PINS AND RECOMMENDED LOGIC LEVELSCOMMENTSREFERENCE FIGURES FOR OPERATION MODESAMPLINGFOR DATA MODE_C/D CLK_I/E LAT_Y/N M1+M1–M2+M2–ANDREAD CONVERSION+VBDAGND AGND +VBDSee Figures 3,411or 0Recommended configuration 1or 2and 5,6,8for or M1=1LVDS or M2=0LVDS more details Single deviceSet SYNC_I and SDI to logic 0See Figures 3,401or 0See commentsSee commentsor +terminal to AGND and –ve 1or 2and 5,6,7for terminal to +VBDmore details Set SYNC_I and SDI to logic 0Multiple 1st Device 01or 00See comments See comments or +terminal to AGND and –ve 1or 2See Figures devices terminal to +VBD3,4,11and 6,12in daisy for more details2nd To last Maximum 4devices supported chain001See comments See comments 1or 2device at 2MSPS with 200-MHz CLK+VBDAGNDAGND+VBD1st Device 1Multiple See Figures or M1=1LVDS or M2=0LVDS (1)devices Maximum 3devices supported 1or 23,4,14and 6,15inat 2MSPS+VBDAGNDAGND+VBDfor more details2nd To last cascade101deviceor M1=0LVDS or M2=0LVDS (1)(1)Specified polarity is suitable for a 100-Ωdifferential load across the LVDS outputs.However,polarity can be reversed to double the output current in order to support two 100-Ωloads on both ends of the transmission lines,resulting in 50-Ωnet load.The sampling and conversion process is controlled by the CSTART (LVDS)or CONVST (CMOS)signal.Both signals are functionally identical.The following diagrams show control with CONVST.The rising edge ofCONVST (or CSTART)starts the sample phase,if the conversion has completed and the device is in the wait state.Figure 2shows the case when the device is in the conversion phase at the rising edge of CONVST.In this case,phase starts immediately at the end of the conversion phase and there is no wait state.Figure 1.Sample and Convert With Wait (Less Than 2MSPS Throughput)9DATA READ OPERATIONDATA READ FOR A SINGLE DEVICE (See Table 1for Device Configuration)ADS8410SLAS493–OCTOBER 2005DETAILED DESCRIPTION (continued)Figure 2.Sample and Convert With No Wait or Back to Back (2MSPS Throughput)The device ends the sample phase and enters the conversion phase on the falling edge of CONVST (CSTART).A high level on the BUSY output indicates an ongoing conversion.The device conversion time is fixed.The falling edge of CONVST (CSTART)during the conversion phase aborts the ongoing conversion.A data read after a conversion abort fetches invalid data.Valid data is only available after a sample phase and a conversion phase has completed.The timing diagram for control with CSTART is similar to Figure 1and Figure 2.Table 2shows the equivalent timing for control with CONVST and CSTART.Table 2.CONVST and CSTART Timing ControlTIMING CONTROL WITH CONVSTTIMING CONTROL WITH CSTARTt w1t w3t w2t w4t d1t d5t d2t d6t d3t d7The ADS8410supports a 200-MHz serial LVDS interface for data read operation.The three signal LVDS interface (SDO,CLK_O,and SYNC_O)is well suited for high-speed data transfers.An application with a single device or multiple devices can be implemented with a daisy chain or cascade configuration.The following sections discuss data read timing when a single device is used.For a single device,there are two possible read cycle starts:a data read cycle start during a wait or sample phase or a data read cycle start at the end of a conversion phase.Read cycle end conditions can change depending on MODE C/D selection.Figure 3explains the data read cycle.The details of a read frame start with the two previous listed conditions and a read cycle end with MODE C/D selection are explained in Figure 5and Figure 6and Figure 7and Figure 8,respectively.10Figure3.Data Read With CS Low and BYTE=0As shown in Figure3,a new data read cycle is initiated with the falling edge of RD,if CS is low and the device is in a wait phase.The device releases the LVDS o/p(SYNC_O,SDO)from3-state and sets BUS_BUSY high at the start of the read cycle.The SYNC_O cycle is16clocks wide(rising edge to rising edge) if BYTE i/p is held low and can be used to synchronize a data frame.The clock count begins with the first CLK_O falling edge after a SYNC_O rising edge.The MSB is latched out on the second rising edge(2R)and each subsequent data bit is latched out on the rising edge of the clock.The receiver can shift data bits on the falling edges of the clock.The next rising edge of SYNC_O coincides with the16th rising edge of the clock.D0is latched out on the17th rising edge of the clock.The receiver can latch the de-serialized16-bit word on the18th rising edge(18R,or the second rising edge after a SYNC_O rising edge).CS high during a data read3-states SYNC_O and SDO.These signals remain in3-state until the start of the next data read cycle.DATA READ IN BYTE MODEByte mode is selected by setting BYTE=1;this mode is allowed for any condition listed in Table1.Figure4 shows a data read operation in byte mode.Figure4.Data Read Timing Diagram with CS Low and BYTE=1Similar to Figure3,a new data read cycle is initiated with the falling edge of RD,if CS is low and the device is in a wait or The device releases the LVDS o/p(SYNC_O,SDO)from3-state and sets BUS_BUSY high at the start of the read cycle.The SYNC_O cycle is8clocks wide(rising edge to rising edge)if BYTE i/p is held high and can be used to synchronize a data frame.The clock count begins with the first falling edge of CLK_O after the rising edge of SYNC_O.The MSB is latched out on the second rising edge(2R)and each subsequent data bit is latched out on the rising edge of the clock.The receiver can shift data bits on the falling edges of clock.The next rising edge of SYNC_O coincides with the8th rising edge of the clock.D8is latched out on the9th rising edge of the clock.The receiver can latch the de-serialized higher byte on the10th rising edge (10R,or second rising edge after a SYNC_O rising edge).The de-serialized lower byte can be latched on the 18th rising edge(18R).CS high during a data read3-states SYNC_O and SDO.These signals remain in3-state until the start of the next data read cycle.DATA READ CYCLE START DURING WAIT OR SAMPLE PHASEAs shown in Figure5,the falling edge of RD,with CS low and the device is in a wait or sample phase,triggers the start of a The cycle starts when BUS_BUSY goes high and SYNC_O and SDO are released from 3-state.SYNC_O is low at the start and rises to a high level t d13ns after the falling edge of RD.As shown in Figure5,the MSB is shifted on the2nd rising edge of the clock(2R).Other details about the data read cycle are in the previous section(see Figure3).Figure5.Start of Data Read Cycle with RD with CS Low and Device in Wait or Sample PhaseDATA READ CYCLE START AT END OF CONVERSION PHASE(Read Without Latency,Back-to-Back) This mode is optimized for a data read immediately after the end of a conversion phase and ensures the data read is complete before the sample end while running at2MSPS.Point A in Figure6indicates a 'pre_conversion_end';it occurs t d19ns before the falling edge of BUSY or[(t d2+t cnv+t d4d19ns after the falling edge of CONVST.A read cycle is initiated at point A if RD is issued before point A while CS is low. Alternately,RD and CS can be held low.At the start of the read cycle,BUS_BUSY rises to a high level and the LVDS outputs are released from3-state.The rising edge of SYNC_O occurs t d12ns after the conversion end.As shown in Figure6,the MSB is shifted on the2nd rising edge of the clock(2R).Other details about the data read cycle are in the previous section(see Figure3).Figure6.Start of Data Read Cycle with End of ConversionDATA READ CYCLE END(With MODE C/D=0)A data read cycle ends after all16bits have been serially latched out.Figure7shows the timing of the falling edge of BUS_BUSY and the rising edge of SYNC_O with respect to rises on the16th rising edge of CLK_O.As shown in Figure5and Figure6,the MSB is shifted out on the2nd rising edge of CLK_O. Therefore,the LSB-1is edge of CLK_O.CS = 0Figure7.Data Read Cycle End with MODE C/D=0DATA READ CYCLE END (With MODE C/D =1)CS = 0RESTRICTIONS ON READ CYCLE STARTThe next two rising edges of CLK_O are shown as 17R and 18R in Figure 7.On 17R the LSB is latched out,and on 18R SDO and SYNC_O go to 3-state.Note that BUS_BUSY d15before the rising edge of SYNC_O when MODE C/D =0.Care must be taken not to allow LVDS bus usage by any other device until the end of the read cycle or (t d15+2/f clk +t d16)ns after the falling edge of BUS_BUSY.A data read cycle ends after all 16bits have been serially latched out.Figure 8shows the timing of the falling edge of BUS_BUSY and the rising edge of SYNCO with respect to rises on the 16th rising edge of CLK_O.As shown in Figure 5and Figure 6,the MSB is shifted out on the 2nd rising edge of CLK_O.Therefore,the LSB-1is edge of CLK_O.Figure 8.Data Read Cycle End with MODE C/D =1The next two rising edges of CLK_O are shown as 17R and 18R in 17R the LSB is latched out and on 18R SDO and SYNC_O go to 3-state.In cascade mode (with =1),unlike daisy chain mode,the falling edge of BUS_BUSY occurs after the LVDS outputs are 3-stated.One can use the falling edge of BUS_BUSY to allow LVDS bus usage by any other device.Figure 9.Read Cycle Restriction RegionThe start of a data read cycle is not allowed in the region bound by t d23and t d24.Previous conversion results are available for a data read cycle start before this region,and current conversion results are available for a read cycle start after this region.MULTIPLE DEVICES IN DAISY CHAIN OR CASCADE DAISY CHAIN(Optional) Last_Device BUS_BUSY or ReceiverMultiple devices can be connected in either a daisy chain or cascade configuration.The following sections describe detailed timing diagrams and electrical connections.The ADS8410provides all of the handshake signals required for both of these modes.CONVST or CSTART is the only external signal needed for operation. Figure10shows the first two devices in daisy chain.The signals shown by double lines are LVDS and the others Daisy chain mode is selected by setting MODE_C/D=0.The first device in the chain is identified by selecting LAT_Y/N=0.Figure10.Connecting Multiple Devices in Daisy ChainFor all other devices in the chain LAT_Y/N=1.See Table1for more details on device configurations.SDO, CLK_O,and SYNC_O of device n are connected to and SYNC_I of device n+1.SDO,CLK_O,and SYNC_O of the last device in the chain go to the receiver.BUS_BUSY of device n is connected to RD of device n+1and so on.Finally,BUS_BUSY of the last device in the chain is connected to RD of device1.This ensures the necessary handshake to seamlessly propagate the data of all devices through the chain(it is also allowed to tie RD=0for device1).TIMING DIAGRAMS FOR DAISY CHAIN OPERATIONThe conversion speed for n devices in the chain must be selected such that:1/conversion speed>read startup delay+n*(data frame duration)+t d16Read startup delay=10ns+(t d19-t d4)+t d12+2/f CLKData frame duration=16/f CLKNote that it is not necessary for all devices in the chain to sample the data simultaneously.But all of the devices must operate with the same exact conversion speed.Figure11.Data Read Operation for Devices in Daisy ChainDATA READ OPERATIONOn power up,BUS_BUSY of all of the devices is low.The devices receive CONVST or CSTART to sample and start the conversion.The first device in the chain starts the data read cycle at the end of its conversion. BUS_BUSY of device1(connected to RD of device2)goes high on the read cycle start.Device2BUS_BUSY goes high on the rising edge of RD.This propagates until the last device in the chain.Device2receives CLK_I, SDI,and SYNC_I from device1and it passes all of these signals to the next device.Device2(and every subsequent device in the chain)passes the received signals to its output until it sees the falling edge of RD (same as BUS_BUSY of the previous device).In daisy chain mode,BUS_BUSY for any device falls when it has passed all of the previous device data followed by its own data.The falling edge of BUS_BUSY occurs before the rising edge of SYNC_O.This indicates to the receiving device that the previous data chain is over and it is its own turn to output the data.The device outputs the data from the last completed conversion.BUS_BUSY of the last device in the chain is fed back to RD of the first device as shown in Figure10(or device1RD tied to0).This makes sure that RD of device1is low before its conversion is over.with only one external signal(CONVST or CSTART)when CS is held low.Every device LVDS output goes to3-state once all data transfer through the device has been completed.CS going high during the data read cycle of any device3-states its SYNC_O and SDO.This halts the propagation of data through the chain.To reset this condition it is necessary to assert CS high for all devices. The new read sequence starts only after CS for all devices is low before point A shown in Figure6.The high pulse on CS must be at least20ns wide.It is better to connect CS of all of the to avoid undesired halting of the daisy chain.CS = 0CASCADE Figure12.Data Propagation from Device n to Device n+1in Daisy Chain ModeAs shown in Figure12there is a propagation delay of t pd1from SYNC_I to SYNC_O or SDI to SDO.Note that the data frames of all devices in the chain appear seamless at the last device output.The rising edge of SYNC occurs at an interval of16clocks(or8clocks in BYTE mode);this can be used as a data frame sync.The deserializer at the output of the last device can shift the data on every falling edge of the clock and it can latch the parallel16-bit word on the second rising edge of CLK_O(shown as18R)after every rising edge of SYNC_O. Figure13shows the cascade connection.The signals shown by double lines are LVDS and the others are mode is selected by setting MODE_C/D=1.Similar to daisy chain,the first device in the chain is identified by selecting LAT_Y/N=0.For all other devices in the chain LAT_Y/N=1.See Table1for more details on device configuration.SDO,CLK_O,and SYNC_O are connected to the common only one device occupies the bus at a time while the LVDS drivers for all other devices3-state.Unlike SDO and SYNC_O,the clock cannot be switched out from device to device as the receiver requires a continuous clock.So only device1outputs the clock and CLK_O of all other devices is3-stated by appropriately setting M1+and M1-as listed in Table1.Figure13.Cascade ConnectionCLOCK SOURCEIn this mode it is very critical to control the skew between the three LVDS o/p signals.It is recommended to use external clock mode only for all of the devices in cascade.BUS_BUSY of device n is connected to RD of device n+1and so on.Finally BUS_BUSY of the last device in the chain is to be connected to RD of device1.This ensures the necessary handshake to control the sequence of data reads for all of the devices in cascade.(It is also allowed to tie RD to0for device1.)TIMING DIAGRAMS FOR CASCADE OPERATIONThe conversion rate for n devices in cascade must be selected such that:1/conversion speed>first device read cycle duration+(n-1)next device read cycle durationFirst device read cycle duration=read startup delay_1+data frame duration+(t d16+t d17)Next device read cycle duration=read startup delay_n+data frame duration+(t d16+t d17)Read startup delay_1=10ns+(t d19-t d4+t d12)+2/f clkRead startup delay_n=(t d13+2/f clk)Data frame duration=16/f clkNote that it is not necessary that all devices in the chain sample the data simultaneously.But all of the devices must operate with the same exact conversion speed.。
8F3E1 Datasheet V1.1说明书
8F3E1 DatasheetContents Preface (3)Disclaimer (3)Customer Support Overview (3)ESD Warning (4)Precautions (5)Limited Product Warranty (5)Introduction (6)Product Features and Specifications (7)Interface function description (10)Typical Installation (12)Recovery Mode (12)Order Information (13)PrefaceDisclaimerThe information contained within this user’s guide,including but not limited to any product specification,is subject to change without notice.Plink assumes no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the user’s guide.Customer Support OverviewIf you experience any difficulties after using the product,please freely contact us directly.Our tech can help you with product installation and difficulties.Our support section is available24hours a day,7days a week on our website at: /en/Jetson.html.Our technical support is always free.ESD WarningElectronic components and circuits are very sensitive to electrostatic discharge.Although the company will do anti-static protection design for the main interface on the circuit board when designing circuit board products,it is difficult to do anti-static safety protection for all components and circuits.Therefore,it is recommended to follow ESD safety precautions when handling any circuit board component.ESD protection measures include but are not limited to the following:-During transportation or storage,place the card in an ESD bag and do not take it out until installation.-Release the static electricity before touching the ing a discharge grounding wrist strap.-Operate the circuit board only in electrostatic discharge safety area.-Avoiding move circuit boards in carpeted areas.-Avoiding contact with components,try to handle the board by the edges.Precautions-Before using the product,please read this manual carefully and keep it properly for future reference-Please pay attention to and follow all warnings and guidelines marked on the product-Please use the matching power adapter to ensure the stability of current and voltage-Please use this product in a cool,dry and clean place-Do not use this product in the environment of alternating cold and heat to avoid condensation and damage to internal components-Do not splash any liquid on the product.It is forbidden to use organic solvent or corrosive liquid to clean the product-Do not use this product in dusty and messy environment.If it is not used for a long time,please pack the product-Do not use it in an environment with excessive vibration.Any falling or knocking may damage the lines and components-Do not plug and unplug the core board and peripheral modules when the power is on-Do not repair or disassemble the product by yourself.If the product fails,contact the company for repair in time-Do not modify or use unauthorized accessories by yourself,and the resulting damage will not be covered by warrantyLimited Product Warranty-Warranty period-Bottom plate and core plate:3years(non-human damage)-Contact informationContacts:RMAAddress:Room718,Jinrongkemao Plaza,No.15Shangdi Xinxi Road,Haidian District,Beijing,ChinaE-mail:******************Telephone:+86-010-********-Mailing instructions:Please contact the sale staff of the company in advance,then arrange technicians to verify and eliminate the errors caused by misoperation as soon as possible.After verification,please mail the equipment to the company.Please attach a list of items and the reason for failure when mailing for easy verification,so as to avoid loss and damage in the process of express delivery.Introduction8F3E1is a IPC with NVIDIA®Jetson™AGX Xavier and AGX ORIN32GB core modules.The main interface is designed for electrostatic safety protection,and a high-reliability power supply application scheme is adopted.The input power supply has over voltage and reverse polarity protection functions,and has a wealth of external interfaces.The internal interface devices are all wide-temperature models.8F3E1provides multiple independent Gigabit network ports through internal M.2ports, miniPCIe ports,and PCIE ports,which is suitable for multi-network port scenarios.Product Features and Specifications-Product size：198mm×197mm×45mm-Power requirements：+12V-Working temperature：-20~+65℃-Weight：1340g-Optional expansion:32GB~1TB SSD storage-Maximum scalability512g TF card memory-4G and WIFI module can be extended-The initial setting can be reset and restored*Remark：when this model is equipped with AGX Xavier module,only one USB Type A supports USB3.0,Supports only one M.2Key M connector and one miniPCIe connectorPanel and interface IDSInterface function descriptionTypical Installation-Ensure power off of all external system-Install the necessary external cables.(e.g.display cable connected to HDMI monitor, power input cable supplying power to the system,USB cable connecting keyboard and mouse...)-Connect the power cord to the power supply-8F3E1could be set as default automatic power on or switch on.Please consult the sales and technical staff of our company for specific methods.Recovery ModeJetson core module can work in normal mode and recovery mode.It can be operated in recovery mode to file system update,kernel update,boot loader update,BCT update and other operationsStep in Recovery mode:-Turn off the system power supply-Use a Micro-USB cable to connect OTG port of the8F3E1with USB of the Jetson developing host-Press and hold on Recovery button(REC)to supply system power.Keep REC button for3seconds above,then release the recovery buttonThe system enters the Recovery mode,and you can perform subsequent operations.Order InformationE-commerce direct purchaseTaobao：https:///Jingdong：https:///index-11467104.html?from=pc Alibaba：https:///。
SC1088数据手册(SILAN公司)-Soiseek
5
10
µV
Signal handling
THD<10%,∆f=±75kHz
200
mV
Signal-to -noise ratio
(S+N)/N See fig.2
56
dB
Total Harmonic distortion
THD
∆f=±22.5kHz
1
1.4
%
∆f=±75kHz
2.4 3.3
1
Silan Semiconductors
BLOCK DIAGRAM
+3V 680pF
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
2
3.3nF
180pF
3.9nF 330pF
0.1µF
67
8 9 10 13
RUN
470pF
22nF
15
3
11
Vp
Supply Current(Pin 4)
Ip
DC voltage of pin 1
V1
DC voltage of pin 3
V3
DC voltage of pin 6 and 7
V6,7
DC voltage of pin 8
V8
DC voltage of pin 9,10 and 13
V9,10,13
Value 5
-10 ~ +70 -55 ~ +150
Unit V °C °C
DC ELECTRICAL CHARACTERISTICS
(Tamb=25°C,Vp=3V ,Unless otherwise specified)
IC datasheet pdf-THS12082,PDF(12-Bit, 8 MSPS, Simultaneous Sampling Analog-to-Digital Converter)
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERSPACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball FinishMSL Peak Temp (3)5962-0051901NXD PREVIEW TSSOP DA 32TBD Call TI Call TITHS12082CDA ACTIVE TSSOP DA 3246Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR THS12082CDAG4ACTIVE TSSOP DA 3246Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR THS12082CDAR ACTIVE TSSOP DA 322000Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR THS12082CDARG4ACTIVE TSSOP DA 322000Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR THS12082IDA ACTIVE TSSOP DA 3246Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR THS12082IDAG4ACTIVE TSSOP DA 3246Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR THS12082IDAR ACTIVE TSSOP DA 322000Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR THS12082IDARG4ACTIVE TSSOP DA 322000Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR THS12082QDA PREVIEW TSSOP DA 32TBD Call TI Call TI THS12082QDARPREVIEWTSSOPDA32TBDCall TICall TI(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement thatlead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM18-Sep-2008TAPE AND REEL INFORMATION*All dimensions are nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant THS12082CDAR TSSOP DA 322000330.024.48.611.5 1.612.024.0Q1THS12082IDARTSSOPDA322000330.024.48.611.51.612.024.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) THS12082CDAR TSSOP DA322000346.0346.041.0 THS12082IDAR TSSOP DA322000346.0346.041.0IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI components.To minimize the risks associated with customer products and applications,customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any TI patent right,copyright,mask work right, or other TI intellectual property right relating to any combination,machine,or process in which TI products or services are rmation published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.Reproduction of this information with alteration is an unfair and deceptive business practice.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.TI products are not authorized for use in safety-critical applications(such as life support)where a failure of the TI product would reasonably be expected to cause severe personal injury or death,unless officers of the parties have executed an agreement specifically governing such use.Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications,and acknowledge and agree that they are solely responsible for all legal,regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications,notwithstanding any applications-related information or support that may be provided by TI.Further,Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or"enhanced plastic."Only products designated by TI as military-grade meet military specifications.Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk,and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS16949requirements.Buyers acknowledge and agree that,if they use any non-designated products in automotive applications,TI will not be responsible for any failure to meet such requirements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers AudioData Converters AutomotiveDLP®Products BroadbandDSP Digital ControlClocks and Timers MedicalInterface MilitaryLogic Optical NetworkingPower Mgmt SecurityMicrocontrollers TelephonyRFID Video&ImagingRF/IF and ZigBee®Solutions WirelessMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2009,Texas Instruments Incorporated。
28130;中文规格书,Datasheet资料
METALIZATION DIAGRAM
TEMPERATURE SCALE CONVERSION EQUATIONS
+2.0 +1.5 +1.0 +0.5
0 –0.5 –1.0 –1.5 –2.0
–25
0
+25
+70
TEMPERATURE – oC
+105
AD592BN Accuracy Over Temperature
TOTAL ERROR – oC TOTAL ERROR – oC
+2.0 +1.5 +1.0 +0.5
+1.0
+0.5
MAXIMUM ERROR OVER TEMPERATURE
TYPICAL ERROR
0 CALIBRATION ERROR LIMIT
–0.5
TOTAL ERROR – oC
IOUT – µA
378
+105oC
298
+25oC
–25oC 248
UP TO 30V
0
1
2
3
4
5
6
SUPPLY VOLTAGE – Volts
66MILS
V+
V–
/
Model
AD592CN AD592BN AD592AN
42MILS
؇C = 5 (؇F –32) 9
H11L1S(TA),H11L1S(TA),H11L1S(TA),H11L1M,H11L1,H11L2M,H11L2,H11L3M, 规格书,Datasheet 资料
Schmitt TriggerH11Lx SeriesFeatures:• High data rate, 1MHz typical (NRZ)• Free from latch up and oscilliation throughout voltage and temperature ranges.• Microprocessor compatible drive• Logic compatible output sinks 16mA at 0.4V maximum • Guaranteed on/off threshold hysteresis• Wide supply voltage capability, compatible with all popular logic systems• High isolation voltage between input and output (Viso=5000 V rms ) • Compact dual-in-line package • Pb free and RoHS compliant. • UL approved (No. E214129) • VDE approval (No.132249 ) • SEMKO approved • NEMKO approved • DEMKO approved• FIMKO approved• CSA approved (No. 2007798)SchematicDescriptionThe H11LX series of devices each consist of a GaAs infrared emitting diode optically coupled a high speed integrated circuit detector. The output detector incorporates a Schmitt trigger, which provides hysteresis for noise immunity and pulse shaping. The devices are in a 6-pin DIP package and available in wide-lead spacing and SMD option.Applications1. Anode2. Cathode3. No Connection4. V O5. GND6. V CCz Logic to logic isolatorz Programmable current level sensorz Line receiver － eliminate noise and transient problems z AC to TTL conversion － square wave shaping z Digital programming of power supplies z Interfaces computers with peripheralsTruth TableInput Output H L L HSchmitt Trigger H11Lx SeriesAbsolute Maximum Ratings (T a =25°C)Parameter Symbol Rating Unit Forward currentI F 60 mA Reverse voltage V R 6 V InputPower dissipation P D 120 mW V 45 Allowed RangeV o 0 to 16 V V 65 Allowed Range V CC3 to 16VOutput Current I 0 50 mA Outputpower dissipationP D 150 mW Total power dissipation P tot 250 mW Isolation voltage *1 V iso 5000 V rms Operating temperature T opr -55~+100 °C Storage temperature T stg -55~+150 °C Soldering temperature *2 T sol260 °CNotes*1 AC for 1 minute, R.H.= 40 ~ 60% R.H. In this test, pins 1, 2 & 3 are shorted together, and pins 4, 5 & 6 are shorted together. *2 For 10 seconds.Schmitt Trigger H11Lx SeriesElectrical Characteristics (T a =25°C unless specified otherwise)InputParameter Symbol Min. Typ.* Max. Unit ConditionForward voltageV F - 1.15 1.5 V I F = 10mA Reverse Leakage current I R - - 10 µA V R = 5VCapacitanceC J- - 100 pF V=0, f=1MHzOutputParameter Symbol Min. Typ.* Max. Unit ConditionOperation Voltage Range V CC 3 - 15 V Supply Current I CC(off) - 1.6 5 mA I F =0mA, Vcc=5V Output Current, High I OH- - 100 µA I F =0mA, Vcc=Vo=15VIsolation ResistanceR ISO 1011- -Ω V I-O =500VDCTransfer CharacteristicsParameter Symbol Min. Typ.* Max. Unit ConditionSupply Current I CC(on) - 1.6 5 mA I F =10mA, Vcc=5V Output Voltage .lowV OL- - 0.4 VVcc=5V, I F =I Fon (max.), R L =270ΩH11L1 - -1.6 H11L2 - - 10Turn on ThresholdCurrent 1H11L3I Fon- - 5 mA Vcc=5V, R L =270Ω Turn off Threshold Current I Foff - 1 - mA Vcc=5V, R L =270Ω Hysteresis Ratio I Fon /I Foff 0.5 - 0.9 Vcc=5V, R L =270ΩTurn on Time t on - - 4 μS Fall Time t r - 0.1 - μS Turn off Time t off - - 4 μS Rise Time t r - 0.1 - μS Vcc=5V, I F =I Fon , R L =270ΩData Rate- 1 - MHz* Typical values at T a = 25°C 1. Max. I F(ON) is the maximum current required to trigger the output. For examples, a 1.6mA maximum trigger current would require the LED to be driven at a current greater than 1.6mA to guarantee the device will turn on. A 10% guard band is recommended to account for degradation of the LED over its lifetime. The maximum allowable LED drive current is 60mA.Schmitt TriggerH11Lx SeriesTypical Performance CurvesSchmitt TriggerH11Lx SeriesOrder InformationPart NumberH11LXY(Z)-VNoteX = Part No. for 1, 2 or 3Y = Lead form option (S, S1, M or none)Z = Tape and reel option (TA, TB or none).V = VDE (optional)quantity Option Description PackingNone Standard DIP-6 65 units per tubeM Wide lead bend (0.4 inch spacing) 65 units per tubeS + TA Surface mount lead form + TA tape & reel option 1000 units per reelS + TB Surface mount lead form + TB tape & reel option 1000 units per reelS1 + TA Surface mount lead form (low profile) + TA tape & reel option 1000 units per reelS1 + TB Surface mount lead form (low profile) + TB tape & reel option 1000 units per reelSchmitt Trigger H11Lx SeriesPackage Drawings(Dimensions in mm)Standard DIP TypeOption M TypeSchmitt Trigger H11Lx Seriesption S1 TypeOSchmitt Trigger H11Lx Series Recommended pad layout for surface mount leadformevice Markingotesdenotes EverlightberDELH11L3YW WVNLEH11L3 denotes Device NumY denotes 1 digit Year codeWW denotes 2 digit Week codeV denotes VDE (optional)Schmitt Trigger H11Lx SeriesTape & Reel Packing Specificationsape dimensionsE FTDimension No. A B Do D1 Dimension (mm)10.4±0.1 7.52±0.1 1.5±0.1 1.5+0.1/-0 1.75±0.1 7.5±0.1Dimension No. Po P1 P2 tW KDimension (mm)4.0±0.15 1.6±0.1 2.0±0.1 0.35±0.03 16.0±0.2 4.5±0.1Schmitt Trigger H11Lx Series Solder Reflow Temperature ProfileTIME (S)6 PIN DIP PHOTO COUPLERSchmitt Trigger Everlight Electronics Co., Ltd. 11 Document No ：DPC-0000022 Rev. 1 January 7, 2009H11Lx Series DISCLAIMERThe specifications in this datasheet may be changed without notice. EVERLIGHT reserves the authority . When using this product, please observe the absolute maximum ratings and the instructions for use as the 3. hese specification sheets include materials protected under copyright of EVERLIGHT. Reproduction in1.on material change for above specification.2outlined in this datasheet. EVERLIGHT assumes no responsibility for any damage resulting from use of product which does not comply with the absolute maximum ratings and the instructions included in this datasheet.T any form is prohibited without the specific consent of EVERLIGHT.芯天下--/。
Silicon Carbide (SiC) 晶体管模块数据手册说明书
MSCSM120AM042CD3AGDatasheet Phase Leg SiC Power ModuleJanuary20201Revision History (1)Revision1.0 (1)Product Overview (2)2.1Features (3)2.2Benefits (3)2.3Applications (3)Electrical Specifications (4)3.1SiC MOSFET Characteristics(Per MOSFET) (4)3.2SiC Schottky Diode Ratings Characteristics(Per SiC Diode) (6)3.3Thermal Package Characteristics (6)3.4Typical SiC MOSFET Performance Curves (7)3.5Typical SiC Diode Performance Curves (10)Package Specifications (11)Table1•Absolute Maximum Ratings (4)Table2•Electrical Characteristics (4)Table3•Dynamic Characteristics (5)Table4•Body Diode Ratings and Characteristics (5)Table5•SiC Schottky Diode Ratings and Characteristics (6)Table6•Package Characteristics (6)Figure1•MSCSM120AM042CD3AG Electrical Schematic (2)Figure2•MSCSM120AM042CD3AG Pinout Location (2)Figure3•Maximum Thermal Impedance (7)Figure4•Output Characteristics,TJ=25°C (7)Figure5•Output Characteristics,TJ=175°C (7)Figure6•Normalized RDS(on)vs.Temperature (7)Figure7•Transfer Characteristics (7)Figure8•Switching Energy vs.Rg (8)Figure9•Switching Energy vs.Current (8)Figure10•Capacitance vs.Drain Source Voltage (8)Figure11•Gate Charge vs.Gate Source Voltage (8)Figure12•Body Diode Characteristics,TJ=25°C (8)Figure13•3rd Quadrant Characteristics,TJ=25°C (8)Figure14•Body Diode Characteristics,TJ=175°C (9)Figure15•3rd Quadrant Characteristics,TJ=175°C (9)Figure16•Operating Frequency vs.Drain Current (9)Figure17•Maximum Thermal Impedance (10)Figure18•Forward Characteristics (10)Figure19•Capacitance vs.Reverse Voltage (10)Figure20•Package Outline (11)1Revision HistoryThe revision history describes the changes that were implemented in the document.The changes are listed by revision,starting with the most current publication.1.1Revision 1.0Revision 1.0is the first publication of this document,published in January 2020.Revision HistoryThe MSCSM120AM042CD3AG is a phase leg1200V/495A silicon carbide power module.Figure1•MSCSM120AM042CD3AG Electrical SchematicFigure2•MSCSM120AM042CD3AG Pinout LocationAll ratings at T J=25°C unless otherwise specified.Caution:These devices are sensitive to electrostatic discharge.Proper handling procedures should befollowed.2.1FeaturesThe following are key features of the MSCSM120AM042CD3AG device:•SiC Power MOSFET◦Low RDS(on)◦High temperature performance•Silicon carbide(SiC)Schottky diode◦Zero reverse recovery◦Zero forward recovery◦Temperature-independent switching behavior◦Positive temperature coefficient on VF•Kelvin emitter for easy drive•High level of integration•Aluminum nitride(AlN)substrate for improved thermal performance•M6power connectors2.2BenefitsThe following are benefits of the MSCSM120AM042CD3AG device:•High efficiency converters•Stable temperature behavior•Direct mounting to heatsink(isolated package)•Low junction-to-case thermal resistance•RoHS Compliant2.3ApplicationsThe MSCSM120AM042CD3AG device is designed for the following applications:•Welding converters•Switched Mode Power Supplies•Uninterruptible Power Supplies•EV motor and traction drive3Electrical SpecificationsThis section shows the electrical specifications of the MSCSM120AM042CD3AG device.3.1SiC MOSFET Characteristics (Per MOSFET)This section describes the electrical characteristics of the MSCSM120AM042CD3AG device.Table 1•Absolute Maximum RatingsUnit Maximum Ratings ParameterSymbol V 1200Drain-source voltage V DSS A4951T C =25°C Continuous drain currentI D3951T C =80°C990Pulsed drain current I DM V –10/25Gate-source voltage V GS mΩ5.2Drain-source ON resistance R DSon W 2031T C =25°CPower dissipationP DNote:1.Specification of SiC MOSFET device but output current must be limited due to the size of power connectors.Table 2•Electrical CharacteristicsUnitMaxTypMinTest ConditionsCharacteristicSym-bol μA 60060V GS =0V;V DS =1200V Zero gate voltage drain current I DSS mΩ5.24.2T J =25°C V GS =20V I D =240ADrain–source on resistanceR DSon6.7T J =175°CV2.81.8V GS =V DS ,I D =6mA Gate threshold voltage V GS(th)nA600V GS =20V,V DS =0VGate–source leakage currentI GSSTable 3•Dynamic CharacteristicsUnit MaxTyp MinTest Conditions Characteristic Symbol pF18.1V GS =0V V DS =1000V f =1MHzInput capacitance C iss 1.6Output capacitance C oss 0.15Reverse transfer capacitance C rss nC1392V GS =–5/20V V Bus =800V Total gate charge Q g 246Gate–source charge Q gs I D =240A 300Gate–drain charge Q gd ns 56V GS =–5/20V V Bus =600V Turn-on delay time T d(on)55Rise time T r I D =300A166Turn-off delay time T d(off)R Gon =1.3Ω;R Goff =0.8ΩTJ =150°C 67Fall time T f mJ 6.1T J =150°CInductive Switching V GS =–5/20V Turn on energy E on mJ5.5T J =150°CTurn off energyE offV Bus =600V I D =300A R Gon =1.3ΩR Goff =0.8ΩΩ1Internal gate resistanceR Gint °C/W0.074Junction-to-case thermal resistanceR thJCTable 4•Body Diode Ratings and CharacteristicsUnit MaxTyp MinTest Conditions Characteristic Symbol V4V GS =0V;I SD =240A Diode forward voltageV SD4.2V GS =–5V;I SD =240Ans 90I SD =240A;V GS =–5V;V R =800V;diF/dt =6000A/μsReverse recovery time t rr nC 3300Reverse recovery charge Q rr A81Reverse recovery currentI rr3.2SiC Schottky Diode Ratings Characteristics (Per SiC Diode)This section shows the SiC Schottky diode ratings and characteristics of the device.Table 5•SiC Schottky Diode Ratings and CharacteristicsUnitMaxTypMinTest ConditionsCharacteristicSym-bol V 1200Peak repetitive reverse voltage V RRM μA120060T J =25°C V R =1200VReverse leakage currentI RRM900T J =175°CA180T C =100°CForward currentI FV1.81.5T J =25°C I F =180ADiode forward voltage V F2.1T J =175°CnC 780V R =600VTotal capacitive charge Q C pF846f =1MHz,V R =400V Total capacitanceC630f =1MHz,V R =800V°C/W0.175Junction-to-case thermal resistance R thJC3.3Thermal Package CharacteristicsThis section shows the thermal and package characteristics of the device.Table 6•Package CharacteristicsUnit MaxMin CharacteristicSymbol V 4000RMS isolation voltage,any terminal to case t =1min,50/60Hz V ISOL °C 175–40Operating junction temperature rangeT J °C T Jmax –25–40Recommended junction temperature under switching conditions T JOP °C 125–40Storage temperature range T STG °C 125–40Operating case temperature T C N.m53M6For terminals Mounting torqueTorque53M6To heatsinkg350Package weightWt3.4Typical SiC MOSFET Performance CurvesThis section shows the typical performance curves of the MSCSM120AM042CD3AG SiC MOSFET.Figure3•Maximum Thermal ImpedanceFigure4•Output Characteristics,T J=25°CFigure6•Normalized RDS(on)vs.TemperatureFigure8•Switching Energy vs.Rg Figure9•Switching Energy vs.CurrentFigure10•Capacitance vs.Drain Source VoltageFigure12•Body Diode Characteristics,T J=25°C°CFigure16•Operating Frequency vs.Drain Current3.5Typical SiC Diode Performance CurvesThis section shows the typical performance curves of the MSCSM120AM042CD3AG SiC diode.Figure17•Maximum Thermal ImpedanceFigure18•Forward CharacteristicsThis section shows the package outline of the MSCSM120AM042CD3AG device.All dimensions are inmillimeters.Figure20•Package OutlineSee application note1908-Mounting instructions for D3and D4power modules on Microsemi's product warranty is set forth in Microsemi's Sales Order Terms and rmation contained in this publication is provided for the sole purpose of designing with and using Microsemi rmation regarding device applications and the like is provided only for your convenience and may be superseded by updates.Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi.It is your responsibility to ensure that your application meets with your specifications.THIS INFORMATION IS PROVIDED "AS IS."MICROSEMI MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,WRITTEN OR ORAL,STATUTORY OR OTHERWISE,RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY ,PERFORMANCE,NON-INFRINGEMENT,MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.IN NO EVENT WILL MICROSEMI BE LIABLE FOR ANY INDIRECT,SPECIAL,PUNITIVE,INCIDENTAL OR CONSEQUENTIAL LOSS,DAMAGE,COST OR EXPENSE WHATSOEVER RELATED TO THIS INFORMATION OR ITS USE,HOWEVER CAUSED,EVEN IF MICROSEMI HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.TO THE FULLEST EXTENT ALLOWED BY LAW,MICROSEMI’S TOTAL LIABILITY ON ALL CLAIMS IN RELATED TO THIS INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES,IF ANY ,YOU PAID DIRECTLY TO MICROSEMI FOR THIS e of Microsemi devices in life support,mission-critical equipment or applications,and/or safety applications is entirely at the buyer’s risk,and the buyer agrees to defend and indemnify Microsemi from any and all damages,claims,suits,or expenses resulting from such use.No licenses are conveyed,implicitly or otherwise,under any Microsemi intellectual property rights unless otherwisestated.Microsemi2355W.Chandler Blvd.Chandler,AZ 85224USAWithin the USA:+1(480)792-7200Fax:+1(480)792-7277 ©2020Microsemi andits corporate affiliates.All rights reserved.Microsemi and the Microsemi logo aretrademarks of Microsemi Corporation and itscorporate affiliates.All other trademarks andservice marks are the property of theirrespective owners.Microsemi Corporation,a subsidiary of Microchip Technology Inc.(Nasdaq:MCHP),and its corporate affiliates are leading providers of smart,connected and secure embedded control solutions.Their easy-to-use development tools and comprehensive product portfolio enable customers to create optimal designs which reduce risk while lowering total system cost and time to market.These solutions serve more than 120,000customers across the industrial,automotive,consumer,aerospace and defense,communications and computing markets.Headquartered in Chandler,Arizona,the company offers outstanding technical support along with dependable delivery and quality.Learn more at .MSCC-0344-DS-01066-1.0-0120Legal。
Silicon Labs C8051F04x 数据手册 v1.7说明书
Effective Date:Bulletin Issue Date:Dec 07, 2022Dec 07, 2022Description of ChangeSilicon Labs is pleased to announce the release of datasheet version 1.7 for the C8051F04x devices.The datasheet has been updated to reflect the changes of the Product Selection Guide table.Link to the datasheet:https:///documents/public/data-sheets/C8051F04x.pdf 2212071371 C8051F04x Datasheet v1.7 Release Product IdentificationExisting Part #C8051F040-GQC8051F040-GQRC8051F041-GQC8051F041-GQRC8051F042-GQC8051F042-GQRC8051F043-GQC8051F043-GQRC8051F044-GQC8051F044-GQRC8051F045-GQC8051F045-GQRC8051F046-GQC8051F046-GQRC8051F047-GQC8051F047-GQRUser RegistrationRegister today to create your account on . Your personalized profile allows you to receive technical document updates, new product announcements, “how-to ” and design documents, product change notices (PCN) and other valuable content available only to registered users. /profileCustomer Actions Needed:Review updated datasheet.This change is considered a minor change which does not affect form, fit, function, quality, or reliability. The information is being provided as a customer courtesy.Please contact your local Silicon Labs sales representative with any questions about this notification. A list of Silicon Labs sales representatives may be found at .Kit IdentificationReason for ChangeRelease of datasheet version 1.71Bulletin #2022-12-07-1371Silicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701 DisclaimerSilicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules andperipherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.Trademark InformationSilicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®,Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®, ISOmodem®, Micrium, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress®, Zentri and others are trademarks or registered trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is aregistered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.。
IC datasheet pdf-DM13A pdf,16-bit Constant Current LED Driver
OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4
25 26 27 28 29 30 31 32
24
1
23
2
22
3
21
QFN32
4
20
5
19
(bottom view)
6
18
7
17
8
16 15 14 13 12 11 10 9
GND GND VDD VDD GND GND GND GND
MIN. 3.3
1.0
⎯
5 ⎯ ⎯ 0.8VDD 0.0 ⎯ 15 15 10 10 10 10
Rth(j-a)
50.0 (PDIP24 )
79.2 (SOP24 )
90.2 (SSOP24 )
Operating Temperature
Top
-40 ~ 85
Storage Temperature
Tstg
-55 ~ 150
UNIT V V mA V
MHz mA
W
°C/W
°C °C
Recommended Operating Condition
Issue Date : 2007/05/21
File Name : SP-DM13A-PRE.001.doc
Total Pages : 23
16-bit Constant Current LED Driver
新竹市科學園區展業一路 9 號 7 樓之 1
SILICON TOUCH TECHNOLOGY INC.
Page 1
點晶科技股份有限公司 SILICON TOUCH TECHNOLOGY INC.