FSB6726中文资料

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2SA966资料

TOSHIBA Transistor Silicon PNP Epitaxial Type (PCT Process)2SA966Audio Power Amplifier Applications• Complementary to 2SC2236 and 3-W output applications.Absolute Maximum Ratings (Ta = 25°C)Characteristics Symbol Rating UnitCollector-base voltage V CBO −30 V Collector-emitter voltage V CEO −30 V Emitter-base voltage V EBO −5 V Collector current I C−1.5 AEmitter currentI E 1.5 A Collector power dissipation P C 900 mW Junction temperature T j 150 °C Storage temperature rangeT stg−55 to 150°CNote: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in thereliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings.Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“HandlingPrecautions”/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc).Unit: mmJEDEC TO-92MOD JEITA ―TOSHIBA 2-5J1A Weight: 0.36 g (typ.)Electrical Characteristics (Ta = 25°C)Characteristics Symbol TestCondition MinTyp.Max UnitCollector cut-off current I CBO V CB = −30 V, I E = 0 ――−100nAEmitter cut-off current I EBO V EB = −5 V, I C = 0 ――−100nA Collector-emitter breakdown voltage V (BR) CEO I C = −10 mA, I B = 0 −30 ―― V Emitter-base breakdown voltage V (BR) EBO I E = −1 mA, I C = 0 −5 ―― VDC current gain h FE(Note)V CE = −2 V, I C = −500 mA 100 ― 320Collector-emitter saturation voltage V CE (sat)I C = −1.5 A, I B = −0.03 A ――−2.0V Base-emitter voltage V BE V CE = −2 V, I C = −500 mA ――−1.0V Transition frequency f T V CE = −2 V, I C = −500 mA ― 120 ― MHz Collector output capacitance C ob V CB = −10 V, I E = 0, f = 1 MHz ― 40 ― pF Note: h FE classification O: 100 to 200, Y: 160 to 320Markinglead (Pb)-free package orlead (Pb)-free finish.indicatorCollector current I C (mA)h FE – ICD C c u r re n t g a i n h F ECollector current I C (mA)V CE (sat) – I CC o l l e c t o r -e m i t t e r s a t u r a t i on v o l t a g eV C E (s a t ) (V )Base-emitter voltage V BE (V)I C – V BEC oll e c t o rc u r r e n t I C (m A )Ambient temperature Ta (°C)P C – TaC o l l e c t o r p owe r d i s s ip a t io n P C (W )Collector-emitter voltage V CE (V)Safe Operating AreaC o l l e c t o r c u r r e n t I C (A )1.00 0 20 40 60 80 100 120 140 160 1800.20.40.60.8−−−−−−−−−−−−−−−−−−Collector-emitter voltage V CE (V)I C – V CEC o l l e c t o r c u r r e n t I C (m A )−−−−−−−−−−−−−−−−−RESTRICTIONS ON PRODUCT USE20070701-EN •The information contained herein is subject to change without notice.•TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer’s own risk.•The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations.• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties.• Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations.。

MPS6726G;MPS6727;MPS6727G;MPS6726;中文规格书,Datasheet资料

VCEO VCBO VEBO
IC PD
−30 −40 −5.0 −1.0 1.0 8.0
Vdc Vdc Vdc Adc W mW/°C
Total Device Dissipation @ TC = 25°C
PD
2.5
W
Derate above 25°C
20
mW/°C
Operating and Storage Junction Temperature Range
0 Cobo Cibo
TJ = 25°C
Cibo
Cobo
-5.0
-10
-15
-20
-25
-1.0
-2.0
-3.0
-4.0
-5.0
VR, REVERSE VOLTAGE (VOLTS)
Figure 6. Capacitance
fT , CURRENT-GAIN - BANDWIDTH PRODUCT (MHz)
C, CAPACITANCE (pF)
VCE = -10 V
100
TJ = 25°C
80
f = 20 MHz
70
40 50
30 -10 -20
-50 -100 -200
-500 -1000
IC, COLLECTOR CURRENT (mA)
Figure 5. Current Gain — Bandwidth Product
Collector −Base Breakdown Voltage (IC = −100 mAdc, IE = 0)
Emitter −Base Breakdown Voltage (IE = −100 mAdc, IC = 0)

LM22676中文资料

November 21, 2008 LM226763A SIMPLE SWITCHER®, Step-Down Voltage Regulator with Precision EnableGeneral DescriptionThe LM22676 series of regulators are monolithic integrated circuits which provide all of the active functions for a step-down (buck) switching regulator capable of driving up to 3A loads with excellent line and load regulation characteristics. High efficiency (>90%) is obtained through the use of a low ON-resistance N-channel MOSFET. The series consists of a fixed 5V output and an adjustable version.The SIMPLE SWITCHER® concept provides for an easy to use complete design using a minimum number of external components and National’s WEBENCH® design tool. National’s WEBENCH® tool includes features such as exter-nal component calculation, electrical simulation, thermal sim-ulation, and Build-It boards for easy design-in. The switching clock frequency is provided by an internal fixed frequency os-cillator which operates at 500 kHz. The LM22676 series also has built in thermal shutdown, current limiting and an enable control input that can power down the regulator to a low 25µA quiescent current standby condition.Features■Wide input voltage range: 4.5V to 42V■Internally compensated voltage mode control■Stable with low ESR ceramic capacitors■120 mΩ N-channel MOSFET TO-263 THIN package■100 mΩ N-channel MOSFET PSOP-8 package■Output voltage options:-ADJ (outputs as low as 1.285V)-5.0 (output fixed to 5V)■±1.5% feedback reference accuracy■Switching frequency of 500 kHz■-40°C to 125°C operating junction temperature range■Precision enable pin■Integrated boot diode■Integrated soft-start■Fully WEBENCH® enabled■Step-down and inverting buck-boost applications Package■PSOP-8 (Exposed Pad)■TO-263 THIN (Exposed Pad)Applications■Industrial Control■Telecom and Datacom Systems■Embedded Systems■Automotive Telematics and Body Electronics■Conversions from Standard 24V, 12V and 5V Input RailsSimplified Application Schematic30076501© 2008 National Semiconductor LM22676 3A SIMPLE SWITCHER®, Step-Down Voltage Regulator with Precision EnableConnection Diagrams300765408-Lead Plastic PSOP-8 Package NS Package Number MRA08B300765027-Lead Plastic TO-263 THIN PackageNS Package Number TJ7AOrdering InformationOutput VoltageOrder Number Package Type NSC Package DrawingSupplied As ADJ LM22676MR-ADJ PSOP-8 Exposed PadMRA08B95 Units in Rails ADJ LM22676MRE-ADJ 250 Units in Tape and Reel ADJ LM22676MRX-ADJ 2500 Units in Tape and Reel ADJ LM22676TJE-ADJ TO-263 THIN Exposed PadTJ7A250 Units in Tape and Reel ADJ LM22676TJ-ADJ 1000 Units in Tape and Reel5.0LM22676MR-5.0PSOP-8 Exposed PadMRA08B95 Units in Rails 5.0LM22676MRE-5.0250 Units in Tape and Reel 5.0LM22676MRX-5.02500 Units in Tape and Reel 5.0LM22676TJE-5.0TO-263 THIN Exposed PadTJ7A250 Units in Tape and Reel 5.0LM22676TJ-5.01000 Units in Tape and Reel 2L M 22676Pin DescriptionsPin Numbers PSOP-8Package Pin NumbersTO-263 THINPackageName Description Application Information13BOOT Bootstrap input Provides the gate voltage for the high side NFET.2, 35NC Not Connected Pins are not electrically connected inside the chip. Pins dofunction as thermal conductor.46FB Feedback pin Inverting input to the internal voltage error amplifier.57EN Precision enable pin When pulled low regulator turns off.64GND System ground Provide good capacitive decoupling between VIN and thispin72VIN Source input voltage Input to the regulator. Operates from 4.5V to 42V.81SW Switch pin Attaches to the switch nodeLM22676Absolute Maximum Ratings (Note 1)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.VIN to GND 43VEN Pin Voltage-0.5V to 6V SW to GND (Note 2)-5V to V IN BOOT Pin Voltage V SW + 7V FB Pin Voltage -0.5V to 7V Power DissipationInternally LimitedJunction Temperature 150°CSoldering Information Infrared (5 sec.)260°CESD Rating (Note 3) Human Body Model±2 kVStorage Temperature Range -65°C to +150°COperating Ratings(Note 1)Supply Voltage (V IN )4.5V to 42V Junction Temperature Range-40°C to +125°CElectrical CharacteristicsLimits in standard type are for T J = 25°C only; limits in boldface type apply over thejunction temperature (T J ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at T A = T J = 25°C, and are provided for reference purposes only. Unless otherwise specified: V IN = 12V.Symbol ParameterConditionsMin (Note 5)Typ (Note 4)Max (Note 5)UnitsLM22676-5.0V FBFeedback VoltageV IN = 8V to 42V4.925/4.95.05.075/5.1VLM22676-ADJV FB Feedback Voltage V IN = 4.7V to 42V 1.266/1.2591.285 1.304/1.311V All Output Voltage VersionsI Q Quiescent Current V FB = 5V 3.46mA I STDBY Standby Quiescent Current EN Pin = 0V 2540µA I CL Current Limit3.4/3.354.25.3/5.5A I L Output Leakage Current V IN = 42V, EN Pin = 0V, V SW = 0V 0.22µA V SW = -1V0.13µA R DS(ON)Switch On-Resistance TO-263 THIN Package 0.120.16/0.22ΩPSOP-8 Package 0.100.16/0.20f O Oscillator Frequency 400500600kHz T OFFMIN Minimum Off-time 300 ns T ONMIN Minimum On-time100 ns I BIAS Feedback Bias Current V FB = 1.3V (ADJ Version Only) 230 nA V EN Enable Threshold Voltage1.3 1.6 1.9V I EN Enable Input Current EN Input = 0V 6 µA T SD Thermal Shutdown Threshold150 °C θJA Thermal Resistance TJ Junction to ambient temperature resistance (Note 6)22 °C/W θJAThermal ResistanceMR Package, Junction to ambient temperature resistance (Note 7)60°C/W 4L M 22676Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the recommended Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and should not be operated beyond such conditions.Note 2:The absolute maximum specification of the ‘SW to GND’ applies to DC voltage. An extended negative voltage limit of -10V applies to a pulse of up to 50ns.Note 3:ESD was applied using the human body model, a 100 pF capacitor discharged through a 1.5 k Ω resistor into each pin.Note 4:Typical values represent most likely parametric norms at the conditions specified and are not guaranteed.Note 5:Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).Note 6:The value of θJA for the TO-263 THIN (TJ) package of 22°C/W is valid if package is mounted to 1 square inch of copper. The θJA value can range from 20 to 30°C/W depending on the amount of PCB copper dedicated to heat transfer. See application note AN-1797 for more information.Note 7:The value of θJA for the PSOP-8 exposed pad (MR) package of 60°C/W is valid if package is mounted to 1 square inch of copper. The θJA value can range from 42 to 115°C/W depending on the amount of PCB copper dedicated to heat transfer.Typical Performance CharacteristicsUnless otherwise specified the following conditions apply: Vin =12V, T J = 25°C.Efficiency vs I OUT and V INV OUT = 3.3V30076527Normalized Switching Frequency vs Temperature30076504Current Limit vs Temperature30076503Normalized R DS(ON) vs Temperature30076508LM22676Feedback Bias Current vs Temperature30076505Normalized Enable Threshold Voltage vs Temperature30076510Standby Quiescent Current vs Input Voltage 30076506Normalized Feedback Voltage vs Temperature30076507Normalized Feedback Voltage vs Input Voltage30076509 6L M 22676Typical Application Circuit and Block Diagram30076514FIGURE 1. 3.3V VOUT, 3A LM22676Detailed Operating DescriptionThe LM22676 switching regulator features all of the functions necessary to implement an efficient high voltage buck regu-lator using a minimum of external components. This easy to use regulator integrates a 42V N-Channel switch with an out-put current capability of 3A. The regulator control method is based on voltage mode control with input voltage feed for-ward. The loop compensation is integrated into the LM22676so that no external compensation components need to be se-lected or utilized. Voltage mode control offers short minimum on-times allowing short duty-cycles necessary in high input voltage applications. The operating frequency is fixed at 500kHz to allow for small external components while avoiding excessive switching losses. The output voltage can be set as low as 1.285V with the -ADJ device. Fault protection features include current limiting, thermal shutdown and remote shut-down capability. The device is available in the TO-263 THIN and PSOP-8 packages featuring an exposed pad to aid ther-mal dissipation.The functional block diagram with typical application of the LM22676 are shown in Figure 1.The internal compensation of the -ADJ option of the LM22676is optimized for output voltages up to 5V. If an output voltage of 5V or higher is needed, the -5.0 fixed output voltage option with an additional external resistive feedback voltage divider may also be used.Precision EnableThe precision enable pin (EN) can be used to shut down the power supply. Connecting this pin to ground or to a voltage less than typical 1.6V will completely turn off the regulator.The current drain from the input supply when off is typically 25 µA with 12V input voltage. The power consumed during this off state is mostly defined by an internal 2 M Ω resistor to VIN. The enable pin has an internal pull-up current source of approximately 6 µA. When driving the enable pin, the high voltage level for the on condition should not exceed the 6V absolute maximum limit. When enable control is not required,the EN pin should be left floating. The precision feature en-ables simple sequencing of multiple power supplies with a resistor divider from another power supply.Maximum Duty-Cycle / Dropout VoltageThe typical maximum duty-cycle is 85% at 500 kHz switching frequency. This corresponds to a typical minimum off-time of 300 ns. When operating at switching frequencies higher than 500 kHz, the 300 ns minimum off-time results in a lower max-imum duty-cycle limit than 85%. This forced off-time is impor-tant to provide enough time for the Cboot capacitor to charge during each cycle.The lowest input voltage required to maintain operation is:Where V D is the forward voltage drop across the re-circulating Schottky diode and V Q is the voltage drop across the internal power N-FET of the LM22676. The R DS(ON) of the FET is specified in the electrical characteristics section of this datasheet to calculate V Q according to the FET current. F is the switching frequency.Minimum Duty-CycleBesides a minimum off-time, there is also a minimum on-time which will take effect when the output voltage is adjusted very low and the input voltage is very high. Should the operation require a shorter minimum on-time than the typical 100 ns,individual switching pulses will be skipped.where D is the duty-cycle.Current LimitWhen the power switch turns on, the slight capacitance load-ing of the Schottky diode, D1, causes a leading-edge current spike with an extended ringing period. This spike can cause the current limit comparator to trip prematurely. A leading edge blanking time (T BLK ) of 110 ns (typical) is used to avoid sampling the spike.When the switch current reaches the current limit threshold,the switch is immediately turned off and the internal switching frequency is reduced. This extends the off time of the switch to prevent a steady state high current condition. As the switch current falls below the current limit threshold, the switch cur-rent will attempt to turn on. If a load fault continues, the switch will again exceed the threshold and turn off. This will result in a low duty-cycle pulsing of the power switch to minimize the overall fault condition power dissipation.The switching frequency will reduce (fold back) if the overload condition causes the output voltage to be 72.4% (typical) of the adjusted output voltage.The current limit will only protect the inductor from a runaway condition if the LM22676 is operating in its safe operating area. A runaway condition of the inductor is potentially catas-trophic to the application. For every design, the safe operating area needs to be calculated. Factors in determining the safe operating area are the switching frequency, input voltage,output voltage, minimum on-time and feedback voltage dur-ing an over current condition.As a first pass check, if the following equation holds true, a given design is considered in a safe operating area and the current limit will protect the circuit:V IN x T BLK x F < V OUT x 0.724If the equation above does not hold true, the following sec-ondary equation will need to hold true to be in safe operating area:If both equations do not hold true, a particular design will not have an effective current limit function which might damage the circuit during startup, over current conditions, or steady state over current and short circuit condition. Oftentimes a reduction of the maximum input voltage will bring a design into the safe operating area.Soft-StartThe soft-start feature allows the regulator to gradually reach the initial steady state operating point, thus reducing start-up stresses and surges. The soft-start is fixed to 500 µs (typical)start-up time and cannot be modified.8L M 22676Boot PinThe LM22676 integrates an N-Channel FET switch and as-sociated floating high voltage level shift / gate driver. This gate driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. A 0.01 µF ceramic capacitor connected with short traces between the BOOT pin and the SW pin is recommended to effectively drive the internal FET switch. During the off-time of the switch, the SW voltage is approximately -0.5V and the external bootstrap capacitor is charged from the internal supply through the internal boot-strap diode. When operating with a high PWM duty-cycle, the buck switch will be forced off each cycle to ensure that the bootstrap capacitor is recharged. See the maximum duty-cy-cle section for more details.Thermal ProtectionInternal Thermal Shutdown circuitry protects the LM22676 in the event the maximum junction temperature is exceeded.When activated, typically at 150°C, the regulator is forced into a low power reset state. There is a typical hysteresis of 15degrees.Internal CompensationThe LM22676 has internal compensation designed for a sta-ble loop with a wide range of external power stage compo-nents.Insuring stability of a design with a specific power stage (in-ductor and output capacitor) can be tricky. The LM22676stability can be verified over varying loads and input and out-put voltages using WEBENCH® Designer online circuit sim-ulation tool at . A quick start spreadsheet can also be downloaded from the online product folder.The internal compensation of the -ADJ option of the LM22676is optimized for output voltages below 5V. If an output voltage of 5V or higher is needed, the -5.0 option with an additional external resistor divider may also be used.The typical location of the internal compensation poles and zeros as well as the DC gain is given in Table 1. The LM22676has internal type III compensation allowing for the use of most output capacitors including ceramics.This information can be used to calculate the transfer function from the FB pin to the internal compensation node (input to the PWM comparator in the block diagram).TABLE 1.Corners Frequency Pole 1150 kHz Pole 2250 kHz Pole 3100 Hz Zero 1 1.5 kHz Zero 215 kHz DC gain37.5 dBFor the power stage transfer function the standard voltage mode formulas for the double pole and the ESR zero apply:The peak ramp level of the oscillator signal feeding into the PWM comparator is V IN /10 which equals a gain of 20dB of this modulator stage of the IC. The -5.0 fixed output voltage option has twice the gain of the compensation transfer func-tion compared to the -ADJ option which is 43.5dB instead of 37.5dB.Generally, calculation as well as simulation can only aid in selecting good power stage components. A good design prac-tice is to test for stability with load transient tests or loop measurement tests. Application note AN-1889 shows how to easily perform a loop transfer function measurement with only an oscilloscope and a function generator.Application InformationEXTERNAL COMPONENTSThe following design procedures can be used to design a non-synchronous buck converter with the LM22676.InductorThe inductor value is determined based on the load current,ripple current, and the minimum and maximum input voltage.To keep the application in continuous current conduction mode (CCM), the maximum ripple current, I RIPPLE , should be less than twice the minimum load current.The general rule of keeping the inductor current peak-to-peak ripple around 30% of the nominal output current is a good compromise between excessive output voltage ripple and ex-cessive component size and cost. When selecting the induc-tor ripple current ensure that the peak current is below the minimum current limit as given in the Electrical Characteris-tics section. Using this value of ripple current, the value of inductor, L, is calculated using the following formula:where F is the switching frequency which is 500 kHz (typical).This procedure provides a guide to select the value of the inductor L. The nearest standard value will then be used in the circuit.Increasing the inductance will generally slow down the tran-sient response but reduce the output voltage ripple amplitude.Reducing the inductance will generally improve the transient response but increase the output voltage ripple.The inductor must be rated for the peak current, I PK+, to pre-vent saturation. During normal loading conditions, the peak current occurs at maximum load current plus maximum ripple.Under an overload condition as well as during load transients,the peak current is limited to 4.2A typical (5.5A maximum).This requires that the inductor be selected such that it can run at the maximum current limit and not only the steady state current.Depending on inductor manufacturer, the saturation rating is defined as the current necessary for the inductance to reduce by 30% at 20°C. In typical designs the inductor will run at higher temperatures. If the inductor is not rated for enough current, it might saturate and due to the propagation delay of the current limit circuitry, the power supply may get damaged.Input CapacitorGood quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch cur-rent during on-time. When the switch turns on, the current into the VIN pin steps to the peak value, then drops to zero at turn-9LM22676off. The average current into VIN during switch on-time is theload current. The input capacitance should be selected forRMS current, IRMS, and minimum ripple voltage. A good ap-proximation for the required ripple current rating necessary isIRMS> IOUT/ 2.Quality ceramic capacitors with a low ESR should be selectedfor the input filter. To allow for capacitor tolerances and volt-age effects, multiple capacitors may be used in parallel. If stepinput voltage transients are expected near the maximum rat-ing of the LM22676, a careful evaluation of ringing and pos-sible voltage spikes at the VIN pin should be completed. Anadditional damping network or input voltage clamp may berequired in these cases.Usually putting a higher ESR electrolytic input capacitor inparallel to the low ESR bypass capacitor will help to reduceexcessive voltages during a line transient and will also movethe resonance frequency of the input filter away from the reg-ulator bandwidth.Output CapacitorThe output capacitor can limit the output ripple voltage andprovide a source of charge for transient loading conditions.Multiple capacitors can be placed in parallel. Very low ESRcapacitors such as ceramic capacitors reduce the output rip-ple voltage and noise spikes, while larger higher ESR capac-itors in parallel provide large bulk capacitance for transientloading conditions. An approximation for the output voltageripple is:where ΔILis the inductor ripple current.Cboot CapacitorThe bootstrap capacitor between the BOOT pin and the SWpin supplies the gate current to turn on the N-channel MOS-FET. The recommended value of this capacitor is 10 nF andshould be a good quality, low ESR ceramic capacitor.It is possible to put a small resistor in series with the Cbootcapacitor to slow down the turn-on transition time of the in-ternal N-channel MOSFET. Resistors in the range of 10Ω to50Ω can slow down the transition time. This can reduce EMIof a switched mode power supply circuit. Using such a seriesresistor is not recommended for every design since it will in-crease the switching losses of the application and makesthermal considerations more challenging.Resistor DividerFor the -5.0 option no resistor divider is required for 5V outputvoltage. The output voltage should be directly connected tothe FB pin. Output voltages above 5V can use the -5.0 optionwith a resistor divider as an alternative to the -ADJ option.This may offer improved loop bandwidth in some applications.See the Internal Compensation section for more details.For the -ADJ option no resistor divider is required for 1.285Voutput voltage. The output voltage should be directly con-nected to the FB pin. Other output voltages can use the -ADJoption with a resistor divider.The resistor values can be determined by the following equa-tions:-ADJ option:-5.0 option:Where VFB= 1.285V typical for the -ADJ option and 5V for the-5.0 option30076523FIGURE 2. Resistive Feedback DividerA maximum value of 10 kΩ is recommended for the sum ofR1 and R2 to keep high output voltage accuracy for the –ADJoption. A maximum of 2 kΩ is recommended for the -5.0 out-put voltage option. For the 5V fixed output voltage option, thetotal internal divider resistance is typically 9.93 kΩ.At loads less than 5 mA, the boot capacitor will not holdenough charge to power the internal high side driver. Theoutput voltage may droop until the boot capacitor isrecharged. Selecting a total feedback resistance to be below3 kΩ will provide some minimal load and can keep the outputvoltage from collapsing in such low load conditions.Catch DiodeA Schottky type re-circulating diode is required for allLM22676 applications. Ultra-fast diodes which are not Schot-tky diodes are not recommended and may result in damageto the IC due to reverse recovery current transients. The nearideal reverse recovery characteristics and low forward volt-age drop of Schottky diodes are particularly important diodecharacteristics for high input voltage and low output voltageapplications common to the LM22676. The reverse recoverycharacteristic determines how long the current surge lastseach cycle when the N-channel MOSFET is turned on. Thereverse recovery characteristics of Schottky diodes mini-mizes the peak instantaneous power in the switch occurringduring turn-on for each cycle. The resulting switching lossesare significantly reduced when using a Schottky diode. Thereverse breakdown rating should be selected for the maxi-mum VIN, plus some safety margin. A rule of thumb is to selecta diode with the reverse voltage rating of 1.3 times the max-imum input voltage.The forward voltage drop has a significant impact on the con-version efficiency, especially for applications with a low outputvoltage. ‘Rated’ current for diodes varies widely from variousmanufacturers. The worst case is to assume a short circuitload condition. In this case the diode will carry the output cur-rent almost continuously. For the LM22676 this current canbe as high as 4.2A (typical). Assuming a worst case 1V drop 10LM22676across the diode, the maximum diode power dissipation can be as high as 4.2W.Circuit Board LayoutBoard layout is critical for switching power supplies. First, the ground plane area must be sufficient for thermal dissipation purposes. Second, appropriate guidelines must be followed to reduce the effects of switching noise. Switch mode con-verters are very fast switching devices. In such devices, the rapid increase of input current combined with the parasitic trace inductance generates unwanted L di/dt noise spikes. The magnitude of this noise tends to increase as the output current increases. This parasitic spike noise may turn into electromagnetic interference (EMI) and can also cause prob-lems in device performance. Therefore, care must be taken in layout to minimize the effect of this switching noise.The most important layout rule is to keep the AC current loops as small as possible. Figure 3 shows the current flow of a buck converter. The top schematic shows a dotted line which rep-resents the current flow during the FET switch on-state. The middle schematic shows the current flow during the FET switch off-state.The bottom schematic shows the currents referred to as AC currents. These AC currents are the most critical since current is changing in very short time periods. The dotted lines of the bottom schematic are the traces to keep as short as possible. This will also yield a small loop area reducing the loop induc-tance. To avoid functional problems due to layout, review the PCB layout example. Providing 3A of output current in a very low thermal resistance package such as the TO-263 THIN is challenging considering the trace inductances involved. Best results are achieved if the placement of the LM22676, the by-pass capacitor, the Schottky diode and the inductor are placed as shown in the example. It is also recommended to use 2oz copper boards or thicker to help thermal dissipation and to reduce the parasitic inductances of board traces.It is very important to ensure that the exposed DAP on the TO-263 THIN package is soldered to the ground area of the PCB to reduce the AC trace length between the bypass ca-pacitor ground and the ground connection to the LM22676. Not soldering the DAP to the board may result in erroneous operation due to excessive noise on the board.30076524FIGURE 3. Current Flow in a Buck ApplicationThermal ConsiderationsThe two highest power dissipating components are the re-circulating diode and the LM22676 regulator IC. The easiestmethod to determine the power dissipation within theLM22676 is to measure the total conversion losses (Pin –Pout) then subtract the power losses in the Schottky diodeand output inductor. An approximation for the Schottky diodeloss is:P = (1 - D) x IOUTx VDAn approximation for the output inductor power is:P = IOUT2 x R x 1.1,where R is the DC resistance of the inductor and the 1.1 factoris an approximation for the AC losses. The regulator has anexposed thermal pad to aid power dissipation. Adding severalvias under the device to the ground plane will greatly reducethe regulator junction temperature. Selecting a diode with anexposed pad will aid the power dissipation of the diode. Themost significant variables that affect the power dissipated bythe LM22676 are the output current, input voltage and oper-ating frequency. The power dissipated while operating nearthe maximum output current and maximum input voltage canbe appreciable. The junction-to-ambient thermal resistance ofthe LM22676 will vary with the application. The most signifi-cant variables are the area of copper in the PC board, thenumber of vias under the IC exposed pad and the amount offorced air cooling provided. The integrity of the solder con-nection from the IC exposed pad to the PC board is critical.Excessive voids will greatly diminish the thermal dissipationcapacity. The junction-to-ambient thermal resistance of theLM22676 TO-263 THIN and PSOP-8 packages are specifiedin the electrical characteristics table under the applicable con-ditions. For more information regarding the TO-263 THINpackage, refer to Application Note AN-1797 at.LM22676。

内存同步

关于内存频率、内存带宽、CPU外频、FSB之间的关系现在的单通道内存控制器一般都是64bit的，8个2进制bit 相当于1个字节，换算成字节是64/8=8，再乘以内存的运行频率，如果是DDR内存就要再乘以2，因为它是以sd内存双倍的速度传输数据的，所以DDR266,运行频率为133MHz，带宽为133*2*64/8=2100MB/s=2.1GB/sDDR333,运行频率为166MHz，带宽为166*2*64/8=2700MB/s=2.7GB/sDDR400,运行频率为200MHz，带宽为200*2*64/8=3200MB/s=3.2GB/s所谓双通道DDR，就是芯片组可以在两个不同的数据通道上分别寻址、读取数据。

这两个相互独立工作的内存通道是依附于两个独立并行工作的，位宽为64-bit的内存控制器下，因此使普通的DDR内存可以达到128-bit的位宽，因此，内存带宽是单通道的两倍，因此双通道DDR266的带宽为133*2*64/8*2=4200MB/s=4.2GB/s双通道DDR333的带宽为166*2*64/8*2=5400MB/s=5.4GB/s双通道DDR400的带宽为200*2*64/8*2=6400MB/s=6.4GB/s关于瓶径问题：CPU与北桥芯片之间的数据传输速率称前端总线(FSB），对于intel的主流平台，其采用Q/P总线技术，FSB=CPU外频*4,如赛扬4的外频为100，其FSB为400，数据带宽为3.2GB/s,P4A 的外频为100，其FSB为400，数据带宽为3.2GB/s,P4B的外频为133，其FSB为533，数据带宽为4.2GB/s,P4C、P4E的外频为200，其FSB为800，数据带宽为6.4GB/s，对于AMD的主流平台，其采用EV6总线技术,FSB=CPU外频*2，对于Athlon XP，其外频为133，166，200，对应的FSB分别为266，333，400，数据带宽分别为2.1，2.7，3.2GB/sFSB与内存带宽相等的情况下，则不存在瓶径问题，如果内存带宽小于FSB则形成内存带宽瓶径，无法完全发挥系统的性能。

3906;中文规格书,Datasheet资料

Mass Dimensions Material of impeller Housing material Direction of air flow Direction of rotation Bearing Lifetime L10 at 40 °C Lifetime L10 at maximum temperature Connection line Motor protection Approval
3906
AC axial compact fan
ebm-papst St. Georgen GmbH & Co. KG Hermann-Papst-Straße 1 D-78112 St. Georgen Phone +49 7724 81-0 Fax +49 7724 81-1309 info2@
Web data sheet XI · Page 2 of 4 ebm-papst St. Georgen GmbH & Co. KG · Hermann-Papst-Straße 1 · D-78112 St. Georgen · Phone +49 7724 81-0 · Fax +49 7724 81-1309 · info2@ ·
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3906
AC axial compact fan
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50
60
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66572资料

April 1996NEC Electronics Inc.A10616EU1V0DS00CMOS-8LHD3.3-Volt, 0.5-Micron CMOS Gate ArraysPreliminary DescriptionNEC's CMOS-8LHD gate-array family combines cell-based-level densities with the fast time-to-market and low development costs of gate arrays. With a unique heterogeneous cell architecture, CMOS-8LHD provides the very dense logic and RAM capabilities required to build devices for fast computer and communications systems.NEC delivers high-speed, 0.5-micron, drawn gate length (Leff=0.35-micron), three-level metal, CMOS technology with an extensive family of macros. I/O macros include GTL, HSTL, and pECL. TTL CMOS I/Os are provided with 5-V tolerance for applications requiring interface to 5-V logic. PCI signaling standards are also supported,including 3.3-V, 66 MHz PCI. The technology is enhanced by a set of advanced features, including phase-locked loops, clock tree synthesis, and high-speed memory. The CMOS-8LHD gate-array family of 3.3-V devices consists of 12 masters, offered in densities of 75K raw gates to 1.123 million raw gates. Usable gates range from 45K to 674K used gates.The gate-array family is supported by NEC's OpenCAD ®design system, a mixture of popular third-party EDA tools,and proprietary NEC tools. NEC proprietary tools include the GALET floorplanner, which helps to reduce design time and improve design speed, and a clock tree synthesis tool that automatically builds a balanced-buffer clock tree to minimize on-chip clock skew.Figure 1. CMOS-8LHD Package Options: BGA & QFPTable 1. CMOS-8LHD Family Features and BenefitsCMOS-8LHD ApplicationsThe CMOS-8LHD family is ideal for use in personal computer systems, engineering workstations, and telecommunications switching and transmission systems, where extensive integration and high speeds are primary design goals. With power dissipation of 0.21 µW/MHz/gate, CMOS-8LHD is also suited for lower-power applications where high performance is required.OpenCAD is a registered trademark of NEC Electronics Inc.CMOS-8LHD2Cell-Based Array ArchitectureThe CMOS-8LHD gate-array family is built with the Cell-Based Array (CBA) architecture licensed from the Silicon Architects Group of Synopsys. CBA architecture uses two types of cells: compute cells and drive cells.This heterogeneous cell architecture enables very high-density design. Compute cells are used to optimize intramacro logic. Drive cells are optimized for intermacro interconnect. The two cell types are also used to build macros with up to three different power/performance/area points.CBA has a rich macrocell library that is optimized for synthesis. RAM blocks are efficiently created from the CBA architecture, using compute cells as memory cores, and sense amplifiers and drive cells as word and address predecoder drivers.As shown in Figure 2, CBA is divided into I/O and array regions. The I/O region contains input and output buffers. The array region contains the gates used to build logic, RAM blocks, and other design features.Power Rail ArchitectureCMOS-8LHD provides additional flexibility for mixedvoltage system designs. As shown in Figure 2, the arrays contain two power rails: a 3.3-V rail, and V DD2.The V DD2 rail is used for interfaces such as 5-V PCI buffers where a clamping diode allows protection for up to an 11-V voltage spike, per the PCI revision 2.1specification.Figure 2. CBA Layout and Cell ConfigurationThe V DD2 rail is separated into sections to give flexibility for including two or more buses requiring special I/O voltage on one device. Each section can operate as an independent voltage zone, and sections can be linked together to form common voltage zones.Packaging and TestNEC utilizes BIST test structures for RAM testing. NEC also offers advanced packaging solutions including Plastic Ball Grid Arrays (PBGA), Plastic Quad Flat Packs (PQFP), and Pin Grid Arrays (PGA). Please call your local NEC ASIC design center representative for a listing of available master/package combinations.PublicationsThis data sheet contains preliminary specifications for the CMOS-8LHD gate-array family. Additional infor-mation will be available in NEC's CMOS-8LHD Block Library and CMOS-8LHD Design Manual . Call your local NEC ASIC design center representative or the NEC literature line for additional ASIC design information; see the back of this data sheet for locations and phone numbers.Table 2. CMOS-8LHD Base Array Line-upDevice Raw Gates Used Gates (1)Total Pads66562750404502416466563997925987518866565125216751292126656617963210777925266568202400121440268665692681281608763086657029792017875232466571359744215845356665725008643005184206657362054437232646866575802240481344532(1) Actual gate utilization varies depending on circuit implementation.Utilization is 60% for 3LM.3CMOS-8LHDInput/Output CapacitanceV DD =V I =0-V; f =1 MHzTerminal Symbol Typ Max Unit Input C IN 1020pF Output C OUT 1020pF I/OC I/O1020pF(1)Values include package pin capacitancePower ConsumptionDescription Limits Unit Internal gate (1)0.21µW/MHz Input buffer 2.546µW/MHz Output buffer10.60µW/MHzAbsolute Maximum RatingsPower supply voltage, V DD –0.5 to +4.6-VInput voltage, V I3.3-V input buffer (at V I < V DD + 0.5-V)–0.5 to +4.6-V 3.3-V fail-safe input buffer (at V I < V DD + 0.5-V)–0.5 to +4.6-V 5 V-tolerant (at V I < V DD + 3.0-V)–0.5 to +4.6-V Output Voltage, V O3.3-V output buffer (at V O < V DD + 0.5-V)–0.5 to +4.6-V 5-V-tolerant output buffer (at V O < V DD + 3.0-V)–0.5 to +4.6-V 5-V open-drain output buffer (at V O < V DD + 3.0-V)–0.5 to +4.6-VLatch-up current, I LATCH >1 A (typ)Operating temperature, T OPT –40 to +85°C Storage temperature, T STG–65 to +150°C (1) Assumes 30% internal gate switching at one timeCaution: Exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The device should not be operated outside the recommended operating conditions.Recommended Operating ConditionsV DD = 3.3-V ±0.165-V; T j = 0 to +100°C3.3-V Interface 5-V Interface5-V PCI 3.3-V PCIBlock BlockLevel LevelParameterSymbol Min Max Min Max Min Max Min Max Unit I/O power supply voltage V DD 3.0 3.6 3.0 3.6 3.0 5.5 3.0 3.6V Junction temperature T J 0+1000+1000+1000+100°C High-level input voltage V IH 2.0V DD 2.0 5.5 2.0V CC 0.5 V CCV CC V Low-level input voltage V IL 00.800.800.800.3 V CCV Positive trigger voltage V P 1.50 2.70 1.50 2.70————V Negative trigger voltage V N 0.60 1.60.60 1.6————V Hysteresis voltage V H 1.10 1.3 1.10 1.3————V Input rise/fall time t R , t F 0200020002000200ns Input rise/fall time, Schmittt R , t F1010————nsAC CharacteristicsV DD = 3.3-V ±0.3-V; T j = –40 to +125°C ParameterSymbol MinTypMax Unit Conditions Toggle frequency (F611)f TOG356MHzD-F/F; F/O = 2 mmDelay time2-input NAND (F322)t PD181ps F/O = 1; L = 0 mmt PD 186ps F/O = 2; L = typ (0.42 mm)Flip-flop (F611)t PD 573ps F/O = 1; L = 0 mm t PD 688ps F/O = 2; L = typ t SETUP 410ps —t HOLD 540ps —Input buffer (FI01)t PD 268ps F/O = 1; L = 0 mm t PD 312ps F/O = 2; L = typ Output buffer (9 mA) 3.3-V (FO01)t PD 1.316ns C L = 15 pF Output buffer (9 mA) 5-V-tolerant (FV01)t PD 1.228ns C L = 15 pF Output buffer (9 mA) 5-V-swing (FY01)t PD 1.517ns C L = 15 pF Output rise time (9 mA) (FO01)t R 1.347ns C L = 15 pF Output fall time (9 mA) (FO01)t F1.284nsC L = 15 pFCMOS-8LHD4(3)Rating is for only one output operating in this mode for less than 1 second.(4)Normal type buffer: I OH < I OL .(5)Balanced buffer: I OH = I OL .(6)Resistor is called 50ký to maintain consistency with previous families.Notes:(1)Static current consumption increases if an I/O block with on-chip pull-up/pull-down resistor or an oscillator is used. Call an NEC ASIC design center repre-sentative for assistance in calculation.(2)Leakage current is limited by tester capabilities. Specification listed representsthis measurement limitation. Actual values will be significantly lower.DC CharacteristicsV DD = 3.3-V ±0.165-V; T j = 0 to +100°C ParameterSymbol Min Typ Max Unit Conditions Quiescent current (1)µPD66578I DDS 2.0300µA V I = V DD or GND µPD66575, 66573, 66572I DDS 1.0300µA V I = V DD or GND Remaining mastersI DDS 0.5200µA V I = V DD or GND Off-state output leakage current3.3-V buffers, 3.3-V PCII OZ ±10µA V O = V DD or GND 5-V-tolerant buffers, 5-V PCI I OZ ±14µA V O = V DD or GND 5-V open-drainI OZ ±14µA V O = V DD or GND Output short circuit current (3)I OS –250mA V O = GND Input leakage current (2)5-V PCI I IH +70, –70µA V IN = 2.7-V, 0.5-V 3.3-V PCI I I ±10µA V IN = V DD or GND RegularI I ±10–5±10µA V I = V DD or GND 50 k Ω pull-up I I –180–40µA V I = GND 5 k Ω pull-up I I –1400–350mA V I = GND 50 k Ω pull-down I I 30160µA V I = V DDResistor values50 k Ω pull-up (6)R pu 2075k Ω5 k Ω pull-upR pu 2.68.6k Ω50 k Ω pull-down (6)R pu 22.5100k ΩInput clamp voltageV IC –1.2V I I = 18 mA Low-level output current (ALL buffer types)3 mA I OL 3mA V OL = 0.4-V 6 mA I OL 6mA V OL = 0.4-V 9 mA I OL 9mA V OL = 0.4-V 12 mA I OL 12mA V OL = 0.4-V 18 mA I OL 18mA V OL = 0.4-V 24 mAI OL 24mA V OL = 0.4-V High-level output current (5-V-tolerant block)3 mA I OH –3mA V OH = V DD –0.4-V 6 mA I OH –3mA V OH = V DD –0.4-V 9 mA I OH –3mA V OH = V DD –0.4-V 12 mA I OH –3mA V OH = V DD –0.4-V 18 mA I OH –4mA V OH = V DD –0.4-V 24 mAI OH –4mA V OH = V DD –0.4-V High-level output current (3.3-V interface block)3 mA I OH –3mA V OH = V DD –0.4-V 6 mA I OH –6mA V OH = V DD –0.4-V 9 mA I OH –9mA V OH = V DD –0.4-V 12 mA I OH –12mA V OH = V DD –0.4-V 18 mA I OH -18mA V OH = V DD –0.4-V 24 mAI OH -24mA V OH = V DD –0.4-V Output voltage (5-V PCI)High-level output voltage V OH 2.4mA I OH = 2 mALow-level output voltage V OL 0.55mA I OL = 3 mA, 6 mA Output voltage (3.3-V PCI)High-level output voltage V OH 0.9 V DDmA I OH = 500 µA Low-level output voltage V OL 0.1 V DDmA I OL = 1500 µA Low-level output voltageV OL 0.1V I OL = 0 mA High-level output voltage, 5-V TTL V OH V DD –0.2V I OL = 0 mA High-level output voltage, 3.3-VV OHV DD –0.1VI OH = 0 mACMOS-8LHD5CMOS-8LHD6Document No. A10616EU1V0DS00For literature, call toll-free 7 a.m. to 6 p.m. Pacific time: 1-800-366-9782or FAX your request to: 1-800-729-9288©1996 NEC Electronics Inc./Printed in U.S.A.NEC ASIC DESIGN CENTERSWEST•3033 Scott Boulevard Santa Clara, CA 95054TEL 408-588-5008FAX 408-588-5017•One Embassy Centre9020 S.W. Washington Square Road,Suite 400Tigard, OR 97223TEL 503-671-0177FAX 503-643-5911THIRD-PARTY DESIGN CENTERSSOUTH CENTRAL/SOUTHEAST•Koos Technical Services, Inc.385 Commerce Way, Suite 101Longwood, FL 32750TEL 407-260-8727FAX 407-260-6227•Integrated Silicon Systems Inc.2222 Chapel Hill Nelson Highway Durham, NC 27713TEL 919-361-5814FAX 919-361-2019•Applied Systems, Inc.1761 W. Hillsboro Blvd., Suite 328Deerfield Beach, FL 33442TEL 305-428-0534FAX 305-428-5906NEC Electronics Inc.CORPORATE HEADQUARTERS2880 Scott Boulevard P.O. Box 58062Santa Clara, CA 95052TEL 408-588-6000No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics Inc. (NECEL). The information in this document is subject to change without notice. ALL DEVICES SOLD BY NECEL ARE COVERED BY THE PROVISIONS APPEARING IN NECEL TERMS AND CONDITIONS OF SALES ONLY. INCLUDING THE LIMITATION OF LIABILITY,WARRANTY, AND PATENT PROVISIONS. NECEL makes no warranty, express, statutory, implied or by description, regarding informa-tion set forth herein or regarding the freedom of the described devices from patent infringement. NECEL assumes no responsibility for any errors that may appear in this document. NECEL makes no commitments to update or to keep current information contained in this document. The devices listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems,aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. “Standard” quality grade devices are recommended for computers, office equipment, communication equipment, test and measurement equipment, machine tools,industrial robots, audio and visual equipment, and other consumer products. For automotive and transportation equipment, traffic control systems, anti-disaster and anti-crime systems, it is recommended that the customer contact the responsible NECEL salesperson to determine the reliabilty requirements for any such application and any cost adder. NECEL does not recommend or approve use of any of its products in life support devices or systems or in any application where failure could result in injury or death.If customers wish to use NECEL devices in applications not intended by NECEL, customer must contact the responsible NECEL sales people to determine NECEL’s willingness to support a given application.SOUTH CENTRAL/SOUTHEAST•16475 Dallas Parkway, Suite 380Dallas, TX 75248TEL 972-735-7444FAX 972-931-8680•Research Triangle Park2000 Regency Parkway, Suite 455Cary, NC 27511TEL 919-460-1890FAX 919-469-5926•Two Chasewood Park 20405 SH 249, Suite 580Houston, TX 77070TEL 713-320-0524FAX 713-320-0574NORTH CENTRAL/NORTHEAST•The Meadows, 2nd Floor 161 Worcester Road Framingham, MA 01701TEL 508-935-2200FAX 508-935-2234•Greenspoint Tower2800 W. Higgins Road, Suite 765Hoffman Estates, IL 60195TEL708-519-3945FAX 708-882-7564。

6732中文资料

Features:Allows user to safely make floatinghigh voltage measurements whileusing general purpose oscilloscopes.Maximum differential voltage up to1000V.Differential amplifier converts andscales floating input signal to a low-voltage signal referenced to earthground.The probe can be used on circuitsassociated with electronic high-powerconverters, motor speed controllers,switching power supplies, and otherhigh voltage circuits requiringisolation.Switchable attenuation settings.High impedance to ground for both positive and negative sides of the balanced input.Input uses shrouded banana test probe tip.Probe tip accepts large alligator c lips and pin-grabber test clips (included).The output to the oscilloscope is a BNC cable with a safety insulated BNC male connector.Optional Universal Power Adapter.Specifications:Input CharacteristicsInput Probe Tip Style: Shrouded banana probe tipProbe Cable Length: 1.5 meter (60 inch)600V CAT III1000V CAT IIInstallation Category III refers to distribution level and fixed installation circuits inside a building. Installation Category II refers to local level, which is applicable for appliances, and portable equipment.1000 VDC, or1000 Vrms, or1200V (DC+AC peak)Note:(DC+AC peak) limit is determined by the point at which the differential voltage probe starts clipping.For derating of each input probe (red or black), see figure below.Output CharacteristicsOutput Cable: Safety designed BNC cableCable Length: 0.5 meter (20 inch)Max. Output Voltage Range: 6.5V into 1 MElectrical CharacteristicsAttenuation: 200x and 20xBandwidth: (into 1 M , 50 pF)200x: DC to 20 MHz (-3 dB)20x: DC to 20 MHz (-3 dB)Rise time:200x: 17.5 ns20x: 17.5 nsCMRR:200x: @60Hz= >80 dB, @1 MHz= >50 dB20x: @60Hz= >70 dB, @1 MHz= >40 dBInput Impedance:Between each input to shielding BNC: 5 M , 6 pFBetween the inputs: 10 M , 5 pFOutput Impedance: 50Noise:200x: <2 mVrms20x: <3 mVrmsOffset:10 mV into 1 MSwitch positions: OFF, 200x, 20xPowerExternal:Via power adapter 6732 (optional)Internal:Battery Power: Alkaline 9V, IEC6LR61Battery life measured @ 25 C with Duracell® alkaline battery. (Delivered with probe.)Battery Life: 8 hour operation400 hour in auto standbyPower indicators:Green LED: ON at normal operation.Blinks in standby.Red LED: ON when battery needs to be replacing. (To change from standby to normal operation turn switch from OFF to 20x or 200x.)Auto Stand By:After 30 minutes, only when battery operatedEnvironmentalMeets requirements of:MIL-T-28800E, Type III, Class 3.EN 50081-1, Electromagnetic Compatibility Generic Emission Standard: EN55022 and EN60555-2.EN 50082-2, Electromagnetic Compatibility Generic Immunity Standard: IEC801-2, -3, -4, -5. (see also Tables 1 and 2) This product is in conformity with Electromagnetic Compatibility Directive 89/336/EEC and Low Voltage Directive73/23/EEC.This conformity is indicated by the symbol , i.e. “Conformité Européenne”.Temperature:Operating: 0C to +50C (+32F to +122F)Storage: -10C to +60C (+14F to +140F)Altitude:Operating: 3 km (9850 feet)Storage: 12 km (40 000 feet)Safety SpecificationsMeets requirements of:EN61010-2-31 (IEC1010-2-31).Compliant with:UL3111-1 (including listing)CSA C22.2 No.1010.1-92 (including approval)Max. Floating Output Voltage:600V Category III, up to 400 Hz. (From shielding to ground)The 6731 conforms with the EEC directive 89/336 for EMC immunity, as defined by IEC801-3, with the addition of the following tables.Optional power adapter:Universal 115V/230V: Model 6732。

台电U盘工具

中文名:晶彩系列
英文名:
型号:CF512/1GB/2GB/4GB/8GBNCU-W2/B2 CF512NCA-B2
详细资料:更多产品>>
详细资料：
台电晶彩酷闪-CoolFlash Driver(USB Flash Disk)是一种基于闪存技术的移动存储产品。

晶彩u盘拥有十分精良的做工技术。

其深蓝色透明外壳使用最新的超声波无缝焊接技术，内壁采用喷砂工艺，牢固且耐磨损，具有极强的抗震性能。

盘体采用超薄设计，纤巧精致让人不得不感叹台电科技的产品工艺技术；USB帽采用紧缩工艺设计，能够有效防止松脱或丢失；先进的绝缘隔离设计，能够有效的防止静电和灰尘的侵袭；采用顶级闪存芯片，配合一流水准的电路设计，保证了晶彩系列U盘产品的实际可存储容量非常充分，比同类产品的实际可用存储容量要高很多；支持USB 2.0高速读写，为快速存储提供了有力保证。

晶彩（NCU）系列驱动程序
专用于晶彩NCU系列WIN98驱动程序及启动、分区、加密制作工具(支持Vista)，适用于全系列（注：从包装彩盒右侧面型号贴纸上可查到产品名称）如：CF4GBNCU-B2
ＬＯＣＫ登入程序
此程序主要解决用户将ＬＯＣＫ程序删除后的解决方法，目前适用于欣喜(晶喜)系列、晶灵II代系列、晶彩系列、晶致系列、欣悦系列产品、晶灵III代系列
酷闪修复工具
此修复工具仅适合以下系列：晶彩系列、晶灵II代、天志系列、晶致系列、欣悦系列、欣喜（晶喜）系列、风尚系列、晶灵III代。

66206-2资料

66206-2 Product DetailsHome | Customer Support | Suppliers | Site Map | Privacy Policy | Browser Support© 2008 Tyco Electronics Corporation All Rights Reserved SearchProducts Documentation Resources My Account Customer Support Home > Products > By Type > Product Feature Selector > Product DetailsNo Image Available66206-2Active Taper Pins and BlocksNot reviewed for RoHS ComplianceProduct Highlights:?Taper Pins?Pin Type = Solid?Pin Style = Standard?53 Series?Loose PieceView all Features | Find SimilarProductsCheck Pricing &AvailabilitySearch for ToolingProduct FeatureSelectorContact Us AboutThis ProductQuick LinksDocumentation & Additional InformationProduct Drawings:?PIN, TAPER, ''53'' SERIES UNINSULATED(PDF, English)Catalog Pages/Data Sheets:?None AvailableProduct Specifications:?Contact, TAYP-AIR Pins and Blocks(PDF, English)?Contact, Taper Pins(PDF, English)Application Specifications:?None AvailableInstruction Sheets:?None AvailableCAD Files:?None AvailableList all Documents Additional Information:?Product Line InformationRelated Products:?ToolingProduct Features (Please use the Product Drawing for all design activity)Product Type Features:?Product Type = Taper Pins?Insulation Support = Un-Insulated Support?Insulation Diameter (mm [in]) = 1.14 – 1.58[0.045 –0.062]?Finish = Gold (30)?Comment = For Stranded Wire Only.Body Related Features:?Pin Type = Solid?Pin Style = Standard?Series = 53?Wire Range (mm [AWG]) = 0.08-0.24²[28-24] ?Overall Length (mm [in]) = 17.27 [0.680]?Mates With = 53 Series Connector Block Industry Standards:?RoHS/ELV Compliance = Not reviewed forELV/RoHS compliance?Lead Free Solder Processes = Not reviewed forlead free solder processPackaging Related Features:?Packaging Method = Loose PieceOther:?Brand = AMPProvide Website Feedback | Contact Customer Support。

AO9926中文资料

SymbolTyp Max 5662.581110R θJL4048Steady-State °C/W Thermal Characteristics Maximum Junction-to-Lead CSteady-State°C/WParameterUnits Maximum Junction-to-Ambient A t ≤ 10s R θJA °C/W Maximum Junction-to-Ambient A AO9926SymbolMin TypMaxUnits BV DSS 20V 1T J =55°C5I GSS 100nA V GS(th)0.40.61V I D(ON)15A 4050T J =125°C56705465m Ω7290m Ωg FS 11S V SD 0.761V I S2A C iss 436pF C oss 66pF C rss 44pF R g3ΩQ g 5.54nC Q gs 1.26nC Q gd 0.52nC t D(on)5ns t r 7ns t D(off)29ns t f 6.2ns t rr 13.7ns Q rr3.8nCI F =5A, dI/dt=100A/µsI F =5A, dI/dt=100A/µsElectrical Characteristics (T J =25°C unless otherwise noted)ParameterConditions STATIC PARAMETERS Drain-Source Breakdown Voltage I D =250µA, V GS =0V I DSS Zero Gate Voltage Drain Current V DS =16V, V GS =0VµA Gate-Body leakage current V DS =0V, V GS =±8V Gate Threshold Voltage V DS =V GS I D =250µA On state drain currentV GS =10V, V DS =5V R DS(ON)Static Drain-Source On-ResistanceV GS =4.5V, I D =5Am ΩV GS =1.8V, I D =2AV GS =2.5V, I D =4A V GS =0V, V DS =0V, f=1MHzForward TransconductanceV DS =5V, I D =5ADiode Forward Voltage I S =1A,V GS =0V Maximum Body-Diode Continuous CurrentDYNAMIC PARAMETERS Input Capacitance V GS =0V, V DS =10V, f=1MHz Output Capacitance Reverse Transfer Capacitance Turn-On Rise Time Turn-Off DelayTime Gate resistanceBody Diode Reverse Recovery TimeBody Diode Reverse Recovery Charge Turn-Off Fall TimeSWITCHING PARAMETERS Total Gate Charge V GS =4.5V, V DS =10V, I D =5AGate Source Charge Gate Drain Charge Turn-On DelayTime V GS =5V, V DS =10V, R L =2Ω, R GEN =6ΩA: The value of R θJA is measured with the device mounted on 1in 2FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The value in any a given application depends on the user's specific board design. The current rating is based on the t ≤ 10s thermal resistance rating.B: Repetitive rating, pulse width limited by junction temperature.C. The R θJA is the sum of the thermal impedence from junction to lead R θJL and lead to ambient.D. The static characteristics in Figures 1 to 6 are obtained using 80 µs pulses, duty cycle 0.5% max.E. These tests are performed with the device mounted on 1 in 2FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The SOA curve provides a single pulse rating.。

华硕主板

数字家庭主板M2NDH-支持AMD®SocketAM2Athlon64FX/Athlo64X2/Athlon64/Sempron -AMDLive!™Ready-强大扩充能力：1xPCI-Ex16、2xPCI-E、3xPCI-华硕WiFi-APSolo-华硕DHRemote™-华硕MP3-In™-华硕Q-Connector-高保真音频中央处理器支持AMD®SocketAM2Athlon64FX/Athlo64X2/Athlon64/Sempron 支持AMDCool'n'Quiet™技术AMD64架构，同时兼容32位和64位计算AMDLive!™Ready芯片组NVIDIAnForce®430MCP前端总线2000/1600MT/s内存双通道内存架构4x240-pinDIMM内存插槽，支持最大容量高达8GB的DDR2800/667/533ECC和non-ECC、un-buffered内存扩充插槽1xPCI-Expressx16插槽2xPCI-Expressx1插槽3xPCI2.2插槽存储装置/RAID-1xUltraDMA133/100/66/33-4xSerialATA3.0Gb/s-NVIDIAMediaShield™RAID通过SerialA TA设备支持RAID0、1、0+1、5和JBOD网络功能NVIDIAnForce®430内建GigabitMAC，支持externalAttansicPHY无线局域网：54MbpsIEEE802.11b/g（华硕WiFi-APSolo）音频功能ADI6声道高保真音频CODEC背板S/PDIF数字音频输出USB高达8个USB2.0/1.1接口M2N-VMDH-AMDSocketAM2-NVIDIAGeForce6100/nForce430-双通道DDR2800/667/533-1xPCIExpressx16+1xPCIExpressx1+2xPCI-双VGA：DVI-D和D-Sub-8声道高保真音频-2x1394a接口中央处理器支持AMD®SocketAM2Athlon64X2/Athlon64FX/Athlon64/Sempro nAMDCool'n'Quiet™技术AMD64架构，兼容32位和64位计算AMDLive!™Ready芯片组NVIDIAGeForce6100/nForce430前端总线2000/1600MT/s 内存双通道内存架构4x240-pinDIMM插槽，支持最大容量为8GB的DDR2800/667/533non-ECC，un-buffered内存显卡集成GeForce6100GPU高清晰视频处理，最高分辨率可达1920x1440（@75Hz）支持RGB显示；UXGA1600x1200（@60Hz）支持DVI-D显示支持双VGA输出：DVI-D和RGB注意：DVI-D不能用来输出RGB信号至CRT。

NZT6726中文资料

Absolute Maximum Ratings*
Symbol
VCEO VCBO VEBO IC TJ, Tstg Collector-Emitter Voltage Collector-Base Voltage Emitter-Base Voltage Collector Current - Continuous
Test Conditions
Min
Max
Units
OFF CHARACTERISTICS
V(BR)CEO V(BR)CBO V(BR)EBO ICBO IEBO Collector-Emitter Breakdown Voltage Collector-Base Breakdown Voltage Emitter-Base Breakdown Voltage Collector-Cutoff Current Emitter-Cutoff Current I C = 10 mA, IB = 0 I C = 100 µA, I E = 0 I E = 100 µA, IC = 0 VCB = 40 V, IE = 0 VEB = 5.0 V, IC = 0 30 40 5.0 0.1 0.1 V V V µA µA
1 PD - POWER DISSIPATION (W)
0.75
TO-226 SOT-223
0.5
0.25
0
0
25
50 75 100 o TEMPERATURE ( C)
125
150
SMALL SIGNAL CHARACTERISTICS
hfe Ccb Small-Signal Current Gain Collector-Base Capacitance I C = 50 mA, VCE = 10 V, f = 20 MHz VCB = 10 V, IE = 0, f = 1.0 MHz 2.5 25 30 pF

BA6406F-E2中文资料

Appendix
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO.,LTD. The contents described herein are subject to change without notice. The specifications for the product described in this document are for reference only. Upon actual use, therefore, please request that specifications to be separately delivered. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. Products listed in this document are no antiradiation design.

SiI3726CBHU资料

Silicon Image, Inc.
Silicon Image, Inc.
June, 2006
Silicon Image, Inc. reserves the right to make changes to the product(s) or specifications to improve performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable, but Silicon Image, Inc. shall not be responsible for any errors that may appear in this document. Silicon Image, Inc. makes no commitment to update or keep current the information contained in this document. However, no responsibility is assumed for its use; or any infringement of patents or other rights of third parties, which may result from its use. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Silicon Image, Inc. products are not designed or intended for use in Life Support Systems. A Life Support System is a product or system intended to support or sustain life, which if it fails, can be reasonably expected to result in significant personal injury or death. If Buyer or any of its direct or indirect customers applies any product purchased or licensed from Silicon Image, Inc. to any such unauthorized use, Buyer shall indemnify and hold Silicon Image, Inc., its affiliates and their respective suppliers, harmless against all claims, costs, damages and expenses arising directly or indirectly, out of any such unintended or unauthorized use, even if such claims alleges that Silicon Image, Inc. or any other person or entity was negligent in designing or manufacturing the product. Specifications are subject to change without notice

IS61LPS51236A中文资料

Integrated Silicon Solution, Inc. — 1-800-379-47741Rev.D 02/11/05ISSI®Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.IS61VPS25672A IS61LPS25672A IS61VPS51236A IS61LPS51236A IS61VPS102418A IS61LPS102418A FEATURES•Internal self-timed write cycle•Individual Byte Write Control and Global Write •Clock controlled, registered address, data and control •Burst sequence control using MODE input •Three chip enable option for simple depth expansion and address pipelining •Common data inputs and data outputs •Auto Power-down during deselect •Single cycle deselect•Snooze MODE for reduced-power standby •JTAG Boundary Scan for PBGA package •Power SupplyLPS: V DD 3.3V + 5%, V DDQ 3.3V/2.5V + 5%VPS: V DD 2.5V + 5%, V DDQ 2.5V + 5%•JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball PBGA, and 209-ball (x72) packages •Lead-free availableDESCRIPTIONThe ISSI IS61LPS/VPS51236A, IS61LPS/VPS102418A,and IS61LPS/VPS25672A are high-speed, low-power syn-chronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LPS/VPS51236A is organized as 524,288 words by 36 bits, the IS61LPS/VPS102418A is organized as 1,048,576 words by 18 bits, and the IS61LPS/VPS25672A is organized as 262,144 words by 72 bits.Fabricated with ISSI 's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single mono-lithic circuit. All synchronous inputs pass through regis-ters controlled by a positive-edge-triggered single clock input.Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs.Separate byte enables allow individual bytes to be written.The byte write operation is performed by using the byte write enable (BWE ) input combined with one or more individual byte write signals (BWx ). In addition, Global Write (GW ) is available for writing all bytes at one time,regardless of the byte write controls.Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller)input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin.The mode pin is used to select the burst sequence order,Linear burst is achieved when this pin is tied LOW.Interleave burst is achieved when this pin is tied HIGH or left floating.256K x 72, 512K x 36, 1024K x 1818Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAMFEBRUARY 2005FAST ACCESS TIMESymbol Parameter250200Units t KQ Clock Access Time 2.6 3.1ns t KCCycle Time 45ns Frequency250200MHzIS61VPS25672A, IS61LPS25672AIS61VPS51236A,IS61LPS51236A, IS61VPS102418A, IS61LPS102418A ISSI®BLOCK DIAGRAM2Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.D02/11/05Integrated Silicon Solution, Inc. — 1-800-379-47743Rev.D 02/11/05IS61VPS25672A, IS61LPS25672AIS61VPS51236A,IS61LPS51236A, IS61VPS102418A, IS61LPS102418AISSI®165-PIN BGA165-Ball, 13x15 mm BGA 1mm Ball Pitch, 11x15 Ball Array119-PIN BGA119-Ball, 14x22 mm BGA1mm Ball Pitch, 7x17 Ball Array209-BALL BGA209-Ball, 14 mm x 22 mm BGA 1 mm Ball Pitch, 11 x 19 Ball Array4Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.D 02/11/05IS61VPS25672A, IS61LPS25672AIS61VPS51236A,IS61LPS51236A, IS61VPS102418A, IS61LPS102418AISSI®PIN CONFIGURATION — 256K X 72, 209-Ball PBGA (TOP VIEW)1234567891011A DQg DQg A CE2ADSP ADSC ADV CE2A DQb DQbB DQg DQg BW c BW g NC BWE A BW b BW f DQb DQb C DQg DQg BW h BW d NC CE NC BW e BW a DQb DQbD DQg DQg VSS NC NC OE GW NC VSS DQb DQb E DQPg DQPc V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQPf DQPbF DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQfG DQc DQc V DDQ V DDQ V DD NC V DD V DDQ V DDQ DQf DQfH DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf J DQc DQc V DDQ V DDQ V DD NC V DD V DDQ V DDQ DQf DQf K NC NC CLK NC VSS NC VSS NC NC NC NC L DQh DQh V DDQ V DDQ V DD NC V DD V DDQ V DDQ DQa DQa M DQh DQh VSS VSS VSS NC VSS VSS VSS DQa DQa N DQh DQh V DDQ V DDQ V DD NC V DD V DDQ V DDQ DQa DQa P DQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa R DQPd DQPh V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQPa DQPe T DQd DQd VSS NC NC MODE NC NC VSS DQe DQe U DQd DQd NC A A A A A NC DQe DQe V DQd DQd A A A A1A A A DQe DQe WDQdDQdTMSTDIAA0ATDOTCKDQeDQe11 x 19 Ball BGA—14 x 22 mm 2 Body—1 mm Ball PitchPIN DESCRIPTIONSSymbolPin NameA Address InputsA0, A1Synchronous Burst Address Inputs ADV Synchronous Burst Address AdvanceADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLKSynchronous Clock CE , CE2, CE2Synchronous Chip Select BW x (x=a,b,c,d Synchronous Byte Write e,f,g,h)ControlsSymbol Pin Name BWE Byte Write Enable OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection TCK, TDO JTAG PinsTMS, TDI NC No ConnectDQx Data Inputs/Outputs DQPx Data Inputs/Outputs V DD 3.3V/2.5V Power SupplyV DDQIsolated Output Power Supply 3.3V /2.5V VssGroundIntegrated Silicon Solution, Inc. — 1-800-379-47745Rev.D 02/11/05IS61VPS25672A, IS61LPS25672AIS61VPS51236A,IS61LPS51236A, IS61VPS102418A, IS61LPS102418AISSI®119 BGA PACKAGE PIN CONFIGURATION-512K X 36 (TOP VIEW)PIN DESCRIPTIONS1234567A V DDQ A A ADSP A A V DDQB NC A A ADSC A A NC C NC A A V DD A A NC D DQc DQPc Vss NC Vss DQPb DQbE DQc DQc Vss CE Vss DQb DQbF V DDQ DQc Vss OE Vss DQb V DDQG DQc DQc BWc ADV BWb DQb DQbH DQc DQc Vss GW Vss DQb DQb J V DDQ V DD NC V DD NC V DD V DDQ K DQd DQd Vss CLK Vss DQa DQa L DQd DQd BWd NC BWa DQa DQa M V DDQ DQd Vss BWE Vss DQa V DDQ N DQd DQd Vss A 1*Vss DQa DQa P DQd DQPd Vss A 0*Vss DQPa DQa R NC A MODE V DD NC A NC T NC NC A A A NC ZZ UV DDQTMSTDITCKTDONC V DDQ SymbolPin NameA Address InputsA0, A1Synchronous Burst Address Inputs ADV Synchronous Burst Address AdvanceADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock CESynchronous Chip Select BW x (x=a-d)Synchronous Byte Write Controls BWEByte Write EnableSymbol Pin Name OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection TCK, TDO JTAG PinsTMS, TDI NC No Connect DQa-DQd Data Inputs/Outputs DQPa-Pd Output Power Supply V DD Power Supply V DDQ Output Power Supply VssGround Note: * A 0 and A 1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.6Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.D 02/11/05IS61VPS25672A, IS61LPS25672AIS61VPS51236A,IS61LPS51236A, IS61VPS102418A, IS61LPS102418AISSI®119 BGA PACKAGE PIN CONFIGURATION 1M X 18 (TOP VIEW)PIN DESCRIPTIONSNote: * A 0 and A 1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.1234567A V DDQ A A ADSP A A V DDQB NC A A ADSC A A NC C NC A A V DD A A NC D DQb NC Vss NC Vss DQPa NCE NC DQb Vss CE Vss NC DQaF V DDQ NC Vss OE Vss DQa V DDQG NC DQb BWb ADV Vss NC DQaH DQb NC Vss GW Vss DQa NC J V DDQ V DD NC V DD NC V DD V DDQ K NC DQb Vss CLK Vss NC DQa L DQb NC Vss NC BWa DQa NC M V DDQ DQb Vss BWE Vss NC V DDQ N DQb NC Vss A 1*Vss DQa NC P NC DQPb Vss A 0*Vss NC DQa R NC A MODE V DD NC A NC T NC A A NC A A ZZ UV DDQTMSTDITCKTDONC V DDQ SymbolPin NameA Address InputsA0, A1Synchronous Burst Address Inputs ADV Synchronous Burst Address AdvanceADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock CESynchronous Chip Select BW x (x=a,b)Synchronous Byte Write Controls BWEByte Write EnableSymbol Pin Name OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection TCK, TDO JTAG PinsTMS, TDI NC No Connect DQa-DQb Data Inputs/Outputs DQPa-Pb Output Power Supply V DD Power Supply V DDQ Output Power Supply VssGroundIntegrated Silicon Solution, Inc. — 1-800-379-47747Rev.D 02/11/05IS61VPS25672A, IS61LPS25672AIS61VPS51236A,IS61LPS51236A, IS61VPS102418A, IS61LPS102418AISSI®PIN DESCRIPTIONS165 PBGA PACKAGE PIN CONFIGURATION512K X 36 (TOP VIEW)Note: * A 0 and A 1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.1234567891011A NC A CE BWc BWb CE2BWE ADSC ADV A NC B NC A CE2BWd BWa CLK GW OE ADSP A NC C DQPc NC V DDQ Vss Vss Vss Vss Vss V DDQ NC DQPbD DQc DQc V DDQ V DD Vss Vss Vss V DD V DDQ DQb DQbE DQc DQc V DDQ V DD Vss Vss Vss V DD V DDQ DQb DQbF DQc DQc V DDQ V DD Vss Vss Vss V DD V DDQ DQb DQbG DQc DQc V DDQ V DD Vss Vss Vss V DD V DDQ DQb DQbH NC Vss NC V DD Vss Vss Vss V DD NC NC ZZ J DQd DQd V DDQ V DD Vss Vss Vss V DD V DDQ DQa DQa K DQd DQd V DDQ V DD Vss Vss Vss V DD V DDQ DQa DQa L DQd DQd V DDQ V DD Vss Vss Vss V DD V DDQ DQa DQa M DQd DQd V DDQ V DD Vss Vss Vss V DD V DDQ DQa DQa N DQPd NC V DDQ Vss NC A Vss Vss V DDQ NC DQPaP NC NC A A TDI A 1*TDO A A A A RMODENCAATMSA 0*TCKAAAASymbol Pin NameA Address InputsA0, A1Synchronous Burst Address Inputs ADV Synchronous Burst Address AdvanceADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLKSynchronous Clock CE , CE2, CE2Synchronous Chip SelectBW x (x=a,b,c,d)Synchronous Byte WriteControlsSymbol Pin Name BWE Byte Write Enable OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection TCK, TDO JTAG PinsTMS, TDI NC No ConnectDQx Data Inputs/Outputs DQPx Data Inputs/Outputs V DD 3.3V/2.5V Power SupplyV DDQIsolated Output Power Supply 3.3V /2.5V VssGround8Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.D 02/11/05IS61VPS25672A, IS61LPS25672AIS61VPS51236A,IS61LPS51236A, IS61VPS102418A, IS61LPS102418AISSI®Note: * A 0 and A 1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.165 PBGA PACKAGE PIN CONFIGURATION1M X 18 (TOP VIEW)PIN DESCRIPTIONS1234567891011A NC A CE BWb NC CE2BWE ADSC ADV A A B NC A CE2NC BWa CLK GW OE ADSP A NC C NC NC V DDQ Vss Vss Vss Vss Vss V DDQ NC DQPa D NC DQb V DDQ V DD Vss Vss Vss V DD V DDQ NC DQa E NC DQb V DDQ V DD Vss Vss Vss V DD V DDQ NC DQa F NC DQb V DDQ V DD Vss Vss Vss V DD V DDQ NC DQa G NC DQb V DDQ V DD Vss Vss Vss V DD V DDQ NC DQa H NC Vss NC V DD Vss Vss Vss V DD NC NC ZZ J DQb NC V DDQ V DD Vss Vss Vss V DD V DDQ DQa NC K DQb NC V DDQ V DD Vss Vss Vss V DD V DDQ DQa NC L DQb NC V DDQ V DD Vss Vss Vss V DD V DDQ DQa NC M DQb NC V DDQ V DD Vss Vss Vss V DD V DDQ DQa NC N DQPb NC V DDQ Vss NC A Vss Vss V DDQ NC NC P NC NC A A TDI A 1*TDO A A A A RMODENCAATMSA 0*TCKAAAASymbol Pin NameA Address InputsA0, A1Synchronous Burst Address Inputs ADV Synchronous Burst Address AdvanceADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLKSynchronous Clock CE , CE2, CE2Synchronous Chip Select BW x (x=a,b)Synchronous Byte Write ControlsSymbol Pin NameBWE Byte Write Enable OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection TCK, TDO JTAG PinsTMS, TDI NC No ConnectDQx Data Inputs/Outputs DQPx Data Inputs/Outputs V DD 3.3V/2.5V Power SupplyV DDQIsolated Output Power Supply 3.3V/2.5V VssGroundIntegrated Silicon Solution, Inc. — 1-800-379-47749Rev.D 02/11/05IS61VPS25672A, IS61LPS25672AIS61VPS51236A,IS61LPS51236A, IS61VPS102418A, IS61LPS102418AISSI®PIN DESCRIPTIONSA0, A1Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus.A Synchronous Address Inputs ADSC Synchronous Controller Address StatusADSP Synchronous Processor Address StatusADV Synchronous Burst Address Advance BWa -BWd Synchronous Byte Write Enable BWESynchronous Byte Write EnableCE , CE2, CE2Synchronous Chip Enable CLKSynchronous ClockDQa-DQd Synchronous Data Input/Output DQPa-DQPd Parity Data Input/OutputGW Synchronous Global Write Enable MODE Burst Sequence Mode Selection OE Output EnableV DD 3.3V/2.5V Power Supply V DDQ Isolated Output Buffer Supply:3.3V/2.5V Vss Ground ZZSnooze EnablePIN CONFIGURATION100-PIN TQFP10Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.D 02/11/05IS61VPS25672A, IS61LPS25672AIS61VPS51236A,IS61LPS51236A, IS61VPS102418A, IS61LPS102418AISSI®PIN CONFIGURATIONPIN DESCRIPTIONSA0, A1Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus.A Synchronous Address Inputs ADSC Synchronous Controller Address Status ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa -BWb Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE , CE2, CE2Synchronous Chip EnableCLK Synchronous ClockDQa-DQb Synchronous Data Input/OutputDQPa-DQPb Parity Data I/O; DQPa is parity for DQa1-8; DQPb is parity for DQb1-8GW Synchronous Global Write Enable MODE Burst Sequence Mode Selection OE Output EnableV DD 3.3V/2.5V Power Supply V DDQ Isolated Output Buffer Supply:3.3V/2.5V Vss Ground ZZSnooze Enable100-PIN TQFPTRUTH TABLE(1-8)(3CE option)OPERATION ADDRESS CE CE2CE2ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power-Down None H X X L X L X X X L-H High-Z Deselect Cycle, Power-Down None L X L L L X X X X L-H High-Z Deselect Cycle, Power-Down None L H X L L X X X X L-H High-Z Deselect Cycle, Power-Down None L X L L H L X X X L-H High-Z Deselect Cycle, Power-Down None L H X L H L X X X L-H High-Z Snooze Mode, Power-Down None X X X H X X X X X X High-Z Read Cycle, Begin Burst External L L H L L X X X L L-H Q Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z Write Cycle, Begin Burst External L L H L H L X L X L-H D Read Cycle, Begin Burst External L L H L H L X H L L-H Q Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z Read Cycle, Continue Burst Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D NOTE:1.X means “Don’t Care.” H means logic HIGH. L means logic LOW.2.For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for allBWx, BWE, GW HIGH.3.BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s andDQPc. BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s and DQPf. BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are avail-able on the x72 version. DQPa and DQPb are available on the x18 version.DQPa-DQPd are available on the x36 version.4.All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.5.Wait states are inserted by suspending burst.6.For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during theinput data hold time.7.This device contains circuitry that will ensure the outputs will be in High-Z during power-up.8.ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte writeenable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.12Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.D PARTIAL TRUTH TABLEFunction GW BWE BWa BWb BWc BWd BWe BWf BWg BWh Read H H X X X X X X X X ReadH L H H H H H H H H Write Byte 1H L L H H H H H H H Write All Bytes H L L L L L L L L L Write All BytesLXXXXXXXXXTRUTH TABLE (1-8)(1CE option)NEXT CYCLE ADDRESS CE ADSP ADSC ADV WRITE OE DQ Deselected None H X L X X X High-Z Read, Begin Burst External L L X X X L Q Read, Begin Burst External L L X X X H High-Z Write, Begin Burst External L H L X L X D Read, Begin Burst External L H L X H L Q Read, Begin Burst External L H L X H H High-Z Read, Continue Burst Next X H H L H L Q Read, Continue Burst Next X H H L H H High-Z Read, Continue Burst Next H X H L H L Q Read, Continue Burst Next H X H L H H High-Z Write, Continue Burst Next X H H L L X D Write, Continue Burst Next H X H L L X D Read, Suspend Burst Current X H H H H L Q Read, Suspend Burst Current X H H H H H High-Z Read, Suspend Burst Current H X H H H L Q Read, Suspend Burst Current H X H H H H High-Z Write, Suspend Burst Current X H H H L X D Write, Suspend BurstCurrentHXHHLXDNOTE:1.X means “Don’t Care.” H means logic HIGH. L means logic LOW.2.For WRITE , L means one or more byte write enable signals (BWa-h ) and BWE are LOW or GW is LOW. WRITE = H for all BWx , BWE , GW HIGH.3.BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s and DQPf. BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are avail-able on the x72 version. DQPa and DQPb are available on the x18 version.DQPa-DQPd are available on the x36 version.4.All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.5.Wait states are inserted by suspending burst.6.For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time.7.This device contains circuitry that will ensure the outputs will be in High-Z during power-up.8.ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.INTERLEAVED BURST ADDRESS TABLE (MODE = V DD or No Connect) External Address1st Burst Address2nd Burst Address3rd Burst Address A1A0A1A0A1A0A1A000011011010011101011000111100100 LINEAR BURST ADDRESS TABLE (MODE = VSS)ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameter Value UnitT STG Storage Temperature–55 to +150°CP D Power Dissipation 1.6WI OUT Output Current (per I/O)100mAV IN, V OUT Voltage Relative to Vss for I/O Pins–0.5 to V DDQ + 0.5VV IN Voltage Relative to Vss for–0.5 to V DD + 0.5Vfor Address and Control InputsV DD Voltage on V DD Supply Relative to Vss–0.5 to 4.6VNotes:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-nent damage to the device. This is a stress rating only and functional operation of the device atthese or any other conditions above those indicated in the operational sections of thisspecification is not implied. Exposure to absolute maximum rating conditions for extendedperiods may affect reliability.2. This device contains circuity to protect the inputs against damage due to high static voltages orelectric fields; however, precautions may be taken to avoid application of any voltage higher thanmaximum rated voltages to this high-impedance circuit.3. This device contains circuitry that will ensure the output devices are in High-Z at power up.OPERATING RANGE (IS61LPSXXXXX)Range Ambient Temperature V DD V DDQCommercial0°C to +70°C 3.3V + 5% 3.3V / 2.5V + 5%Industrial–40°C to +85°C 3.3V + 5% 3.3V / 2.5V + 5%OPERATING RANGE (IS61VPSXXXXX)Range Ambient Temperature V DD V DDQCommercial0°C to +70°C 2.5V + 5% 2.5V + 5%Industrial–40°C to +85°C 2.5V + 5% 2.5V + 5%DC ELECTRICAL CHARACTERISTICS (Over Operating Range)3.3V 2.5VSymbol Parameter Test Conditions Min.Max.Min.Max.UnitV OH Output HIGH Voltage I OH = –4.0 mA (3.3V) 2.4— 2.0—VI OH = –1.0 mA (2.5V)V OL Output LOW Voltage I OL = 8.0 mA (3.3V)—0.4—0.4VI OL = 1.0 mA (2.5V)V IH Input HIGH Voltage 2.0V DD + 0.3 1.7V DD + 0.3VV IL Input LOW Voltage-0.30.8-0.30.7VI LI Input Leakage Current Vss ≤ V IN≤ V DD(1)-55-55µAI LO Output Leakage Current Vss ≤ V OUT≤ V DDQ,-55-55µAOE = V IHPOWER SUPPLY CHARACTERISTICS(1)(Over Operating Range)-250-200MAX MAXSymbol Parameter Test Conditions Temp. r ange x18x36x72x18x36x72Uni t I CC AC Operating Device Selected,Com.450450600425425550mASupply Current OE = V IH, ZZ ≤ V IL,Ind.500500650475475600All Inputs ≤ 0.2V or ≥ V DD – 0.2V,Cycle Time ≥ t KC min.I SB Standby Current Device Deselected,Com.150150150150150150mATTL Input V DD = Max.,Ind.150150150150150150All Inputs ≤ V IL or ≥ V IH,ZZ ≤ V IL, f = Max.I SBI Standby Current Device Deselected,Com.110110110110110110mACMOS Input V DD = Max.,Ind.125125125125125125V IN≤ V SS + 0.2V or ≥V DD – 0.2Vf = 0I SB2Sleep Mode ZZ>V IH Com.606060606060mAInd.757575757575Note:1.MODE pin has an internal pullup and should be tied to V DD or V SS. It exhibits ±100µA maximum leakage current when tied to ≤V SS + 0.2V or ≥ V DD – 0.2V.14Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.DCAPACITANCE (1,2)Symbol Parameter Conditions Max.Unit C IN Input Capacitance V IN = 0V 6pF C OUTInput/Output CapacitanceV OUT = 0V8pFNotes:1.Tested initially and after any design or process changes that may affect these parameters.2.Test conditions: T A = 25°C, f = 1 MHz, V DD =3.3V.3.3V I/O AC TEST CONDITIONSParameterUnit Input Pulse Level0V to 3.0V Input Rise and Fall Times 1.5 ns Input and Output Timing 1.5V and Reference Level Output LoadSee Figures 1 and 2AC TEST LOADSFigure 2Figure 116Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.D 2.5V I/O AC TEST CONDITIONSParameterUnit Input Pulse Level0V to 2.5V Input Rise and Fall Times 1.5 ns Input and Output Timing 1.25V and Reference Level Output LoadSee Figures 3 and 42.5 I/O OUTPUT LOAD EQUIVALENTFigure 4Figure 3READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)-250 -200Symbol Parameter Min.Max.Min.Max.Unit f MAX Clock Frequency—250—200MHz t KC Cycle Time 4.0—5—ns t KH Clock High Time 1.7—2—ns t KL Clock Low Time 1.7—2—ns t KQ Clock Access Time— 2.6— 3.1ns t KQX(2)Clock High to Output Invalid0.8— 1.5—ns t KQLZ(2,3)Clock High to Output Low-Z0.8—1—ns t KQHZ(2,3)Clock High to Output High-Z— 2.6— 3.0ns t OEQ Output Enable to Output Valid— 2.8— 3.1ns t OELZ(2,3)Output Enable to Output Low-Z0—0—ns t OEHZ(2,3)Output Disable to Output High-Z— 2.6— 3.0ns t AS Address Setup Time 1.2— 1.4—ns t WS Read/Write Setup Time 1.2— 1.4—ns t CES Chip Enable Setup Time 1.2— 1.4—ns t AVS Address Advance Setup Time 1.2— 1.4—ns t DS Data Setup Time 1.2— 1.4—ns t AH Address Hold Time0.3—0.4—ns t WH Write Hold Time0.3—0.4—ns t CEH Chip Enable Hold Time0.3—0.4—ns t AVH Address Advance Hold Time0.3—0.4—ns t DH Data Hold Time0.3—0.4—ns t PDS ZZ High to Power Down—2—2cyc t PUS ZZ Low to Power Down—2—2cyc Note:1. Configuration signal MODE is static and must not change during normal operation.2. Guaranteed but not 100% tested. This parameter is periodically sampled.3.Tested with load in Figure 2.READ/WRITE CYCLE TIMING18Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.DWRITE CYCLE TIMINGSNOOZE MODE ELECTRICAL CHARACTERISTICSSymbol Parameter Conditions Min.Max.UnitI SB2Current during SNOOZE MODE ZZ ≥ Vih—60mAt PDS ZZ active to input ignored—2cycle t PUS ZZ inactive to input sampled2—cycle t ZZI ZZ active to SNOOZE current—2cycle t RZZI ZZ inactive to exit SNOOZE current0—nsSNOOZE MODE TIMING20Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.DIntegrated Silicon Solution, Inc. — 1-800-379-477421Rev.D 02/11/05IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)The IS61LPS/VPSxxxxxx products have a serial boundary scan Test Access Port (TAP) in the PBGA package only.(The TQFP package not available.) This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance.These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels.DISABLING THE JTAG FEATUREThe SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (Vss) to prevent clocking of the device. TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to V DD through a pull-up resistor. TDO should be left disconnected. On power-up, the device will start in a reset state which will not interfere with the device operation.TEST ACCESS PORT (TAP) - TEST CLOCKThe test clock is only used with the TAP controller. All inputs are captured on the rising edge of TCK and outputs are driven from the falling edge of TCK.TEST MODE SELECT (TMS)The TMS input is used to send commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left disconnected if the TAP is not used. The pin is internally pulled up, resulting in a logic HIGH level.TEST DATA-IN (TDI)The TDI pin is used to serially input information to the registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the instruction loaded into the TAP instruction register.For information on instruction register loading, see the TAP Controller State Diagram. TDI is internally pulled up and can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register.TAP CONTROLLER BLOCK DIAGRAM22Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.D 02/11/05TEST DATA OUT (TDO)The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register.PERFORMING A TAP RESETA Reset is performed by forcing TMS HIGH (V DD ) for five rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a high-Z state.TAP REGISTERSRegisters are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry . Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.Instruction RegisterThree-bit instructions can be serially loaded into the instruc-tion register. This register is loaded when it is placed between the TDI and TDO pins. (See TAP Controller Block Diagram)At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as previously described.When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path.Bypass RegisterTo save time when serially shifting data through registers,it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass registeris set LOW (V SS ) when the BYPASS instruction is ex-ecuted.Boundary Scan RegisterThe boundary scan register is connected to all input and output pins on the SRAM . Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 75-bit-long register and the x18 configuration also has a 75-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the Input and Output ring.The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.Identification (ID) RegisterThe ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has vendor code and other information described in the Identification Register Definitions table.Scan Register SizesRegister Bit Size Bit Size Bit Size Name (x18)(x36)(x72)Instruction 333Bypass 111ID323232Boundary S can7575TBDIDENTIFICATION REGISTER DEFINITIONSInstruction Field Description256K x 72512K x 361M x 18Revision N umber (31:28)Reserved for version number.xxxx xxxx xxxx Device D epth (27:23)Defines depth of SRAM. 512K, 1M or 256K 001100011101000Device W idth (22:18)Defines width of the SRAM. x72, x36 or x18001010010000011ISSI Device ID (17:12)Reserved for future use.xxxx xxxxx xxxxx ISSI J EDEC I D (11:1)Allows u nique i dentification o f S RAM v endor.00110101010001101010100011010101ID Register Presence (0)Indicate the presence of an ID register.111。

C6726+Flash+Boot调试笔记

在调试TMS320C6726片外Flash启动时，遇到了许多问题，网上借鉴了很多方法，现在也总结下我们的调试步骤，希望给初学者以帮助。

1.Flash操作采用的Flash芯片是SST39LF200,是128K*16位，硬件连接采用的是EMIF（TMS320C672x DSP External emory Interface (EMIF)）手册上的接法，EM_BA[1]接A[0]。

高4位地址用GPIO来控制。

这里就需要注意：Flash芯片的偏移地址要*2才与DSP芯片上的偏移地址相对应。

其中，EM_A[11:0]给出的是32位字地址的最低有效位，EM_BA[1:0]给出半字(16bit)和字节(8bit)信号，或者给出EM_A[23:22]信号，这取决于A1CR中的数据线宽度配置。

这里数据线宽度为16bit，所以EM_BA[1:0]给出半字和字节信号。

（参看EMIF手册）例如，Flash芯片上的偏移地址0x5555与DSP芯片上的0x9000AAAA 相对应，因此，有以下定义（这两个地址在对Flash操作时要用到）：Uint16 *Flash_Add5555 = (Uint16 *)0x9000AAAA;Uint16 *Flash_Add2AAA = (Uint16 *)0x90005554;剩下的就是flash的erase 和program了，写入相应的关键字就行了，这个不难。

2.flash启动2.1 两个重要的参数（参看手册Using the TMS320C672x Bootloader）：1. The first 8-bits on the flash device gives information about the data bits (8/16) that can beaccessed from the parallel flash simultaneously.2. The first 1024 bytes of data are copied from the FLASH memory into the first 1kBytes ofTMS320C672xx internal memory. The bootloader sets the program counter to 0x10000004 (offset of 0x4 in internal memory) and execution of code begins at this address.所以：1.需要在flash的第一个空间里写入0x0001，表示16位2.具体函数代码从flash的第3个空间开始，即0x22.2 程序小于1KB，如果程序小于1Kb，则不需要second boot。

A67P93361资料

A67P06181/A67P93361Series Preliminary1M X 18, 512K X 36 LVTTL, Flow-through ZeBL TM SRAMDocument Title1M X 18, 512K X 36 LVTTL, Flow-through ZeBL TM SRAMRevision HistoryDate RemarkRev. No. History Issueissue September, 20, 2004 Preliminary0.0 InitialA67P06181/A67P93361Series Preliminary1M X 18, 512K X 36 LVTTL, Flow-through ZeBL TM SRAMFeaturesFast access time: 6.5/7.5/8.5 ns(153, 133, 117 MHz)Zero Bus Latency between READ and WRITE cycles allows 100% bus utilizationSignal +2.5V ± 5% power supplyIndividual Byte Write control capabilityClock enable (CEN) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signalsRegistered output for pipelined applicationsThree separate chip enables allow wide range of options for CE control, address pipeliningInternally self-timed write cycleSelectable BURST mode (Linear or Interleaved)SLEEP mode (ZZ pin) providedAvailable in 100 pin LQFP packageGeneral DescriptionThe AMIC Zero Bus Latency (ZeBL TM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.The A67P06181, A67P93361 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable (CE), two additional chip enables for easy depth expansion (CE2, CE2), cycle start input (ADV/LD), synchronous clock enable (CEN), byte write enables (BW1,BW2,BW3,BW4) and read/write (R/W).Asynchronous inputs include the output enable (OE), clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and burst mode (MODE). Burst Mode can provide either interleaved or linear operation, burst operation can be initiated by synchronous address Advance/Load (ADV/LD) pin in Low state. Subsequent burst address can be internally generated by the chip and controlled by the same input pin ADV/LD in High state.Write cycles are internally self-time and synchronous with the rising edge of the clock input and when R/W is Low. The feature simplified the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3controls I/Oc pins; and BW4controls I/Od pins. Cycle types can only be defined when an address is loaded.The SRAM operates from a +2.5V power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for high bandwidth utilization systems.Pin ConfigurationBlock Diagram (512K X 36)Block Diagram (1M X 18)Pin DescriptionPin Description (continued)Truth Table (Notes 5 - 7)Notes:1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ orWRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is executed first.2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITEAbort means a WRITE command is given, but no operation is performed.3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off theoutput drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not meet their requirements.4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occursduring a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock Edge cycle.5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BW1,BW2,BW3and BW4) are HIGH. BWx = L means one or more byte write signals are LOW.6. BW1enables WRITEs to Byte “a” (I/Oa pins); BW2enables WRITEs to Byte “b” (I/Ob pins); BW3enables WRITEs toByte “c” (I/Oc pins); BW4 enables WRITEs to Byte “d” (I/Od pins).7. The address counter is incremented for all Continue Burst cycles.Partial Truth Table for READ/WRITE Commands (X18)Note : Using R/W and BYTE WRITE(s), any one or more bytes may be written.Partial Truth Table for READ/WRITE Commands (X36)Note : Using R/W and BYTE WRITE(s), any one or more bytes may be written.Linear Burst Address Table (MODE = LOW)(Internal)AddressAddressFirst Address (External) Second(Internal)Third Address (Internal) Fourth X . . . X00 X . . . X01 X . . . X10 X . . . X11X . . . X01 X . . . X10 X . . . X11 X . . . X00X . . . X10 X . . . X11 X . . . X00 X . . . X01X . . . X11 X . . . X00 X . . . X01 X . . . X10 Interleaved Burst Address Table (MODE = HIGH or NC)Address(Internal)(Internal)Third Address (Internal) Fourth First Address (External) SecondAddressX . . . X00 X . . . X01 X . . . X10 X . . . X11X . . . X01 X . . . X00 X . . . X11 X . . . X10X . . . X10 X . . . X11 X . . . X00 X . . . X01X . . . X11 X . . . X10 X . . . X01 X . . . X00Absolute Maximum Ratings*Power Supply Voltage (VCC) . . . . . . . . . . -0.3V to +3.6V Voltage Relative to GND for any Pin Except VCC (Vin, Vout) . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V Operating Temperature (Topr) . . . . . . . . . . . 0°C to 70°C Storage Temperature (Tbias) . . . . . . . . . . -10°C to 85 °C Storage Temperature (Tstg) . . . . . . . . . . -55°C to 125°C *CommentsStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.DC Electrical Characteristics and Operating Conditions(0°C ≤ T A ≤ 70°C, VCC, VCCQ = +2.5V ± 5% unless otherwise noted)Symbol Parameter Conditions Min. Max. Unit NoteV IH Input High Voltage 1.7 VCC+0.3 V 1,2 V IL Input Low Voltage-0.3 0.7 V1,2IL I Input Leakage Current 0V ≤ V IH ≤ VCC -2.02.0µAIL OOutput Leakage CurrentOutput(s) disabled, 0V ≤ V IN ≤ VCC-2.0 2.0 µAV OH Output High Voltage I OH = -1.0mA 2.0 V 1,3 V OLOutput Low VoltageI OL = 1.0mA0.4V 1,3 VCC Supply Voltage 2.375 2.625 V 1 VCCQ Isolated Output Buffer Supply2.375VCCV1,4CapacitanceSymbol Parameter Conditions Typ. Max. Unit Note C I Control Input Capacitance 3 4 pF 6 C OInput/Output Capacitance (I/O)45pF6C A Address Capacitance T A = 25°C; f = 1MHz VCC = 2.5V3 3.5 pF 6Note : 1. All voltages referenced to VSS (GND).2. Overshoot : V IH ≤ +3.6V for t ≤ t KHKH /2 for I ≤ 20mA Undershoot : V IL ≥ -0.7V for t ≤ t KHKH /2 for I ≤ 20mAPower-up : V IH ≤ +2.625V and VCC ≤ 2.375V for t ≤ 200ms3. The load used for V OH , V OL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curves are available upon request.4. VCC and VCCQ can be externally wired together to the same power supply.5. This parameter is sampled.I CC Operating Condition and Maximum LimitsMax.Symbol Parameter-6.5 -7.5 -8.5Unit ConditionsI CC Power Supply Current :OperatingTBD TBD TBD mADevice selected; All inputs ≤ V ILor ≥ V IH; Cycle time ≥ t KC (MIN);VCC = MAX; Output openI SB Standby TBD TBD TBD mA Device deselected; VCC = MAX; All inputs ≤ VSS+0.2 or ≥ VCC-0.2; Cycle time ≥ t KC (MIN)I SB Standby TBD TBD TBD mA Device deselected; VCC = MAX; All inputs ≤VSS+0.2 or ≥ VCC-0.2; All inputs static; CLKfrequency=MAX; ZZ ≥ V CC-0.2VI SB2Standby TBD TBD TBD mA Device deselected; VCC = MAX; All inputs ≤ V IL; or ≥ V IH; All inputs static; CLK frequency=0I SB2Z SLEEPMode TBD TBD TBD mA ZZ≥ V IHAC Characteristics (Note 4)(0°C ≤ T A≤ 70°C, VCC = +2.5V± 5%)Notes: 1. This parameter is sampled.2. Output loading is specified with C1=5pF as in Figure 2.3. Transition is measured ±200mV from steady state voltage.4. OE can be considered a “Don’t Care” during WRITE; however, controlling OE can help fine-tune a system forturnaround timing.5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges ofCLK when ADV/LD is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK (when ADV/LD is LOW) to remain enabled.AC Test ConditionsInput Pulse Levels GND to 2.5V Input Rise and Fall Times 1.0nsInput Timing Reference Levels 1.25V Output Reference Levels 1.25V Output LoadSee Figures 1 and 2Figure 1 Output Load EquivalentFigure 2 Output Load EquivalentSLEEP ModeSLEEP Mode is a low current “Power-down” mode in which the device is deselected and current is reduced to I SB2Z . This duration of SLEEP Mode is dictated by the length of time the ZZ is in a HIGH state. After entering SLEEP Mode, all inputs except ZZ become disabled and all outputs go to High-Z. The ZZ pin is asynchronous, active high input that causes the device to enter SLEEP Mode. When the ZZ pin becomes logic HIGH, ISB2Z is guaranteed after the time t ZZI is met. Any operation pending when entering SLEEP Mode is not guaranteed to successfully complete. Therefore, SLEEP Mode (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SLEEP Mode during t RZZ , only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP Mode.SLEEP Mode Electrical Characteristics(VCC, VCCQ = +2.5V ±5%)Symbol Parameter Conditions Min. Max. Unit Note I SB2Z Current during SLEEP Mode ZZ ≥ V IH - TBD mAt ZZ ZZ active to input ignored 0 2(t KHKH ) ns1 t RZZ ZZ inactive to input sampled 02(t KHKH ) ns 1t ZZI ZZ active to snooze current - 2(t KHKH ) ns 1 t RZZIZZ inactive to exit snooze currentns1Note : 1. This parameter is sampled.SLEEP Mode Waveform: Don't CareREAD/WRITE TimingNote : 1. For this waveform, ZZ is tied LOW.2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BRST operations are optional.3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1.4. Data coherency is provided for all possible operations. If a READ is initiated the most current data is used. The most recent data may be from the input data register.WRITE D(A1)WRITE D(A2)BURST WRITE D(A2+1)READ Q(A3)READ Q(A4)BURST READ Q(A4+1)WRITE D(A5)READ Q(A6)WRITE D(A7)DESELECT: Don't Care: UndefinedCOMMANDNOP, STALL and Deselect CyclesNote : 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CEN being used to create a “pause.” A WRITE isnot performed during this cycle.2. For this waveform, ZZ and OE are tied LOW.3. CE represents three signals. When CE = 0, it represents CE = 0, 2CE = 0, CE2 = 1.4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register.: Don't Care: Undefined12345678910CLK CEN CE ADV/LD R/W BWx ADDRESSI/OOrdering InformationPart No. Configure Cycle Time / Access TimePackageA67P06181E-6.5 7.5ns / 6.5ns A67P06181E-7.5 8.5ns / 7.5ns A67P06181E-8.5 1M X 1810ns / 8.5ns 100L LQFPA67P93361E-6.5 7.5ns / 6.5ns A67P93361E-7.5 8.5ns / 7.5ns A67P93361E-8.5512K X 36 10ns / 8.5ns100L LQFPPackage InformationLQFP 100L Outline Dimensions unit: inches/mmNotes:1. Dimensions D and E do not include mold protrusion.2. Dimensions b does not include dambar protrusion.Total in excess of the b dimension at maximum material condition.Dambar cannot be located on the lower radius of the foot.。

XC6103B626资料

1/26XC6101_07_XC6111_17 ETR0207_009Preliminary◆CMOS Voltage Detector◆Manual Reset Input ◆Watchdog Functions ◆Built-in Delay Circuit ◆Detect Voltage Range: 1.6~5.0V, ± 2% ◆Reset Function is Selectable V DFL (Low When Detected) V DFH (High When Detected)■GENERAL DESCRIPTION The XC6101~XC6107, XC6111~XC6117 series aregroups of high-precision, low current consumption voltage detectors with manual reset input function and watchdog functions incorporating CMOS process technology. The series consist of a reference voltage source, delay circuit, comparator, and output driver.With the built-in delay circuit, the XC6101 ~ XC6107, XC6111 ~ XC6117 series’ ICs do not require any external components to output signals with release delay time. Moreover, with the manual reset function, reset can be asserted at any time. The ICs produce two types of output; V DFL (low when detected) and V DFH (high when detected).With the XC6101 ~ XC6105, XC6111 ~ XC6115 series’ ICs, the WD pin can be left open if the watchdog function is not used. Whenever the watchdog pin is opened, the internal counter clears before the watchdog timeout occurs. Since the manual reset pin is internally pulled up to the V IN pin voltage level, the ICs can be used with the manual reset pin left unconnected if the pin is unused.The detect voltages are internally fixed 1.6V ~ 5.0V in increments of 100mV, using laser trimming technology. Six watchdog timeout period settings are available in a range from 6.25msec to 1.6sec. Seven release delay time 1 are available in a range from 3.13msec to 1.6sec.■APPLICATIONS●Microprocessor reset circuits●Memory battery backup circuits ●System power-on reset circuits ●Power failure detection■TYPICAL APPLICATION CIRCUIT* Not necessary with CMOS output products.■FEATURESDetect Voltage Range: 1.6V ~ 5.0V, +2% (100mV increments)Hysteresis Range : V DF x 5%, TYP .(XC6101~XC6107)V DF x 0.1%, TYP .(XC6111~XC6117)Operating Voltage Range : 1.0V ~ 6.0V Detect Voltage Temperature Characteristics : +100ppm/O C (TYP .) Output Configuration : N-channel open drain,CMOSWatchdog Pin : Watchdog inputIf watchdog input maintains ‘H’ or ‘L’ within the watchdog timeout period, a reset signal is output to the RESET output pinManual Reset Pin : When driven ‘H’ to ‘L’levelsignal, the MRB pin voltage asserts forced reset on theoutput pin.Release Delay Time : 1.6sec, 400msec, 200msec,100msec, 50msec, 25msec, 3.13msec (TYP .) can be selectable.Watchdog Timeout Period : 1.6sec, 400msec, 200msec,100msec, 50msec,6.25msec (TYP .) can be selectable.■TYPICAL PERFORMANCE CHARACTERISTICS ●Supply Current vs. Input Voltage* ‘x’ represents both ‘0’ and ‘1’. (ex. XC61x1⇒XC6101 and XC6111)2/26XC6101~XC6107, XC6111~XC6117 SeriesPIN NUMBERXC6101, XC6102 XC6103 XC6104, XC6105XC6106, XC6107XC6111, XC6112 XC6113 XC6114, XC6115XC6116, XC6117SOT-25 USP-6C SOT-25 USP-6C SOT-25 USP-6C SOT-25USP-6CPIN NAMEFUNCTION1 4 - - 1 4 1 4 R ESETB Reset Output(V DFL : Low Level When Detected)2 5 2 5 2 5 2 5 V SSGround3 2 3 2 - -4 1 M RB ManualReset 4 1 4 1 4 1 - - WDWatchdog5 6 5 6 5 6 5 6 V IN Power Input - - 1 4 3 2 3 2 RESETReset Output (V DFH: High Level When Detected)■PIN CONFIGURATION SOT-25 (TOP VIEW)MRBV IN WD RESETBV SSMRBWD RESETV SSV IN RESETWD RESETBV SS V IN SOT-25 (TOP VIEW)RESETMRB RESETBV SS V IN SOT-25 (TOP VIEW) ■PIN ASSIGNMENT●SOT-25XC6101, XC6102 SeriesXC6111, XC6112 SeriesSOT-25 (TOP VIEW)XC6103 & XC6113 SeriesXC6104, XC6105 Series XC6114, XC6115 SeriesXC6106, XC6107 Series XC6116, XC6117 Series●USP-6CXC6101, XC6102 Series XC6111, XC6112 SeriesXC6103 & XC6113 SeriesXC6104, XC6105 Series XC6114, XC6115 SeriesXC6106, XC6107 Series XC6116, XC6117 SeriesUSP-6C (BOTTOM VIEW)USP-6C (BOTTOM VIEW)USP-6C (BOTTOM VIEW)USP-6C (BOTTOM VIEW)* The dissipation pad for the USP-6C package should be solder-plated in recommended mount pattern and metal masking so as to enhance mounting strength and heat release. If the pad needs to be connected to other pins, it should be connected to the V SS pin.3/26XC6101 ~ XC6107, XC6111~ XC6117SeriesRESET OUTPUTSERIES WATCHDOGMANUAL RESET V DFL (RESETB)V DFH (RESET)XC6101 XC6111 Available Available CMOS - XC6102XC6112AvailableAvailableN-channel open drain-XC6103 XC6113 Available Available - CMOS XC6104 XC6114 Available Not AvailableCMOS CMOS XC6105 XC6115 Available Not Available N-channel open drain CMOS XC6106 XC6116 Not Available AvailableCMOSCMOS XC6107XC6117Not AvailableAvailableN-channel open drainCMOSDESIGNATORDESCRIPTIONSYMBOLDESCRIPTION0 : V DF x 5% (TYP .) with hysteresis ① Hysteresis Range1 : V DF x 0.1% (TYP .) without hysteresis② Functions and Type of Reset Output1 ~ 7: Watchdog and manual functions, and reset output type as per Selection Guide in the above chartA : 3.13msec (TYP .)B : 25msec (TYP .) C: 50msec (TYP .) D : 100msec (TYP .) E : 200msec (TYP .) F : 400msec (TYP .) ③ Release Delay Time * H : 1.6sec (TYP .)0 : No WD timeout period forXC6106, XC6107, XC6116, XC6117 Series 1: 6.25msec (TYP .) 2 : 50msec (TYP .) 3 : 100msec (TYP .) 4 : 200msec (TYP .) 5 : 400msec (TYP .) ④ Watchdog Timeout Period6: 1.6sec (TYP .) ⑤⑥ Detect Voltage 16 ~ 50: Detect voltageex.) 4.5V: ⑤⇒4, ⑥⇒5M : SOT-25 ⑦ Package E : USP-6C R : Embossed tape, standard feed ⑧ Device OrientationL: Embossed tape, reverse feed* Please set the release delay time shorter than or equal to the watchdog timeout period. ex.) XC6101D427MR or XC6101D327MR■PRODUCT CLASSIFICATION ●Selection Guide ●Ordering Information XC61①②③④⑤⑥⑦⑧4/26XC6101~XC6107, XC6111~XC6117 Series■PACKAGING INFORMATION●SOT-25●USP-6C5/26XC6101 ~ XC6107, XC6111~ XC6117Series④ Represents production lot number0 to 9 and A to Z and inverted 0 to 9 and A to Z repeated. (G, I, J, O, Q, W expected.) * ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)■MARKING RULE●SOT-25①②③④SOT-25 (TOP VIEW)6/26XC6101~XC6107, XC6111~XC6117 Series① Represents product series② Represents release delay time MARK RELEASE DELAY TIME PRODUCT SERIES A 3.13msec XC61XxAxxxxx B 25msec XC61XxBxxxxx C 50msec XC61XxCxxxxx D 100msec XC61XxDxxxxx E 200msec XC61XxExxxxx F 400msec XC61XxFxxxxx H 1.6sec XC61XxHxxxxx③ Represents watchdog timeout period MARK WATCHDOG TIMEOUT PERIOD PRODUCT SERIES 0 XC61X6, XC61X7 series XC61Xxx0xxxx 1 6.25msec XC61Xxx1xxxx 2 50msec XC61Xxx2xxxx 3 100msec XC61Xxx3xxxx 4 200msec XC61Xxx4xxxx 5 400msec XC61Xxx5xxxx 6 1.6sec XC61Xxx6xxxx④⑤ Represents detect voltage MARK④ ⑤DETECT VOLTAGE (V)PRODUCT SERIES3 3 3.3 XC61Xxxx33xx 5 0 5.0XC61Xxxx50xx⑥ Represents production lot number0 to 9 and A to Z repeated. (G, I, J, O, Q, W excepted.)* No character inversion used. ** ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)MARK PRODUCT SERIES MARK PRODUCT SERIES 3 XC6101xxxxxx 8 XC6111xxxxxx 4 XC6102xxxxxx 9 XC6112xxxxxx 5 XC6103xxxxxx A XC6113xxxxxx 6 XC6104xxxxxx B XC6114xxxxxx 7 XC6105xxxxxx C XC6115xxxxxx 3 XC6106xxxxxx 8 XC6116xxxxxx 4 XC6107xxxxxx 9 XC6117xxxxxx■MARKING RULE (Continued)●USP-6CUSP-6C (TOP VIEW)7/26XC6101 ~ XC6107, XC6111~ XC6117Series■BLOCK DIAGRAMS●XC6101, XC6111 Series●XC6102, XC6112 Series●XC6103, XC6113 Series8/26XC6101~XC6107, XC6111~XC6117 Series■BLOCK DIAGRAMS (Continued)●XC6107, XC6117 Series●XC6106, XC6116 Series●XC6105, XC6115 Series●XC6104, XC6114 Series9/26XC6101 ~ XC6107, XC6111~ XC6117SeriesPARAMETERSYMBOL RATINGSUNITSV INV SS -0.3 ~ 7.0 VM RBV SS -0.3 ~ V IN +0.3 VInput Voltage WD V SS -0.3 ~ 7.0V Output Current I OUT 20 mACMOS Output RESETB/RESET V SS -0.3 ~ V IN +0.3Output Voltage N-ch Open Drain Output RESETB V SS -0.3 ~ 7.0VSOT-25 250Power Dissipation USP-6C Pd 100mWOperational Temperature Range Topr -40 ~ +85 OCStorage Temperature Range Tstg -40 ~ +125 OC■ABSOLUTE MAXIMUM RATINGSTa = 25O C10/26XC6101~XC6107, XC6111~XC6117 SeriesNOTE:*1: XC6101~XC6107 (with hysteresis) *2: XC6111~XC6117 (without hysteresis)*3: ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111) *4: V DF(T): Setting detect voltage*5: If only “V DF ” is indicated, it represents both V DFL (low when detected) and V DFH (high when detected).PARAMETERSYMBOLCONDITIONSMIN.TYP .MAX. UNITS CIRCUITDetect Voltage V DFL V DFHV DF(T)× 0.98V DF(T) V DF(T)× 1.02 V 1 Hysteresis Range XC6101~XC6107 (*1) V HYS V DF × 0.02V DF × 0.05 V DF× 0.08 V 1Hysteresis Range XC6111~XC6117 (*2) V HYS 0 V DF × 0.001 V DFx 0.01V 1V IN =V DF(T)×0.9V - 5 11 V IN =V DF(T)×1.1V- 10 16 XC61X1/XC61X2/XC61X3XC61X4/XC61X5 (*3)(The MRB & the WD Pin: No connection) V IN =6.0V - 1218 V IN =V DF(T)×0.9V - 4 10 V IN =V DF(T)×1.1V - 8 14 Supply Current I SS XC61X6/XC61X7 (*3)(The MRB Pin: No connection)V IN = 6.0V - 1016 µA 2Operating Voltage V IN 1.0 - 6.0 V 1VIN = 1.0V 0.15 0.5 -V IN =2.0V (V DFL(T)> 2.0V) 2.0 2.5 - V IN =3.0V (V DFL(T) >3.0V) 3.0 3.5 -N-ch.V DS = 0.5V V IN =4.0V (V DFL(T) >4.0V) 3.5 4.0 - 3 V DFL Output Current (RESETB) I RBOUTCMOS,P-chV DS = 0.5V V IN = 6.0V - - 1.1 -0.8 mA 4 N-chV DS = 0.5VV IN =6.0V 4.4 4.9 - 3V IN =1.0V - - 0.08 - 0.02 V IN =2.0V (V DFH(T)> 2.0V)- - 0.50 - 0.30 V IN =3.0V (V DFH(T)>3.0V)- - 0.75 - 0.55V DFHOutput Current (RESET) I ROUT P-ch. V DS = 0.5V V IN =4.0V (V DFH(T)>4.0V)- - 0.95 - 0.75 mA 4Temperature Characteristics △V DF / △Topr ・V DF -40OC < Topr < 85 O C - +100 - ppm / O C12 3.13 5 13 25 3825 50 75 60 100 140 120 200 280 240 400 560Release Delay Time(V DF <1.8V)T DR Time until V IN is increased from1.0V to2.0Vand attains to the release time level,and the Reset output pin inverts.960 1600 2240 ms 5 2 3.13 5 13 25 38 25 50 7560 100 140 120 200 280 240 400 560 Release Delay Time(V DF >1.9V)T DRTime until V IN is increased from1.0V to (V DF x1.1V) and attains to the releasetime level,and the Reset output pin inverts. 960 1600 2240ms 5 Detect Delay Time T DFTime until V IN is decreased from 6.0V to 1.0V and attains to the detect voltage level, and the Reset output pin detectswhile the WD pin left opened.- 3 30 µs 5V DFL /V DFH CMOS Output Leak CurrentI LEAK V IN =6.0V, RESETB=6.0V (V DFL ) V IN =6.0V, RESET=0V (V DFH )- 0.01 - µA 3V DFL N-ch Open DrainOutput Leak CurrentI LEAKV IN =6.0V, RESETB=6.0V-0.010.10µA 3■ELECTRICAL CHARACTERISTICS●XC6101~XC6107, XC6111~XC6117 SeriesTa = 25O CSeriesPARAMETERSYMBOL CONDITIONS MIN.TYP . MAX. UNITS CIRCUIT3.13 6.25 9.38 25 50 7560 100 140 120 200 280240 400 560 Watchdog Timeout Period (V DF <1.8V)T WDTime until V IN increases form1.0V to2.0V andthe Reset output pin is released to go into the detection state. (WD=V SS )960 1600 2240 ms 6 3.13 6.25 9.38 25 50 75 60 100 140 120 200 280240 400 560 Watchdog Timeout Period (V DF >1.9V)T WDTime until V IN increases form1.0V to (V DF x1.1V)and the Reset output pin is released to go into the detection state. (WD=V SS )960 1600 2240 ms 6 WatchdogMinimum Pulse Width T WDIN V IN =6.0V,Apply pulse from 6.0V to 0Vto the WD pin. 300 - - ns 7 Watchdog High Level VoltageV WDH V IN =V DF x 1.1V ~ 6.0V V IN x 0.7- 6 V 7 Watchdog Low Level Voltage V WDL V IN =V DF x 1.1V ~ 6.0V0 - V IN x 0.3 V 7 V IN =6.0V, V WD =6.0V (Avg. when peak )- 12 19Watchdog Input Current I WD V IN =6.0V, V WD =0V (Avg. when peak) - 19 -12 -µA 8 Watchdog Input ResistanceR WDV IN =6.0V, V WD =0V, R WD =V IN / |I WD |315500880k Ω8PARAMETERSYMBOL CONDITIONS MIN.TYP . MAX.UNITS CIRCUITMRBHigh Level VoltageV MRH V IN =V DF x1.1V ~ 6.0V 1.4 - V IN 9MRBLow Level VoltageV MRL V IN =V DF x1.1V ~ 6.0V-0.35 V9MRBPull-up Resistance R MR V IN =6.0V, MRB=0V, R MR =V IN / |I MRB | 1.6 2.4 3.0 M Ω 10 MRB Minimum Pulse Width (*3) XC6101~XC6105 XC6111~XC6115 T MRINV IN =6.0V,Apply pulse from 6.0V to 0V tothe MRB pin 2.8 - -MRB Minimum Pulse Width (*4) XC6106, XC6107 XC6116, XC6117T MRIN V IN =6.0V,Apply pulse from 6.0V to 0V tothe MRB pin1.2 - -µs11●XC6101 ~ XC6103, XC6106 ~ XC6107, XC6111 ~ XC6113, XC6116 ~ XC6117 Series NOTE:*1: V DF(T): Setting detect voltage *2: If only “V DF ” is indicated, it represents both V DFL (low when detected) and V DFH (high when detected). *3: Watchdog function is available. *4: Watchdog function is not available.Ta = 25O CTa = 25O C ■ELECTRICAL CHARACTERISTICS (Continued)●XC6101~XC6105, XC6111~XC6115 Series■OPERATIONAL EXPLANATIONThe XC6101~XC6107, XC6111~XC6117 series compare, using the error amplifier, the voltage of the internal voltage reference source with the voltage divided by R1, R2 and R3 connected to the V IN pin. The resulting output signal from the error amplifier activates the watchdog logic, manual reset logic, delay circuit and the output driver. When the V IN pin voltage gradually falls and finally reaches the detect voltage, the RESETB pin output goes from high to low in the case of the V DFL type ICs, and the RESET pin output goes from low to high in the case of the V DFH type ICs.<RESETB / RESET Pin Output Signal>* V DFL (RESETB) type - output signal: Low when detected.The RESETB pin output goes from high to low whenever the V IN pin voltage falls below the detect voltage, or whenever the MRB pin is driven from high to low. The RESETB pin remains low for the release delay time (T DR) after the V IN pin voltage reaches the release voltage. If neither rising nor falling signals are applied to the WD pin within the watchdog timeout period, the RESETB pin output remains low for the release delay time (T DR), and thereafter the RESET pin outputs high level signal. * V DFH (RESET) type – output signal: High when detected.The RESET pin output goes from low to high whenever the V IN pin voltage falls below the detect voltage, or whenever the MRB pin is driven from high to low. The RESET pin remains high for the release delay time (T DR) after the V IN pin voltage reaches the release voltage. If neither rising nor falling signals are applied to the WD pin within the watchdog timeout period, the V OUT pin output remains high for the release delay time (T DR), and thereafter the RESET pin outputs low level signal.<Hysteresis>When the internal comparator output is high, the NMOS transistor connected in parallel to R3 is turned ON, activating the hysteresis circuit. The difference between the release and detect voltages represents the hysteresis range, as shown by the following calculations:V DF (detect voltage) = (R1+R2+R3) x Vref(R2+R3)V DR (release voltage) = (R1+R2) x Vref(R2)V HYS (hysteresis range)=V DR-V DF (V)V DR > V DF* Detect voltage (V DF) includes conditions of both V DFL (low when detected) and V DFH (high when detected).* Please refer to the block diagrams for R1, R2, R3 and Vref.Hysteresis range is selectable from V DF x 0.05V (XC6101~XC6107) or V DF x 0.001V (XC6111~XC6117).<Watchdog (WD) Pin>The XC6101~XC6107, XC6111~XC6117 series use a watchdog timer to detect malfunction or “runaway” of the microprocessor. If neither rising nor falling signals are applied from the microprocessor within the watchdog timeout period, the RESETB/RESET pin output maintains the detection state for the release delay time (T DR), and thereafter the RESET/RESETB pin output returns to the release state (Please refer to the FUNCTION CHART). The timer in the watchdog is then restarted. Six watchdog timeout period settings are available in 1.6sec, 400msec, 200msec, 100msec, 50msec, 6.25msec.<MRB Pin>Using the MRB pin input, the RESET/RESETB pin signal can be forced to the detection state. When the MRB pin is driven from high to low, the RESETB pin output goes from high to low in the case of the V DFL type ICs, and the RESET pin output goes from low to high in the case of the V DFH type. Even after the MRB pin is driven back high, the RESET/RESETB pin output maintains the detection state for the release delay time (T DR). Since the MRB pin is internally pulled up to the V IN pin voltage level, leave the MRB pin open if unused (Please refer to the FUNCTION CHART). A diode, which is an input protection element, is connected between the MRB pin and V IN pin. Therefore, if the MRB pin is applied voltage that exceeds V IN, the current will flow to V IN through the diode. Please use this IC within the stated maximum ratings (V SS -0.3 ~ V IN+0.3) on the MRB pin.<Release Delay Time>Release delay time (T DR) is the time that elapses from when the V IN pin reaches the release voltage, or when the watchdog timeout period expires with no rising signal applied to the WD pin, until the RESET/RESETB pin output is released from the detection state. Seven release delay time (T DR) watchdog timeout period settings are available in 1.6sec, 400msec, 200msec, 100msec, 50msec, 25msec, 3.13msec.<Detect Delay Time>Detect Delay Time (T DF) is the time that elapses from when the V IN pin voltage falls to the detect voltage until the RESET/ RESETB pin output goes into the detection state.Series■TIMING CHARTS●CMOS Output●T DF (CMOS Output)VINVDFL LevelGNDVIN Level VDFL Level GNDVIN x 0.1V■NOTES ON USE1. Please use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent damage to the device.2. When a resistor is connected between the V IN pin and the input, the V IN voltage drops while the IC is operating and a malfunction may occur as a result of the IC’s through current. For the CMOS output products, the V IN voltage drops while the IC is operating and malfunction may occur as a result of the IC’s output current. Please be careful with using the XC6111~XC6117 series (without hysteresis).3. In order to stabilize the IC’s operations, please ensure that the V IN pin’s input frequency’s rise and fall times are more than 1 µ sec/V.4. Noise at the power supply may cause a malfunction of the watchdog operation or the circuit. In such case, please strength the line between V IN and the GND pin and connect about 0.22µF of a capacitor between the V IN pin and the GND pin.5. Protecting against a malfunction while the watchdog time out period, an ignoring time (no reaction time) occurs to the rise and fall times. Referring to the figure below, the ignoring time (no reaction time) lasts for 900µsec at maximum.GNDGNDGNDVIN Pin Wave FormWD Pin Wave FormRESETB Pin Wave Form (VDFL)SeriesPIN NAMELOGIC CONDITIONSH V IN >V DF +V HYS V IN L V IN <V DF H MRB>1.40V MRBL MRB<0.35V H When keeping W D >V WDH more than T WD L When keeping W D <V WDL more than T WD L → H V WDL → V WDH , T WDIN >300nsec WDH → L V WDH →V WDH , T WDIN >300nsecV IN MRB WD RESETB (*2) H HH LRepeat detect and release (H →L →H)H OpenH L → HH H or Open H → L H HLL *1 LV IN MRB WD RESETB (*3) H HH LRepeat detect and release (L →H →L)H OpenH L → HH H or Open H → L L HLL *1 HV IN WD RESETB (*2) RESET (*3) H HH L Repeat detect and release (H →L →H)Repeat detect and release (L →H →L)H OpenH L → HH H → L H L HL*1 L HV IN MRB RESETB (*2)RESET (*3)H H or Open H LH LL L H■PIN LOGIC CONDITIONSNOTE:*1: If only “V DF ” is indicated, it represents both V DFL (low when detected) and V DFH (high when detected).*2: For the details of each parameter, please see the electrical characteristics. V DF : Detect VoltageV HYS : Hysteresis RangeV WDH : WD High Level Voltage V WDL: WD Low Level Voltage T WDIN : WD Pulse Width T WD : WD Timeout Period■FUNCTION CHART●XC6103/XC61113 Series●XC6104/XC61114, XC6105/XC6115 Series●XC6106/XC61116, XC6107/XC6117 Series●XC6101/XC61111, XC6102/6112 Series*1: Including all logic of WD (WD=H, L, L →H, H →L, OPEN). *2: When the RESETB is High, the circuit is in the release state. When the RESETB is Low, the circuit is in the detection state. *3: When the RESET is High, the circuit is in the release state. When the RESET is Low, the circuit is in the detection state.■TEST CIRCUITSCircuit 1Circuit 2Circuit 3Circuit 4Series ■TEST CIRCUITS (Continued)Circuit 5Circuit 6Circuit 7■TEST CIRCUITS (Continued)Circuit 8Circuit 9Circuit 10Circuit 11Series■TYPICAL PERFORMANCE CHARACTERISTICS(1.1) Supply Current vs. Input Voltage(1.2) Supply Current vs. Input Voltage■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)(2) Detect, Release Voltage vs. Ambient Temperature(1.2) Supply Current vs. Input Voltage (Continued)Series■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (3-1) Output Voltage vs. Input Voltage (V DFL ) (3.1) Detect, Release Voltage vs. Input Voltage (V DFL )(3.2) Detect, Release Voltage vs. Input Voltage (V DFH )■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)(4) N-ch Driver Output Current vs. V DSSeries(6) P-ch Driver Output Current vs. Input Voltage 1■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)(8) Release Delay Time vs. Ambient Temperature(7) P-ch Driver Output Current vs. Input Voltage 2■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (10) Release Delay Time vs. Input Voltage(11) Watchdog Timeout Period vs. Input VoltageSeries■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)(14) MRB Low Level Voltage vs. Ambient Temperature(15) MRB High Level Voltage vs. Ambient Temperature* ‘X’ represents both ‘0’ and ‘1’. (ex. XC61X1⇒XC6101 and XC6111)。

FSB

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FSB6726
PNP General Purpose Amplifier
This device is designed for general purpose medium power amplifiers and switches requiring collector currents
to 1.0 A. Sourced from Process 77.
Absolute Maximum Ratings*
Page 1 of 2
fsb6726lwp Pr77 RevA
SuperSOT TM -3
FSB6726
C
E B
-
25
2.5
I C = 50 mA,V CE = 10V, f=20MHz
Small Signal Current Gain
hfe
pF 30V CB = 10 V, f = 1MHz
Collector-Base Capacitance C cb SMALL SIGNAL CHARACTERISTICS V
1.2
I C = 1 A, V CE = 1 V
Base-Emitter On Voltage
V BE(on)
mV 500I C = 1 A, I B = 100 mA
Collector-Emitter Saturation Voltage V CE(sat)--2506050
I C = 100 mA, V CE = 1 V
I C = 1 A, V CE = 1V
DC Current Gain
h FE ON CHARACTERISTICS *nA
100
V EB = 5V
Emitter Cutoff Current
I EBO
nA 100V CB = 40 V Collector Cutoff Current I CBO V
5
I E = 100 µA Emitter-Base Breakdown Voltage BV EBO V 40I C = 100 µA Collector-Base Breakdown Voltage BV CBO V 30I C = 10 mA Collector-Emitter Breakdown Voltage BV CEO OFF CHARACTERISTICS Units
Max
Min
Test Conditions
Parameter
Symbol
PNP General Purpose Amplifier
(continued)
Electrical Characteristics T A = 25°C unless otherwise noted
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
Page 2 of 2
fsb6726lwp Pr77 RevA
FSB6726
TRADEMARKS
ACEx™CoolFET™
CROSSVOLT™E 2CMOS TM FACT™
FACT Quiet Series™FAST ®FASTr™GTO™HiSeC™
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.As used herein:
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Quiet Series™SuperSOT™-3SuperSOT™-6SuperSOT™-8TinyLogic™
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition
Advance Information
Preliminary No Identification Needed Obsolete This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.
Formative or In Design
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