SN74LVC1G86单路2输入异或门

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SN74LVC1G86
ZHCSGC5Q –APRIL 1999–REVISED JUNE 2017
SN74LVC1G86单路2输入异或门
1特性
•
静电放电(ESD)保护性能超过JESD 22规范的要求
–2000V 人体放电模型(A114-A)–1000V 组件充电模式(C101)•适用于–40°C 至+125°C •支持5V V CC 运行
•输入为高达5.5V 过压容差•支持下行转换到V CC
• 3.3V 和15pF 负载条件下t pd 最大值为4ns •低功耗，85°C 条件下I CC 最大值为10µA •电压为3.3V 时，输出驱动为±24mA •I off 支持部分断电模式和后驱动保护•采用德州仪器(TI)的NanoFree™封装
•
锁断性能超过100mA ，符合JESD 78II 类规范的要求
2应用
•无线耳机
•电机驱动与控制•电视•机顶盒•
音频
3说明
SN74LVC1G86器件以正逻辑执行布尔函数Y =AB +AB 。

该单路2输入异或门适用于1.65V 至5.5V V CC 运行环境。

如果一个输入为低电平，另一个输入则可在输出时重新生成真实形态。

如果一个输入为高电平，另一个输入的信号则可在输出时重新生成反向信号。

该器件功耗低，3.3V 和15pF 电容性负载条件下t pd 最大值为4ns 。

最大输出驱动为±32mA/4.5V 和±24mA/3.3V 。

该器件完全适用于使用I off 的局部掉电应用。

I off 电路可禁用输出，以防在器件断电时电流回流对器件造成损坏。

器件信息(1)
器件型号
封装
封装尺寸（标称值）SN74LVC1G86DBV SOT-23(5) 2.90mm ×1.60mm SN74LVC1G86DCK SC70(5) 2.00mm ×1.25mm SN74LVC1G86DRL SOT (5) 1.60mm ×1.20mm SN74LVC1G86YZP
DSBGA (5)
1.44mm ×0.94mm
(1)要了解所有可用封装，请参见数据表末尾的可订购产品附录。

功能框图
异或门具有多种应用，并可用其他逻辑符号更好地表示其中部分应用。

共有五种等效异或门符号适用于采用正逻辑的SN74LVC1G86门；任意两个端口可能显示否定逻辑。

SN74LVC1G86
ZHCSGC5Q–APRIL1999–REVISED
目录
1特性 (1)
2应用 (1)
3说明 (1)
4修订历史记录 (2)
5Pin Configuration and Functions (3)
6Specifications (4)
6.1Absolute Maximum Ratings (4)
6.2ESD Ratings (4)
6.3Recommended Operating Conditions (4)
6.4Thermal Information (5)
6.5Electrical Characteristics (5)
6.6Switching Characteristics,C L=15pF (6)
6.7Switching Characteristics,C L=30pF or50pF (6)
6.8Operating Characteristics (6)
6.9Typical Characteristics (6)
7Parameter Measurement Information (7)
8Detailed Description (8)
8.1Overview (8)
8.2Functional Block Diagram (8)
8.3Feature Description (8)
8.4Function Table (9)
9Application and Implementation (10)
9.1Application Information (10)
9.2Typical Application (10)
10Power Supply Recommendations (11)
11Layout (12)
11.1Layout Guidelines (12)
11.2Layout Example (12)
12器件和文档支持 (13)
12.1接收文档更新通知 (13)
12.2社区资源 (13)
12.3商标 (13)
12.4静电放电警告 (13)
12.5Glossary (13)
13机械、封装和可订购信息 (13)
4修订历史记录
注：之前版本的页码可能与当前版本有所不同。

Changes from Revision P(September2015)to Revision Q Page
•Changed YZP(DSBGA)package pinout diagram and added DSBGA column (3)
•Added Balanced High-Drive CMOS Push-Pull Outputs,Standard CMOS Inputs,Clamp Diodes,Partial Power Down
(I off),and Over-voltage Tolerant Inputs sections (8)
Changes from Revision O(December2013)to Revision P Page •已添加应用部分、器件信息表、ESD额定值表、热性能信息表、典型特性部分、特性说明部分、器件功能模式、应用和实施部分、电源相关建议部分、布局部分、器件和文档支持部分以及机械、封装和可订购信息部分 (1)
Changes from Revision N(January2007)to Revision O Page
•将文档更新为了新的TI数据表格式。

(1)
•删除了订购信息表。

(1)
•更新了I off（特性部分）。

(1)
•Updated operating temperature range (4)
C B A 2
B V C
C 5
1A 34
GND
Y
5
1V CC
A 2
B 3
4
GND
Y
2B
3
4GND
V CC
5
A Y
1SN74LVC1G86
ZHCSGC5Q –APRIL 1999–REVISED JUNE 2017
5Pin Configuration and Functions
DBV Package 5-Pin SOT-23Top View
DRL Package 5-Pin SOT Top View
DCK Package 5-Pin SC70Top View
YZP Package 5-Pin DSBGA Bottom View
(1)
See mechanical drawings for dimensions.
Pin Functions (1)
PIN
I/O DESCRIPTION
NAME DBV,DRL,DCK
DSBGA A 1A1I Input A B 2B1I Input B GND 3C1—Ground V CC 5A2—Positive Supply Y 4
C2
O
Output Y
SN74LVC1G86
ZHCSGC5Q –APRIL 1999–REVISED JUNE 2017
(1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(3)
The value of V CC is provided in the Recommended Operating Conditions table.
6Specifications
6.1Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX UNIT V CC Supply voltage –0.5 6.5V V I Input voltage (2)
–0.5 6.5V V O Voltage applied to any output in the high-impedance or power-off state (2)–0.5 6.5V V O Voltage applied to any output in the high or low state (2)(3)–0.5
V CC +0.5V I IK Input clamp current V I <0–50mA I OK Output clamp current V O <0
–50mA I O Continuous output current
±50mA Continuous current through V CC or GND ±100mA T J Junction temperature 150°C T stg Storage temperature
–65
150
°C
(1)JEDEC document JEP155states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2)
JEDEC document JEP157states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2ESD Ratings
VALUE
UNIT V (ESD)Electrostatic discharge
Human body model (HBM),per ANSI/ESDA/JEDEC JS-001(1)
2000V
Charged-device model (CDM),per JEDEC specification JESD22-C101
(2)
1000
(1)All unused inputs of the device must be held at V CC or GND to ensure proper device operation.See Implications of Slow or Floating CMOS Inputs ,SCBA004.
6.3Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX UNIT V CC
Supply voltage
Operating
1.65 5.5
V
Data retention only 1.5V IH
High-level input voltage
V CC =1.65V to 1.95V
0.65×V CC
V
V CC =2.3V to 2.7V 1.7V CC =3V to 3.6V 2V CC =4.5V to 5.5V 0.7×V CC
V IL
Low-level input voltage
V CC =1.65V to 1.95V
0.35×V CC
V V CC =2.3V to 2.7V 0.7V CC =3V to 3.6V 0.8V CC =4.5V to 5.5V
0.3×V CC
V I Input voltage 0 5.5V V O
Output voltage
0V CC V I OH
High-level output current
V CC =1.65V –4mA V CC =2.3V
–8V CC =3V –16–24V CC =4.5V
–32
SN74LVC1G86
ZHCSGC5Q –APRIL 1999–REVISED JUNE 2017
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
I OL
Low-level output current
V CC =1.65V 4mA V CC =2.3V
8V CC =3V 1624V CC =4.5V
32Δt/Δv Input transition rise or fall rate
V CC =1.8V ±0.15V,2.5V ±0.2V
20ns/V V CC =3.3V ±0.3V 10V CC =5V ±0.5V
5T A
Operating free-air temperature
YZP package
–4085°C DCK,DBV,and DRL packages
–40
125
(1)
For more information about traditional and new thermal metrics,see the Semiconductor and IC Package Thermal Metrics application report.
6.4Thermal Information
THERMAL METRIC (1)
SN74LVC1G86
UNIT
DBV (SOT-23)
DCK (SC70)YZP (DSBGA)
5PINS 5PINS 5PINS R θJA Junction-to-ambient thermal resistance
206
252
132
°C/W (1)
All typical values are at V CC =3.3V,T A =25°C.
6.5Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V CC
MIN TYP (1)
MAX
UNIT
V OH
I OH =–100µA 1.65V to 5.5V
V CC –0.1
V
I OH =–4mA
1.65V 1.2I OH =–8mA
2.3V 1.9I OH =–16mA 3V 2.4I OH =–24mA 2.3I OH =–32mA 4.5V
3.8
V OL
I OL =100µA 1.65V to 5.5V
0.1V I OL =4mA
1.65V 0.45I OL =8mA
2.3V 0.3I OL =16mA 3V 0.4I OL =24mA 0.55I OL =32mA
4.5V 0.55I I A or B input
V I =5.5V or GND 0to 5.5V
±5µA I off V I or V O =5.5V 0
±10µA I CC V I =V CC or GND,
I O =0
–40°C to 85°C 1.65V to 5.5V 10µA –40°C to 125°C
15ΔI CC One input at V CC –0.6V,Other inputs at V CC or GND 3V to 5.5V 500
µA C i V I =V CC or GND
3.3V
6
pF
V OH(V)
SN74LVC1G86
ZHCSGC5Q–APRIL1999–REVISED
6.6Switching Characteristics,C L=15pF
over recommended operating free-air temperature range(unless otherwise noted)(see Figure2)
PARAMETE
R
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
V CC=1.8V
±0.15V
V CC=2.5V
±0.2V
V CC=3.3V
±0.3V
V CC=5V
±0.5V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
t pd A or B Y T A=–40°C to+85°C 2.19.11 4.50.640.8 3.3ns
6.7Switching Characteristics,C L=30pF or50pF
over recommended operating free-air temperature range(unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
V CC=1.8V
±0.15V
V CC=2.5V
±0.2V
V CC=3.3V
±0.3V
V CC=5V
±0.5V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
t pd A or B Y –40°C to+85°C temperature
range,see Figure2
3.59.9 1.8 5.5 1.3514
ns –40°C to+125°C temperature
range,see Figure2
3.512 1.87 1.3615
6.8Operating Characteristics T A=25°C
PARAMETER TEST CONDITIONS V CC=1.8V V CC=2.5V V CC=3.3V V CC=5V
UNIT TYP TYP TYP TYP
C pd Power dissipation capacitance f=10MHz22222224pF
6.9Typical
Figure1.V oh vs I oh at4.5V
From Output
Under Test
(see Note
LOAD CIRCUIT
Open
Data Input
Timing Input
0 V
0 V
0 V
Input
0 V
Input
Output
Waveform 1
S1 at V
(see Note B)
LOAD
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
0 V
»0 V Output
Output
t/t
PLH PHL
Open
TEST S1
Output
Control
1.8 V0.15 V
±
2.5 V0.2 V
±
3.3 V0.3 V
±
5 V0.5 V
±
1 MΩ
1 MΩ
1 MΩ
1 MΩ
V
CC
R
L
2 ×V
CC
2 ×V
CC
6 V
2 ×V
CC
V
LOAD
C
L
15 pF
15 pF
15 pF
15 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
D
3 V
V
I
V
CC
/2
V
CC
/2
1.5 V
V
CC
/2
V
M
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
t/t
r f
V
CC
V
CC
V
CC
V
LOAD
t/t
PLZ PZL
GND
t/t
PHZ PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW-AND HIGH-LEVEL ENABLING
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A.C includes probe and jig capacitance.
B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C.All input pulses are supplied by generators having the following characteristics: PRR10 MHz, Z= 50.
D.The outputs are measured one at a time, with one transition per measurement.
E.t and t are the same as t.
F.t and t are the same as t.
G.t and t are the same as t.
H.All parameters and waveforms are not applicable to all devices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
≤Ω
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
V
I
V/2
LOAD
V
OL
V
OH
V
I
V
I
V
OH
V
OL
SN74LVC1G86 ZHCSGC5Q–APRIL1999–REVISED JUNE2017 7Parameter Measurement Information
Figure2.Load Circuit and Voltage Waveforms
= 1
EXCLUSIVE OR
SN74LVC1G86
ZHCSGC5Q –APRIL 1999–REVISED JUNE 2017
8Detailed Description
8.1Overview
The SN74LVC1G86device performs the Boolean function Y =AB +AB in positive logic.This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V V CC operation.
A common application is as a true and complement element.If the input is low,the other input is reproduced in true form at the output.If the input is high,the signal on the other input is reproduced inverted at the output.NanoFree package technology is a major breakthrough in IC packaging concepts,using the die as the package.This device is fully specified for partial-power-down applications using I off .The I off circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
8.2Functional Block Diagram
These are five equivalent exclusive-OR symbols valid for an SN74LVC1G86gate in positive logic;negation may be shown at any two ports.
8.3Feature Description
8.3.1Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents.The high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.Additionally,the outputs of this device are capable of driving larger currents than the device can sustain without being damaged.It is important for the power output of the device to be limited to avoid thermal runaway and damage due to over-current.The electrical and thermal limits defined the in the Absolute Maximum Ratings must be followed at all times.8.3.2Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics .The worst case resistance is calculated with the maximum input voltage,given in the Recommended Operating Conditions ,and the maximum input leakage current,given in the Electrical Characteristics ,using ohm's law (R =V ÷I).
Signals applied to the inputs need to have fast edge rates,as defined by Δt/Δv in Recommended Operating Conditions to avoid excessive currents and oscillations.If tolerance to a slow or noisy input signal is required,a device with a Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS input.
Input Output SN74LVC1G86
ZHCSGC5Q–APRIL1999–REVISED JUNE2017 Feature Description(continued)
8.3.3Clamp Diodes
The inputs and outputs to this device have negative clamping diodes.
CAUTION
Avoid any voltage below or above the input or output voltage specified in the Absolute
Maximum Ratings.In this event,the current must be limited to the maximum input or
output clamp current value indicated in the Absolute Maximum Ratings to avoid
damage to the device.
Figure3.Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4Partial Power Down(I off)
The inputs and outputs for this device enter a high impedance state when the supply voltage is0V.The maximum leakage into or out of any input or output pin on the device is specified by I off in the Electrical Characteristics.
8.3.5Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum input voltage value specified in the Recommended Operating Conditions.
8.4Function Table
Table1lists the functional modes of the SN74LVC1G86device.
Table1.Function Table
INPUTS OUTPUT
Y
A B
L L L
L H H
H L H
H H L
SN74LVC1G86
ZHCSGC5Q–APRIL1999–REVISED 9Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification,and TI does not warrant its accuracy or completeness.TI’s customers are
responsible for determining suitability of components for their purposes.Customers should
validate and test their design implementation to confirm system functionality.
9.1Application Information
The SN74LVC1G86device can accept input voltages up to5.5V at any valid V CC which makes the device suitable for down translation.This feature of the SN74LVC1G86makes it ideal for various bus interface applications.
9.2Typical Application
Figure4.Typical Application Schematic
9.2.1Design Requirements
This device uses CMOS technology and has balanced output drive.Take care to avoid bus contention because it can drive currents that would exceed maximum limits.The high drive will also create fast edges into light loads, so routing and load conditions should be considered to prevent ringing.
9.2.2Detailed Design Procedure
1.Recommended Input Conditions
–For rise time and fall time specifications,seeΔt/ΔV in the Recommended Operating Conditions table.
–For specified High and low levels,see V IH and V IL in the Recommended Operating Conditions table.
–Inputs are overvoltage tolerant allowing them to go as high as5.5V at any valid V CC.
2.Recommended Output Conditions
–Load currents should not exceed32mA per output and50mA total for the part.
–Outputs should not be pulled above V CC.
I C C (m A )
SN74LVC1G86
ZHCSGC5Q –APRIL 1999–REVISED JUNE 2017
Typical Application (continued)
9.2.3Application Curve
Figure 5.I CC vs.V IN
10Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions table.
Each V CC pin must have a good bypass capacitor to prevent power disturbance.For devices with a single supply,0.1µF is recommended.If there are multiple V CC pins,0.01µF or 0.022µF is recommended for each power pin.It is acceptable to parallel multiple bypass caps to reject different frequencies of noise.A 0.1-µF and 1-µF are commonly used in parallel.The bypass capacitor must be installed as close to the power pin as possible for best results.
WORST
BETTER BEST
W
SN74LVC1G86
ZHCSGC5Q –APRIL 1999–REVISED JUNE 2017
11Layout
11.1Layout Guidelines
Even low data rate digital signals can have high frequency signal components due to fast edge rates.When a PCB trace turns a corner at a 90°angle,a reflection can occur.A reflection occurs primarily because of the change of width of the trace.At the apex of the turn,the trace width increases to 1.414times the width.This increase upsets the transmission-line characteristics,especially the distributed capacitance and self–inductance of the trace which results in the reflection.Not all PCB traces can be straight and therefore some traces must turn corners.Figure 6shows progressively better techniques of rounding corners.Only the last example (BEST)maintains constant trace width and minimizes reflections.
11.2Layout Example
Figure 6.Trace Example
SN74LVC1G86 ZHCSGC5Q–APRIL1999–REVISED JUNE2017
12器件和文档支持
12.1接收文档更新通知
要接收文档更新通知，请导航至上的器件产品文件夹。

请单击右上角的通知我进行注册，即可收到任意产品信息更改每周摘要。

有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。

12.2社区资源
The following links connect to TI community resources.Linked contents are provided"AS IS"by the respective contributors.They do not constitute TI specifications and do not necessarily reflect TI's views;see TI's Terms of Use.
TI E2E™Online Community TI's Engineer-to-Engineer(E2E)Community.Created to foster collaboration among engineers.At ,you can ask questions,share knowledge,explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.3商标
NanoFree,E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4静电放电警告
这些装置包含有限的内置ESD保护。

存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止MOS门极遭受静电损伤。

12.5Glossary
SLYZ022—TI Glossary.
This glossary lists and explains terms,acronyms,and definitions.
13机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。

这些信息是指定器件的最新可用数据。

这些数据发生变化时，我们可能不会另行通知或修订此文档。

如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。

PACKAGING INFORMATION
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G86 :
•Enhanced Product: SN74LVC1G86-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Type Package Drawing Pins SPQ
Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant SN74LVC1G86DBVR SOT-23DBV 53000178.09.0 3.3 3.2 1.4 4.08.0Q3SN74LVC1G86DBVR SOT-23DBV 53000180.08.4 3.23 3.17 1.37 4.08.0Q3SN74LVC1G86DBVR SOT-23DBV 53000178.09.0 3.23 3.17 1.37 4.08.0Q3SN74LVC1G86DBVR SOT-23DBV 53000178.09.2 3.3 3.23 1.55 4.08.0Q3SN74LVC1G86DBVRG4SOT-23DBV 53000178.09.0 3.23 3.17 1.37 4.08.0Q3SN74LVC1G86DBVT SOT-23DBV 5250178.09.0 3.3 3.2 1.4 4.08.0Q3SN74LVC1G86DBVT SOT-23DBV 5250178.09.0 3.23 3.17 1.37 4.08.0Q3SN74LVC1G86DBVT SOT-23DBV 5250180.09.2 3.17 3.23 1.37 4.08.0Q3SN74LVC1G86DCKR SC70DCK 53000178.09.2 2.4 2.4 1.22 4.08.0Q3SN74LVC1G86DCKR SC70DCK 53000178.09.0 2.4 2.5 1.2 4.08.0Q3SN74LVC1G86DCKT SC70DCK 5250180.09.2 2.3 2.55 1.2 4.08.0Q3SN74LVC1G86DCKT SC70DCK 5250178.09.2 2.4 2.4 1.22 4.08.0Q3SN74LVC1G86DCKT SC70DCK 5250178.09.0 2.4 2.5 1.2 4.08.0Q3SN74LVC1G86DRLR SOT-5X3DRL 54000180.09.5 1.78 1.780.69 4.08.0Q3SN74LVC1G86DRLR SOT-5X3DRL 54000180.08.4 1.98 1.780.69 4.08.0Q3SN74LVC1G86YZPR
DSBGA
YZP
5
3000
178.0
9.2
1.02
1.52
0.63
4.0
8.0
Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) SN74LVC1G86DBVR SOT-23DBV53000180.0180.018.0 SN74LVC1G86DBVR SOT-23DBV53000202.0201.028.0 SN74LVC1G86DBVR SOT-23DBV53000180.0180.018.0 SN74LVC1G86DBVR SOT-23DBV53000180.0180.018.0
SN74LVC1G86DBVRG4SOT-23DBV53000180.0180.018.0 SN74LVC1G86DBVT SOT-23DBV5250180.0180.018.0 SN74LVC1G86DBVT SOT-23DBV5250180.0180.018.0 SN74LVC1G86DBVT SOT-23DBV5250205.0200.033.0 SN74LVC1G86DCKR SC70DCK53000180.0180.018.0 SN74LVC1G86DCKR SC70DCK53000180.0180.018.0 SN74LVC1G86DCKT SC70DCK5250205.0200.033.0 SN74LVC1G86DCKT SC70DCK5250180.0180.018.0 SN74LVC1G86DCKT SC70DCK5250180.0180.018.0 SN74LVC1G86DRLR SOT-5X3DRL54000184.0184.019.0 SN74LVC1G86DRLR SOT-5X3DRL54000202.0201.028.0
SN74LVC1G86YZPR DSBGA YZP53000220.0220.035.0
PACKAGE OUTLINE
DSBGA - 0.5 mm max height
YZP0005
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
EXAMPLE BOARD LAYOUT
DSBGA - 0.5 mm max height
YZP0005
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (/lit/snva009).
EXAMPLE STENCIL DESIGN
DSBGA - 0.5 mm max height
YZP0005
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
PACKAGE OUTLINE
SOT-23 - 1.45 mm max height
DBV0005A SMALL OUTLINE TRANSISTOR
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
EXAMPLE BOARD LAYOUT
SOT-23 - 1.45 mm max height
DBV0005A SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
EXAMPLE STENCIL DESIGN
SOT-23 - 1.45 mm max height
DBV0005A SMALL OUTLINE TRANSISTOR
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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