A CMOS 5GHz Image-Reject Receiver Front-End Architecture

A CMOS 5GHz Image-Reject Receiver Front-End ArchitectureDicle Ozis 1,2, Jeyanandh Paramesh 1,3, and David J. Allstot 1 ∗1University of Washington, Seattle, WA, 98195 2Now with Telegent Systems, Inc., Sunnyvale, CA 94085 3Now with Carnegie Mellon University, Pittsburgh, PA 15213∗Research supported by National Science Foundation contract CCR-0086032 and Semiconductor Research Corp. contract 2006-HJ-1427. J. Paramesh was supported by Graduate Fellowships from the Intel Corp.Abstract —A fully-integrated double quadrature heterodyne receiver front-end uses a two-stage Lange coupler and achieves a measured image rejection ratio > 55 dB over a200MHz bandwidth at 5.25 GHz without any tuning ortrimming. It also features 23.5 dB gain, -79 dBm sensitivity,5.6 dB SSB noise figure, -7 dBm IIP3, -18dB S 11 and 1mm x 2mm chip area in 0.18 µm CMOS. Index Terms —CMOS integrated circuits, receivers, couplers, lumped-element microwave circuits, transformers. I. I NTRODUCTIONThe repeatable image rejection ratio (IRR ) of an un-calibrated single-quadrature (SQ) receiver is limited by mismatches to 35-40dB over ~2% fractional bandwidths. In a double-quadrature (DQ) architecture [1], I/Q signals are generated in both the RF and LO paths. Consequently, I/Q errors in the two paths multiply [Eqns. (1) and (2)] so that a much higher uncalibrated IRR is obtained than with an SQ receiver. Note also that I/Q mismatches in the mixers are additive so careful layout is essential for high IRR . The overall phase and amplitude errors are:()()()()2/tan tan tan tan Mixers LO RF φφφφ∆+∆⋅∆=∆ (1) ()()()2Mixers RF LO A A A A A A (A A)∆=∆⋅∆+∆ (2)Typical DQ receivers use simple RC-based I /Qgeneration to obtain high IRR over a limited bandwidth. In contrast, the use of high-order RC polyphase networks enables high, wideband IRR , but the associated high losses mandate a large preceding gain that relegates their use to I F frequencies. This paper introduces a DQ image-reject receiver (Fig. 1) wherein two-stage Lange couplers are used for the first time in a fully-integrated 0.18µm CMOS front-end to achieve high IRR over a wide bandwidth (~200MHz @ f C = 5GHz) without calibration. Single-stage passive couplers are usually not used in the signal path due to their loss and limited bandwidth. However, the two-stage Lange coupler design described herein achieves high bandwidth with acceptable noise figure; it provides a new tool for designers to use in their quest for low-noise, low-power RF circuits and systems. These techniques arewidely applicable and this paper demonstrates their effectiveness over the 5.15-5.35 GHz band. In the 70MHz-IF architecture (Fig. 1), the RF signal is first low-noise amplified and then separated into in-phase and quadrature paths using two-stage lumped-element Lange couplers [2]. The 0.18µm CMOS chip comprises an LNA, Lange couplers, down-conversion mixers, and a frequency divider with LO buffers.II. C IRCUIT B LOCKSA. Low-Noise AmplifierThe fully-differential single-stage common-source cascode LNA uses inductive source degeneration to set Z in = 50Ω. I ts output impedance is matched to the coupler input impedance using an L-match network. High coupler characteristic impedance requires a large inductance, which leads to higher losses and a low-Q match to the LNA and vice-versa. I n view of this trade-off and to facilitate stand-alone characterization of the coupler, its impedance is also set to 50. The LNA uses symmetric inductors to save chip area and a bank of switched capacitors in the output LC-tank to match its center frequency to that of the couplers.)LO sin f t )cos f t π)Fig. 1. Block diagram of the double-quadrature image-rejectreceiver front-end.nge CouplerPower dividers and directional couplers are passive microwave components used for power division or power combining. For a 3dB coupler, the power applied to any port is split equally between a pair of output ports. Hybrid couplers and power dividers mutually isolate the output ports and preserve input and output impedance levels. Quadrature couplers provide a 90-degree phase shift between output ports. Although they are typically designed using quarter wavelength transmission lines of different types for microwave and mm wave I C applications, area savings are realized by approximating the transmission lines using lumped-element networks at lower frequencies. Because the lumped-element representation is accurate only at a single frequency, lumped-element hybrids are inherently narrow-band networks but transmission line couplers are also narrowband because the quarter-wavelength restriction is satisfied exactly only at a single frequency.Fig. 2. Two Lange Couplers are cascaded to form a two-stage Lange Hybrid.The original Lange coupler, proposed in [2] connects several coupled transmission lines in parallel to divide the input signal into I/Q components with equal power. Whereas a branch-line coupler uses only electrical (capacitive) coupling, the Lange coupler employs electromagnetic (inductive) coupling to achieve a larger bandwidth. A lumped-element Lange coupler may be synthesized by replacing the coupled lines with a transformer [3], which can be constructed compactly on-chip with low loss at 5GHz. Although the bandwidth of a single-stage Lange coupler is fairly wide, it is insufficient in this design where the image is located 140MHz from the RF carrier. Therefore,a two-stage cascade coupler (Fig. 2) is developed and optimized for amplitude and phase accuracy to maximize IRR over a wide frequency range.A single-stage Lange coupler requires a monolithic transformer with a coupling factor k = 0.707, which is very difficult to realize in a bulk CMOS technology at 5GHz. I n contrast, signal flow graph analysis and synthesis show that a two-stage Lange coupler requires only k = 0.38 for each transformer. Hence, both stages are designed as identical Lange couplers. I nductive coupling in both stages provides a larger bandwidth and occupies a smaller area; a Lange coupler can be designed using a single transformer whereas a branch-line coupler requires two separate inductors. This key circuit technique enables high IRR over the entire 5.15-5.35GHz band. A transformer layout with four-fold symmetrical windings is chosen because of the required symmetry between its primary and secondary windings. I solated ports of the Lange couplers are terminated with on-chip 50 resistors. Note that an alternative two-stage coupler is presented in [4]. I t uses a capacitively-coupled (branch-line) first stage followed by an inductively-coupled (Lange) second stage, and features cancellation of phase mismatches due to the finite Q values of the passive elements. This coupler uses a transformer with k = 0.38. Due to the small k value, the overall phase response is less sensitive to variations in k; i.e., modeling errors, process variations, etc.Fig. 3. Measured image rejection ratio of the two-stage Lange hybrid with IRR > 30dB and IRR > 35dB overbandwidths of 500MHz and 275MHz, respectively.C.Double Quadrature MixerA double-balanced Gilbert-type mixer (Fig. 3) is employed in each RF path to down convert 5.15-5.35GHz RF to 70MHz IF.Fig. 4. Down-conversion mixers.To maximize power transfer, the differential RF input of the mixer is matched to 100. The output of the coupler is matched to the input RF port of the mixer using a wideband common-gate transconductance stage. The cross-coupled capacitors provide a gm-boosting mechanismthat improves noise performance without using additionalFrequency (MHz)IRR(dB)power [5]. In a standard common-gate topology, g m of the input transistor is constrained by the input impedance which imposes a tight link between noise figure and input match. The g m -boosting mechanism eases this trade-off. The negative coupling required between source and gate terminals is achieved by cross coupling. The quadrature mixers share a g m -stage to save power; hence, two g m and four switching stages are needed for DQ down conversion. A current bleeding method implemented by connecting current sources to the common-source nodes of the switching differential pairs allows independent biasing of the input and switching stages. Better switching is thus achieved with smaller transistor sizes due to the smaller bias currents of the switching transistors. This method also decreases the noise contributed by the switching stage and enables higher gain through the use of larger load resistances. As mentioned earlier, the multiplication of RF and LO amplitude and phase mismatches in the DQ front-end improves overall IRR , but mismatches in the mixers add error terms. Therefore, careful layout is critical for high IRR .Open-drain drivers buffer the outputs of the IF mixers to drive off-chip 50 measurement loads; they consume 16 mA from a 1.8V supply. Bias conditions and device sizes of the buffers are adjusted so that the measured gain of the downconverter is not affected by the 50 loading of the measurement equipment. The bias currents of buffers are mirrored from the same reference, and no tuning of buffer bias conditions is used for IRR measurements.To obtain accurate I /Q LO signals, a 2X frequency reference is divided on-chip using a master/slave D-type flip-flop. The CML latches in the divider are each biased at 4mA to ensure reliable operation from 10.44 to 10.84GHz over all process, voltage, and temperature (PVT) variations. On-chip buffers before and after the divider consume 9mA and 12mA from the 1.8V power supply, respectively. The buffers are designed to achieve adequate bandwidth versus PVT variations, and to operate with a low LO drive of < -5 dBm; they can be optimized for lower current consumption for a given system.III. M EASUREMENT R ESULTSThe DQ receiver prototype (Fig. 5) is designed for the IEEE 802.11a standard and characterized by wafer probing. The measured input return loss is < -18dB over the 200 MHz bandwidth, the gain is 23.5dB, and the SSB noise figure is < 5.6dB. Because there is no on-chip filtering, both the in-band and out-of-band IIP3 values are measured at –7dBm.Fig. 5. Chip micrograph of the image-reject receiver front-end in0.18µm CMOS.Fig. 6. Measured IRR of 15 chips (from a single wafer) for theI EEE 802.11a WLAN standard. Channel frequencies= 5.18, 5.20 ... 5.32GHz. Across the eight channels, 55dB< IRR < 63dB with µ = 58.85dB, and σ = 1.68dB.T ABLE IP ERFORMANCE C OMPARISON WITH P REVIOUS C ALIBRATION -F REE D ESIGNSRF (GHz) IF (MHz)IRR (dB) NF (dB) Gain (dB)IIP3 (dBm)-1dB Compression Point (dBm)Chip Area(mm 2) ProcessIDD @ 1.8V (mA) [6] 5.3 250 36 6.8 14 -5.5 N/A 2.4 x 1.8 0.5µm SiGe10.3[7] 5.2 30 50.2 8.516 -13 -24 2 x 1.5 0.18µm CMOS12.4This work 5.15-5.35 70 > 55 5.623.5 -7 -182 x 10.18µm CMOS 20 (LNA+Mixers)Channel numberI R R (d B )MixersLN Lange Coupler 2 mmMixers LNA Lange CouplersLO buffers& Frequency dividerinput 1 mmFig. 7. An instrumentation amplifier is connected after the I F output for sensitivity measurements.To measure IRR, sensitivity, and 802.11a-specific performance, the 70MHz IF outputs are digitized using a four-channel sampling oscilloscope with 8-bit ADCs. The digital data is fed into a vector signal analyzer that implements the digital 802.11a demodulation in software. With this setup, the measured results show IRR > 55dB without calibration for 15 samples over a wide bandwidth (~200MHz) with insensitivity to process variations and device mismatches (Fig. 6).The measurements are repeated for all data rates and coding schemes specified for 802.11a. To facilitate comparison with previous analog transceivers that derive the sensitivity from the required optimum SNR, we define sensitivity as the input power for which EVM < -18.5dB (C/I > 18.5dB) with 64-QAM OFDM @ 54Mbps. I n this test, input power is swept and EVM is measured. Because the chip features a fixed gain of 23.5dB, it is important to ensure that the sensitivity measurement is not limited by the test setup. At low input power levels, however, EVM is limited by the coarse 8-bit ADC of the digitizing scope and insufficient gain programmability of the VSA. Therefore, an instrumentation LNA is connected between the IF output of the chip and the digitizing scope (i.e., at the output as in Fig. 7) for additional gain so that ADC input range can be set to an optimal level. The measured input sensitivity is consistently -79 dBm (Fig. 8) for all 8 channels. At higher input power levels where the instrumentation LNA introduces significant distortion, the measured EVM is that of the receiver alone.VI.C ONCLUSIONSTable I compares this receiver to other calibration-free image-reject 5GHz front ends. An SQ front-end in SiGe [6] achieves IRR < 36dB; a DQ front-end in CMOS [7] achieves IRR > 50dB, but over a smaller bandwidth with a higher noise figure. Our architecture achieves IRR > 55dB over a bandwidth exceeding 200MHz with excellent overall performance, and occupies less area despite the extensive use of on-chip inductors. Hence, the two-stage Lange coupler provides accurate quadrature signal generation, and is a useful circuit technique in RF CMOS circuit and system design.Fig. 8. Measured input sensitivity of the image-reject front-end for Channel 1 at a data rate of 54Mbps. For low inputpower levels, an off-chip amplifier is cascaded with thedesigned receiver front-end.R EFERENCES[1] J. Crols and M.S.J. Steyaert., “A single-chip 900-MHzCMOS receiver front-end with a high-performance low-I F topology,”IEEE J. Solid-State Circuits, vol. 30, pp. 1483-1492, Dec. 1995.[2] J. Lange, "I nterdigitated stripline quadrature hybrid," IEEETrans. Microwave Theory Tech., vol. 17, pp. 1150-1151, Dec. 1969.[3] R. Frye, S .Kapur, and R.C. Melville, "A 2-GHz quadraturehybrid implemented in CMOS technology," IEEE J. Solid-State Circuits, vol. 38, pp. 550-555, March 2003.[4] D. Ozis and D.J. Allstot, “A CMOS 5GHz phase-compensated quadrature coupler,”IEEE Radio and WirelessSymposium, Jan. 2006, pp. 51-54.[5] X. Li, S. Shekhar, and D.J. Allstot, "Low-power GMm-boosted LNA and VCO circuits in 0.18µm CMOS," IEEEInt. Solid-State Circuits Conf., Feb. 2005, pp. 534-536. [6] J.R. Long, “A low-voltage 5.1-5.8 GHz image-rejectdownconverter RFIC,”IEEE J. Solid-State Circuit s, vol. 35,pp. 1320-1328, Sept. 2000.[7] C.-Y. Wu and C.-Y. Chou, "A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator," IEEE J. Solid-State Circuits, vol. 39, pp. 519-521, March 2004.VNANF = 5.6 dB IIP3 = - 7 dBGain=29 dBNF=2.9 dBIIP3=-15 dBmInput power (dBm)EVM(dB)。