DE2 70 Pin Assignment
QuartusII实验过程示范
QuartusII实验过程⽰范实验⼆⼗进制计数器实验该实验将使⽤Verilog 硬件描述语⾔在DE2-70 开发平台上设计⼀个基本时序逻辑电路——1 位⼗进制计数器。
通过这个实验，读者可以了解使⽤Quartus ⼯具设计硬件的基本流程以及使⽤Quartus II 内置的⼯具进⾏仿真的基本⽅法和使⽤SignalTap II 实际观察电路运⾏输出情况。
SignalTap II 是Quartus ⼯具的⼀个组件，是⼀个⽚上的逻辑分析仪，可以通过JTAG 电缆将电路运⾏的实际输出传回Quartus 进⾏观察，从⽽省去了外界逻辑分析仪时的很多⿇烦。
实验步骤3.1建⽴⼯程并完成硬件描述设计1. 打开Quartus II ⼯作环境，如图3-1 所⽰。
图3-1 Quartus II⼯作环境界⾯2. 点击菜单项File->New Project Wizard 帮助新建⼯程。
参看图3-2。
图3-2 选择New Project Wizard打开Wizard 之后，界⾯如图3-3 所⽰。
点击Next，如图3-3。
第23 页共208 页图3-3 New Project Wizard界⾯3. 输⼊⼯程⼯作路径、⼯程⽂件名以及顶层实体名。
这次实验会帮助读者理解顶层实体名和⼯程名的关系，记住⽬前指定的⼯程名与顶层实体名都是Counter10，输⼊结束后，如图3-4 所⽰。
点击Next。
图3-4输⼊设计⼯程信息4. 添加设计⽂件。
界⾯如图3-5 所⽰。
如果⽤户之前已经有设计⽂件（⽐如.v ⽂件）。
那么再次添加相应⽂件，如果没有完成的设计⽂件，点击Next 之后添加并且编辑设计⽂件。
图3-5添加设计⽂件5. 选择设计所⽤器件。
由于本次实验使⽤Altera 公司提供的DE2-70 开发板，⽤户必须选择与DE2-70 开发板相对应的FPGA 器件型号。
在Family 菜单中选择Cyclone II，Package 选FBGA，Pin Count 选896，Speed grade 选6，确认Available devices 中选中EP2C70F896C6，如图3-6。
DDR2内存引脚功能定义
《计算机维修技术第2版》易建勋编著清华大学出版社2009.8附件3-6：64位DDR2SDRAM Unb-DIMM内存条引脚功能定义（240脚）Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name 1VREF41VSS81DQ33121VSS161NC(CB4)201VSS 2VSS42NC(CB0)*82VSS122DQ4162NC(CB5)*202DM4 3DQ043NC(CB1)*83DQS4123DQ5163VSS203NC 4DQ144VSS84DQS4124VSS164NC(DM8)*204VSS 5VSS45NC(DQS8)*85VSS125DM0165NC205DQ38 6DQS046NC(DQS8)*86DQ34126NC166VSS206DQ39 7DQS047VSS87DQ35127VSS167NC(CB6)*207VSS 8VSS48NC(CB2)*88VSS128DQ6168NC(CB7)*208DQ44 9DQ249NC(CB3)*89DQ40129DQ7169VSS209DQ45 10DQ350VSS90DQ41130VSS170VDDQ210VSS 11VSS51VDDQ91VSS131DQ12171CKE1211DM5 12DQ852CKE092DQS5132DQ13172VDD212NC 13DQ953VDD93DQS5133VSS173A15213VSS 14VSS54BA294VSS134DM1174A14214DQ46 15DQS155NC95DQ42135NC175VDDQ215DQ47 16DQS156VDDQ96DQ43136VSS176A12216VSS 17VSS57A1197VSS137CK1177A9217DQ52 18NC58A798DQ48138CK1178VDD218DQ53 19NC59VDD99DQ49139VSS179A8219VSS 20VSS60A5100VSS140DQ14180A6220CK2 21DQ1061A4101SA2141DQ15181VDDQ221CK222DQ1162VDDQ102NC,TEST1142VSS182A3222VSS23VSS63A2103VSS143DQ20183A1223DM624DQ1664VDD104DQS6144DQ21184VDD224NC25DQ1765VSS105DQS6145VSS185CK0225VSS26VSS66VSS106VSS146DM2186CK0226DQ5427DQS267VDD107DQ50147NC187VDD227DQ5528DQS268NC108DQ51148VSS188A0228VSS29VSS69VDD109VSS149DQ22189VDD229DQ6030DQ1870A10/AP110DQ56150DQ23190BA1230DQ6131DQ1971BA0111DQ57151VSS191VDDQ231VSS32VSS72VDDQ112VSS152DQ28192RAS232DM733DQ2473WE113DQS7153DQ29193S0233NC34DQ2574CAS114DQS7154VSS194VDDQ234VSS35VSS75VDDQ115VSS155DM3195ODT0235DQ6236DQS376S1116DQ58156NC196A13236DQ6337DQS377ODT1117DQ59157VSS197VDD237VSS38VSS78VDDQ118VSS158DQ30198VSS238VDDSPD 39DQ2679VSS119SDA159DQ31199DQ36239SA040DQ2780DQ32120SCL160VSS200DQ37240SA1DDR2内存引脚Front BackPin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol1VREF31DQ1961A491VSS121VSS151VSS181VDDQ211DM5/DQS14 2VSS32VSS62VDDQ92DQS5#122DQ4152DQ28182A3212NC/DQS14# 3DQ033DQ2463A293DQS5123DQ5153DQ29183A1213VSS4DQ134DQ2564VDD94VSS124VSS154VSS184VDD214DQ465VSS35VSS65VSS95DQ42125DM0/DQS9155DM3/DQS12185CK0215DQ476DQS0#36DQS3#66VSS96DQ43126NC/DQS9#156NC/DQS12#186CK0#216VSS7DQS037DQS367VDD97VSS127VSS157VSS187VDD217DQ528VSS38VSS68PAR_IN98DQ48128DQ6158DQ30188A0218DQ539DQ239DQ2669VDD99DQ49129DQ7159DQ31189VDD219VSS10DQ340DQ2770A10/AP100VSS130VSS160VSS190BA1220RFU11VSS41VSS71BA0101SA2131DQ12161CB4191VDDQ221RFU12DQ842CB072VDDQ102NC132DQ13162CB5192RAS#222VSS13DQ943CB173WE#103VSS133VSS163VSS193S0#223DM6/DQS15 14VSS44VSS74CAS#104DQS6#134DM1/DQS10164DM8/DQS17194VDDQ224NC/DQS15# 15DQS1#45DQS8#75VDDQ105DQS6135NC/DQS10#165NC/DQS17#195ODT0225VSS16DQS146DQS876S1#106VSS136VSS166VSS196NC/A13226DQ5417VSS47VSS770DT1107DQ50137RFU167CB6197VDD227DQ5518RESET#48CB278VDDQ108DQ51138RFU168CB7198VSS228VSS19NC49CB379VSS109VSS139VSS169VSS199DQ36229DQ6020VSS50VSS80DQ32110DQ56140DQ14170VDDQ200DQ37230DQ6121DQ1051VDDQ81DQ33111DQ57141DQ15171CKE1201VSS231VSS22DQ1152CKE082VSS112VSS142VSS172VDD202DM4/DQS13232DM7/DQS16 23VSS53VDD83DQS4#113DQS7#143DQ20173NC203NC/DQS13#233NC/DQS16# 24DQ1654NC/BA284DQS4114DQS7144DQ21174NC204VSS234VSS25DQ1755ERR_OUT85VSS115VSS145VSS175VDDQ205DQ38235DQ6226VSS56VDDQ86DQ34116DQ58146DM2/DQS11176A12206DQ39236DQ6327DQS2#57A1187DQ35117DQ59147NC/DQS11#177A9207VSS237VSS28DQS258A788VSS118VSS148VSS178VDD208DQ44238VDDSPD29VSS59VDD89DQ40119SDA149DQ22179A8209DQ45239SA030DQ1860A590DQ41120SCL150DQ23180A6210VSS240SA1Note:Pin196is NC for512MB,or A13for1GB and2GB;pin54is NC for512MB and1GB,or BA2for2GB.Pin DescriptionsPin numbers may not correlate with symbols;refer to Pin Assignment table above for more information.Pin Numbers Symbol Type Description195ODT0Input On-Die Termination:ODT(registered HIGH)enables termination resistance internal to the DDR2SDRAM.When enabled,ODT is only applied to each of the following pins:DQ,DQS,DQS#,RDQS,RDQS#,CB,and DM.The ODT input will be ignored if disabled via the LOAD MODE command.185,186CK0,CK0#Input Clock:CK and CK#are differential clock inputs.All address and control input signals are sampled on thecrossing of the positive edge of CK and negative edge of CK#.Output data(DQs and DQS/DQS#)isreferenced to the crossings of CK and CK#.52CKE0Input Clock Enable:CKE(registered HIGH)activates and CKE(registered LOW)deactivates clocking circuitry onthe DDR2SDRAM.The specific circuitry that is enabled/disabled is dependent on the DDR2SDRAMconfiguration and operating mode.CKE LOW provides PRECHARGE POWER-DOWN and SELFREFRESH operations(all device banks idle),or ACTIVE POWERDOWN(row ACTIVE in any device bank).CKE is synchronous for POWER-DOWN entry,POWER-DOWN exit,output disable,and for SELFREFRESH entry.CKE is asynchronous for SELF REFRESH exit.Input buffers(excluding CK,CK#,CKE,and ODT)are disabled during POWER-DOWN.Input buffers(excluding CKE)are disabled during SELFREFRESH.CKE is an SSTL_18input but will detect a LVCMOS LOW level once VDD is applied duringfirst power-up.After Vref has become stable during the power on and initialization sequence,it must bemaintained for proper operation of the CKE receiver.For proper self-refresh operation VREF must bemaintained to this input.193S0#Input Chip Select:S#enables(registered LOW)and disables(registered HIGH)the command decoder.Allcommands are masked when S#is registered HIGH.S#provides for external rank selection on systems withmultiple ranks.S#is considered part of the command code.73,74,192RAS#,CAS#,Input Command Inputs:RAS#,CAS#,and WE#(along with S#)define the command being entered.WE#54(2GB),71,190BA0,BA1,BA2(2GB)Input Bank Address Inputs:BA0–BA1/BA2define to which device bank an ACTIVE,READ,WRITE,or PRECHARGE command is being applied.BA0–BA1define which mode register including MR,EMR,EMR(2),and EMR(3)is loaded during the LOAD MODE command.57,58,60,61,63,70,176,177,179,180, 182,183,188,196(1GB,2GB)A0–A12(512MB)A0–A13(1GB,2GB)Input Address Inputs:Provide the row address for ACTIVE commands,and the column address and auto prechargebit(A10)for Read/Write commands,to select one location out of the memory array in the respective bank.A10sampled during a PRECHARGE command determines whether the PRECHARGE applies to one devicebank(A10LOW,device bank selected by BA0–BA1/BA2)or all device banks(A10HIGH).The addressinputs also provide the op-code during a LOAD MODE command.3,4,9,10,12,13,21,22,24,25,30,31,33,34,39,40,80,81,86,87,89,90,95,96,98,99,107,108,110,111,116,117,122,123,128,129,131,132,140,141,143,144,149,150,152,153,158,159,199,200,205,206,208,209,214,215,217,218,226,227,229,230,235,236DQ0–DQ63I/O Data Input/Output:Bidirectional data bus.6,7,15,16,27,28,36,37,45,46,83,84, 92,93,104,105,113,114,126,135,147, 156,165,203,212,224,233125,134,146, 155,164,202,211,223,232DQS0–DQS8,DQS0#–DQS17#,DM0–DM8(DQS9–DQS17)I/O Data Strobe:Output with read data,input with write data for source synchronous operation.Edge-alignedwith read data,center aligned with write data.DQS#is only used when differential data strobe mode isenabled via the LOAD MODE command.Input Data Mask:DM is an input mask signal for write data.Inputdata is masked when DM is sampled HIGH along with that input data during a WRITE access.DM issampled on both edges of DQS.Although DM pins are input-only,the DM loading is designed to match thatof DQ and DQS pins.If RDQS is disabled,DQS0–DQS17become DM0–DM8and DQS9#–DQS17#are notused.42,43,48,49,161,162,167,168CB0–CB7I/O Check Bits.68PAR_IN Input Parity bit for the address and control bus.55ERR_OUT Output Parity error found on the address and control bus.120SCL Input Serial Clock for Presence-Detect:SCL is used to synchronize the presence-detect data transfer to and fromthe module.101,239,240SA0–SA2Input Presence-Detect Address Inputs:These pins are used to configure the presence-detect device.119SDA I/O Serial Presence-Detect Data:SDA is a bidirectional pin used to transfer addresses and data into and out of thepresence-detect portion of the module.18RESET#Input Asynchronously forces all registered outputs LOW when RESET#is LOW.This signal can be used duringpower up to ensure that CKE is LOW and DQs are High-Z.VDD Supply Power Supply:1.8V±0.1V.53,59,64,67,69,172,178,184,187,189,197,51,56,62,72,75,78,170,175,181,191,VDDQ Supply DQ Power Supply:1.8V±0.1V.194,1VREF Supply SSTL_18reference voltage.VSS Supply Ground.2,5,8,11,14,17,20,23,26,29,32,35,38,41,44,47,50,65,66,79,82,85,88,91,94,97,100,103,106,109,112,115,118,121,124,127,130,133,136,139,142,145,148,151,154,157,160,163,166,169,198,201,204,207,210,213,216,219,222,225,228,231,234,237238VDDSPD Supply Serial EEPROM positive power supply:+1.7V to+3.6V.19,54(512MB,1GB),76,77,102,171,NC—No Connect:These pins should be left unconnected.196(512MB),173,174,137,138,220,221RFU—Reserved for future use.。
MAC对应PIN码表
5C63BF95：4886
5C63BFC9：1078
5C63BFEE：0342
74EA3A3E：4323
940C6D3F26BE：26515526
940C6D5A：0044
940C6D5A：2505
940C6D64：4320
B0487A3A：3190
B0487A4A：4889
A0:21:B7:9A:71:A8 20724245
14:E6:F4:C8:DA:8E 80253877
40:16:9F:49:A2:8E 41162682
00:21:27:46:8B:78 28538264
F4:EC:38:59:61:1C 11625735
00:1f:a3:0a:6b:04 10009321
C0:3F:0E:B8:33:E0 74454532
38:83:45:86:92:03 62331166
38:83:45:2C *85710306
14:E6:E4:66:28:91 29314195
F4:EC:38 *53848406
C8:3A:35:1E:42:F8 19880712
00:10:60:9F:23:05 12448166
5C:63:BF:52:19:74 39397294
C8:3A:35:3B:41:10 38832802
5C:63:BF:46:3D:C2 65840054
5c:63:bf:47:12:xx 94598711
E0:05:C5:20:49:1A 80769316
MAC对应PIN码表(私藏分享)
有些朋友PJ出来的MAC和PIN有一些关系，基本上MAC前4位相同的，PIN码也相同，故做了以下工作
FPGA中为什么要把NCEO设置为普通的IO口[精品文档]
![FPGA中为什么要把NCEO设置为普通的IO口[精品文档]](https://img.taocdn.com/s3/m/60b50e27a300a6c30d229f1d.png)
AbstractDE2-70初學者常常會遇到這個錯誤訊息，在(原創) 如何解決DE2-70的『Error: Can't place pins assigned to pin location Pin_AD25 (IOC_X95_Y2_N1)』的錯誤訊息? (SOC) (Quartus II) (DE2-70)曾經討論過解決方式，不過當時並有解釋為什麼要這樣解(因為我當時也不懂)，本文重新徹底討論之。
Introduction使用環境：Quartus II 10.1 + DE2-70 (Cyclone II EP2C70F896CN)本文將討論以下主題：1.『Error：Can't place pins assigned to pin location Pin_AD25 (IOC_X95_Y2_N1)』錯誤訊息的意義。
2. 什麼是Dual-Purpose Pin?3.什麼是nCEO?4.如何使用Quartus II GUI將nCEO設定成regular I/O pin?5.如何使用Tcl將nCEO設定成regular I/O pin?『Error：Can't place pins assigned to pin location Pin_AD25 (IOC_X95_Y2_N1)』錯誤訊息的意義在DE2-70，若用到SW[7]，根據[1] DE2-70 User Manual v1.08，在pin assignment時會指定到PIN_AD25。
在編譯時，一定會遇到以下錯誤訊息：在(原創) 如何解決DE2-70的『Error: Can't place pins assigned to pin location Pin_AD25 (IOC_X95_Y2_N1)』的錯誤訊息? (SOC) (Quartus II) (DE2-70)曾經討論過解決方式，基本上只要跟著做就可以解決問題，不過當初並沒有解釋為什麼要這樣做。
各种视频插头插座接口介绍
SCART plug & connector: CENELEC (ComitéEuropéen de Normalisation Electrotechnique) EN 50 049-1 / IEC 933-1Pin No. Signal Inter Conne-ction Pin No.1 Audio right channel output (0.5 Vrms, < 1K ohms) 22 Audio right channel input (0.5 Vrms, > 10K ohms) 13 Audio left channel output (0.5 Vrms, < 1K ohms) 64 Audio ground 45 Blue signal ground 56 Audio left channel input (0.5 Vrms, > 10K ohms) 37 Blue signal I/O (0.7 Vp-p, 75 ohms) 78 Function switching I/O (L: < 2V, H: > 10V, 10K ohms) 89 Green signal ground 910 Intercommunication data line No. 1 1011 Green signal I/O (0.7 Vp-p, 75 ohms) 1112 Intercommunication data line No. 2 1213 Red signal ground 1314 Blanking signal ground 1415 Red signal I/O (0.7 Vp-p, 75 ohms) 1516 Blanking signal I/O (L: < 0.4V, H: >1.0V, 75 ohms) 1617 Composite video signal ground 1818 Blanking signal ground 1719 Composite video signal output (1 Vp-p, 75 ohms, sync: negative) 2020 Composite video signal input (1 Vp-p, 75 ohms, sync: negative) 1921 Plug shield (common ground) 21此主题相关图片如下：EIAJ RGB plug & connector: EIAJ TTC-003Outlook of plug and connector including pin assignment are the same as SCART plug and connect orPin No. Signal Inter Conne-ction Pin No.1 Audio left channel input (0.40 mVrms, > 47K ohms) 12 Audio left channel output (0.40 mVrms, > 10K ohms) 23 Audio ground 34 Audio ground 45 Audio right channel input (0.40 mVrms, > 47K ohms) 66 Audio right channel output (0.40 mVrms, > 10K ohms) 57 Video ground 78 Video ground 89 CVBS input (1 Vp-p, 75 ohms, sync: negative) 1010 CVBS output (1 Vp-p, 75 ohms, sync: negative) 911 AV control input 1112 Ym input (switch for R, G & B signal to half tone level, L: < 0.4,H: > 1.0, 75 ohms) 1213 Red signal ground 1314 Ground 1415 Red signal I/O (0.7 Vp-p, 75 ohms) 1516 Ys input (switch for R, G & B signal from/to internal and external,L: < 0.4, H: > 1.0, 75 ohms) 1617 Green signal ground 1718 Blue signal ground 1819 Green signal I/O (0.7 Vp-p, 75 ohms) 1920 Blue signal I/O (0.7 Vp-p, 75 ohms) 2021 Plug shield 21S-connector: EIAJ CP-1211, IEC 84(s)80Pin No. Signal1 Luminance (Y) signal ground2 Chrominance (C) signal ground3 Luminance (Y) signal I/O (1 Vp-p, 75 ohms, sync: negative)4 Chrominance (C) signal I/O (burst: 0.286 Vp-p, 75 ohms)S1 and S2 connectorPin No. S1 connector S2 connector1 Luminance (Y) signal ground Luminance (Y) signal ground2 Chrominance (C) signal ground Chrominance (C) signal ground3 Luminance (Y) signal I/O (1 Vp-p, 75 ohms, sync: negative) Luminance (Y) signal I/O (1 Vp-p, 7 5 ohms, sync: negative)4 Chrominance (C) signal I/O (burst: 0.286 Vp-p, 75 ohms)Squeeze control input:+ 5V DC / >100KW Chrominance (C) signal I/O (burst: 0.286 Vp-p, 75 ohms)Squeeze control input:+ 5V DC / >100KWLetterbox control input:+ 2.2V DC / >100KWEIAJ D-connector D1/2/3/4/5: EIAJ RC-5237Pin No. Signal1 Y signal I/O (+700 mV & sync: +/-300 mV *1, 75 ohms)2 Y_GND3 PB (+/- 350 mV, 75 ohms)4 PB_GND5 PR (+/- 350 mV, 75 ohms)6 PR_GND7 Reserved line 18 Line 1 (0V: 525 lines, 2.2V: 750 lines, 5V: 1125 lines)9 Line 2 (0V: 59.94i / 60i, 2.2V: -, 5V: 59.94p / 60p)10 Reserved line 211 Line 3 (0V: 4:3, 2.2V: 4:3 letter box, 5V: 16:9)12 Plug insert detect GND13 Reserved line 314 Plug insert detect (output: 10K ohms, input: >100K ohms)hooks Shell GND*1: for 1125i and 750p. -300mV for 525p/525i, superimposed in Y signal Note: Indication for video signal format (i: interlace, p: progressive)D1: 525iD2: 525i, 525pD3: 525i, 525p, 1125iD4: 525i, 525p, 1125i, 750pD5: 525i, 525p, 1125i, 750p, 1125pVESA DFP connector: VESA (Video Electronics Standards Association) Digital Flat Panel (DFP) Sta ndardPin No. Signal Name Signal1 TX1+ TMDS positive differential output, channel 12 TX1- TMDS negative differential output, channel 13 SHLD1 Shield for TMDS channel 14 SHLDC Shield for TMDS clock5 TXC+ TMDS positive differential output, reference clock6 TXC- TMDS negative differential output, reference clock7 GND Logic Ground8 +5V Logic +5V DC Supply from the Host9 No Connect No Connection10 No Connect No Connection11 TX2+ TMDS positive differential output, channel 212 TX2- TMDS negative differential output, channel 213 SHLD2 Shield for TMDS channel 214 SHLD0 Shield for TMDS channel 015 TX0+ TMDS positive differential output, channel 016 TX0- TMDS negative differential output, channel 017 No Connect No Connection18 HPD Hot Plug Detection (+5V DC to Host)19 DDC_DAT DDC2B Data20 DDC_CLK DDC2B ClockTMDSTM: Transition Minimized Differential SignalingDDC: Display Data ChannelDDC2B: Simplest of the DDC modes defined in the VESA DDC standard此主题相关图片如下：VESA P&D connector: Plug and Display Standard (P&DTM)Pin No. SignalPin No. Signal1 TMDS Data2 + 16 USB data +2 TMDS Data2 - 17 USB data -3 TMDS Data return 18 1394 outer sahield (optional) & Charge Power return4 Unused 19 1394 Vg5 Unused 20 1394 Vp6 Unused 21 TMDS Data0 +7 TMDS Clock return 22 TMDS Data0 -8 Charge power + 23 TMDS Data return9 1394 pair A, data - 24 Unused10 1394 pair A, data + 25 DDC return11 TMDS Data1 + 26 DDC data (SDA)12 TMDS Data1 - 27 DDC clock (SCL)13 TMDS Data return 28 +5V DC14 TMDS Clock + 29 1394 pair B, clock +15 TMDS Clock - 30 1394 pair B, clock -(TMDS: Trademark of Silicon Image, USB: universal serial bus, DDC: display data channel, SDA: s erial data, SCL: serial clock)此主题相关图片如下：IEEE 1394-1995:Pin No. Signal Name Signal Inter ConnectionInter Connection with i-Link1 VP Cable power 12 VG Cable ground 23 TPB* Strobe on receive, data on transmit (differential pair) 5 14 TPB 6 25 TPA* Strobe on receive, data on transmit (differential pair) 3 36 TPA 4 4i-Link: 4-pin type IEEE 1394-1995Pin No. Signal Name Signal Inter ConnectionInter Connection with 1394-19951 TPB* Strobe on receive, data on transmit (differential pair) 3 52 TPB 4 63 TPA* Strobe on receive, data on transmit (differential pair) 1 34 TPA 2 4此主题相关图片如下：VGA (15-pin Dsub connector: for analog interface of PC monitorPin No. SignalPin No. Signal1 Red video input 9 No pin2 Green video input 10 Digital ground3 Blue video input 11* Monitor ID 0 / Ground4 Monitor ID 2 / Ground 12* Monitor ID 1 / Serial data line (SDA)5* Digital ground / Self test 13 Horizontal sync / H+V6 Red video ground 14 Vertical sync (VCLK for DDC)7 Green video ground 15* Reserved / Data clock line (DCL)8 Blue video ground串口通信基本接线方法目前较为常用的串口有9针串口（DB9）和25针串口（DB25），通信距离较近时(<12m)，可以用电缆线直接连接标准RS232端口(RS422,RS485较远)，若距离较远，需附加调制解调器（MODEM）。
DE2-115所有引脚分配表
表1 拨动开关引脚配置
表2 按钮开关引脚配置
表3 LED 引脚配置
表4 七段数码管引脚配置
表5 时钟信号引脚配置信息
表6 LCD 模块引脚配置
表7 HSMC 接口引脚配置
表8 GPIO 引脚配置信息
表9 扩展接口引脚配置信息
表10 ADV7123 引脚配置
表11 音频编解码芯片引脚配置
表12 RS-232 引脚配置
表13 PS/2 引脚配置
表14 千兆以太网芯片引脚配置
表15 TV 解码芯片引脚配置
表16 USB (ISP1362)引脚配置
表17 IR 引脚配置
表18 SRAM 引脚配置
表19 SDRAM 引脚配置
表20 SDRAM 引脚配置
表21 Flash 引脚配置
表22 EEPROM 引脚配置
表23 SD 卡插槽引脚配置。
EDA技术实训_DE2使用教程
Altera DE2 使用教程电子信息科学与技术系目录DE2开发板资源: (3)FPGA简要介绍 (5)Quaturs使用基础 (7)用HDL写代码 (22)管脚的输入方式 (25)NIOSII 实验 (25)FAQ (36)DE2开发板资源:Table. DE2 Board InformationFPGA•Cyclone II EP2C35F672C6 with EPCS16 16-Mbit serial configuration deviceI/O Devices•Built-in USB-Blaster TM cable for FPGA configuration•10/100 Ethernet•RS232•Video out (VGA 10-bit DAC)•Video in (NTSC/PAL/multi-format)•USB 2.0 (type A and type B)•PS/2 mouse or keyboard port•Line in/out, microphone in (24-bit Audio CODEC)•Expansion headers (76 signal pins)•Infrared portMemory•8-MBytes SDRAM, 512K SRAM, 4-MBytes flash•SD memory card slotDisplays•16 x 2 LCD display•Eight 7-segment displaysSwitches and LEDs•18 toggle switches•18 red LEDs•9 green LEDs•Four debounced push-button switchesClocks•50-MHz crystal for FPGA clock input•27-MHz crystal for video applications•External SMA clock input可以在目前开发板上做的实验包括基本的VHDL以及Verilog HDL实验接口实验高级实验NIOS II CPU 实验开发套件清单1DE2开发板一个2ByteBlasterII 下载电缆1根35v电源一个4光盘一张FPGA简要介绍FPGA是英文Field Programmable Gate Array的缩写，即现场可编程门阵列，它是在PAL、GAL、EPLD等可编程器件的基础上进一步发展的产物。
MAC对应PIN码表
14:E6:F4:C8:DA:8E 80253877
40:16:9F:49:A2:8E 41162682
00:21:27:46:8B:78 28538264
பைடு நூலகம் F4:EC:38:59:61:1C 11625735
00:1f:a3:0a:6b:04 10009321
2012年2月17日
TP
D85D4C3D：6820
5C:63:BF:9B * 8582
e0:05:c5:66:c5:0e 01929720
00:25:86:5A:EA:08 74850914
40:16:9F:B3:DE:9E 61608993
38:83:45:4F:43:06 38953408
MAC对应PIN码表(私藏分享)
有些朋友PJ出来的MAC和PIN有一些关系，基本上MAC前4位相同的，PIN码也相同，故做了以下工作
前4位指的是把MAC地址按“：”来区分，可认为是分成6位，其中的前4位，举例： F4EC386C：4264，就是MAC前4位F4：EC：38：6C， PIN码前4位：4264
38:83:45:94:65:FA 32231915
5c:63:bf:42:04:80 21095023
D8:5D:4C:72:D3:1C 94494099
38:83:45:8f:a0:c0 05084869
5C:63:BF:70:B3:BC 38629211
14:e6:e4:96:dd:56 02240701
C8:3A:35:0A:EE *0716
54:E6:FC:7F:4B:1C 41219713
1500个无线路由器pin码表
MAC 8C:21:0A:55:B8:D0 F4:EC:38:66:1C:22 38:83:45:B6:4C:AC 40:16:9F:F8:D1:48 74:EA:3A:1F:09:CC EC:88:8F:39:79:5C C8:3A:35:0D:AA:98 5C:63:BF:A3:9F:74 8C:21:0A:B3:2B:F6 6C:E8:73:A7:AB:AC 14:e6:e4:7b:77:7c EC:88:8F:69:FC:80 54:E6:FC:22:72:B6 8c:21:oa:61:12:3e 38:83:45:BA:13:48 38:83:45:A9:17 * c8:3a:35:01:ae:f0 F4:EC:38:3B:9F:3E 28:10:7B:61:91:BD 14:e6:e4:4e:57:28 38:83:45:A9:11 * c8:3a:35:33:c5:08 B0:48:7A:77:6B:86 5C:63:BF:CE:38:F8 14:E6:14:AD:18:34 1C:7E:E5:E3:38:E2 F4:EC:38:77:E5:62 5c:63:bf:64:55:2c f4:ec:38:45:11:64 C8:3A:35:2B:FC:30 54:E6:FC:2A:DA * 38:83:45:84:0F:70 C8:3A:35:40:DC:28 5C:63:BF:61:06:F0 38:83:45:8E:60:52 54:E6:FC:3f:91:f0 38:83:45:BF:O5:O8 6C:E8:73:49:21:EA B0:48:7A:21:0A:FB E0:05:C5:67:FD:CE 00:0A:EB:O9:4B:97 38:83:45:E3:E6:BA 38:83:45:48:A3:04 14:e6:E4:92:4A:32 ec:88:8f:33:f5:4e 08:10:76:47:AF:F7
可编程逻辑器件实验指导书V1.5
图2(a)给出是2选1数据选择器(multiplexer)的电路原理图，2选1数据选择有多种实现方式。图2(a)给出的是积之和(sum-of-product)形式，其中输入s代表选择输入(select input)。如果s= 0，则多路器的输出m等于输入x，如果s= 1则输出等于y。图2(b)给出了2选1数据选择器的真值表(True Table)，图2(c)给出的是2选1数据选择器的电路符号。
例1DE2开发板上使用拨动开关和发光二极管的Verilog代码
//连接拨动开关SW和红色的发光二极管LEDR的简单的VerilogHDL模块
module part1（SW，LEDR）；
input [17:0] SW;
output [17:0] LEDR;
assign LEDR = SW;
endmodule
具体操作步骤如下：
1.新建Quartus II工程；
2.编写7段显示译码电路的Verilog HDL文件。连接拨动开关SW2-0到译码电路的输入c2，c1，c0，连接译码电路的输出到DE2开发板上的数码管HEX0。数码管的每个笔段分别叫做HEX00，HEX01，…，HEX06，如图6所示。代码中需要声明7位宽的输出端口
2、编写电路的VerilogHDL源文件，并将其包含到Quartus工程。将FPGA引脚连接到相应的拨动开关和7段显示数码管。(参考User Manual for the DE2 board)。引脚分配过程也可以参考Quartus II Introduction using Verilog Design，该文件可以在Altera公司网站大学计划网站的DE2 System CD上找到。
3、引脚分配，确保作为电路的输入端口的Cyclone II FPGA的引脚正确连接到拨动开关SW，作为电路输出的PPGA引脚正确与LEDR和LEDG连接；
quartus_II教程以及操作基本方法
输入是 两个加数：ain,bin, 一个进位：cin 这三个输入数据是1位（1bit),可由DE2的 SW0,SW1,SW2提供 为了显示更加清楚，可以将ain,bin,cin的输出引 出到DE2上的红色发光二极管显示，可选用 LEDR0,LEDR1,LEDR2. 输出是： 输出是： 和:sum 进位:cout 输出可由DE2的绿色发光二极管显示，可选用 LEDG0,LEDG1
• 设置综合，仿真，时序分析软件，在此可以捆绑 第三方工具，本次实验，选用软件自带的工具， 按Next继续
• 设置参数的总结，按Finish完成project的建 立。
• 步骤二：设计half_adder的VHDL模块 步骤二：设计 的 模块
• 由File->new,可打开下面的选项，选择 VHDL File,按OK继续
• 由Edit->end time，打开如下对话框，选择 仿真时间区域，这次实验选择1us:
• 将波形文件存盘为half_adder.vwf：
• 将模块的端口信号选入波形编辑框中。打 开view->utility windows->node finder
• 将打开的窗口中选择出现在设计中的所有端口， 用鼠标拖至波形编辑窗口：
• 锁定引脚方法二： 1）根据DE2_pin_assignments文件内容、 格式制作本设计引脚对应文件的引脚锁定 文件：full_adder.csv 2) 由Assignments->Import Assignment，打 开对话框，调入引脚对应文件即可。
• 步骤五：下载 步骤五：
• 首次使用，须安装DE2的驱动程序, • 将DE2通过USB端口连接到计算机，并接上电源。（可能 需要关闭杀毒软件） • 由Tools->Programmer,弹出对话框：
VerilogHDL十进制计数器实验Quartus非常详细的步骤
2.
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打开
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图
3.
这次实验会帮助读者理解顶层实体名和工程名的关系，记住目前指定的工程名与顶层 实体名都是
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必须选择与DE2-70开发板相对应的FPGA器件型号。
在Family菜单中选择CycloneII，Package选
FBGA，Pin Count选896, Speed grade资料个人收集整
理，勿做商业用途
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Bev PzdJcd Tizazdz SuAsary [page GnSG]
When you rfcK Finish, the project岬il tn created wdh the folpwrg sflHings：
BIOS设置内容
BIOS设置内容电脑设置BIOS内容进入BIOS主界面目录：Phoenix-Award BIOS CMOS Setup utility Standard CMOS Features 标准CMOS设置Advanced BIOS Features 进阶功能设定（高级BIOS设置）Advanced Chipset Features 高级芯片组设置Integrated Peripherals 外部集成设备设置Power Management Setup 电源管理设置PnP/PCI Configurations 即插即用和PCI设置Load Fail-SafeDefaults 载入BIOS默认安全设置Load BIOS Defaults 载入BIOS预设置Load Oprimum Settngs 载入主板BIOS出厂设置Load OptimizedDefaults 载入BIOS默认优化设置Set Supervisor Password 管理员口令（密码）设置Supervisor Password 管理者密码Set user Password 普通用户口令（密码）设置user Password 用户（密码）Save & Exit Setup 保存设置后退出Exit Without Saving 不保存设置退出Primary IDE Master (Slave):第一个IDE 主盘（从盘）；Not Detected没有发现。
Secondary IDE Master (Slave): 第一个IDE 主盘（从盘）OnChip USB Controller (开启或关闭USB端口)USB2.0 Controller (开启或关闭USB2.0端口传输模式)OnChip Audio Controller (开启或关闭集成声卡设备)Phoenix-Award BIOS CMOS Setup utilityStandard CMOS Features标准CMOS设置Date（mm:dd:yy）日期设定Time（hh:mm:ss）时间设定▲IDE Channel 0 master （IDE设备设置） [WDC WD800BB-22FJAO]IDE HDD Auto-Detection （IDE硬盘自动检测） [Press Enter]按EnterIDE Channel 0 Master [Auto] 自动AccessMode 存取方式；存取方法 [Auto] 自动Capacity 容量 80GBCylinder 38309Head 16Precomp 0Landing Zone 38308Sector 255▲IDE Channel 0 Slave （IDE设备设置） [None]IDE HDD Auto-Detection [Press Enter] 按Enter IDE Channel 0 Master [Auto] 自动AccessMode 存取方式；存取方法 [Auto] 自动Capacity 0GBCylinder 0Head 0Precomp 0Landing Zone 0Sector 0▲IDE Channel 2 master （IDE设备设置） [None]IDE Auto-Detection [Press Enter] 按Enter Extended IDE Drive [Auto] 自动AccessMode 存取方式；存取方法 [Auto] 自动Capacity 0GBCylinder 0Head 0Precomp 0Landing Zone 0Sector 0▲IDE Channel 2 Slave （IDE设备设置） [Asus DVD-E818ATT] IDE Auto-Detection [Press Enter] 按EnterExtended IDE Drive [Auto] 自动AccessMode 存取方式；存取方法 [Auto]自动Capacity 0GBCylinder 0Head 0Precomp 0Landing Zone 0Sector 0Video 视频模式 [EGA/VGA]Halt on [AllErrors]Base Memory 639KExtended Memory 513024KTotal Memory 514048KPhoenix-Award BIOS CMOS Setup utilityAdvanced BIOS Features高级BIOS设置▲CpuFedture [press enter] 按Enter Limit CPU ID Maxval （限制CPU编号Maxval） [Disabled] 禁用CIE Function （CIE功能） [Auto]自动Execute Disable Bit （执行禁用位） [Enabled] 开启Virtualization Technology （虚拟化技术） [Enabled] 开启▲Hard Disk Boot priority 开机硬盘引导顺序[press Enter] 按Enter1.Chom. : WDC WD800BB-22FJAO2.Bootable A dd-in Cards （可引导的外部储存设备）▲CD-ROM Boot priority CD-ROM引导优先级 [press Enter] 按Enter 1.Chz S. :Asus DVD-E818A7TGVirus warning 病毒警告（反病毒保护） [Enabled]开启CPU L1 & L2 cache CPU的L1 和 L2高速缓存 [Enabled] 开启CPU L3 cache CPU的L3高速缓存 [Enabled] 开启Hyper-Threading T echnolongy [Enabled] 开启Quick power on self Test快速启动选择（快速开机自我检测）[Enabled] 开启First Boot Device 第一引导设备 [Hard Disk]硬盘Second Boot Device 第二引导设备 [CDROM]光盘Third Boot Device 第三引导设备 [Removable]可拆卸Boot other Device 其它引导设备 [Enabled] 开启Boot up NumLOCK status 启动时NUMLOCK 灯是否开启 [on] Gate A20 OPTION （A20地址线选择） [Normal]正常Typematic Rate setting （键盘重复速率设定）； [Disabled]禁用×Typematic Rate（chars/sec）(字节/秒)； 6×Typematic Delay（Msec）（设定首次延迟时间） 250Security option 安全选项口令（密码）设置[system] （要密码）×APCIMode 模式 Enabled开启Mps version control For os （面向操作系统的MPS版本） [1.1] OS select For RAM﹥64MB （操作系统怎样处理大于64MB的内存）[Non-os2]（设定OS2使用内存容量）如果正在使用OS/2系统并且系统内存大于64MB,则该项应为Enable,否则高于64MB的内存无法使用,一般情况下为DisableReport No FDD For WIN95 （对于Win95的报告没有软驱）[No]无Delay For HDD（secs）（硬盘推迟读取时间） [2]Full screen LoGo show （全屏LoGo设置） [Enabled] 开启Small LOGO(EPA) show （小标识PEA的显示） [Enabled] 开启Phoenix-Award BIOS CMOS Setup utilityAdvanced chipset Feaevres高级芯片组设置DRAM Timing selec table 内存参数设置 [ByspD]×CAS Latency Time Auto自动×DRAM RAS# to CAS# Delay Auto自动×DRAM RAS# precharge Auto自动×Precharge dealy（tRAS） Auto自动×System Memory Frequenoy BySPDSystem BIOS cacheable （系统BIOS缓冲） [Enabled] 开启Memory Hole At 15M-16M （在15M到16M 之间的内存保留区） [Disabled] 禁用PCI Express Root port Func [Press enter] 按Enter PCI Express port 1 [Auto]自动PCI Express port 2 [Auto]自动PCI Express port 3 [Auto]自动PCI Express port 4 [Auto]自动PCI Express port 5 [Auto]自动PCI Express port 6 [Auto]自动PCI-E Compliancy Mode [V1.0 Oa]××VGAsetting××PEG/onchipVGAcontrol [Auto] 自动On-chip Frame Buffer Size [8MB]DVMT Mode [DVMT]DVMT/FIXED Memory size [128MB]Phoenix-Award BIOS CMOS Setup utilityIntegrated Peripherals外部集成设备设置onchip IDE Device 板载IDE设备设置 [press Enter] 按Enter IDE HDD Biock Mode [Disabled] 禁用IDE DMA transfer auess [Enabled] 开启On-Chip primary PCI IDE [Enabled] 开启IDE Primary Master PIO [Auto] 自动IDE Primary Slave PIO [Auto] 自动IDE Primary Master UDMA [Disabled] 禁用IDE Primary Slave UDMA [Disabled] 禁用On-Chip Secondary PCI IDE [Enabled] 开启IDE Secondary Master PIO [Auto] 自动IDE Secondary Slave PIO [Auto] 自动IDE Secondary Master UDMA [Disabled] 禁用IDE Primary Slave UDMA [Disabled] 禁用×××On-Chip Serial ATA Setting×××On-Chip Serial ATA [Enhanced Mode]SATA PORT Speed Settings [Disabled] 禁用PATA IDE Mode PrimarySATA Port P1 P3 is Secondary onboard Device 板载设备 [press Enter] 按Enter Onboard Audio [Auto]自动Onboard LAN Controller [Enabled] 开启PXE Function Support [Disabled] 禁用Systm BIOS Protect [Enabled] 开启USB 1.1 Controller [Enabled] 开启USB 2.0 Controller [Disabled] 禁用×USB Operation Mode Fu11/Low SpeedUSB Keyboard Support (USB键盘支持) [Enabled]开启USB Mouse Support （USB鼠标支持） [Enabled] 开启USB Storage Support [Disabled] 禁用×××USB Mass Storage Device BOOT Setting×××super Io Device 板载端口设置 [press Enter] 按Enter KBC lnput Clock [12 MHz]Onboard Seria l Port1 [3F8/IRQ4]Onboard Seria 2 [2F8/IRQ3]UART Mode Select [Normal]×RXD,TXD Active Hi,Lo×IR Transmission De lay Enabled×UR 2 Duple mode Half×USE IR Pins IR-R×2T×2Onboard parallel port [378/IRQ7]Parallel port mode [spp]×EPP mode Select EPP1.9×EPP mode use DMA 3PWRON After PWR-Fail [off]Phoenix-Award BIOS CMOS Setup utilityPower Management Setup电源管理设置95W（over）TDP CPU Support （95W（以上）的TDP的CPU 支持）[Disabled] 禁用A CPI Function [Enabled] 开启Power management （电源管理）[userDefine] ViDeo off Method （视频关闭方法）[Blank screen]黑屏ViDeo off Insuspend [NO]Suspend Type [stopGrant] MoDEM use IRQ （MoDEM使用的IRQ号） [3]Suspend Mode （睡眠模式）[Disabled] 禁用HDD PowerDown （硬盘断电）[Disabled] 禁用Soft-off by PWRBTTN （电源按钮关机） [Instant-off] Wake-up by PCI CARD （唤醒PCI 卡）[Disabled] 禁用Wake-up by PCI E card （唤醒PCI E卡）[Disabled] 禁用Power on by Alarm [Disabled] 禁用×Date（of month）Alarm 0 报警日期×Time（hh:mm:ss）Alarm 0:0:0 报警时间××Reload Global Timer Events××Primary IDE 0 （主IDE第一个设备接口）[Disabled] 禁用Primary IDE 1 （主IDE第二个设备接口）[Disabled] 禁用Secondary IDE 0（副IDE第一个设备接口）[Disabled] 禁用Secondary IDE 1（副IDE第二个设备接口）[Disabled] 禁用Phoenix-Award BIOS CMOS Setup utilityPnP/PCI Configurations即插即用和PCI设置Init Displapy First （显示器适配器选择） [PCI slot]Reset Configuration Data [Disabled] 禁用Resources ControlledBy [AOto(EscD)]×IRQ Resources 系统中断设置 [press Enter]按Enter PCI/VGA Palette snoop （显卡兼容设定） [Disabled] 禁用PCI Latency Timer(CLK) （PCI搜索时间设置)[16]INT Pin 1 Assignment [Auto]自动INT Pin 2 Assignment [Auto] 自动INT Pin 3 Assignment [Auto] 自动INT Pin 4 Assignment 其它IRQ编号 [Auto] 自动INT Pin 5 Assignment [Auto] 自动INT Pin 6 Assignment [Auto] 自动INT Pin 7 Assignment [Auto] 自动INT Pin 8 Assignment [Auto] 自动××PCI Express relative items××Maximm Payload Size [4096]戴尔BIOS设置热键： F 2戴尔主板OWF887芯片组：英特尔82865G/PE/P,82848P –82801EB/ER （ICH5/ICH5R）制造日期：2006/01/03Dell- Dell DE051 SeriesInter ○RCeleron TM Processor:2.80GHz BIOS Version:A01Level 2 Cache:256KB Integrated Service Tag:CCKJZ1X System TimeSystem Date▲Drive Config uration Diskette Drive A: 3.5inch.1.44MBPrimary Slave Drive OffSecondary Master Drive CD-ROM DeviceSecondary Slave Drive OffIDE Drive UDMA On▲Hard Disk Drive Sequence1.System BIOS boot devices/doc/b116192079.html,B device（not installed）+.- to move down/up▲Boot Squence1.Hard-Disk Drive C:2.IDE CD-ROM DeviceSPACE to enable/disable 1+,- to Move down/up▲Memory Information 内存信息Installed System Memory 256MB DDR SDRAMSystem Memory Speed 333MHzSystem Memory Channelmode SingleAGP Aperture 128MB▲CPU InformationCPU Speed NormalBUS Speed 533 MHzProcessor O ID F49Clock Speed 2.80GHzL2 Cache Size 256KB▲Integrated Devices（Legacy Select Options）Sound 声音 onNetwork Interface Conroller 网络接口onMouse Port 鼠标端口 onUSB Emulation onUSB Controller USB总线控制器 onSerial Port 1 串行端口1 AutoPariallel PortDiskette Interface 软磁盘接口 offPrimary Video Controller 视频控制器 AutoOndoard video Buffer 视频缓冲设置 1MB▲Power Management 电源管理设置Suspend Mode 挂起＼睡眠模 S3AC Power Recovery offLow Power Mode设置系统休眠或关闭模式；低功率模式Disabled▲System Security 安全模式Password Status 密码状态 unlokedSystem Password 系统密码；开机密码设置 Not Enabled 不使用Setup Password 设置密码 Not Enabled 不使用 Post Hotkeys 自检热键 F2 and F12PXE Bis Default Policy 默认＼预设设置 Deny▲Keyboard NumLock 键盘数字锁定设定 on▲Re pport Keyboard Errors Report▲Auto Power on 自动开机 Disabled Auto Power on Mode 自动开机模式 DisabledAuto Power on Time 自动开机时间 00:00▲Fast Boot on▲OS Install Mode 操作系统安装模式 off▲Limit CPU ID Value Disabled ▲IDE Hard Drive Acoustics Mode Bypass▲System Event Log Cu rrent Event Log Status UNREADDisplay System Event Clear System Event Log Mar1Xa11 Entries as READ 热键： F 121、Normal2、Primary Master Drive3、Hard – Disk Drive C: 硬磁盘C4、IDE CD-ROM Device5、System Setup 系统设定6、IDE Drive Diagnostics IDE驱动诊断7、Boot utility Partition Enter a, Choice:1。
初识DE2开发板
初识DE2开发板默认分类2009-10-09 21:39:25 阅读1626 评论2字号：大中小订阅DE2的资源DE2的资源非常丰富，包括1. 核心的FPGA芯片-Cyclone II 2C35 F672C6，从名称可以看出，它包含有35千个LE，在Altera 的芯片系列中，不算最多，但也绝对够用。
Altera下载控制芯片- EPCS16以及USB-Blaste对Jtag的支持。
2.存储用的芯片有：512-KB SRAM，8-Mbyte SDRAM，4-Mbyte Flash memory3. 经典IO配置：拥有4个按钮，18个拨动开关，18个红色发光二极管，9个绿色发光二极管，8个七段数码管，16*2字符液晶显示屏，4. 超强多媒体：24位CD音质音频芯片WM8731(Mic输入+LineIn+ 标准音频输出)，视频解码芯片(支持NTSC/PAL制式)，带有高速DAC视屏输出VGA模块。
5.更多标准接口：通用串行总线USB控制模块以及A、B型接口，SD Card接口，IrDA红外模块，10/100M自适应以太网络适配器，RS-232标准串口，PS/2键盘接口6.其他：50M，27M晶振各一个，支持外部时钟，80针带保护电路的外接IO7.此外还有：配套的光盘资料，QutuarsII6软件，NiosII 6.0IDE，例程与说明文档。
DE2的使用关于DE2资料光盘的使用主要的可以参看他的用户手册，里面有关于DE2的资料的详细使用说明，板子的电路原理图，模块图，管脚图，和各个模块的Datasheet等等。
可以这样来看：DE2_System：\Datasheet DE2板子上的各个模块的详细的官方Datasheet，来自各个芯片厂商。
\DE2_demonstrations 丰富的例程，里面很多适用的例子，比如SD_Music_Player.等\DE2_lab_exercises DE2提供的试验内容，里面有很详细的操作步骤截图。
DE0使用说明中文
5.1 DE0 默认配置 ................................................................................................................................... 42 5.2 SD 卡设计范例.................................................................................................................................. 43 5.3 VGA color pattern 设计范例............................................................................................................... 46
2
第1章.
DE0 包装
DE0 开发板套件包含了在 Windows 操作系统下运行所需的所有组件。
1.1 包装内容
DE0 开发板套件之包装图 1-1 所示。
DE0 开发板套件包含：
图 1-1 DE0 开发板套件包装 3
DE0 开发板 用于 FPGA 编程控制的 USB 电缆线 DE0 开发板系统 CD 包含：
早上
1
目录..............................................................................................3
1.1 包装内容............................................................................................................................................. 3 1.2 DE0 开发板组装 .................................................................................................................................. 4
PIN码对照表
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8C:21:0A:AD:7A:7083463853 8C:21:0A:AF:E0:1866078C:21:0A:B3:B9:B*69867811 8C:21:0A:B4:40:5407136283 8C:21:0A:B4:D9:9017914994 8C:21:0A:B5:CF:4012841141 8C:21:0A:B6:A5:5687053340 8C:21:0A:B6:FA:9418570984 8C:21:0A:BC:2F:BC89952641 8C:21:0A:C1 *18028C:21:0A:C3:10:6C82363413 8C:21:0A:C5:7B:DE15482600 8C:21:0A:CB:F5:8E06615536 8C;21;04;28;0C;1A46861849 8C210A868FF2 *10151587 8C210ABE4AB0 *60741080 91:4E:6E:43:BB:7069430862 94:0C:6D:27 *6541 94:0C:6D:35:B9:B451908010 94:0C:6D:3A:D4:6606565558 94:0C:6D:3E:FF:A688674926。
DE2-70开发板介绍
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14
功能单元LAB
LAB控制信号： 两个时钟 两个时钟使能 两个异步清零 一个同步清零 一个同步置位
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15
I/O单元模块
遍布在Cyclone II器件周围的I/O管脚由IOE反馈，IOE位于LAB行和 列的终端。Cyclone II器件IOES 包含了一个双向I/O缓冲区和三个 完整的嵌入式双向单数据速率传 输寄存器，如右图所示。IOE包 含了一个输出寄存器，输入寄存 器和一个输出使能寄存器。设计 人员可以使用输入寄存器快速设 置启动时间，使用输出寄存器快 速设置时钟到输出的时间。
both JTAG and Active Serial – 2-Mbyte SSRAM – Two 32-Mbyte SDRAM – 8-Mbyte Flash memory – SD Card socket – 4 pushbutton switches – 18 toggle switches – 18 red user LEDs – 9 green user LEDs – 50-MHz oscillator and 28.63-MHz oscillator for clock sources
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25
小结
• M4K 嵌入式存储器块：由带校验的4K位(4096 位)真双口 RAM组成。Cyclone II系列FPGA的M4K 嵌入式存储器的容量 从119K位至1152K 位不等。 •每个嵌入式乘法器：可以配制成两个9×9或一个18×18的 乘法器，处理速度最高达250MHz，Cyclone II 的嵌入式乘 法器在FPGA上按列排列。 •输入输出单元IOE 配列在逻辑阵列块的行和列的末端。可 以提供各种类型的单端或差分逻辑输入输出。