54ACTQ573F资料

54ACQ573•54ACTQ573
Quiet Series Octal Latch with TRI-STATE ®Outputs
General Description
The ’ACQ/’ACTQ573is a high-speed octal latch with buff-ered common Latch Enable (LE)and buffered common Out-put Enable (OE)inputs.The ’ACQ/’ACTQ573is functionally identical to the ’ACQ/’ACTQ373but with inputs and outputs on opposite sides of the package.The ’ACQ/’ACTQ utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance.FACT Quiet Series ™features GTO ™output control and un-dershoot corrector in addition to a split ground bus for supe-rior performance.
Features
n I CC and I OZ reduced by 50%
n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch-up immunity
n Inputs and outputs on opposite sides of package allow easy interface with microprocessors n Outputs source/sink 24mA
n Faster prop delays than standard ’ACT573n 4kV minimum ESD immunity
n Standard Microcircuit Drawing (SMD)—’ACTQ573:5962-92194—’ACQ573:5962-92180
Logic Symbols
Pin Names Description
D 0–D 7Data Inputs
LE Latch Enable Input
OE TRI-STATE Output Enable Input O 0–O 7
TRI-STATE Latch Outputs
GTO ™is a trademark of National Semiconductor Corporation.
TRI-STATE ®is a registered trademark of National Semiconductor Corporation.FACT ®is a registered trademark of Fairchild Semiconductor Corporation.FACT Quiet Series ™is a trademark of Fairchild Semiconductor Corporation.
DS100242-1
IEEE/IEC
August 1998
54ACQ573•54ACTQ573Quiet Series Octal Latch with TRI-STATE Outputs
©1998National Semiconductor Corporation
Connection Diagrams
Functional Description
The ’ACQ/’ACTQ573contains eight D-type latches with TRI-STATE output buffers.When the Latch Enable (LE)in-put is HIGH,data on the D n inputs enters the latches.In this condition the latches are transparent,i.e.,a latch output will change state each time its D input changes.When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW tran-sition of LE.The TRI-STATE buffers are controlled by the Output Enable (OE)input.When OE is LOW,the buffers are enabled.When OE is HIGH the buffers are in the high im-pedance mode but this does not interfere with entering new data into the latches.
Truth Table
Inputs
Outputs
OE LE D O n L H H H L H L L L L X O 0H
X
X
Z
H =HIGH Voltage L =LOW Voltage Z =High Impedance X =Immaterial
O 0=Previous O 0before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Pin Assignment for DIP
and Flatpak
DS100242-3
Pin Assignment for LCC
DS100242-4
DS100242-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings(Note2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage(V CC)−0.5V to+7.0V DC Input Diode Current(I IK)
V I=−0.5V−20mA V I=V CC+0.5V+20mA DC Input Voltage(V I)−0.5V to V CC+0.5V DC Output Diode Current(I OK)
V O=−0.5V−20mA V O=V CC+0.5V+20mA DC Output Voltage(V O)−0.5V to V CC+0.5V DC Output Source
or Sink Current(I O)±50mA DC V CC or Ground Current
per Output Pin(I CC or I GND)±50mA Storage Temperature(T STG)−65˚C to+150˚C DC Latchup Source
or Sink Current±300mA Junction Temperature(T J)
CDIP175˚C Recommended Operating Conditions
Supply Voltage(V CC)
’ACQ 2.0V to6.0V ’ACTQ 4.5V to5.5V Input Voltage(V I)0V to V CC Output Voltage(V O)0V to V CC Operating Temperature(T A)
54ACQ/ACTQ−55˚C to+125˚C Minimum Input Edge Rate∆V/∆t
’ACQ Devices
V IN from30%to70%of V CC
V CC@3.0V,4.5V,5.5V125mV/ns Minimum Input Edge Rate∆V/∆t
’ACTQ Devices
V IN from0.8V to2.0V
V CC@4.5V,5.5V125mV/ns Note1:All commercial packaging is not recommended for applications re-quiring greater than2000temperature cycles from−40˚C to+125˚C.
Note2:Absolute maximum ratings are those values beyond which damage to the device may occur.The databook specifications should be met,without exception,to ensure that the system design is reliable over its power supply, temperature,and output/input loading variables.National does not recom-mend operation of FACT®circuits outside databook specifications.
DC Characteristics for’ACQ Family Devices
54ACQ
Symbol Parameter V CC T A=−55˚C to+125˚C Units Conditions
(V)Guaranteed Limits
V IH Minimum High Level 3.0 2.1V OUT=0.1V Input Voltage 4.5 3.15V or V CC−0.1V
5.5 3.85
V IL Maximum Low Level 3.00.9V OUT=0.1V Input Voltage 4.5 1.35V or V CC−0.1V
5.5 1.65
V OH Minimum High Level 3.0 2.9I OUT=−50µA Output Voltage 4.5 4.4V
5.5 5.4
(Note3)
V IN=V IL or V IH
3.0 2.4I OH=−12mA
4.5 3.7V I OH=−24mA
5.5 4.7I OH=−24mA
V OL Maximum Low Level 3.00.1I OUT=50µA Output Voltage 4.50.1V
5.50.1
(Note3)
V IN=V IL or V IH
3.00.50I OL=12mA
4.50.50V I OL=24mA
5.50.50I OL=24mA
I IN Maximum Input 5.5±1.0µA V I=V CC,GND
Leakage Current(Note5)
3
DC Characteristics for’ACQ Family Devices(Continued)
54ACQ
Symbol Parameter V CC T A=−55˚C to+125˚C Units Conditions
(V)Guaranteed Limits
I OLD(Note4)
Minimum Dynamic
Output Current 5.550mA V OLD=1.65V Max
I OHD 5.5−50mA V OHD=3.85V Min I CC Maximum Quiescent 5.580.0µA V IN=V CC
Supply Current or GND(Note5)
I OZ Maximum TRI-STATE V I(OE)=V IL,V IH
Leakage Current 5.5±5.0µA V I=V CC,GND
V O=V CC,GND
V OLP Quiet Output 5.0 1.75V
Maximum Dynamic V OL(Notes6,7)
V OLV Quiet Output 5.0−1.2V
Minimum Dynamic V OL(Notes6,7) Note3:All outputs loaded;thresholds on input associated with output under test.
Note4:Maximum test duration2.0ms,one output loaded at a time.
Note5:I IN and I CC@3.0V are guaranteed to be less than or equal to the respective limit@5.5V V CC.
I CC for54ACQ@25˚C is identical to74ACQ@25˚C.
Note6:Plastic DIP package.
Note7:Max number of outputs defined as(n).Data Inputs are driven0V to5V.One output@GND.
DC Characteristics for’ACTQ Family Devices
54ACTQ
Symbol Parameter V CC T A=−55˚C to+125˚C Units Conditions
(V)Guaranteed Limits
V IH Minimum High Level 4.5 2.0V V OUT=0.1V Input Voltage 5.5 2.0or V CC−0.1V
V IL Maximum Low Level 4.50.8V V OUT=0.1V Input Voltage 5.50.8or V CC−0.1V
V OH Minimum High Level 4.5 4.4V I OUT=−50µA Output Voltage 5.5 5.4
(Note8)
V IN=V IL or V IH
4.5 3.70V I OH=−24mA
5.5 4.70I OH=−24mA
V OL Maximum Low Level 4.50.1V I OUT=50µA Output Voltage 5.50.1
(Note8)
V IN=V IL or V IH
4.50.50V I OL=24mA
5.50.50I OL=24mA
I IN Maximum Input 5.5±1.0µA V I=V CC,GND
Leakage Current
I OZ Maximum TRI-STATE 5.5±5.0µA V I=V IL,V IH
Leakage Current V O=V CC,GND
I CCT Maximum 5.5 1.6mA V I=V CC−2.1V
I CC/Input
4
DC Characteristics for’ACTQ Family Devices(Continued)
54ACTQ
Symbol Parameter V CC T A=−55˚C to+125˚C Units Conditions
(V)Guaranteed Limits
I OLD(Note9)
Minimum Dynamic
Output Current 5.550mA V OLD=1.65V Max
I OHD 5.5−50mA V OHD=3.85V Min
I CC Maximum Quiescent 5.580.0µA V IN=V CC
Supply Current or GND(Note10)
V OLP Quiet Output 5.0 1.5V(Notes11,12) Maximum Dynamic V OL
V OLV Quiet Output 5.0−1.2V(Notes11,12) Minimum Dynamic V OL
Note8:All outputs loaded;thresholds on input associated with output under test.
Note9:Maximum test duration2.0ms,one output loaded at a time.
Note10:I CC for54ACTQ@25˚C is identical to74ACTQ@25˚C.
Note11:Plastic DIP package.
Note12:Max number of outputs defined as(n).Data Inputs are driven0V to3V.One output@GND.
AC Electrical Characteristics
54ACQ
V CC T A=−55˚C Fig. Symbol Parameter(V)to+125˚C Units No.
(Note13)C L=50pF
Min Max
t PHL,Propagation Delay 3.3 1.516.0ns
t PLH D n to O n 5.0 1.511.0
t PLH,Propagation Delay 3.3 1.515.0ns
t PHL LE to O n 5.0 1.511.0
t PZL,Output Enable Time 3.3 1.513.5ns
t PZH 5.0 1.510.0
t PHZ,Output Disable Time 3.3 1.513.0ns
t PLZ 5.0 1.010.5
Note13:Voltage Range5.0is5.0V±0.5V
Voltage Range3.3is3.3V±0.3V
AC Operating Requirements
54ACQ
V CC T A=−55˚C
Symbol Parameter(V)to+125˚C Units
(Note14)C L=50pF
Guaranteed
Minimum
t S Setup Time,HIGH or LOW 3.3 4.0ns
D n to L
E 5.0 4.0
t H Hold Time,HIGH or LOW 3.3 2.0ns
D n to L
E 5.0 2.0
t W LE Pulse Width,HIGH 3.3 5.0ns
5.0 5.0
Note14:Voltage Range5.0is5.0V±0.5V
Voltage Range3.3is3.3V±0.3V
5
AC Electrical Characteristics
54ACTQ
V CC T A=−55˚C Fig.
Symbol Parameter(V)to+125˚C Units No.
(Note15)C L=50pF
Min Max
t PHL,Propagation Delay 5.0 1.510.0ns
t PLH D n to O n
t PLH,Propagation Delay 5.0 1.511.0ns
t PHL LE to O n
t PZL,t PZH Output Enable Time 5.0 1.511.0ns
t PHZ,t PLZ Output Disable Time 5.0 1.511.0ns
Note15:Voltage Range5.0is5.0V±0.5V
AC Operating Requirements
54ACTQ
V CC T A=−55˚C Fig.
Symbol Parameter(V)to+125˚C Units No.
(Note16)C L=50pF
Guaranteed Minimum
t S Setup Time,HIGH or LOW 5.0 3.5ns
D n to LE
t H Hold Time,HIGH or LOW 5.0 1.5ns
D n to LE
t W LE Pulse Width,HIGH 5.0 5.0ns
Note16:Voltage Range5.0is5.0V±0.5V
Capacitance
Symbol Parameter Typ Units Conditions
C IN Input Capacitance 4.5pF V CC=OPEN
C P
D Power Dissipation42.0pF V CC=5.0V
Capacitance
6
Physical Dimensions inches(millimeters)unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier(L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package(D)
NS Package Number J20A
7
Physical Dimensions inches(millimeters)unless otherwise noted(Continued)
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the body,or(b)support or sustain life,and whose fail-
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with instructions for use provided in the labeling,can
be reasonably expected to result in a significant injury
to the user.
2.A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system,or to affect its safety or effectiveness.
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20-Lead Ceramic Flatpak(F)
NS Package Number W20A
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National does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。