GS8321E36GE-166中文资料

GS8321ZV18E-166I中文资料

GS8321ZV18/32/36E-250/225/200/166/150/13336Mb Pipelined and Flow ThroughSynchronous NBT SRAM250 MHz–133 MHz1.8 V V DD 1.8 V I/O165-Bump FP-BGA Commercial Temp Industrial Temp Features• User-configurable Pipeline and Flow Through mode• NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization• Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs• IEEE 1149.1 JTAG-compatible Boundary Scan • 1.8 V +10%/–10% core power supply• LBO pin for Linear or Interleave Burst mode• Pin-compatible with 2Mb, 4Mb, 8Mb, and 18Mb devices • Byte write operation (9-bit Bytes)• 3 chip enable signals for easy depth expansion • ZZ pin for automatic power-down• JEDEC-standard 165-bump FP-BGA packageFunctional DescriptionThe GS8321ZV18/32/36E is a 36Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.The GS8321ZV18/32/36E may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the deviceincorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.The GS8321ZV18/32/36E is implemented with GSI's high performance CMOS technology and is available in JEDEC-standard 165-bump FP-BGA package.Parameter Synopsis-250-225-200-166-150-133Unit Pipeline 3-1-1-1t KQ tCycle 2.54.0 2.74.4 3.05.0 3.56.0 3.86.6 4.07.5ns ns (x18)Curr (x32/x36)350320295260240215mA Flow Through 2-1-1-1t KQ tCycle 6.56.57.07.07.57.58.08.08.58.58.58.5ns ns (x18)Curr (x32/x36)235225210200190175mA165 Bump BGA—x18 Commom I/O—Top View (Package E)1234567891011A NC A E1BB NC E3CKE ADV A A A AB NC A E2NC BA CK W G A A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQA CD NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA DE NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA EF NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA FG NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA GH FT MCH NC V DD V SS V SS V SS V DD NC NC ZZ H J DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC J K DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC K L DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC L M DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC M N DQB NC V DDQ V SS NC NC NC V SS V DDQ NC NC N P NC NC A A TDI A1TDO A A A NC P R LBO A A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch165 Bump BGA—x32 Common I/O—Top View (Package E)1234567891011A NC A E1BC BB E3CKE ADV A A NC AB NC A E2BD BA CK W G A A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC NC CD DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB DE DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB EF DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB FG DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB GH FT MCH NC V DD V SS V SS V SS V DD NC NC ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N NC NC V DDQ V SS NC NC NC V SS V DDQ NC NC N P NC NC A A TDI A1TDO A A A NC P R LBO A A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch165 Bump BGA—x36 Common I/O—Top View (Package E)1234567891011A NC A E1BC BB E3CKE ADV A A NC AB NC A E2BD BA CK W G A A NC BC DQC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQB CD DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB DE DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB EF DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB FG DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB GH FT MCH NC V DD V SS V SS V SS V DD NC NC ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N DQD NC V DDQ V SS NC NC NC V SS V DDQ NC DQA N P NC NC A A TDI A1TDO A A A NC P R LBO A A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump PitchGS8321ZV18/32/36E 165-Bump BGA Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter Preset InputsAn I Address InputsDQ ADQ BI/O Data Input and Output pins DQ CDQ DB A, B B, B C, B D I Byte Write Enable for DQ A, DQ B, DQ C, DQ D I/Os; active lowNC—No ConnectCK I Clock Input Signal; active highCKE I Clock Enable; active lowW I Write Enable; active lowE1I Chip Enable; active lowE3I Chip Enable; active lowE2I Chip Enable; active highFT I Flow Through / Pipeline Mode ControlG I Output Enable; active lowADV I Burst address counter advance enable; active highZZ I Sleep mode control; active highLBO I Linear Burst Order mode; active lowTMS I Scan Test Mode SelectTDI I Scan Test Data InTDO O Scan Test Data OutTCK I Scan Test ClockMCH—Must Connect HighV DD I Core power supplyV SS I I/O and Core GroundV DDQ I Output driver power supplyGS8321ZV18/32/36 NBT SRAM Functional Block DiagramK18S A 1S A 0B u r s tC o u n t e rL B OA D VM e m o r y A r r a yGC KC K ED QF TD Q a –D Q nKS A 1’S A 0’D QM a t c hW r i t e A d d r e s sR e g i s t e r 2W r i t e A d d r e s sR e g i s t e r 1W r i t e D a t aR e g i s t e r 2W r i t e D a t aR e g i s t e r 1KKKKKKS e n s e A m p sW r i t e D r i v e r sR e a d , W r i t e a n dD a t a C o h e r e n c yC o n t r o l L o g i cF TA 0–A nE 3E 2E 1WB DB CB BB AFunctional DetailsClockingDeassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.Pipeline Mode Read and Write OperationsAll inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable inputs will deactivate the device.Function W B A B B B C B DRead H X X X XWrite Byte “a”L L H H HWrite Byte “b”L H L H HWrite Byte “c”L H H L HWrite Byte “d”L H H H LWrite all Bytes L L L L LWrite Abort/NOP L H H H HRead operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (B A, B B, B C & B D) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.Flow Through Mode Read and Write OperationsOperation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.Synchronous Truth TableOperation Type Address CK CKE ADV W Bx E1E2E3G ZZ DQ Notes Read Cycle, Begin Burst R External L-H L L H X L H L L L QRead Cycle, Continue Burst B Next L-H L H X X X X X L L Q1,10 NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z2 Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z1,2,10 Write Cycle, Begin Burst W External L-H L L L L L H L X L D3 Write Cycle, Continue Burst B Next L-H L H X L X X X X L D1,3,10 Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z1,2,3,10 Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z Deselect Cycle D None L-H L L L H L H L X L High-Z1 Deselect Cycle, Continue D None L-H L H X X X X X X L High-Z1 Sleep Mode None X X X X X X X X X H High-ZClock Edge Ignore, Stall Current L-H H X X X X X X X L-4 Notes:1.Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-lect cycle is executed first.2.Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the Wpin is sampled low but no Byte Write pins are active so no write operation is performed.3.G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off duringwrite cycles.4.If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the buswill remain in High Z.5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Writesignals are Low6.All inputs, except G and ZZ must meet setup and hold times of rising clock edge.7.Wait states can be inserted by setting CKE high.8.This device contains circuitry that ensures all outputs are in High Z during power-up.9. A 2-bit burst counter is incorporated.10.The address counter is incriminated for all Burst continue cycles.Pipelined and Flow Through Read Write Control State DiagramDeselectNew ReadNew WriteBurst ReadBurst WriteWRBRBWDDBBWRD BWRDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input commandcodes as indicated in the Synchronous Truth Table.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipelined and Flow Through Read/Write Control State DiagramWRPipeline Mode Data I/O State DiagramIntermediateIntermediateIntermediateIntermediateIntermediateIntermediateHigh Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)TransitionƒInput Command CodeKeyTransitionIntermediate State (N+1)Notes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateIntermediate ƒn n+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipeline Mode Data I/O State DiagramNext StateStateFlow Through Mode Data I/O State DiagramHigh Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for: Pipeline and Flow through Read Write Control State DiagramBurst CyclesAlthough NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.Burst OrderThe burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have beenaccessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details.Note:There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.Burst Counter SequencesBPR 1999.05.18Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved BurstPower Down ControlZZL or NC Active HStandby, I DD = I SBThe burst counter wraps to initial state on the 5th clock.The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1staddress 000110112nd address 010011103rd address 101100014th address11100100Sleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramDesigning for CompatibilityThe GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V DD or V DDQ on pipelined parts and V SS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.tZZRtZZHtZZStKLtKHtKCCKZZAbsolute Maximum Ratings(All voltages reference to V SS)Symbol Description Value UnitV DD Voltage on V DD Pins–0.5 to 3.6VV DDQ Voltage in V DDQ Pins–0.5 to 3.6VV I/O Voltage on I/O Pins–0.5 to V DDQ +0.5 (≤ 3.6 V max.)VV IN Voltage on Other Input Pins–0.5 to V DD +0.5 (≤ 3.6 V max.)VI IN Input Current on Any Pin+/–20mAI OUT Output Current on Any I/O Pin+/–20mAP D Package Power Dissipation 1.5WT STG Storage Temperature–55 to 125o CT BIAS Temperature Under Bias–55 to 125o C Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.Power Supply Voltage RangesParameter Symbol Min.Typ.Max.Unit Notes1.8 V Supply Voltage V DD1 1.6 1.82.0V1.8 V V DDQ I/O Supply Voltage V DDQ1 1.6 1.82.0VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.Note:These parameters are sample tested.Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.3*V DD V 1V DDQ I/O Input High Voltage V IHQ 0.6*V DD —V DDQ + 0.3V 1,3V DDQ I/O Input Low VoltageV ILQ–0.3—0.3*V DDV1,3Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.Capacitance(T A = 25o C, f = 1 MH Z , V DD = 2.5 V)ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pF20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILAC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. DC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA ZZ Input Current I IN1V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH –1 uA –1 uA 1 uA 100 uA FT, SCD, and ZQ Input Current I IN2V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL–100 uA –1 uA 1 uA 1 uA Output Leakage Current I OL Output Disable, V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V—Output Low VoltageV OL1I OL = 4 mA, V DD = 1.6 V—0.4 VDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceN o t e s : 1.I D D a n d I D D Q a p p l y t o a n y c o m b i n a t i o n o f V D D 3, V D D 2, V D D Q 3, a n d V D D Q 2 o p e r a t i o n .2.A l l p a r a m e t e r s l i s t e d a r e w o r s t c a s e s c e n a r i o .O p e r a t i n g C u r r e n t sP a r a m e t e r T e s t C o n d i t i o n sM o d e S y m b o l -250-225-200-166-150-133U n i t 0t o 70°C–40 t o 85°C 0t o 70°C –40 t o 85°C 0t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C O p e r a t i n g C u r r e n tD e v i c e S e l e c t e d ; A l l o t h e r i n p u t s ≥V I H o r ≤ V I LO u t p u t o p e n(x 32/x 36)P i p e l i n e I D DI D D Q 300503205027545295452554027540225352453521030230301902521025m AF l o w T h r o u g h I D D I D D Q210252202520025210251902020020180201902017020180201601517015m A(x 18)P i p e l i n eI D DI D D Q260252802524025260252252024520200202202019020210201701519015m AF l o w T h r o u g hI D DI D D Q190152001518015190151701518015160151701515015160151401515015m AS t a n d b y C u r r e n tZ Z ≥ V D D – 0.2 V—P i p e l i n eI S B608060806080608060806080m AF l o w T h r o u g hI S B608060806080608060806080m AD e s e l e c t C u r r e n tD e v i c e D e s e l e c t e d ; A l l o t h e r i n p u t s ≥ V I H o r ≤ V I L—P i p e l i n eI D D100115951109010585100851008095m AF l o w T h r o u g hI D D85100851008095809575907085m ANotes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.AC Electrical CharacteristicsParameter Symbol -250-225-200-166-150-133UnitMin Max Min Max Min Max Min Max Min Max Min Max Flow ThroughClock Cycle Time tKC 5.5— 6.0— 6.5—7.0—7.5—8.5—ns Clock to Output ValidtKQ — 5.5— 6.0— 6.5—7.0—7.5—8.5ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3— 1.3— 1.5— 1.7—ns Clock LOW Time tKL 1.5—1.5—1.5—1.5— 1.7—2—ns Clock to Output inHigh-Z tHZ 1 1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns G to Output Valid tOE — 2.5— 2.7— 3.0— 3.5— 3.8— 4.0ns G to output in Low-Z tOLZ 10—0—0—0—0—0—ns G to output in High-Z tOHZ 1— 2.5— 2.7— 3.0— 3.0— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—20—nsPipeline Mode Timing (NBT)Write AWrite BWrite B+1Read CContRead DWrite ERead FDESELECTD(A)D(B)D(B+1)Q(C)Q(D)D(E)Q(F)tOLZtOEtOHZtHZtKQXtKQtLZ tHtStHtStHtStHtStHtStHtStHtStKC tKLtKHA BCD E FG*Note: E=High(False) if E1 = 1 or E2 = 0 or E3 = 1CKCKEE*ADVWBnA0–An DQa–DQd GFlow Through Mode Timing (NBT)JTAG Port OperationOverviewThe JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V DD . The JTAG output drivers are powered by V DDQ .Disabling the JTAG PortIt is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V DD or V SS . TDO should be left unconnected.Write AWrite BWrite B+1Read CCont Read D Write E Read F Write GD(A)D(B)D(B+1)Q(C)Q(D)D(E)Q(F)D(G)tOLZ tOEtOHZtKQXtKQtLZtHZtKQX tKQ tLZtHtStHtStHtStHtStHtStHtStHtStKCtKLtKHABCDEFG*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1CKCKEEADVWBnA0–AnDQGJTAG Port RegistersOverviewThe various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.Instruction RegisterThe Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.Bypass RegisterThe Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.Boundary Scan RegisterThe Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is inCapture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.JTAG Pin Descriptions PinPin NameI/ODescriptionTCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.TMSTest Mode SelectInThe TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level.TDI Test Data In InThe TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.TDO Test Data OutOut Output that is active depending on the state of the TAP state machine. Output changes inresponse to the falling edge of TCK. This is the output side of the serial registers placed betweenTDI and TDO.This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.。

GS864436B-166I中文资料

Product PreviewGS864418(B/E)/GS864436(B/E)/GS864472(C)4M x 18, 2M x 36, 1M x 7272Mb S/DCD Sync Burst SRAMs250 MHz –133MHz 2.5 V or 3.3 V V DD 2.5 V or 3.3 V I/O119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp Features• FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable• IEEE 1149.1 JTAG-compatible Boundary Scan• ZQ mode pin for user-selectable high/low output drive • 2.5 V or 3.3 V +10%/–10% core power supply • LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications• JEDEC-standard 119-, 165-, and 209-bump BGA packageFunctional DescriptionApplicationsThe GS864418/36/72 is a 75,497,472-bit high performancesynchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application insynchronous SRAM applications, ranging from DSP main store to networking chip set support.ControlsAddresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.SCD and DCD Pipelined ReadsThe GS864418/36/72 is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.FLXDrive™The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.Sleep ModeLow power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS864418/36/72 operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.Parameter Synopsis-250-225-200-166-150-133UnitPipeline 3-1-1-1t KQ (x18/x36)t KQ (x72)tCycle 2.53.04.0 2.73.04.4 3.03.05.0 3.53.56.0 3.83.86.7 4.04.07.5ns ns ns Curr (x36)Curr (x72)450540415505385460345405325385295345mA mA Flow Through 2-1-1-1t KQ tCycle 6.5 6.5 6.57.07.58.5ns Curr (x36)Curr (x72)290345290345290345280335265315245300mA mAGS864418(B/E)/GS864436(B/E)/GS864472(C) GS864472C Pad Out—209-Bump BGA—Top View (Package C)1234567891011A DQ G DQ G A E2ADSP ADSC ADV E3A DQB DQ B AB DQ G DQ G BC BG NC BW A BB BF DQ B DQ B BC DQ G DQ G BH BD NC E1NC BE BA DQ B DQ B CD DQ G DQ G V SS NC NC G GW NC V SS DQ B DQ B DE DQP G DQP C V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQPF DQP B EF DQ C DQ C V SS V SS V SS ZQ V SS V SS V SS DQ F DQ F FG DQ C DQ C V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQ F DQ F GH DQ C DQ C V SS V SS V SS MCL V SS V SS V SS DQ F DQ F H J DQ C DQ C V DDQ V DDQ V DD MCL V DD V DDQ V DDQ DQ F DQ F J K NC NC CK NC V SS MCL V SS NC NC NC NC K L DQ H DQ H V DDQ V DDQ V DD FT V DD V DDQ V DDQ DQ A DQ A L M DQ H DQ H V SS V SS V SS MCL V SS V SS V SS DQ A DQ A M N DQ H DQ H V DDQ V DDQ V DD SCD V DD V DDQ V DDQ DQ A DQ A N P DQ H DQ H V SS V SS V SS ZZ V SS V SS V SS DQ A DQ A P R DQP D DQP H V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQP A DQP E R T DQ D DQ D V SS NC NC LBO NC NC V SS DQ E DQ E T U DQ D DQ D A A A A A A A DQ E DQ E U V DQ D DQ D A A A A1A A A DQ E DQ E V W DQ D DQ D TMS TDI A A0A TDO TCK DQ E DQ E W11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump PitchGS864418(B/E)/GS864436(B/E)/GS864472(C)GS864472 209-Bump BGA Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter Preset Inputs.A I Address InputsDQ ADQ BDQ CDQ DI/O Data Input and Output pinsDQ EDQ FDQ GDQ HB A, B B I Byte Write Enable for DQ A, DQ B I/Os; active lowB C,B D I Byte Write Enable for DQ C, DQ D I/Os; active lowB E, B F, B G,B H I Byte Write Enable for DQ E, DQ F, DQ G, DQ H I/Os; active lowNC—No ConnectCK I Clock Input Signal; active highGW I Global Write Enable—Writes all bytes; active lowE1I Chip Enable; active lowE3I Chip Enable; active lowE2I Chip Enable; active highG I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active highFT I Flow Through or Pipeline mode; active lowLBO I Linear Burst Order mode; active lowSCD I Single Cycle Deselect/Dual Cycle Deselect Mode ControlMCH I Must Connect HighGS864418(B/E)/GS864436(B/E)/GS864472(C)MCL Must Connect Low BW I Byte Enable; active lowZQ I FLXDrive Output Impedance Control(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS864472 209-Bump BGA Pin Description (Continued)SymbolType DescriptionGS864418(B/E)/GS864436(B/E)/GS864472(C) 165-Bump BGA—x18 Commom I/O—Top View (Package E)1234567891011A NC A E1BB NC E3BW ADSC ADV A A AB NC A E2NC BA CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPA CD NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA DE NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA EF NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA FG NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA GH FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ HJ DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC JK DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC KL DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC LM DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC MN DQPB SCD V DDQ V SS NC A NC V SS V DDQ NC NC NP NC A A A TDI A1TDO A A A A PR LBO A A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump PitchGS864418(B/E)/GS864436(B/E)/GS864472(C) 165-Bump BGA—x36 Common I/O—Top View (Package E)1234567891011A NC A E1BC BB E3BW ADSC ADV A NC AB NC A E2BD BA CK GW G ADSP A NC BC DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB CD DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB DE DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB EF DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB FG DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB GH FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ HJ DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA JK DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA KL DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA LM DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA MN DQPD SCD V DDQ V SS NC A NC V SS V DDQ NC DQPA NP NC A A A TDI A1TDO A A A A PR LBO A A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump PitchGS864418(B/E)/GS864436(B/E)/GS864472(C)GS864418/36 165-Bump BGA Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter Preset InputsA I Address InputsDQ ADQ BDQ CDQ DI/O Data Input and Output pinsB A, B B, B C, B D I Byte Write Enable for DQ A, DQ B, DQ C, DQ D I/Os; active low (x36 Version)NC—No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active lowGW I Global Write Enable—Writes all bytes; active lowE1I Chip Enable; active lowE3I Chip Enable; active lowE2I Chip Enable; active highG I Output Enable; active lowADV I Burst address counter advance enable; active l0w ADSC, ADSP I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep mode control; active highFT I Flow Through or Pipeline mode; active lowLBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])TMS I Scan Test Mode SelectTDI I Scan Test Data InTDO O Scan Test Data OutTCK I Scan Test ClockMCL—Must Connect Low SCD—Single Cycle Deselect/Dual Cyle Deselect Mode Control V DD I Core power supplyV SS I I/O and Core GroundV DDQ I Output driver power supplyGS864418(B/E)/GS864436(B/E)/GS864472(C) GS864436B Pad Out—119-Bump BGA—Top View (Package B)1234567A V DDQ A A ADSP A A V DDQ AB NC A A ADSC A A NC BC NC A A V DD A A NC CD DQ C DQP C V SS ZQ V SS DQP B DQ B DE DQ C DQ C V SS E1V SS DQ B DQ B EF V DDQ DQ C V SSG V SS DQ B V DDQ FG DQ C DQ C BC ADV BB DQ B DQ B GH DQ C DQ C V SS GW V SS DQ B DQ B HJ V DDQ V DD NC V DD NC V DD V DDQ JK DQ D DQ D V SS CK V SS DQ A DQ A KL DQ D DQ D BD SCD BA DQ A DQ A LM V DDQ DQ D V SS BW V SS DQ A V DDQ MN DQ D DQ D V SS A1V SS DQ A DQ A NP DQ D DQP D V SS A0V SS DQP A DQ A PR NC A LBO V DD FT A NC RT NC A A A A A ZZ TU V DDQ TMS TDI TCK TDO NC V DDQ U7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump PitchGS864418(B/E)/GS864436(B/E)/GS864472(C) GS864418B Pad Out—119-Bump BGA—Top View (Package B)1234567A V DDQ A A ADSP A A V DDQ AB NC A A ADSC A A NC BC NC A A V DD A A NC CD DQ B NC V SS ZQ V SS DQP A NC DE NC DQ B V SS E1V SS NC DQ A EF V DDQ NC V SSG V SS DQ A V DDQ FG NC DQ B BB ADV NC NC DQ A GH DQ B NC V SS GW V SS DQ A NC HJ V DDQ V DD NC V DD NC V DD V DDQ JK NC DQ B V SS CK V SS NC DQ A KL DQ B NC NC SCD BA DQ A NC LM V DDQ DQ B V SS BW V SS NC V DDQ MN DQ B NC V SS A1V SS DQ A NC NP NC DQP B V SS A0V SS NC DQ A PR NC A LBO V DD FT A NC RT A A A A A A ZZ TU V DDQ TMS TDI TCK TDO NC V DDQ U7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump PitchGS864418(B/E)/GS864436(B/E)/GS864472(C)GS864418/36 119-Bump BGA Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter Preset InputsA I Address InputsDQ ADQ BDQ CDQ DI/O Data Input and Output pinsB A, B B, B C, B D I Byte Write Enable for DQ A, DQ B, DQ C, DQ D I/Os; active lowNC—No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active lowGW I Global Write Enable—Writes all bytes; active lowE1I Chip Enable; active lowG I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep mode control; active highFT I Flow Through or Pipeline mode; active lowLBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])SCD I Single Cycle Deselect/Dual Cyle Deselect Mode Control TMS I Scan Test Mode SelectTDI I Scan Test Data InTDO O Scan Test Data OutTCK I Scan Test ClockV DD I Core power supplyV SS I I/O and Core GroundV SS I I/O and Core GroundV DDQ I Output driver power supplyGS864418(B/E)/GS864436(B/E)/GS864472(C)GS864418/36/72 Block DiagramA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–An LBO ADV CK ADSC ADSP GW BW E 1FT GZZPower Down ControlMemory Array36364AQD DQx1–DQx93636Note: Only x36 version shown for simplicity.SCD3636B AB BB CB DGS864418(B/E)/GS864436(B/E)/GS864472(C)Note:There are pull-up devices onthe ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.Burst Counter SequencesBPR 1999.05.18Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, I DD = I SB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance ControlZQL High Drive (Low Impedance)H or NCLow Drive (High Impedance)Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100GS864418(B/E)/GS864436(B/E)/GS864472(C)1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C , and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.Byte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytesHLLLLL2, 3, 4Write all bytes L X X X X XGS864418(B/E)/GS864436(B/E)/GS864472(C) Synchronous Truth TableOperation Address UsedStateDiagramKey5E1ADSP ADSC ADV W3DQ4Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CW H X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend Burst Current H X H H T D Notes:1.X = Don’t Care, H = High, L = Low2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS864418(B/E)/GS864436(B/E)/GS864472(C)Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWX XWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs andassumes ADSP is tied high and ADV is tied low.GS864418(B/E)/GS864436(B/E)/GS864472(C)Simplified State Diagram with GFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS864418(B/E)/GS864436(B/E)/GS864472(C)Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage in V DDQ Pins –0.5 to 4.6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCPower Supply Voltage RangesParameterSymbolMin.Typ.Max.UnitNotes3.3 V Supply Voltage V DD3 3.0 3.3 3.6V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 3.3 V V DDQ I/O Supply Voltage V DDQ3 3.0 3.3 3.6V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.52.7VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS864418(B/E)/GS864436(B/E)/GS864472(C)V DDQ3 Range Logic LevelsParameter Symbol Min.Typ.Max.Unit Notes V DD Input High Voltage V IH 2.0—V DD + 0.3V1V DD Input Low Voltage V IL–0.3—0.8V1V DDQ I/O Input High Voltage V IHQ 2.0—V DDQ + 0.3V1,3V DDQ I/O Input Low Voltage V ILQ–0.3—0.8V1,3 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.V DDQ2 Range Logic LevelsParameter Symbol Min.Typ.Max.Unit Notes V DD Input High Voltage V IH0.6*V DD—V DD + 0.3V1V DD Input Low Voltage V IL–0.3—0.3*V DD V1V DDQ I/O Input High Voltage V IHQ0.6*V DD—V DDQ + 0.3V1,3V DDQ I/O Input Low Voltage V ILQ–0.3—0.3*V DD V1,3 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.Recommended Operating TemperaturesParameter Symbol Min.Typ.Max.Unit Notes Ambient Temperature (Commercial Range Versions)T A02570°C2 Ambient Temperature (Industrial Range Versions)T A–402585°C2 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS864418(B/E)/GS864436(B/E)/GS864472(C)Note:These parameters are sample tested.Capacitance(T A = 25o C, f = 1 MH Z , V DD = 2.5 V)ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 810pF Input/Output Capacitance C I/OV OUT = 0 V1214pFAC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 1Notes:1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. 20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceGS864418(B/E)/GS864436(B/E)/GS864472(C)DC Electrical CharacteristicsParameter Symbol Test Conditions Min Max Input Leakage Current(except mode pins)I IL V IN = 0 to V DD–1 uA 1 uAZZ Input Current I IN1V DD≥V IN ≥V IH0 V≤ V IN ≤ V IH–1 uA–1 uA1 uA100 uAFT, SCD, and ZQ Input Current I IN2V DD≥V IN ≥V IL0 V≤ V IN ≤ V IL–100 uA–1 uA1 uA1 uAOutput Leakage Current I OL Output Disable, V OUT = 0 to V DD–1 uA 1 uA Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V 1.7 V—Output High Voltage V OH3I OH = –8 mA, V DDQ = 3.135 V 2.4 V—Output Low Voltage V OL I OL = 8 mA—0.4 VGS864418(B/E)/GS864436(B/E)/GS864472(C)N o t e s : 1.I D D a n d I D D Q a p p l y t o a n y c o m b i n a t i o n o f V D D 3, V D D 2, V D D Q 3, a n d V D D Q 2 o p e r a t i o n .2.A l l p a r a m e t e r s l i s t e d a r e w o r s t c a s e s c e n a r i o .O p e r a t i n g C u r r e n t sP a r a m e t e r T e s t C o n d i t i o n s M o d eS y m b o l -250-225-200-166-150-133U n i t0t o 70°C –40 t o 85°C0t o 70°C–40 t o 85°C 0t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C O p e r a t i n g C u r r e n tD e v i c e S e l e c t e d ; A l l o t h e r i n p u t s ≥V I H o r ≤ V I LO u t p u t o p e n(x 72)P i p e l i n eI D DI D D Q480605156044560480604105044550365404004034540380403153035030m AF l o w T h r o u g hI D DI D D Q315303403031530340303153034030305303303028530310302802030520m A(x 36)P i p e l i n eI D DI D D Q400504355037045405453454038040310353453529530330302702530525m AF l o w T h r o u g hI D DI D D Q270202952027020295202702029520260202852024520270202301525515m A(x 18)P i p e l i n eI D DI D D Q360253952533525370253152035020285203202027520310202501528515m AF l o w T h r o u g hI D DI D D Q250152751525015275152501527515240152601522515250152101523515m AS t a n d b y C u r r e n tZ Z ≥ V D D – 0.2 V—P i p e l i n eI S B 120160120160120160120160120160120160m AF l o w T h r o u g hI S B120160120160120160120160120160120160m AD e s e l e c t C u r r e n tD e v i c e D e s e l e c t e d ; A l l o t h e r i n p u t s ≥ V I H o r ≤ V I L—P i p e l i n eI D D200230190220180210170200170200160190m AF l o w T h r o u g hI D D170200170200160190160190150180140170m AGS864418(B/E)/GS864436(B/E)/GS864472(C)Notes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.AC Electrical CharacteristicsParameterSymbol-250-225-200-166-150-133UnitMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxPipelineClock Cycle Time tKC 4.0— 4.4— 5.0— 6.0— 6.7—7.5—ns Clock to Output Valid(x18/x36)tKQ — 2.5— 2.7— 3.0— 3.5— 3.8— 4.0ns Clock to Output Valid(x72)tKQ — 3.0— 3.0— 3.0— 3.5— 3.8— 4.0ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Setup time tS 1.3— 1.3— 1.4— 1.5— 1.5— 1.5—ns Hold Time tH 0.2—0.3—0.4—0.5—0.5—0.5—ns Flow ThroughClock Cycle Time tKC 6.5— 6.5— 6.5—7.0—7.5—8.5—ns Clock to Output ValidtKQ — 6.5— 6.5— 6.5—7.0—7.5—8.5ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3— 1.3— 1.5— 1.7—ns Clock LOW Time tKL 1.5—1.5—1.5—1.5— 1.7—2—ns Clock to Output inHigh-Z (x18/x36)tHZ 1 1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns Clock to Output in High-Z (x72)tHZ 1 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns G to Output Valid (x18/x36)tOE — 2.5— 2.7— 3.2— 3.5— 3.8— 4.0ns G to Output Valid(x72)tOE — 3.0— 3.0— 3.2— 3.5— 3.8— 4.0ns G to output in Low-Z tOLZ 10—0—0—0—0—0—ns G to output in High-Z (x18/x36)tOHZ 1— 2.5— 2.7— 3.0— 3.0— 3.0— 3.0ns G to output in High-Z (x72)tOHZ 1— 3.0— 3.0— 3.0— 3.0— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—20—ns。

GS8662S08E-250I资料

PreliminaryGS8662S08/09/18/36E-333/300/250/200/16772Mb Burst of 2DDR SigmaSIO-II SRAM333 MHz–167 MHz1.8 V V DD1.8 V and 1.5 V I/O165-Bump BGA Commercial Temp Industrial Temp Features• Simultaneous Read and Write SigmaSIO™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface• Byte Write controls sampled at data-in time• DLL circuitry for wide output data valid window and future frequency scaling• Burst of 2 Read and Write• 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation• Fully coherent read and write pipelines• ZQ mode pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • Pin-compatible with future 144Mb devices• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package availableSigmaRAM ™ Family OverviewGS8662S08/09/18/36 are built in compliance with the SigmaSIO-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array Bottom ViewJEDEC Std. MO-216, Variation CAB-1Clocking and Addressing SchemesA Burst of 2 SigmaSIO-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K. The device also allows the user to manipulate the output register clock input quasi independently with dual output register clock inputs, C and C. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Each Burst of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs, CQ and CQ, which are synchronized with read data output. When used in a source synchronous clocking scheme, the Echo Clock outputs can be used to fire input registers at the data’s destination.Because Separate I/O Burst of 2 RAMs always transfer data in two packets, A0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a Burst of 2 RAM is always one address pin less than the advertised index depth (e.g., the 4M x 18 has a 1M addressable index).Parameter Synopsis- 333-300-250-200-167tKHKH 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns tKHQV0.45 ns0.45 ns0.45 ns0.45 ns0.5 ns8M x 8 SigmaQuad SRAM—Top View1234567891011ACQ SA SA R/W NW1K NC LD SA SA CQ B NC NC NC SA NC K NW0SA NC NC Q3C NC NC NC V SS SA SA SA V SS NC NC D3D NC D4NC V SS V SS V SS V SS V SS NC NC NC E NC NC Q4 V DDQ V SS V SS V SS V DDQ NC D2Q2F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC D5Q5 V DDQ V DD V SS V DD V DDQ NC NC NC H D OFF V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC Q1D1K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC Q6D6 V DDQ V SS V SS V SS V DDQ NC NC Q0M NC NC NC V SS V SS V SS V SS V SS NC NC D0N NC D7NC V SS SA SA SA V SS NC NC NC P NC NC Q7SA SA C SA SA NC NC NC RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.2.It is recommended that H1 be tied low for compatibility with future devices.GS8662S08/09/18/36E-333/300/250/200/1678M x 9 SigmaQuad SRAM—Top View1234567891011ACQ SA SA R/W NC K NC LD SA SA CQ B NC NC NC SA NC K BW SA NC NC Q4C NC NC NC V SS SA SA SA V SS NC NC D4D NC D5NC V SS V SS V SS V SS V SS NC NC NC E NC NC Q5 V DDQ V SS V SS V SS V DDQ NC D3Q3F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC D6Q6 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC Q2D2K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC Q7D7 V DDQ V SS V SS V SS V DDQ NC NC Q1M NC NC NC V SS V SS V SS V SS V SS NC NC D1N NC D8NC V SS SA SA SA V SS NC NC NC P NC NC Q8SA SA C SA SA NC D0NC RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.BW controls writes to D0:D71.It is recommended that H1 be tied low for compatibility with future devices.GS8662S08/09/18/36E-333/300/250/200/1674M x 18 SigmaQuad SRAM—Top View1234567891011ACQ V SS /SA (144Mb)SA R/W BW1K NC LD SA SA CQ B NC Q9D9SA NC K BW0SA NC NC Q8C NC NC D10V SS SA SA SA V SS NC Q7D8D NC D11Q10V SS V SS V SS V SS V SS NC NC D7E NC NC Q11 V DDQ V SS V SS V SS V DDQ NC D6Q6F NC Q12D12 V DDQ V DD V SS V DD V DDQ NC NC Q5G NC D13Q13 V DDQ V DD V SS V DD V DDQ NC NC D5H D OFF V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC D14 V DDQ V DD V SS V DD V DDQ NC Q4D4K NC NC Q14V DDQ V DD V SS V DD V DDQ NC D3Q3L NC Q15D15 V DDQ V SS V SS V SS V DDQ NC NC Q2M NC NC D16 V SS V SS V SS V SS V SS NC Q1D2N NC D17Q16 V SS SA SA SA V SS NC NC D1P NC NC Q17SA SA C SA SA NC D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.2.It is recommended that H1 be tied low for compatibility with future devices.GS8662S08/09/18/36E-333/300/250/200/1672M x 36 SigmaQuad SRAM—Top View1234567891011ACQ V SS /SA (288Mb)SA R/W BW2K BW1LD SA V SS /SA (144Mb)CQ B Q27Q18D18SA BW3K BW0SA D17Q17Q8C D27Q28D19V SS SA SA SA V SS D16Q7D8D D28D20Q19V SS V SS V SS V SS V SS Q16D15D7E Q29D29Q20 V DDQ V SS V SS V SS V DDQ Q15D6Q6F Q30Q21D21 V DDQ V DD V SS V DD V DDQ D14Q14Q5G D30D22Q22 V DDQ V DD V SS V DD V DDQ Q13D13D5H D OFF V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J D31Q31D23 V DDQ V DD V SS V DD V DDQ D12Q4D4K Q32D32Q23V DDQ V DD V SS V DD V DDQ Q12D3Q3L Q33Q24D24 V DDQ V SS V SS V SS V DDQ D11Q11Q2M D33Q34D25 V SS V SS V SS V SS V SS D10Q1D2N D34D26Q25 V SS SA SA SA V SS Q10D9D1P Q35D35Q26SA SA C SA SA Q9D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.2.BW2 controls writes to D18:D26. BW3 controls writes to D27:D35.3.It is recommended that H1 be tied low for compatibility with future devices.GS8662S08/09/18/36E-333/300/250/200/167Pin Description TableSymbolDescriptionTypeCommentsSA Synchronous Address InputsInput —NC No Connect ——R/W Read/Write Contol Pin Input Write Active Low; Read Active HighNW0–NW1Synchronous Nybble Writes Input Active Low x08 Version BW0–BW1Synchronous Byte Writes Input Active Low x18 Version BW0–BW3Synchronous Byte WritesInput Active Low x36 Version K Input Clock Input Active High C Output Clock Input Active HighTMS Test Mode Select Input —TDI Test Data Input Input —TCK Test Clock Input Input —TDO Test Data Output Output —V REF HSTL Input Reference Voltage Input —ZQ Output Impedance Matching InputInput —K Input Clock Input Active Low C Output Clock Output Active Low D OFF DLL Disable —Active Low LD Synchronous Load Pin —Active Low CQ Output Echo Clock Output Active Low CQ Output Echo Clock Output Active HighDn Synchronous Data Inputs Input Qn Synchronous Data OutputsOutput V DD Power Supply Supply 1.8 V Nominal V DDQ Isolated Output Buffer Supply Supply 1.8 or 1.5 V NominalV SSPower Supply: GroundSupply—1.C, C, K, or K cannot be set to V REF voltage.2.When ZQ pin is directly connected to V DD , output impedance is set to minimum value and it cannot be connected to ground or leftunconnected.3.NC = Not Connected to die or any other pinGS8662S08/09/18/36E-333/300/250/200/167GS8662S08/09/18/36E-333/300/250/200/167BackgroundSeparate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write addresses like SigmaCIO SRAMs, but in a separate I/O configuration.Like a SigmaQuad SRAM, a SigmaSIO-II SRAM can execute an alternating sequence of reads and writes. However, doing so results in the Data In port and the Data Out port stalling with nothing to do on alternate transfers. A SigmaQuad device would keep both ports running at capacity full time. On the other hand, the SigmaSIO device can accept a continuous stream of read commands and read data or a continuous stream of write commands and write data. The SigmaQuad device, by contrast, restricts the user from loading a continuous stream of read or write addresses. The advantage of the SigmaSIO device is that it allows twice the random address bandwidth for either reads or writes than could be acheived with a SigmaQuad version of the device. SigmaCIO SRAMs offer this same advantage, but do not have the separate Data In and Data Out pins offered on the SigmaSIO SRAMs. Therefore, SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of burst traffic between two electrically independent busses is desired.Each of the three SigmaQuad Family SRAMs—SigmaQuad, SigmaCIO, and SigmaSIO—supports similar address rates because random address rate is determined by the internal performance of the RAM. In addition, all three SigmaQuad Family SRAMs are based on the same internal circuits. Differences between the truth tables of the different devices proceed from differences in how the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application at hand.Burst of 2 Sigma SIO-II SRAM DDR ReadThe status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A high on the R/W pin begins a read cycle. The two resulting data output transfers begin after the next rising edge of the K clock. Data is clocked out by the next rising edge of the C if it is active. Otherwise, data is clocked out at the next rising edge of K. The next data chunk is clocked out on the rising edge of C, if active. Otherwise, data is clocked out on the rising edge of K.Burst of 2 Sigma SIO-II SRAM DDR WriteThe status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A low on the R/W pin, begins a write cycle. Data is clocked in by the next rising edge of K and then the rising edge of K.GS8662S08/09/18/36E-333/300/250/200/167Power-Up Sequence for SigmaQuad-II SRAMsSigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.Power-Up Sequence1. Power-up and maintain Doff at low state.1a.Apply V DD .1b. Apply V DDQ .1c. Apply V REF (may also be applied at the same time as V DDQ ).2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.Note:If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become stablized.DLL Constraints•The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t KCVar on page 21).•The DLL cannot operate at a frequency lower than 119 MHz.•If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage.Power-Up Sequence (Doff controlled)Power UP IntervalUnstable Clocking IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoffPower-Up Sequence (Doff tied High)Power UP IntervalUnstable Clocking IntervalStop Clock IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoff30ns MinNote:If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.GS8662S08/09/18/36E-333/300/250/200/167Special FunctionsByte Write and Nybble Write ControlByte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence.Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18 version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence.Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NWx” may be substituted in all the discussion above.Example x18 RAM Write Sequence using Byte Write EnablesData In SampleBW0BW1D0–D8D9–D17TimeBeat 101Data In Don’t CareBeat 210Don’t Care Data InResulting Write OperationBeat 1Beat 2D0–D8D9–D17D0–D8D9–D17Written Unchanged Unchanged WrittenOutput Register ControlSigmaSIO-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs.A K LD R/WA 0–A nK LD 0D 1–D nBank 0Bank 1Bank 2Bank 3R/W 0D A K R/W D A K R/W D A KR/W D LDLDLD QQQ QCCCCQ 1–Q nC LD 1R/W 1LD 2R/W 2LD 3R/W 3Note:For simplicity BWn is not shown.GS8662S08/09/18/36E-333/300/250/200/167Example Four Bank Depth Expansion SchematicGS8662S08/09/18/36E-333/300/250/200/167Burst of 2 SigmaSIO-II SRAM Depth ExpansionWrite BRead C Write D Read E Write F Read G Read H Read J NOPBCDEFGHJBB+1FF+1DD+1EE+1HH+1CC+1GG+1JK K Address LD Bank 1LD Bank 2R/W Bank 1R/W Bank 2BWx Bank 1BWx Bank 2D Bank 1D Bank 2C Bank 1C Bank 1Q Bank 1CQ Bank 1CQ Bank 1C Bank 2C Bank 2Q Bank 2CQ Bank 2CQ Bank 2GS8662S08/09/18/36E-333/300/250/200/167FLXDrive-II Output Driver Impedance ControlHSTL I/O SigmaSIO-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-specified tolerance is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Impedance updates for “0s” occur whenever the SRAM is driving “1s” for the same DQs (and vice-versa for “1s”) or the SRAM is in HI-Z.Separate I/O Burst of 2 Sigma SIO-II SRAM Truth TableA LD R/WCurrentOperationD D Q QK ↑(t n)K ↑(t n)K ↑(t n)K ↑(t n)K ↑(t n+1)K ↑(t n+1)K ↑(t n+1)K ↑(t n+1)X1X Deselect X—Hi-Z—V01Read X—Q0Q1 V00Write D0D1Hi-Z—Notes:1.“1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”2.“—” indicates that the input requirement or output state is determined by the next operation.3.Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations.4.D0 and D1 indicate the first and second pieces of input data transferred during Write operations.5.Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-ceded by a Read command.6.CQ is never tristated.ers should not clock in metastable addresses.x18 Byte Write Clock Truth TableBW BW Current OperationD D K ↑(t n+1)K ↑(t n+2)K ↑(t n )K ↑(t n+1)K ↑(t n+2)TTWriteDx stored if BWn = 0 in both data transfers D1D2T F WriteDx stored if BWn = 0 in 1st data transfer only D1XF T WriteDx stored if BWn = 0 in 2nd data transfer onlyX D2F F Write AbortNo Dx stored in either data transferX XNotes:1.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.2.If one or more BWn = 0, then BW = “T”, else BW = “F”.GS8662S08/09/18/36E-333/300/250/200/167x36 Byte Write Enable (BWn) Truth TableBW3BW2BW1BW0D27–D35D18–D26D9–D17D0–D81111Don’t Care Don’t Care Don’t Care Don’t Care 0111Don’t Care Don’t Care Don’t Care Data In 1011Don’t Care Don’t Care Data In Don’t Care 0011Don’t Care Don’t Care Data In Data In 1101Don’t Care Data In Don’t Care Don’t Care 0101Don’t Care Data In Don’t Care Data In 1001Don’t Care Data In Data In Don’t Care 0001Don’t Care Data In Data In Data In 1110Data In Don’t Care Don’t Care Don’t Care 0110Data In Don’t Care Don’t Care Data In 1010Data In Don’t Care Data In Don’t Care 0010Data In Don’t Care Data In Data In 1100Data In Data In Don’t Care Don’t Care 0100Data In Data In Don’t Care Data In 1000Data In Data In Data In Don’t Care 0Data InData InData InData Inx8 Nybble Write Enable (NWn) Truth Table NW1NW0D9–D17D0–D811Don’t Care Don’t Care 01Don’t Care Data In 10Data In Don’t Care 0Data InData InGS8662S08/09/18/36E-333/300/250/200/167GS8662S08/09/18/36E-333/300/250/200/167State DiagramPower-UpNOPLoad NewDDR Read DDR WriteREADLOADWRITELOADLOADLOADLOADLOADAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 2.9V V DDQ Voltage in V DDQ Pins –0.5 to V DD V V REF Voltage in V REF Pins –0.5 to V DDQV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.3 (≤ 2.9 V max.)V V IN Voltage on Other Input Pins –0.5 to V DDQ +0.3 (≤ 2.9 V max.)V I IN Input Current on Any Pin +/–100mA dc I OUT Output Current on Any I/O Pin +/–100mA dcT J Maximum Junction Temperature125o C T STGStorage Temperature–55 to 125oCNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.GS8662S08/09/18/36E-333/300/250/200/167Recommended Operating ConditionsPower SuppliesParameterSymbolMin.Typ.Max.UnitSupply Voltage V DD 1.7 1.8 1.9V I/O Supply Voltage V DDQ 1.7 1.8 1.9V Reference VoltageV REF0.68—0.95VNotes:1.Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ V DDQ ≤ 1.6 V (i.e., 1.5 V I/O)and 1.7 V ≤ V DDQ ≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.2.The power supplies need to be powered up simultaneously or in the following sequence: V DD , V DDQ , V REF , followed by signal inputs. Thepower down sequence must be the reverse. V DDQ must not exceed V DD .Operating TemperatureParameterSymbolMin.Typ.Max.UnitAmbient Temperature (Commercial Range Versions)T A 02570°C Ambient Temperature (Industrial Range Versions)T A–402585°CGS8662S08/09/18/36E-333/300/250/200/167HSTL I/O DC Input CharacteristicsParameterSymbolMinMaxUnitsNotesDC Input Logic High V IH (dc)V REF + 0.1V DDQ + 0.3mV 1DC Input Logic LowV IL (dc)–0.3V REF – 0.1mV1Note:Compatible with both 1.8 V and 1.5 V I/O driversHSTL I/O AC Input CharacteristicsParameterSymbolMinMaxUnitsNotesAC Input Logic High V IH (ac)V REF + 0.2—mV 3,4AC Input Logic LowV IL (ac)—V REF – 0.2mV 3,4V REF Peak to Peak AC VoltageV REF (ac)—5% V REF (DC)mV1Notes:1.The peak to peak AC component superimposed on V REF may not exceed 5% of the DC component of V REF .2.To guarantee AC characteristics, V IH ,V IL , Trise, and Tfall of inputs and clocks must be within 10% of each other.3.For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.4.See AC Input Definition drawing below.V IH (ac)V REF V IL (ac)HSTL I/O AC Input Definitions20% tKHKHV SS – 1.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKHKHV DD + 1.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DDParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Output CapacitanceC OUTV OUT = 0 V67pFNote: This parameter is sample tested.GS8662S08/09/18/36E-333/300/250/200/167AC Test ConditionsParameterConditionsInput high level V DDQ Input low level 0 V Max. input slew rate 2 V/ns Input reference level V DDQ /2Output reference levelV DDQ /2Note:Test conditions as specified with output loading as shown unless otherwise noted.DQVT = V DDQ /250ΩRQ = 250 Ω (HSTL I/O)V REF = 0.75 VAC Test Load DiagramInput and Output Leakage CharacteristicsParameterSymbolTest ConditionsMin.MaxNotesInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –2 uA 2 uA DoffI INDOFF V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL –100 uA –2 uA 2 uA 2 uA Output Leakage CurrentI OLOutput Disable,V OUT = 0 to V DDQ–2 uA2 uA(T A = 25= 3.3 V)GS8662S08/09/18/36E-333/300/250/200/167Programmable Impedance HSTL Output Driver DC Electrical CharacteristicsParameterSymbolMin.Max.UnitsNotesOutput High Voltage V OH1 V DDQ /2 – 0.12V DDQ /2 + 0.12V 1, 3Output Low Voltage V OL1 V DDQ /2 – 0.12V DDQ /2 + 0.12V 2, 3Output High Voltage V OH2 V DDQ – 0.2V DDQ V 4, 5Output Low VoltageV OL2Vss0.2V4, 6Notes:1. I OH = (V DDQ /2) / (RQ/5) +/– 15% @ V OH = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).2. I OL = (V DDQ /2) / (RQ/5) +/– 15% @ V OL = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).3.Parameter tested with RQ = 250Ω and V DDQ = 1.5 V or 1.8 V4.Minimum Impedance mode, ZQ = V SS5.I OH = –1.0 mA6.I OL = 1.0 mAOperating CurrentsParameterSymbolTest Conditions-333-300-250-200-167Notes0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C Operating Current (x36): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBDTBDTBDTBDTBDTBDTBDTBDTBDTBD2, 3Operating Current (x18): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x9): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x8): DDR I DDV DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Standby Current (NOP): DDR I SB1Device deselected,I OUT= 0 mA, f = Max,All Inputs ≤ 0.2 V or ≥ V DD – 0.2 VTBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 4Notes:1.Power measured with output pins floating.2.Minimum cycle, I OUT = 0 mA3.Operating current is calculated with 50% read cycles and 50% write cycles.4.Standby Current is only after all pending read and write burst operations are completed.GS8662S08/09/18/36E-333/300/250/200/167GS8662S08/09/18/36E-333/300/250/200/167AC Electrical CharacteristicsParameterSymbol-333-300-250-200-167UnitsN o t e sMin Max Min Max Min Max Min Max Min MaxClockK, K Clock Cycle Time C, C Clock Cycle Time t KHKH t CHCH 3.0 3.5 3.3 4.2 4.0 6.3 5.07.9 6.08.4ns tTKC Variablet KCVar —0.2—0.2—0.2—0.2—0.2ns 5K, K Clock High Pulse Width C, C Clock High Pulse Width t KHKL t CHCL 1.2— 1.32— 1.6— 2.0— 2.4—ns K, K Clock Low Pulse Width C, C Clock Low Pulse Width t KLKH t CLCH 1.2— 1.32— 1.6— 2.0— 2.4—ns K to K High C to C Hight KHKH 1.35— 1.49— 1.8— 2.2— 2.7—ns K, K Clock High to C, C Clock High t KHCH 0 1.30 1.450 1.80 2.30 2.8ns DLL Lock Time t KCLock 1024—1024—1024—1024—1024—cycle 6K Static to DLL resett KCReset 30—30—30—30—30—nsOutput TimesK, K Clock High to Data Output Valid C, C Clock High to Data Output Valid t KHQV t CHQV —0.45—0.45—0.45—0.45—0.5ns 3K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold t KHQX t CHQX –0.45—–0.45—–0.45—–0.45—–0.5—ns 3K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid t KHCQV t CHCQV —0.45—0.45—0.45—0.45—0.5ns K, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold t KHCQX t CHCQX –0.45—–0.45—–0.45—–0.45—–0.5—ns CQ, CQ High Output Valid t CQHQV —0.25—0.27—0.30—0.35—0.40ns 7CQ, CQ High Output Hold t CQHQX –0.25—–0.27—–0.30—–0.35—–0.40—ns 7K Clock High to Data Output High-Z C Clock High to Data Output High-Z t KHQZ t CHQZ —0.45—0.45—0.45—0.45—0.5ns 3K Clock High to Data Output Low-Z C Clock High to Data Output Low-Zt KHQX1t CHQX1–0.45—–0.45—–0.45—–0.45—–0.5—ns3Setup TimesAddress Input Setup Time t AVKH 0.4—0.4—0.5—0.6—0.7—ns Control Input Setup Time t IVKH 0.4—0.4—0.5—0.6—0.7—ns 2Data Input Setup Timet DVKH0.28—0.3—0.35—0.4—0.5—nsGS8662S08/09/18/36E-333/300/250/200/167Hold TimesAddress Input Hold Time t KHAX 0.4—0.4—0.5—0.6—0.7—ns Control Input Hold Time t KHIX 0.4—0.4—0.5—0.6—0.7—ns Data Input Hold Timet KHDX0.28—0.3—0.35—0.4—0.5—nsNotes:1.All Address inputs must meet the specified setup and hold times for all latching clock edges.2.Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).3.If C, C are tied high, K, K become the references for C, C timing parameters4.To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus conten-tion because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and tempera-tures.5.Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.6.V DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V DD and input clock are stable.7.Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheetparameters reflect tester guard bands and test setup variations.AC Electrical Characteristics (Continued)ParameterSymbol-333-300-250-200-167UnitsN o t e sMin Max Min Max Min Max Min Max Min Max。

GS881Z36T-66I中文资料

Rev: 1.10 8/20001/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see .NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.PreliminaryGS881Z18/36T-11/100/80/668Mb Pipelined and Flow Through Synchronous NBT SRAMs 100 MHz–66 MHz3.3 V V DD2.5 V and3.3 V V DDQ100-Pin TQFP Commercial Temp Industrial TempRev: 1.10 8/20002/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/20003/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/20004/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/20005/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/20006/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/20007/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/20008/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/20009/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200010/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200011/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200012/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200013/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200014/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200015/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200016/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200017/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200018/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200019/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200020/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200021/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200022/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200023/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200024/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200025/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200026/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200027/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200028/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200029/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200030/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200031/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200032/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200033/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66Rev: 1.10 8/200034/34© 1998, Giga Semiconductor, Inc.Specifications cited are subject to change without notice. For latest documentation see Preliminary.GS881Z18/36T-11/100/80/66。

GS841E18AB-166中文资料

GS841E18AT/B-180/166/150/130/100256K x 18 Sync Cache Tag 180 MHz–100 MHz3.3 V V DD3.3 V and 2.5 V I/OTQFP, BGACommercial Temp Industrial Temp Features• 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O supply• Dual Cycle Deselect (DCD)• Intergrated data comparator for Tag RAM application • FT mode pin for flow through or pipeline operation• LBO pin for Linear or Interleave (Pentium TM and X86) Burst mode• Synchronous address, data I/O, and control inputs • Synchronous Data Enable (DE)• Asynchronous Output Enable (OE)• Asynchronous Match Output Enable (MOE)• Byte Write (BWE) and Global Write (GW) operation • Three chip enable signals for easy depth expansion • Internal self-timed write cycle• JTAG Test mode conforms to IEEE standard 1149.1• JEDEC-standard 100-lead TQFP package and 119-BGA • Pb-Free 100-lead TQFP package availableFunctional DescriptionThe GS841E18A is a 256K x 18 high performance synchronous DCD SRAM with integrated Tag RAM comparator. A 2-bit burst counter is included to provide burst interface with Pentium TM and other high performance CPUs. It is designed to be used as a Cache Tag SRAM, as well as data SRAM. Addresses, data IOs, match output, chip enables (CE1, CE2, CE3), address control inputs (ADSP, ADSC, ADV), and write control inputs (BW1, BW2, BWE, GW, DE) are synchronous and are controlled by a positive-edge-triggered clock (CLK).Output Enable (OE), Match Output Enable, and power down control (ZZ) are asynchronous. Burst can be initiated with either ADSP or ADSC inputs. Subsequent burst addresses are generated internally and are controlled by ADV. The burst sequence is either interleave order (Pentium TM or x86) or linear order, and is controlled by LBO.Output registers and the Match output register are provided andcontrolled by the FT mode pin (Pin 14). Through use of the FT mode pin, I/O registers can be programmed to perform pipeline or flow through operation. Flow Through mode reduces latency.Byte write operation is performed by using Byte Write Enable (BWE) input combined with two individual byte write signals BW1-2. In addition, Global Write (GW) is available for writing all bytes at one time.Compare cycles begin as a read cycle with output disabled so that compare data can be loaded into the data input register. Thecomparator compares the read data with the registered input data and a match signal is generated. The match output can be either in Pipeline or Flow Through modes controlled by the FT signal.Low power (Standby mode) is attained through the assertion of the ZZ signal, or by stopping the clock (CLK). Memory data is retained during Standby mode.JTAG boundary scan interface is provided using IEEE standard 1149.1 protocol. Four pins—Test Data In (TDI), Test Data Out(TDO), Test Clock (TCK) and Test Mode Select (TMS)—are used to perform JTAG function.The GS841E18A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate output (V DDQ ) pins are used to allow both 3.3 V or 2.5 V IO interface.Dual Cycle Deselect (DCD)The GS841E18A is a DCD pipelines synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD SRAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of the clock.Parameter Synopsis–180-166-150-133-100Pipeline 3-1-1-1t cycle t KQ I DD 5.5 ns 3.2 ns 335 mA 6.0 ns 3.5 ns 310 mA 6.6 ns 3.8 ns 275 mA 7.5 ns 4.0 ns 250 mA 10 ns 4.5 ns 190 mA Flow Through 2-1-1-1t KQ t cycle I DD8 ns 9.1 ns 210 mA8.5 ns 10 ns 190 mA10 ns 10 ns 190 mA11 ns 15 ns 140 mA12 ns 15 ns 140 mAGS841E18AT/B-180/166/150/130/100Pin Configuration (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS D DQ V SS V DDQ DQ DQ V DD NC V SS DQ DQ V DDQ V SS DQ DQ DQ P V SS V DDQ V DDQ V SS DQ DQ V SS VDDQ DQ DQ V SS NC V DD ZZ DQ DQ V DDQ V SS DQ DQ V SS V DDQL B O A A A A A 1A 0T M S T D I V S SV D DT D O T C K A A A A A AA A C E 1C E 2 N C N C B W 2B W 1C E 3C L K G W B W E VD DV S SO E A D S C A D S P A D V A AA 256K x 18Top View DQ P A NC NC NC NC NC DE MATCHMOENC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950FTGS841E18AT/B-180/166/150/130/100 GS841E18A PadOut—119-Bump BGA—Top View (Package B)1234567A V DDQ A A ADSP A A V DDQB NC E2A ADSC A E3NCC NC A A V DD A A NCD DQ B NC V SS NC V SS DQ P NCE NC DQ B V SS E1V SS NC DQ AF V DDQ NC V SSG V SS DQ A V DDQG NC D Q B B B ADV NC NC DQ AH DQ B N C V SS GW V SS DQ A NCJ V DDQ V DD NC V DD NC V DD V DDQK NC DQ B V SS CK V SS NC DQ AL DQ B NC NC NC B A DQ A NCM V DDQ DQ B V SS BW V SS MATCH V DDQN DQ B NC V SS A1V SS DQ A DEP NC DQ P V SS A0V SS MOE DQ AR NC A LBO V DD FT A NCT NC A A NC A A ZZU V DDQ TMS TDI TCK TDO NC V DDQGS841E18AT/B-180/166/150/130/100TQFP Pin DescriptionSymbol DescriptionAn Address Input Signals—Inputs are registered and must meet setup and hold times, as specified onpage 11.CLK Clock Input SignalBWE Byte Write Enable Signal—The byte write enable signal needs to be combined with one of the fourbyte write signals for a write operation to occur.BW1Byte Write signal for data outputs 1 thru 8BW2Byte Write signal for data outputs 9 thru 16GW Global Write EnableCE1,CE2, CE3Chip EnablesOE Output EnableADV Burst address advanceADSP, ADSC Address status signalsDQ Data Input and Output pinsDQP Parity Input and Output pinsMATCH Match OutputMOE Match Output EnableDE Data Enable—Data input registers are updated only when DE is active.ZZ Power down control—Application of ZZ will result in a low standby power consumption.FT Flow Through or Pipeline modeLBO Linear Order Burst modeTMS Test Mode SelectTDI Test Data InTDO Test Data OutTCK Test ClockV DD 3.3 V power supplyV SS GroundV DDQ 2.5 V/3.3 V output power supplyNC No ConnectGS841E18AT/B-180/166/150/130/100PBGA Pin DescriptionSymbol DescriptionAn Address Input Signals—Inputs are registered and must meet setup and hold times, as specified onpage 11.CLK Clock Input SignalBWE Byte Write Enable Signal—The byte write enable signal needs to be combined with one of the fourbyte write signals for a write operation to occur.BW1Byte Write signal for data outputs 1 thru 8BW2Byte Write signal for data outputs 9 thru 16GW Global Write EnableCE1,CE2, CE3Chip EnablesOE Output EnableADV Burst address advanceADSP, ADSC Address status signalsDQ Data Input and Output pinsDQP Parity Input and Output pinsMATCH Match OutputMOE Match Output EnableDE Data Enable—Data input registers are updated only when DE is active.ZZ Power down control—Application of ZZ will result in a low standby power consumption.FT Flow Through or Pipeline modeLBO Linear Order Burst modeTMS Test Mode SelectTDI Test Data InTDO Test Data OutTCK Test ClockV DD 3.3 V power supplyV SS GroundV DDQ 2.5 V/3.3 V output power supplyNC No ConnectGS841E18AT/B-180/166/150/130/100Functional Block DiagramA1A0A0A1D0D1Q1Q0B INARY C OUNTERLoadD QR EGISTE RD QRegister D QRegister D QRegister D QRegister D QRegister DQRegisterDQRegisterA0-17LBO ADV CLK ADSC ADSPGW BWE BW1BW2CE1CE2CE3FTDQ1-16OE ZZPowerdown Control256K X 18Memory Array18181818218AQDDQP1-2DEDQRegisterMatchTAP ControllerInstruction Reg.ID Reg.Bypass Reg Boundary Scan Registers 54TCKTMS TDIA, DQ, ControlTDOMOE always (Ø)GS841E18AT/B-180/166/150/130/100Mode Pin FunctionLBOFunctionL Linear Burst H or NCInterleaved BurstFTFunctionL Flow Through H or NCPipelinePower Down ControlNote:There are pull up devices on LBO and FT pins and pull down device on ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.ZZFunctionL or NC Active HStandby, IDD = ISBLinear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Note: H = logic high, L = logic low, NC = no connectByte Write FunctionFunctionGWBWEBW1BW2Read H H X X Read H L H H Write all bytes L X X X Write all bytes H L L L Write byte 1H L L H Write byte 2HLHLGS841E18AT/B-180/166/150/130/100Notes:1.X means “don’t care,” H means “logic high,” L means “logic low.”2.Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.3.All inputs, except OE, must meet setup and hold on rising edge of CLK.4.Suspending busrt generates a wait cycle.5.ADSP LOW along with SRAM being selected always initiates a Read cycle at the L-H edge of the clock (CLK).6.A Write cycle can only be performed by setting Write low for the clock L-H edge of the subsequent wait cycle. Refer to page 12 for the Write timing diagram.Synchronous Truth TableOperationAddress UsedCE1CE2CE3ADSP ADSC ADV Write OE CLK DQ Deselect Cycle, Power Down none H X X X L X X X L-H High-Z Deselect Cycle, Power Down none L L X L X X X X L-H High-Z Deselect Cycle, Power Down none L X H L X X X X L-H High-Z Deselect Cycle, Power Down none L L X H L X X X L-H High-Z Deselect Cycle, Power Down none L X H H L X X X L-H High-Z Read Cycle, Begin Burst external L H L L X X X L L-H Q Read Cycle, Begin Burst external L H L L X X X H L-H High-Z Read Cycle, Begin Burst external L H L H L X H L L-H Q Read Cycle, Begin Burst external L H L H L X H H L-H High-Z Write Cycle, Begin Burst external L H L H L X L X L-H D Read Cycle, Continue Burst next X X X H H L H L L-H Q Read Cycle, Continue Burst next X X X H H L H H L-H High-Z Read Cycle, Continue Burst next H X X X H L H L L-H Q Read Cycle, Continue Burst next H X X X H L H H L-H High-Z Write Cycle, Continue Burst next X X X H H L L X L-H D Write Cycle, Continue Burst next H X X X H L L X L-H D Read Cycle, Suspend Burst current X X X H H H H L L-H Q Read Cycle, Suspend Burst current X X X H H H H H L-H High-Z Read Cycle, Suspend Burst current H X X X H H H L L-H Q Read Cycle, Suspend Burst current H X X X H H H H L-H High-Z Write Cycle, Suspend Burst current X X X H H H L X L-H D Write Cycle, Suspend BurstcurrentHXXXHHLXL-HDGS841E18AT/B-180/166/150/130/100Notes:1.X means “don’t care,” H means “logic high,” L means “logic low.”2.Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.3.CE is defined as CE1=L, CE2=H and CE3=L4.All signals are synchronous and are sampled by CLK except OE and MOE. OE and MOE are asynchronous and drive the bus immediately.)Note:Permanent damage to the device may occur if the Absolute Maximun Ratings are exceeded. Functional operation should be restricted to the recommended operation conditions. Exposure to higher than recommended voltages, for an extended period of time, could effect the performance and reliability of this component.Truth Table For Read/Write/Compare/Fill Write OperationCEWriteDEMOEOEMatchDQRead L H X X L —Q Write L L L X H —D Compare L H L L H Data Out D Fill Write L L H X X —X Match Deselect H X X L X High High Z DeselectHXXHXHigh ZHigh ZAbsolute Maximum Ratings (Voltage reference to V SS = 0 V)SymbolDescriptionCommericalUnitV DD Supply Voltage –0.5 to 4.6V V DDQ Output Supply Voltage –0.5 to V DD V V CLK CLK Input Voltage –0.5 to 6V V in Input Voltage –0.5 to V DD + 0.5 (≤ 4.6 V max. )V V out Output Voltage –0.5 to V DD + 0.5 (≤ 4.6 V max. )V I out Output Current per I/O +/–20mA P D Power Dissipation 1.5WT OPR Operating Temperature 0 to 70o C T STGStorage Temperature–55 to 125oCGS841E18AT/B-180/166/150/130/100Notes:1.Junction temperature is a function of SRAM power dissapation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance.2.SCMI G-38-87.3.Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.Package Thermal CharacteristicsRatingLayer BoardSymbolTQFP maxPBGA maxUnitNotesJunction to Ambient (at 200 lfm)single R ΘJA 3228°C/W 1,2Junction to Ambient (at 200 lfm)four R ΘJA 2018°C/W 1,2Junction to Case (TOP)—R ΘJC74°C/W3Notes: 1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.3.Output load 2 for t LZ , t HZ , t OLZ and t OHZ .4.Device is deselected as defined by the Truth Table.AC Test Conditions(VDD = 3.135 V–3.6 V, Ta = 0–70°C)ParameterConditionsInput high level V IH = 2.3 V Input low level V IL = 0.2 V Input slew rate TR = 1 V/ns Input reference level 1.25 V Output reference level1.25 V Output loadFig. 1& 2DQVT = 1.25 V50W 30pF 1DQ2.5 V F IG . 1Output load 1Output load 2F IG . 2225W 225W5pF 1GS841E18AT/B-180/166/150/130/100DC Characteristics and Supply Currents(Voltage reference to V SS = 0 V)(VDD = 3.135 V–3.6 V, Ta = 0–70°C for Commercial Temperature Offering)Parameter Symbol Test Conditions Min MaxInput Leakage Current(except ZZ, FT, LBO pins)I IL V IN = 0 to V DD–1 uA 1 uAZZ Input Current Iin ZZ V DD ≥V IN ≥V IH0 V≤ V IN ≤ V IH–1 uA–1 uA1 uA300 uAMode Input Current (FT & LBO pins)Iin MV DD ≥V IN ≥V IL0 V≤ V IN ≤ V IL–30 0uA–1 uA1 uA1 uAOutput Leakage Current I ol Output Disable,V OUT = 0 to V DD–1 uA 1 uAOutput High Voltage V OH I OH = –4 mA, V DDQ = 2.375 V 1.7 VOutput High Voltage V OH I OH = –4 mA, V DDQ = 3.135 V 2.4 VOutput Low Voltage V OL I OL = +4 mA0.4 VGS841E18AT/B-180/166/150/130/100Operating CurrentsParameter Test Conditions Symbol-180-166-150-133-100Unit 0to70°C–40to85°Cto70°C–40to+85°Cto70°C–40to+85°Cto70°C–40to+85°Cto70°C–40to+85°CO perating Current Device Selected;All other inputs≥ V IH O r ≤ V ILOutput openI DDPipeline335345310320275285250260190200mAI DDFlowThrough210220190200190200140150140150mAStandby Current ZZ≥ V DD – 0.2 VI SBPipeline20303040304030403040mAI SBFlowThrough20303040304030403040mADeselect Supply Current Device Deselected;All other inputs≥ V IH OR≤ V ILI DDPipeline55651101201051151001108090mAI DDFlowThrough40508090809065756575mAGS841E18AT/B-180/166/150/130/100Notes:1.These parameters are sampled and are not 100% tested2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.AC Electrical CharacteristicsParameterSymbol-180-166-150-133-100UnitMinMaxMinMaxMinMaxMinMaxMinMaxPipelineClock Cycle Time tKC 5.5— 6.0— 6.7—7.5—10—ns Clock to Output Valid tKQ — 3.2— 3.5— 3.8—4— 4.5ns Clock to Output InvalidtKQX 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-Z tLZ 1 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Match Valid tKM — 3.2— 3.5— 3.8—4— 4.5ns Clock to Match Invalid tKMX 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Match in Low-Z tMLZ 1 1.5— 1.5— 1.5— 1.5— 1.5—ns Flow ThroughClock Cycle Time tKC 9.1—10.0—10.0—15.0—15.0—ns Clock to Output Valid tKQ —8.0—8.5—10.0—11.0—12.0ns Clock to Output InvalidtKQX 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-Z tLZ 1 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Match Valid tKM —8.5—8.5—10.0—11.0—12.0ns Clock to Match Invalid tKMX 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Match in Low-Z tMLZ 1 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock HIGH Time tKH 1.3— 1.3— 1.5— 1.7—2—ns Clock LOW Time tKL 1.5— 1.5— 1.7—1.9—2.2—ns Clock to Output in High-Z tHZ 1 1.53.2 1.5 3.5 1.5 3.8 1.54 1.55ns OE to Output Valid tOE — 3.2— 3.5— 3.8—4—5ns OE to output in Low-Z tOLZ 10—0—0—0—0—ns OE to output in High-Z tOHZ 1— 3.2— 3.5— 3.8—4—5ns MOE to Match Valid tMOE — 3.2— 3.5— 3.8—4—5ns MOE to Match in Low-Z tMOLZ 10—0—0—0—0—ns MOE to Match in High-ZtMOHZ 1— 3.2— 3.5— 3.8—4—5ns Setup time tS 1.5— 1.5— 1.5— 2.0— 2.0—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—ns ZZ setup time tZZS 25—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—nsGS841E18AT/B-180/166/150/130/100Pipeline Mode TimingBegin Read A Cont Deselect Deselect Write BRead C Read C+1Read C+2Read C+3Cont Deselect DeselecttHZtKQXtKQtLZtHtStOHZtOEtHtStHtStHtStH tStHtStStHtStHtStHtStKCtKL tKHQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCHi-ZDeselected with E1E2 and E3 only sampled with ADSCADSC initiated readCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdGS841E18AT/B-180/166/150/130/100Flow Through Mode TimingBegin Read A ContDeselect Write B Read C Read C+1Read C+2Read C+3Read C DeselecttHZtKQX tLZtH tStOHZtOE tKQtHtS tHtS tHtStH tStHtS tHtStHtS tHtS tH tStH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSP and ADSCE1 masks ADSPADSC initiated readDeselected with E1E1 masks ADSPFixed HighCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdGS841E18AT/B-180/166/150/130/100Pipeline Compare Fill Write CycleHit Miss Fill WriteA BBA A tKMtKMtKMXtKM tMOE tMLZtH tStH tStH tStH tStH tSKAddressDQCEW GDE MOEMatchGS841E18AT/B-180/166/150/130/100Flow Through Compare Fill Write CycleHit Miss Fill WriteA BBA A tKMtKM tKMXtKM tMOE tMLZtH tStH tStH tStH tStH tSKAddressDQCEW GDE MOEMatchGS841E18AT/B-180/166/150/130/100TQFP Package Drawing (Package T)D1D E1EPin 1be cLL1A2A1YθNotes:1.All dimensions are in millimeters (mm).2.Package width and length do not include mold protrusion.SymbolDescriptionMin.Nom.MaxA1Standoff 0.050.100.15A2Body Thickness 1.35 1.40 1.45b Lead Width 0.200.300.40c Lead Thickness 0.09—0.20D Terminal Dimension 21.922.022.1D1Package Body 19.920.020.1E Terminal Dimension 15.916.016.1E1Package Body 13.914.014.1e Lead Pitch —0.65—L Foot Length 0.450.600.75L1Lead Length —1.00—Y Coplanarity 0.10θLead Angle0°—7°GS841E18AT/B-180/166/150/130/100Package Dimensions—119-Bump FPBGA (Package B, Variation 2)A B C D E F G H J K L M N P R T U1 2 3 4 5 6 77 6 5 4 3 2 1A1 TOP VIEWA1 BOTTOM VIEW 1.277.621.2720.3214±0.1022±0.10BA 0.20(4x)Ø0.10Ø0.30CC A B S S Ø0.60~0.90 (119x)CSEATING PLANE0.15C0.50~0.701.86.±0.130.70±0.050.15CA B C D E F G H J K L M N P R T U0.56±0.05S SGS841E18AT/B-180/166/150/130/100 Ordering InformationOrg Part Number1Type Package Speed 2(MHz/ns)T A3Status256K x 18GS841E18AT-180DCD Pipeline/Flow Through TQFP180/8C256K x 18GS841E18AT-166DCD Pipeline/Flow Through TQFP166/8.5C256K x 18GS841E18AT-150DCD Pipeline/Flow Through TQFP150/10C256K x 18GS841E18AT-133DCD Pipeline/Flow Through TQFP133/11C256K x 18GS841E18AT-100DCD Pipeline/Flow Through TQFP100/12C256K x 18GS841E18AT-180I DCD Pipeline/Flow Through TQFP180/8I256K x 18GS841E18AT-166I DCD Pipeline/Flow Through TQFP166/8.5I256K x 18GS841E18AT-150I DCD Pipeline/Flow Through TQFP150/10I256K x 18GS841E18AT-133I DCD Pipeline/Flow Through TQFP133/11I256K x 18GS841E18AT-100I DCD Pipeline/Flow Through TQFP100/12I256K x 18GS841E18AGT-180DCD Pipeline/Flow Through Pb-Free TQFP180/8C256K x 18GS841E18AGT-166DCD Pipeline/Flow Through Pb-Free TQFP166/8.5C256K x 18GS841E18AGT-150DCD Pipeline/Flow Through Pb-Free TQFP150/10C256K x 18GS841E18AGT-133DCD Pipeline/Flow Through Pb-Free TQFP133/11C256K x 18GS841E18AGT-100DCD Pipeline/Flow Through Pb-Free TQFP100/12C256K x 18GS841E18AGT-180I DCD Pipeline/Flow Through Pb-Free TQFP180/8I256K x 18GS841E18AGT-166I DCD Pipeline/Flow Through Pb-Free TQFP166/8.5I256K x 18GS841E18AGT-150I DCD Pipeline/Flow Through Pb-Free TQFP150/10I256K x 18GS841E18AGT-133I DCD Pipeline/Flow Through Pb-Free TQFP133/11I256K x 18GS841E18AGT-100I DCD Pipeline/Flow Through Pb-Free TQFP100/12I256K x 18GS841E18AB-180DCD Pipeline/Flow Through119 BGA (var. 2)180/8C256K x 18GS841E18AB-166DCD Pipeline/Flow Through119 BGA (var. 2)166/8.5C256K x 18GS841E18AB-150DCD Pipeline/Flow Through119 BGA (var. 2)150/10C256K x 18GS841E18AB-133DCD Pipeline/Flow Through119 BGA (var. 2)133/11C256K x 18GS841E18AB-100DCD Pipeline/Flow Through119 BGA (var. 2)100/12C256K x 18GS841E18AB-180I DCD Pipeline/Flow Through119 BGA (var. 2)180/8I256K x 18GS841E18AB-166I DCD Pipeline/Flow Through119 BGA (var. 2)166/8.5I256K x 18GS841E18AB-150I DCD Pipeline/Flow Through119 BGA (var. 2)150/10I256K x 18GS841E18AI-133I DCD Pipeline/Flow Through119 BGA (var. 2)133/11I256K x 18GS841E18AB-100I DCD Pipeline/Flow Through119 BGA (var. 2)100/12INotes:1.Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS841E18AT-166T.2.The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Eachdevice is Pipeline / Flow through mode selectable by the user.3.T A = C = Commercial Temperature Range. T A = I = Industrial Temperature Range.4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of whichare covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.GS841E18AT/B-180/166/150/130/100Specifications cited are subject to change without notice. For latest documentation see .Rev: 1.03 4/200521/21© 2001, GSI Technology 4Mb Synchronous Tag RAM Datasheet Revision History Rev. Code: Old;NewTypes of Changes Format or Content Page /Revisions;Reason GS841E18A_r1• Creation of new datasheet GS841E18A_r1;GS841E18A_r1_01Content • Moved TCK from U6 (incorrect placement) to U4 (correct placement) on BGA• Changed U6 to NCGS841E18A_r1_01; GS841E18A_r1_02Format/Content • Updated format• Added 180 MHz speed bin• Updated timing diagrams• Updated mechanical drawings• Added Pb-Free info for TQFPGS841E18A_r1_02;GS841E18A_r1_03Content• Added Pipeline Compare Fill Write Cycle and Flow ThroughCompare Fill Write Cycle timing diagrams 元器件交易网。

GS8662R08E-300I资料

GS8662R08/09/18/36E-333/300/250/200/16772Mb SigmaCIO DDR-II Burst of 4 SRAM333 MHz–167 MHz1.8 V V DD1.8 V and 1.5 V I/O165-Bump BGA Commercial Temp Industrial Temp Features• Simultaneous Read and Write SigmaCIO™ Interface • Common I/O bus• JEDEC-standard pinout and package • Double Data Rate interface• Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 4 Read and Write• 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface• Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines• ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan• Pin-compatible with present 9Mb, 18Mb, 36Mb and future 144Mb devices• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package availableSigmaCIO ™ Family OverviewThe GS8662R08/09/18/36E are built in compliance with the SigmaCIO DDR-II SRAM pinout standard for Common I/O synchronous SRAMs. They are 75,497,472-bit (72Mb)SRAMs. The GS8662R08/09/18/36E SigmaCIO SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed toimplement economical high performance networking systems.Clocking and Addressing SchemesThe GS8662R08/09/18/36E SigmaCIO DDR-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate theoutput register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-endedclock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead.Common I/O x36 and x18 SigmaCIO DDR-II B4 RAMs always transfer data in four packets. When a new address is loaded, A0 and A1 preset an internal 2 bit linear addresscounter. The counter increments by 1 for each beat of a burst of four data transfer. The counter always wraps to 00 after reaching 11, no matter where it starts.Common I/O x8 SigmaCIO DDR-II B4 RAMs always transfer data in four packets. When a new address is loaded, the LSBs are internally set to 0 for the first read or write transfer, and incremented by 1 for the next 3 transfers. Because the LSBs are tied off internally, the address field of a x8 SigmaCIO DDR-II B4 RAM is always two address pins less than the advertised index depth (e.g., the 4M x 18 has a 1024K addressable index).Parameter Synopsis-333-300-250-200-167tKHKH 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns tKHQV0.45 ns0.45 ns0.45 ns0.45 ns0.5 ns165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump ArrayBottom View2M x 36 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ MCL/SA (144Mb)SA R/W BW2K BW1LD SA SA CQ B NC DQ27DQ18SA BW3K BW0SA NC NC DQ8C NC NC DQ28V SS SA SA0SA1V SS NC DQ17DQ7D NC DQ29DQ19V SS V SS V SS V SS V SS NC NC DQ16E NC NC DQ20 V DDQ V SS V SS V SS V DDQ NC DQ15DQ6F NC DQ30DQ21 V DDQ V DD V SS V DD V DDQ NC NC DQ5G NC DQ31DQ22 V DDQ V DD V SS V DD V DDQ NC NC DQ14H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC DQ32 V DDQ V DD V SS V DD V DDQ NC DQ13DQ4K NC NC DQ23V DDQ V DD V SS V DD V DDQ NC DQ12DQ3L NC DQ33DQ24 V DDQ V SS V SS V SS V DDQ NC NC DQ2M NC NC DQ34 V SS V SS V SS V SS V SS NC DQ11DQ1N NC DQ35DQ25 V SS SA SA SA V SS NC NC DQ10P NC NC DQ26SA SA C SA SA NC DQ9DQ0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes toDQ27:DQ352.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/1674M x 18 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ SA SA R/W BW1K NC LD SA SA CQ B NC DQ9NC SA NC K BW0SA NC NC DQ8C NC NC NC V SS SA SA0SA1V SS NC DQ7NC D NC NC DQ10V SS V SS V SS V SS V SS NC NC NC E NC NC DQ11 V DDQ V SS V SS V SS V DDQ NC NC DQ6F NC DQ12NC V DDQ V DD V SS V DD V DDQ NC NC DQ5G NC NC DQ13 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC DQ4NC K NC NC DQ14V DDQ V DD V SS V DD V DDQ NC NC DQ3L NC DQ15NC V DDQ V SS V SS V SS V DDQ NC NC DQ2M NC NC NC V SS V SS V SS V SS V SS NC DQ1NC N NC NC DQ16 V SS SA SA SA V SS NC NC NC P NC NC DQ17SA SA C SA SA NC NC DQ0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ172.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/1678M x 9 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ SA SA R/W NC K NC LD SA SA CQ B NC NC NC SA NC K BW SA NC NC DQ4C NC NC NC V SS SA NC SA V SS NC NC NC D NC NC NC V SS V SS V SS V SS V SS NC NC NC E NC NC DQ5 V DDQ V SS V SS V SS V DDQ NC NC DQ3F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC NC DQ6 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC DQ2NC K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC DQ7NC V DDQ V SS V SS V SS V DDQ NC NC DQ1M NC NC NC V SS V SS V SS V SS V SS NC NC NC N NC NC NC V SS SA SA SA V SS NC NC NC P NC NC DQ8SA SA C SA SA NC NC DQ0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to0 at the beginning of each access.2.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/1678M x 8 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ SA SA R/W NW1K NC LD SA SA CQ B NC NC NC SA NC K NW0SA NC NC DQ3C NC NC NC V SS SA NC SA V SS NC NC NC D NC NC NC V SS V SS V SS V SS V SS NC NC NC E NC NC DQ4 V DDQ V SS V SS V SS V DDQ NC NC DQ2F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC NC DQ5 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC DQ1NC K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC DQ6NC V DDQ V SS V SS V SS V DDQ NC NC DQ0M NC NC NC V SS V SS V SS V SS V SS NC NC NC N NC NC NC V SS SA SA SA V SS NC NC NC P NC NC DQ7SA SA C SA SA NC NC NC RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to0 at the beginning of each access.2.NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ73.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/167Pin Description TableSymbolDescriptionTypeCommentsSA Synchronous Address InputsInput —NC No Connect ——R Synchronous Read Input Active High W Synchronous Write Input Active Low BW0–BW3Synchronous Byte Writes Input Active Low x18/x36 only NW0–NW1Nybble Write Control Pin Input Active Low x8 only LD Synchronous Load PinInput Active Low K Input Clock Input Active High K Input Clock Input Active Low C Output Clock Input Active High C Output Clock Input Active LowTMS Test Mode Select Input —TDI Test Data Input Input —TCK Test Clock Input Input —TDO Test Data Output Output —V REF HSTL Input Reference Voltage Input —ZQ Output Impedance Matching InputInput —MCL Must Connect Low——DQ Data I/O Input/Output Three State Doff Disable DLL when low Input Active LowCQ Output Echo Clock Output —CQ Output Echo Clock Output —V DD Power Supply Supply 1.8 V Nominal V DDQ Isolated Output Buffer Supply Supply 1.5 V NominalV SSPower Supply: GroundSupply—GS8662R08/09/18/36E-333/300/250/200/167Note:NC = Not Connected to die or any other pinGS8662R08/09/18/36E-333/300/250/200/167BackgroundCommon I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications. Therefore, the SigmaCIO DDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed Common I/O SRAM data bandwidth in half.Burst OperationsRead and write operations are “burst” operations. In every case where a read or write command is accepted by the SRAM, it will respond by issuing or accepting four beats of data, executing a data transfer on subsequent rising edges of K and K#, as illustrated in the timing diagrams. It is not possible to stop a burst once it starts. Four beats of data are always transferred. This means that it is possible to load new addresses every other K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are inserted.Deselect CyclesChip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the four beat read data transfer and then execute the deselect command, returning the output drivers to high-Z.A high on the LD# pin prevents the RAM from loading read or write commandinputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer operations.SigmaCIO DDR-II B4 SRAM Read CyclesThe status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst transfer inresponse to a read command, if the previous command captured was a read or write command, the Address, LD# and R/W# pins are ignored. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes pipelined reads. The read command is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM produces data out in response to the next rising edge of C# (or the next rising edge of K#, if C and C# are tied high). The second beat of data is transferred on the next rising edge of C, then on the next rising edge of C# and finally on the next rising edge of C, for a total of four transfers per address load.SigmaCIO DDR-II B4 SRAM Write CyclesThe status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst transfer in response to a write command, if the previous command captured was a read or write command, the Address, LD# and R/ W# pins are ignored at the next rising edge of K. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes “late write” data transfers. Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command and the write address. To complete the remaining three beats of the burst of four write transfer the SRAM captures data in on the next rising edge of K#, the following rising edge of K and finally on the next rising edge of K#, for a total of four transfers per address load.GS8662R08/09/18/36E-333/300/250/200/167Power-Up Sequence for SigmaQuad-II SRAMsSigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.Power-Up Sequence1. Power-up and maintain Doff at low state.1a.Apply V DD .1b. Apply V DDQ .1c. Apply V REF (may also be applied at the same time as V DDQ ).2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.Note:If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become stablized.DLL Constraints•The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t KCVar on page 20).•The DLL cannot operate at a frequency lower than 119 MHz.•If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage.Power-Up Sequence (Doff controlled)Power UP IntervalUnstable Clocking IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoffPower-Up Sequence (Doff tied High)Power UP IntervalUnstable Clocking IntervalStop Clock IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoff30ns MinNote:If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.GS8662R08/09/18/36E-333/300/250/200/167Special FunctionsByte Write and Nybble Write ControlByte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence.Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18 version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence.Nybble Write (4-bit) write control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NBx” may be substituted in all the discussion above.Example x18 RAM Write Sequence using Byte Write EnablesData In SampleTimeBW0BW1D0–D8D9–D17Beat 101Data In Don’t CareBeat 210Don’t Care Data InBeat 300Data In Data InBeat 410Don’t Care Data InResulting Write OperationByte 1 D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Written Unchanged Unchanged Written Written Written Unchanged Written Beat 1Beat 2Beat 3Beat 4Output Register ControlSigmaCIO DDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs isare tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM.A K R/W LDA 0–A nKBank 0Bank 1Bank 2Bank 3A KLD A K LD A K LD R/W R/W R/W DQDQDQ DQCC CCDQ 1–C R/WLD 0LD 1LD 2LD 3Note:For simplicity BWn (or NWn), K, and C are not shown.CQ CQ CQ CQ CQGS8662R08/09/18/36E-333/300/250/200/167Example Four Bank Depth Expansion SchematicGS8662R08/09/18/36E-333/300/250/200/167FLXDrive-II Output Driver Impedance ControlHSTL I/O SigmaCIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver isimplemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.Common I/O SigmaCIO DDR-II B4 SRAM Truth TableK nLDR/WDQOperationA + 0A + 1A + 2A + 3↑1X Hi-Z Hi-Z Hi-Z Hi-Z Deselect ↑00D@K n+1D@K n+1D@K n+2D@K n+2Write ↑1Q@K n+1or C n+1Q@K n+2or C n+2Q@K n+2or C n+2Q@K n+3or C n+3ReadNote:Q is controlled by K clocks if C clocks are not used.B4 Byte Write Clock Truth TableBW BW BW BW Current OperationD D D D K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)K ↑(t n )K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)TTTTWriteDx stored if BWn = 0 in all four data transfers D0D2D3D4T F F F WriteDx stored if BWn = 0 in 1st data transfer only D0X X XF T F F WriteDx stored if BWn = 0 in 2nd data transfer only X D1X XF F T F WriteDx stored if BWn = 0 in 3rd data transfer only X X D2XF F F T WriteDx stored if BWn = 0 in 4th data transfer only X X X D3F F F F Write AbortNo Dx stored in any of the four data transfersX X X XNotes:1.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.2.If one or more BWn = 0, then BW = “T”, else BW = “F”.GS8662R08/09/18/36E-333/300/250/200/167*Assuming stable conditions, the RAM can achieve optimum impedance within 1024 cycles.B4 Nybble Write Clock Truth TableNW NW NW NW Current OperationD D D D K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)K ↑(t n )K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)TTTTWriteDx stored if NWn = 0 in all four data transfers D0D2D3D4T F F F WriteDx stored if NWn = 0 in 1st data transfer only D0X X XF T F F WriteDx stored if NWn = 0 in 2nd data transfer only X D1X XF F T F WriteDx stored if NWn = 0 in 3rd data transfer only X X D2XF F F T WriteDx stored if NWn = 0 in 4th data transfer only X X X D3F F F F Write AbortNo Dx stored in any of the four data transfersX X X XNotes:1.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.2.If one or more NWn = 0, then NW = “T”, else NW = “F”.GS8662R08/09/18/36E-333/300/250/200/167x36 Byte Write Enable (BWn) Truth TableBW0BW1BW2BW3D0–D8D9–D17D18–D26D27–D351111Don’t Care Don’t Care Don’t Care Don’t Care 0111Data In Don’t Care Don’t Care Don’t Care 1011Don’t Care Data In Don’t Care Don’t Care 0011Data In Data In Don’t Care Don’t Care 1101Don’t Care Don’t Care Data In Don’t Care 0101Data In Don’t Care Data In Don’t Care 1001Don’t Care Data In Data In Don’t Care 0001Data In Data In Data In Don’t Care 1110Don’t Care Don’t Care Don’t Care Data In 0110Data In Don’t Care Don’t Care Data In 1010Don’t Care Data In Don’t Care Data In 0010Data In Data In Don’t Care Data In 1100Don’t Care Don’t Care Data In Data In 0100Data In Don’t Care Data In Data In 1000Don’t Care Data In Data In Data In 0Data InData InData InData Inx18 Byte Write Enable (BWn) Truth Table BW0BW1D0–D8D9–D1711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData Inx8 Nybble Write Enable (NWn) Truth Table NW0NW1D0–D3D4–D711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData InGS8662R08/09/18/36E-333/300/250/200/167GS8662R08/09/18/36E-333/300/250/200/167B4 State DiagramPower-UpNOPLoad New AddressDDR Read DDR WriteLOADREAD WRITE LOADLOADLOADLOADNotes:1.The internal burst address counter is a 4-bit linear counter (i.e., when first address is A0, next internal burst address is A0+1).2.“READ” refers to read active status with R/W = High, “WRITE” refers to write inactive status with R/W = Low.3.“LOAD” refers to read new address active status with LD = Low, “LOAD” refers to read new address inactive status with LD = High.LOAD Increment Read Address Increment Write AddressAlwaysAlwaysREADWRITEAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 2.9V V DDQ Voltage in V DDQ Pins –0.5 to V DD V V REF Voltage in V REF Pins –0.5 to V DDQV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V V IN Voltage on Other Input Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V I IN Input Current on Any Pin +/–100mA dc I OUT Output Current on Any I/O Pin +/–100mA dcT J Maximum Junction Temperature125o C T STGStorage Temperature–55 to 125oCNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.GS8662R08/09/18/36E-333/300/250/200/167Recommended Operating ConditionsPower SuppliesParameterSymbolMin.Typ.Max.UnitSupply Voltage V DD 1.7 1.8 1.9V I/O Supply Voltage V DDQ 1.7 1.8 1.9V Reference VoltageV REF0.68—0.95VNotes:1.Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ V DDQ ≤ 1.6 V (i.e., 1.5 V I/O)and 1.7 V ≤ V DDQ ≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.2.The power supplies need to be powered up simultaneously or in the following sequence: V DD , V DDQ , V REF , followed by signal inputs. Thepower down sequence must be the reverse. V DDQ must not exceed V DD ..Operating TemperatureParameterSymbolMin.Typ.Max.UnitAmbient Temperature (Commercial Range Versions)T A 02570°C Ambient Temperature (Industrial Range Versions)T A–402585°CGS8662R08/09/18/36E-333/300/250/200/167HSTL I/O DC Input CharacteristicsParameterSymbolMinMaxUnitsNotesDC Input Logic High V IH (dc)V REF + 0.10V DD + 0.3 V V 1DC Input Logic LowV IL (dc)–0.3 VV REF – 0.10V1Notes:patible with both 1.8 V and 1.5 V I/O drivers2.These are DC test criteria. DC design criteria is V REF ± 50 mV. The AC V IH /V IL levels are defined separately for measuring timing parame-ters.3.V IL (Min) DC = –0.3 V, V IL (Min) AC = –1.5 V (pulse width ≤ 3 ns).4.V IH (Max) DC = V DDQ + 0.3 V, V IH (Max) AC = V DDQ + 0.85 V (pulse width ≤ 3 ns).HSTL I/O AC Input CharacteristicsParameterSymbolMinMaxUnitsNotesAC Input Logic High V IH (ac)V REF + 0.20—V 3,4AC Input Logic LowV IL (ac)—V REF – 0.20V 3,4V REF Peak to Peak AC VoltageV REF (ac)—5% V REF (DC)V1Notes:1.The peak to peak AC component superimposed on V REF may not exceed 5% of the DC component of V REF .2.To guarantee AC characteristics, V IH ,V IL , Trise, and Tfall of inputs and clocks must be within 10% of each other.3.For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.20% tKHKHV SS – 1.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKHKHV DD + 1.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DDParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Output Capacitance C OUT V OUT = 0 V67pF Clock CapacitanceC CLK—56pFNote:This parameter is sample tested.GS8662R08/09/18/36E-333/300/250/200/167AC Test ConditionsParameterConditionsInput high level V DDQ Input low level 0 V Max. input slew rate 2 V/ns Input reference level V DDQ /2Output reference levelV DDQ /2Note:Test conditions as specified with output loading as shown unless otherwise noted.DQVT = V DDQ /250ΩRQ = 250 Ω (HSTL I/O)V REF = 0.75 VAC Test Load DiagramInput and Output Leakage CharacteristicsParameterSymbolTest ConditionsMin.MaxNotesInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –2 uA 2 uA DoffI INDOFF V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL –100 uA –2 uA 2 uA 2 uA Output Leakage CurrentI OLOutput Disable,V OUT = 0 to V DDQ–2 uA2 uA(T A = 25= 3.3 V)GS8662R08/09/18/36E-333/300/250/200/167Programmable Impedance HSTL Output Driver DC Electrical CharacteristicsParameterSymbolMin.Max.UnitsNotesOutput High Voltage V OH1 V DDQ /2V DDQ V 1, 3Output Low Voltage V OL1 Vss V DDQ /2V 2, 3Output High Voltage V OH2 V DDQ – 0.2V DDQ V 4, 5Output Low VoltageV OL2Vss0.2V4, 6Notes:1. I OH = (V DDQ /2) / (RQ/5) +/– 15% @ V OH = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).2. I OL = (V DDQ /2) / (RQ/5) +/– 15% @ V OL = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).3.Parameter tested with RQ = 250Ω and V DDQ = 1.5 V or 1.8 V4.Minimum Impedance mode, ZQ = V SS5.I OH = –1.0 mA6.I OL = 1.0 mAOperating CurrentsParameterSymbolTest Conditions-333-300-250-200-167Notes0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C Operating Current (x36):DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBDTBDTBDTBDTBDTBDTBDTBDTBDTBD2, 3Operating Current (x18):DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x9):DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x8):DDR I DDV DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Standby Current (NOP):DDRI SB1Device deselected,I OUT = 0 mA, f = Max,All Inputs ≤ 0.2 V or ≥ V DD – 0.2 VTBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 4Notes:1.Power measured with output pins floating.2.Minimum cycle, I OUT = 0 mA3.Operating current is calculated with 50% read cycles and 50% write cycles.4.Standby Current is only after all pending read and write burst operations are completed.GS8662R08/09/18/36E-333/300/250/200/167AC Electrical CharacteristicsParameterSymbol-333-300-250-200-167UnitsN o t e sMin Max Min Max Min Max Min Max Min MaxClockK, K Clock Cycle Time C, C Clock Cycle Time t KHKH t CHCH 3.0 3.5 3.3 4.2 4.0 6.3 5.07.88 6.08.4ns tTKC Variablet KCVar —0.2—0.2—0.2—0.2—0.2ns 5K, K Clock High Pulse Width C, C Clock High Pulse Width t KHKL t CHCL 1.2— 1.32— 1.6— 2.0— 2.4—ns K, K Clock Low Pulse Width C, C Clock Low Pulse Width t KLKH t CLCH 1.2— 1.32— 1.6— 2.0— 2.4—ns K to K High C to C Hight KHKH 1.35— 1.49— 1.8— 2.2— 2.7—ns K, K Clock High to C, C Clock High t KHCH 0 1.30 1.450 1.80 2.30 2.8ns DLL Lock Time t KCLock 1024—1024—1024—1024—1024—cycle 6K Static to DLL resett KCReset 30—30—30—30—30—nsOutput TimesK, K Clock High to Data Output Valid C, C Clock High to Data Output Valid t KHQV t CHQV —0.45—0.45—0.45—0.45—0.5ns 3K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold t KHQX t CHQX –0.45—–0.45—–0.45—–0.45—–0.5—ns 3K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid t KHCQV t CHCQV —0.45—0.45—0.45—0.45—0.5ns K, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold t KHCQX t CHCQX –0.45—–0.45—–0.45—–0.45—–0.5—ns CQ, CQ High Output Valid t CQHQV —0.25—0.27—0.30—0.35—0.40ns 7CQ, CQ High Output Hold t CQHQX –0.25—–0.27—–0.30—–0.35—–0.40—ns 7K Clock High to Data Output High-Z C Clock High to Data Output High-Z t KHQZ t CHQZ —0.45—0.45—0.45—0.45—0.5ns 3K Clock High to Data Output Low-Z C Clock High to Data Output Low-Zt KHQX1t CHQX1–0.45—–0.45—–0.45—–0.45—–0.5—ns3Setup TimesAddress Input Setup Time t AVKH 0.4—0.4—0.5—0.6—0.7—ns Control Input Setup Time t IVKH 0.4—0.4—0.5—0.6—0.7—ns 2Data Input Setup Timet DVKH0.28—0.3—0.35—0.4—0.5—ns。

利德威滤清器超级目录2019-OIL

3
O3
现代起亚:26320-3CAA0
4
O4
现代起亚:26320-3C300
5
O5
丰田:04152-31080、 04152-0P010、04152YZZA3
起亚霸锐(进口) 3.8L 产品类型：产品无塑料盖，发动机型号：内置环保纸芯 G6DA，时间：200701-至今现代劳恩斯(进口) 3.8L 发动机型号：G6DA，时间：200701201212 维拉克斯(进口) 3.8L 产品类型：产品长度105MM无塑料盖，发动机型号：G6DA，时间：200701-201312 丰田 4Runner(N280 2009-)(进口) 2.7L 发动机型号：2TR，时内置环保纸芯间：200903-至今 4.0L 发动机型号：1GR，时间：200903-至今 FJ 酷路泽(进口) 4.0L 发动机型号：1GR，滤清器材质：纸滤，时间：200601-至今皇冠(S180 2004-2010) 2.5L 发动机型号：5GR，时间： 200408-201012 3.0L 发动机型号：3GR，时间：200408-201012 皇冠(S200 2009-2014) 2.5L 发动机型号：5GR，时间： 200906-201412 3.0L 发动机型号：3GR，时间：200906-201412 皇冠(S210 2015-) 2.5L 发动机型号：5GR，时间：201502-至今柯斯达 4.0L 发动机型号：6GR，时间：201201-至今兰德酷路泽(陆地巡洋舰)(J200 2007-) 4.0L 发动机型号：1GR，时间：201202-至今兰德酷路泽(陆地巡洋舰)(J200 2007-)(进口) 4.0L 发动机型号： 1GR，滤清器材质：纸滤，时间：200706-至今普拉多(J150 2009-)(进口) 4.0L 发动机型号：1GR，时间： 200902-至今普拉多(J150 2010-) 4.0L 发动机型号：1GR，时间：201001201512 锐志(X120 2005-2010) 2.5L 发动机型号：5GR，时间： 200504-201012 3.0L 发动机型号：3GR，时间：200510-201012 锐志(X130 2010-2017) 2.5L 发动机型号：5GR，时间： 201003-201709 3.0L 发动机型号：3GR，时间：201003-201709 红旗盛世(HQ) 3.0L 发动机型号：3GR-FE，时间：200704201212 雷克萨斯 GS250 F SPORT(L10 2011-)(进口) 2.5L 发动机型号： 4GR，时间：201110-至今

GS881Z32BT-250V资料

GS881Z18/32/36B(T/D)-xxxV9Mb Pipelined and Flow ThroughSynchronous NBT SRAM250 MHz–150 MHz 1.8 V or 2.5 V V DD 1.8 V or 2.5 V I/O100-Pin TQFP & 165-Bump BGA Commercial Temp Industrial Temp Features• User-configurable Pipeline and Flow Through mode• NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization• Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs• IEEE 1149.1 JTAG-compatible Boundary Scan• On-chip write parity checking; even or odd selectable • 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply• LBO pin for Linear or Interleave Burst mode • Pin-compatible with 2M, 4M, and 18M devices • Byte write operation (9-bit Bytes)• 3 chip enable signals for easy depth expansion • ZZ pin for automatic power-down • JEDEC-standard packages• RoHS-compliant 100-lead TQFP and 165-bump BGA packages availableFunctional DescriptionThe GS881Z18/32/36B(T/D)-xxxV is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.The GS881Z18/32/36B(T/D)-xxxV may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.The GS881Z18/32/36B(T/D)-xxxV is implemented with GSI's high performance CMOS technology and is available inJEDEC-standard 100-pin TQFP and 165-bump BGA packages.Paramter Synopsis-250-200-150UnitPipeline 3-1-1-1KQ tCycle 4.0 5.0 6.7ns Curr (x18)Curr (x32/x36)200230170195140160mA mA Flow Through 2-1-1-1t KQ tCycle 5.55.5 6.56.57.57.5ns ns Curr (x18)Curr (x32/x36)160185140160128145mA mA807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B FT V DD NC V SS DQ B DQ B6V DD V SS DQ B DQ B DQP BV SS V DDQ V DDQ V SS DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0T M S T D I V S SV D DT D O T C K A A A A A A 1A A E 1E 2 N C N C B BB AE 3C K W C K E VD DV S SG A D V N C A A AA 512K x 18Top View DQP A A NC NC NC NC NC NC NC NCNC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881Z18/32/36B(T/D)-xxxVGS881Z18BT-xxxV 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C FT V DD NC V SS DQ D DQ D2V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0T M S T D I V S SV D DT D O T C K A A A A A AA A E 1E 2 B DB CB BB AE 3C K W C K E VD DV S SG A D V N C A A AA 256K x 32Top View DQB NC DQ B DQ B DQ B DQ A DQ A DQ A DQ A NCDQ C DQ C DQ C DQ D DQ D DQ D NCDQ C NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881Z18/32/36B(T/D)-xxxVGS881Z32BT-xxxV 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C FT V DD NC V SS DQ D DQ D2V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0T M S T D I V S SV D DT D O T C K A A A A A AA A E 1E 2 B DB CB BB AE 3C K W C K E VD DV S SG A D V N C A A AA 256K x 36Top View DQB DQP B DQ B DQ B DQ B DQ A DQ A DQ A DQ A DQP ADQ C DQ C DQ C DQ D DQ D DQ D DQP DDQ C DQP C 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881Z18/32/36B(T/D)-xxxVGS881Z36BT-xxxV 100-Pin TQFP Pinout (Package T)100-Pin TQFP Pin DescriptionsSymbolTypeDescriptionA 0, A 1In Burst Address Inputs; Preload the burst counterA In Address Inputs CK In Clock Input SignalB A In Byte Write signal for data inputs DQ A1–DQ A9; active low B B In Byte Write signal for data inputs DQ B1–DQ B9; active low BC In Byte Write signal for data inputs DQ C1–DQ C9; active low BD In Byte Write signal for data inputs DQ D1–DQ D9; active lowW In Write Enable; active low E 1In Chip Enable; active lowE 2In Chip Enable—Active High. For self decoded depth expansion E 3In Chip Enable—Active Low. For self decoded depth expansionG In Output Enable; active lowADV In Advance/Load; Burst address counter control pinCKE In Clock Input Buffer Enable; active lowNC —No ConnectDQ A I/O Byte A Data Input and Output pins DQ B I/O Byte B Data Input and Output pins DQ C I/O Byte C Data Input and Output pins DQ D I/O Byte D Data Input and Output pins ZZ In Power down control; active high FT In Pipeline/Flow Through Mode Control; active lowLBO InLinear Burst Order; active low.TMS Scan Test Mode Select TDI Scan Test Data In TDO Scan Test Data Out TCK Scan Test Clock V DD In Core power supplyV SS In GroundV DDQInOutput driver power supplyGS881Z18/32/36B(T/D)-xxxVGS881Z18/32/36B(T/D)-xxxV165 Bump BGA—x18 Commom I/O—Top View 1234567891011A NC A E1BB NC E3CKE ADV A17A A A B NC A E2NC BA CK W G NC A NC B C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQA C D NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA D E NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA E F NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA F G NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA G H FT MCH NC V DD V SS V SS V SS V DD NC NC ZZ H J DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC J K DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC K L DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC L M DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC M N DQB NC V DDQ V SS NC NC NC V SS V DDQ NC NC N P NC NC A A TDI A1TDO A A A NC P RLBONCAATMSA0TCKAAAAR11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch(Package D)GS881Z18/32/36B(T/D)-xxxV165 Bump BGA—x32 Common I/O—Top View 1234567891011A NC A E1BC BB E3CKE ADV A17A NC A B NC A E2BD BA CK W G NC A NC B C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC NC C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCH NC V DD V SS V SS V SS V DD NC NC ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N NC NC V DDQ V SS NC NC NC V SS V DDQ NC NC N P NC NC A A TDI A1TDO A A A NC P RLBONCAATMSA0TCKAAAAR11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch(Package D)GS881Z18/32/36B(T/D)-xxxV165 Bump BGA—x36 Common I/O—Top View 1234567891011A NC A E1BC BB E3CKE ADV A A NC A B NC A E2BD BA CK W G NC A NC B C DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCH NC V DD V SS V SS V SS V DD NC NC ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N DQPD NC V DDQ V SS NC NC NC V SS V DDQ NC DQPA N P NC NC A A TDI A1TDO A A A NC P RLBONCAATMSA0TCKAAAAR11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch(Package D)GS881Z18/32/36D-xxxV165-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsA I Address Inputs DQ A DQB DQC DQD I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active lowNC —No ConnectCK I Clock Input Signal; active high CKE I Clock Enable; active low W I Write Enable; active low E 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active highZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowTMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCH —Must Connect High DNU —Do Not Use V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS881Z18/32/36B(T/D)-xxxVK18S A 1S A 0Bu r s t C o u n t e rL B OA D VM e m o r y A r r a yGC KC K ED QF TN CN CD Q a –D Q nKS A 1’S A 0’D QM a t c hW r i t e A d d r e s sR e g i s t e r 2W r i t e A d d r e s sR e g i s t e r 1W r i t e D a t aR e g i s t e r 2W r i t e D a t aR e g i s t e r 1KKKKKKS e n s e A m p sW r i t e D r i v e r sR e a d , W r i t e a n dD a t a C o h e r e n c yC o n t r o l L o g i cD QKP a r i t y C h e c kF TA 0–A nE 3E 2E 1WB DB CB BB AGS881Z18/32/36B(T/D)-xxxVGS881Z18/32/36B(T/D)-xxxV NBT SRAM Functional Block DiagramGS881Z18/32/36B(T/D)-xxxVFunctional DetailsClockingDeassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.Pipeline Mode Read and Write OperationsAll inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E 1, E 2 and E 3). Deassertion of any one of the Enable inputs will deactivate the device. Function W B A B B B C B D Read H X X X X Write Byte “a”L L H H H Write Byte “b”L H L H H Write Byte “c”L H H L H Write Byte “d”L H H H L Write all Bytes L L L L L Write Abort/NOPLHHHHRead operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E 1, E 2, and E 3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (B A , B B , B C & B D ) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.Flow Through Mode Read and Write OperationsOperation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.Synchronous Truth TableOperationType Address CK CKE ADV W Bx E 1E 2E 3G ZZDQNotesRead Cycle, Begin Burst R External L-H L L H X L H L L L Q Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3Write Cycle, Continue Burst B Next L-H L H X L X X X X L D1,3,10Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z Deselect Cycle D None L-H L L L H L H L X L High-Z 1Deselect Cycle, Continue DNone L-H L H X X X X X X L High-Z 1Sleep ModeNone X X X X X X X X X H High-Z Clock Edge Ignore, StallCurrentL-HHXXXXXXXL-4Notes:1.Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-lect cycle is executed first.2.Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the Wpin is sampled low but no Byte Write pins are active so no write operation is performed.3.G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off duringwrite cycles.4.If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the buswill remain in High Z.5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Writesignals are Low6.All inputs, except G and ZZ must meet setup and hold times of rising clock edge.7.Wait states can be inserted by setting CKE high.8.This device contains circuitry that ensures all outputs are in High Z during power-up.9. A 2-bit burst counter is incorporated.10.The address counter is incriminated for all Burst continue cycles.GS881Z18/32/36B(T/D)-xxxVGS881Z18/32/36B(T/D)-xxxVDeselectNew ReadNew WriteBurst ReadBurst WriteWRBRBWDDBBWRD BWRDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input commandcodes as indicated in the Synchronous Truth Table.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipelined and Flow Through Read/Write Control State DiagramWRPipelined and Flow Through Read Write Control State DiagramGS881Z18/32/36B(T/D)-xxxVIntermediateIntermediateIntermediateIntermediateIntermediateIntermediateHigh Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)TransitionƒInput Command CodeKeyTransitionIntermediate State (N+1)Notes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateIntermediate ƒn n+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipeline Mode Data I/O State DiagramNext StateStatePipeline Mode Data I/O State DiagramGS881Z18/32/36B(T/D)-xxxVFlow Through Mode Data I/O State Diagram High Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for: Pipeline and Flow through Read Write Control State DiagramGS881Z18/32/36B(T/D)-xxxVBurst CyclesAlthough NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.Burst OrderThe burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have beenaccessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details.Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down ControlZZL or NC Active HStandby, I DD = I SBNote:There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table.Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS881Z18/32/36B(T/D)-xxxVSleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramtZZRtZZHtZZStKLtKHtKCCKZZDesigning for CompatibilityThe GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V DD or V DDQ on pipelined parts and V SS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.Pin 66, a No Connect (NC) on GSI’s GS8160Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36B NBT SRAM, is often marked as a power pin on other vendor’s NBT compatible SRAMs. Specifically, it is marked V DD or V DDQ on pipelined parts and V SS on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity feature may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline modeapplications or tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage on V DDQ Pins –0.5 to V DDV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCGS881Z18/32/36B(T/D)-xxxVNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges (1.8 V/2.5 V Version)ParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD1 1.7 1.82.0V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 1.8 V V DDQ I/O Supply Voltage V DDQ1 1.7 1.8V DD V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.5V DDVNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS881Z18/32/36B(T/D)-xxxVV DDQ2 & V DDQ1 Range Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low VoltageV IL–0.3—0.3*V DDV1Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceFigure 1Input high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS881Z18/32/36B(T/D)-xxxVDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA FT, ZZ Input Current I IN V DD ≥ V IN ≥ 0 V –100 uA 100 uA Output Leakage CurrentI OLOutput Disable, V OUT = 0 to V DD–1 uA1 uADC Output Characteristics (1.8 V/2.5 V Version)ParameterSymbolTest ConditionsMinMax1.8 V Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V —2.5 V Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V1.7 V —1.8 V Output Low Voltage V OL1I OL = 4 mA —0.4 V2.5 V Output Low VoltageV OL2I OL = 8 mA—0.4 VGS881Z18/32/36B(T/D)-xxxVOperating CurrentsParameterTest ConditionsModeSymbol-250-200-150Unit0to 70°C–40 to 85°C0to 70°C –40to 85°C 0 to 70°C –40to 85°COperating CurrentDevice Selected; All other inputs ≥V IH o r ≤ V IL Output open(x32/x36)PipelineI DD I DDQ 200302203017025190251402016020mA Flow Through I DD I DDQ 160251802514020160201301515015mA (x18)PipelineI DD I DDQ 185152051515515175151301015010mA Flow ThroughI DD I DDQ 1451516515130101501012081408mA Standby Current ZZ ≥ V DD – 0.2 V —Pipeline I SB 405040504050mA Flow Through I SB 405040504050mA Deselect CurrentDevice Deselected; All other inputs ≥ V IH or ≤ V IL—PipelineI DD 859075806065mA Flow Through I DD606550555055mA1.I DD and I DDQ apply to any combination of V DD1, V DD2, V DDQ1, and V DDQ2 operation.2.All parameters listed are worst case scenario.。

GS8321V18E-166资料

GS8321V18/32/36E-250/225/200/166/150/1332M x 18, 1M x 32, 1M x 3636Mb Sync Burst SRAMs250 MHz –133 MHz1.8 V V DD 1.8 V I/O165-Bump FP-BGA Commercial Temp Industrial Temp Features• IEEE 1149.1 JTAG-compatible Boundary Scan • 1.8 V +10%/–10% core power supply • 1.8 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications • JEDEC-standard 165-bump FP-BGA package • Pb-Free 165-bump BGA package availableFunctional DescriptionApplicationsThe GS8321V18/32/36E is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. ControlsAddresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may beconfigured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.SCD Pipelined ReadsThe GS8321V18/32/36E is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.Sleep ModeLow power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS8321V18/32/36E operates on a 1.8 V power supply. All input are 1.8 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 1.8 V compatible.Parameter Synopsis-250-225-200-166-150-133Unit Pipeline 3-1-1-1KQ tCycle 4.0 4.4 5.0 6.0 6.67.5ns Curr (x18)Curr (x32/x36)285350265320245295220260210240185215mA mA Flow Through 2-1-1-1t KQ tCycle 6.57.07.58.08.58.5ns Curr (x18)Curr (x32/x36)205235195225185210175200165190155175mA mAGS8321V18/32/36E-250/225/200/166/150/133165 Bump BGA—x18 Commom I/O—Top View (Package E)1234567891011A NC A E1BB NC E3BW ADSC ADV A A AB NC A E2NC BA CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPA CD NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA DE NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA EF NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA FG NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA GH FT MCL NC V DD V SS V SS V SS V DD NC NC ZZ HJ DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC JK DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC KL DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC LM DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC MN DQPB NC V DDQ V SS NC A NC V SS V DDQ NC NC NP NC NC A A TDI A1TDO A A A A PR LBO A19A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump PitchGS8321V18/32/36E-250/225/200/166/150/133165 Bump BGA—x32 Common I/O—Top View (Package E)1234567891011A NC A E1BC BB E3BW ADSC ADV A NC AB NC A E2BD BA CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC NC CD DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB DE DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB EF DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB FG DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB GH FT MCL NC V DD V SS V SS V SS V DD NC NC ZZ HJ DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA JK DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA KL DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA LM DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA MN NC NC V DDQ V SS NC A NC V SS V DDQ NC NC NP NC NC A A TDI A1TDO A A A A PR LBO A A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump PitchGS8321V18/32/36E-250/225/200/166/150/133165 Bump BGA—x36 Common I/O—Top View (Package E)1234567891011A NC A E1BC BB E3BW ADSC ADV A NC AB NC A E2BD BA CK GW G ADSP A NC BC DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB CD DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB DE DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB EF DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB FG DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB GH FT MCL NC V DD V SS V SS V SS V DD NC NC ZZ HJ DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA JK DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA KL DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA LM DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA MN DQPD NC V DDQ V SS NC A NC V SS V DDQ NC DQPA NP NC NC A A TDI A1TDO A A A A PR LBO A A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump PitchGS8321V18/32/36E 165-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsA I Address Inputs DQ A DQB DQC DQD I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active lowNC —No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active l0w ADSC, ADSPI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowTMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCL —Must Connect Low V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8321V18/32/36E-250/225/200/166/150/133GS8321V18/32/36E-250/225/200/166/150/133A1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterD QR e g i s t e rDQ RegisterA0–AnLBO ADV CK ADSC ADSP GW BW E 1FT GZZPower Down ControlMemory Array36364AQD DQx1–DQx9NCParity NCParity EncodeCompare3643636432Note: Only x36 version shown for simplicity.13636DQR e g i s t e r 4B AB BB CB DGS8321V18/32/36 Block DiagramMode Pin FunctionsMode NamePin NameStateFunctionBurst Order ControlLBO L Linear Burst H Interleaved Burst Output Register ControlFT L Flow Through H or NC Pipeline Power Down ControlZZL or NC Active HStandby, I DD = I SBGS8321V18/32/36E-250/225/200/166/150/133Note:There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.The burst counter wraps to initial state on the 5th clock.The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014thaddress11000110I nterleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1staddress 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS8321V18/32/36E-250/225/200/166/150/133Byte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytes H L L L L L 2, 3, 4Write all bytesLXXXXX1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.Synchronous Truth TableOperationAddress UsedState Diagram Key 5E 1ADSPADSCADVW 3DQ 4Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CWH X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend BurstCurrentHXHHTDNotes:1.X = Don’t Care, H = High, L = Low2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS8321V18/32/36E-250/225/200/166/150/133First WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, andassumes ADSP is tied high and ADV is tied low.GS8321V18/32/36E-250/225/200/166/150/133Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.3.Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS8321V18/32/36E-250/225/200/166/150/133Simplified State Diagram with GAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 3.6V V DDQ Voltage in V DDQ Pins –0.5 to 3.6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 3.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 3.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCGS8321V18/32/36E-250/225/200/166/150/133Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage RangesParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD 1.6 1.82.0V 1.8 V V DDQ I/O Supply VoltageV DDQ1.61.82.0VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS8321V18/32/36E-250/225/200/166/150/133Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.3*V DD V 1V DDQ I/O Input High Voltage V IHQ 0.6*V DD —V DDQ + 0.3V 1,3V DDQ I/O Input Low VoltageV ILQ–0.3—0.3*V DDV1,3Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS8321V18/32/36E-250/225/200/166/150/133DQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA ZZ Input Current I IN1V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH –1 uA –1 uA 1 uA 100 uA FT Input Current I IN2V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL–100 uA –1 uA 1 uA 1 uA Output Leakage Current I OL Output Disable, V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V—Output Low VoltageV OL1I OL = 4 mA, V DD = 1.6 V—0.4 VGS8321V18/32/36E-250/225/200/166/150/133O p e r a t i n g C u r r e n t sP a r a m e t e r T e s t C o n d i t i o n s M o d eS y m b o l -250-225-200-166-150-133U n i t0t o 70°C –40 t o 85°C0t o 70°C–40 t o 85°C0t o 70°C–40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°CO p e r a t i n g C u r r e n tD e v i c e S e l e c t e d ; A l l o t h e r i n p u t s ≥V I H o r ≤ V I LO u t p u t o p e n(x 32/x 36)P i p e l i n e I D DI D D Q300503205027545295452554027540225352453521030230301902521025m AF l o w T h r o u g hI D DI D D Q210252202520025210251902020020180201902017020180201601517015m A(x 18)P i p e l i n e I D DI D D Q260252802524025260252252024520200202202019020210201701519015m AF l o w T h r o u g hI D DI D D Q190152001518015190151701518015160151701515015160151401515015m AS t a n d b y C u r r e n tZ Z ≥ V D D – 0.2 V—P i p e l i n eI S B 608060806080608060806080m AF l o w T h r o u g hI S B608060806080608060806080m AD e s e l e c t C u r r e n tD e v i c e D e s e l e c t e d ; A l l o t h e r i n p u t s ≥ V I H o r ≤ V I L—P i p e l i n eI D D100115951109010585100851008095m AF l o w T h r o u g hI D D85100851008095809575907085m AN o t e s : 1.I D D a n d I D D Q a p p l y t o a n y c o m b i n a t i o n o f V D D 3, V D D 2, V D D Q 3, a n d V D D Q 2 o p e r a t i o n .2.A l l p a r a m e t e r s l i s t e d a r e w o r s t c a s e s c e n a r i o .AC Electrical CharacteristicsParameter Symbol -250-225-200-166-150-133UnitMin Max Min Max Min Max Min Max Min Max Min Max Flow ThroughClock Cycle Time tKC 5.5— 6.0— 6.5—7.0—7.5—8.5—ns Clock to Output ValidtKQ — 5.5— 6.0— 6.5—7.0—7.5—8.5ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3— 1.3— 1.5— 1.7—ns Clock LOW Time tKL 1.5— 1.5— 1.5— 1.5— 1.7—2—ns Clock to Output inHigh-Z tHZ 1 1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns G to Output Valid tOE — 2.5— 2.7— 3.0— 3.5— 3.8— 4.0ns G to output in Low-Z tOLZ 10—0—0—0—0—0—ns G to output in High-Z tOHZ 1— 2.5— 2.7— 3.0— 3.0— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—20—ns GS8321V18/32/36E-250/225/200/166/150/133Notes:1.These parameters are sampled and are not 100% tested2.ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.GS8321V18/32/36E-250/225/200/166/150/133Pipeline Mode TimingBegin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3ContDeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStHtStHtStStHtStHtStHtSBurst ReadtKCtKL tKH Single Write Single ReadQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E1 masks ADSPE2 and E3 only sampled with ADSP and ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS8321V18/32/36E-250/225/200/166/150/133Flow Through Mode TimingBegin Read A ContCont Write B Read C Read C+1Read C+2Read C+3Read C Cont DeselecttHZtKQXtKQ tLZtH tStOHZtOEtHtS tHtS tHtStHtS tHtS tHtStHtS tHtS tH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSCADSC initiated readDeselected with E1Fixed HighCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS8321V18/32/36E-250/225/200/166/150/133Sleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramtZZRtZZHtZZSHoldSetup tKLtKHtKCCKADSP ADSCZZApplication TipsSingle and Dual Cycle DeselectSCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usuallyassures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.JTAG Port OperationOverviewThe JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V DD . The JTAG output drivers are powered by V DDQ .Disabling the JTAG PortIt is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V DD or V SS . TDO should be left unconnected.JTAG Pin DescriptionsPinPin NameI/ODescriptionTCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.TMSTest Mode SelectInThe TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level.TDI Test Data In InThe TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.TDO Test Data OutOut Output that is active depending on the state of the TAP state machine. Output changes inresponse to the falling edge of TCK. This is the output side of the serial registers placed betweenTDI and TDO.This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.GS8321V18/32/36E-250/225/200/166/150/133JTAG Port RegistersOverviewThe various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.Instruction RegisterThe Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.Bypass RegisterThe Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.Boundary Scan RegisterThe Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is inCapture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.。

GS8640V18T-167中文资料

GS8640V18/32/36T-300/250/200/1674M x 18, 2M x 32, 2M x 3672Mb Sync Burst SRAMs 300 MHz –167 MHz1.8 V V DD 1.8 V I/O100-Pin TQFP Commercial Temp Industrial Temp Features• FT pin for user-configurable flow through or pipeline operation• Single Cycle Deselect (SCD) operation • 1.8 V +10%/–10% core power supply • 1.8 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode• Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package • Pb-Free 100-lead TQFP package availableFunctional DescriptionApplicationsThe GS8640V18/32/36T is a 75,497,472-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. ControlsAddresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burstcycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear orinterleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.Sleep ModeLow power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS8640V18/32/36T operates on a 1.8 V power supply. All input are 1.8 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 1.8 V compatible.Parameter Synopsis-300-250-200-167Unit Pipeline 3-1-1-1KQ tCycle 3.3 4.0 5.0 6.0ns (x18)Curr (x32/x36)480410350305mA Flow Through 2-1-1-1t KQ tCycle 5.55.5 6.56.57.57.58.08.0ns ns Curr (x18)Curr (x32/x36)285330245280220250210240mA mAGS8640V18/32/36T-300/250/200/167GS8640V18 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V DD NC V SS DQ B DQ B V DDQ V SS DQ B DQ B DQP BV SS V DDQ V DDQ V SS DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0A A V S SV D DA A A A A A A AA A E 1E 2 N C N C B BB AE 3C K G W B W VD DV S SG A D S C A D S P A D V A AA 4M x 18Top View DQP A A NC NC NC NC NC NC NC NCNC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950FTGS8640V18/32/36T-300/250/200/167GS8640V32 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0A A V S SV D DA A A A A A A AA A E 1E 2 B DB CB BB AE 3C K G W B W VD DV S SG A D S C A D S P A D V A AA 2M x 32Top View DQB NC DQ B DQ B DQ B DQ A DQ A DQ A DQ A NCDQ C DQ C DQ C DQ D DQ D DQ D NCDQ C NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950FTGS8640V18/32/36T-300/250/200/167GS8640V36 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C3V SS V DDQ DQ C DQ C V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0A A V S SV D DA A A A A A A AA A E 1E 2 B DB CB BB AE 3C K G W B W VD DV S SG A D S C A D S P A D V A AA 2M x 36Top View DQB DQP B DQ B DQ B DQ B DQ A DQ A DQ A DQ A DQP ADQ C DQ C DQ C DQ D DQ D DQ D DQP DDQ C DQP C 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS8640V18/32/36T-300/250/200/167TQFP Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter preset InputsA I Address InputsDQ ADQ BI/O Data Input and Output pinsDQ CDQ DNC No ConnectBW I Byte Write—Writes all enabled bytes; active lowB A, B B I Byte Write Enable for DQ A, DQ B Data I/Os; active lowB C, B D I Byte Write Enable for DQ C, DQ D Data I/Os; active lowCK I Clock Input Signal; active highGW I Global Write Enable—Writes all bytes; active lowE1, E3I Chip Enable; active lowE2I Chip Enable; active highG I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active highFT I Flow Through or Pipeline mode; active lowLBO I Linear Burst Order mode; active lowV DD I Core power supplyV SS I I/O and Core GroundV DDQ I Output driver power supplyGS8640V18/32/36T-300/250/200/167GS8640V18/32/36 Block DiagramA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–AnLBO ADV CK ADSC ADSP GW BW E 1GZZPower Down ControlMemory Array36364AQDE 2E 3DQx1–DQx9Note: Only x36 version shown for simplicity.B AB BB CB DFTGS8640V18/32/36T-300/250/200/167Note:There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.Burst Counter SequencesBPR 1999.05.18Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down ControlZZL or NC Active HStandby, I DD = I SBNote:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100GS8640V18/32/36T-300/250/200/1671.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x32 and x36 versions.Byte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytesHLLLLL2, 3, 4Write all bytes L X X X X XGS8640V18/32/36T-300/250/200/167Synchronous Truth TableOperation AddressUsedStateDiagramKey5E1E2ADSP ADSC ADV W3DQ4Deselect Cycle, Power Down None X H X X L X X High-Z Deselect Cycle, Power Down None X L F L X X X High-Z Deselect Cycle, Power Down None X L F H L X X High-Z Read Cycle, Begin Burst External R L T L X X X Q Read Cycle, Begin Burst External R L T H L X F Q Write Cycle, Begin Burst External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend Burst Current H X X H H T D1.X = Don’t Care, H = High, L = Low2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 13.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.4.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).5.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.6.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.7.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS8640V18/32/36T-300/250/200/167Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWX XWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, andassumes ADSP is tied high and ADV is tied low.GS8640V18/32/36T-300/250/200/167Simplified State Diagram with GFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS8640V18/32/36T-300/250/200/167Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 3.6V V DDQ Voltage in V DDQ Pins –0.5 to 3.6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 3.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 3.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125o CPower Supply Voltage RangesParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD1 1.6 1.82.0V 1.8 V V DDQ I/O Supply VoltageV DDQ11.61.82.0VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.GS8640V18/32/36T-300/250/200/167Note:These parameters are sample tested.Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.3*V DD V 1V DDQ I/O Input High Voltage V IHQ 0.6*V DD —V DDQ + 0.3V 1,3V DDQ I/O Input Low VoltageV ILQ–0.3—0.3*V DDV1,3Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.Capacitance(T A = 25o C, f = 1 MH Z , V DD = 2.5 V)ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pF20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILGS8640V18/32/36T-300/250/200/167AC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. DC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA ZZ Input Current I IN1V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH –1 uA –1 uA 1 uA 100 uA FT Input Current I IN2V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL–100 uA –1 uA 1 uA 1 uA Output Leakage Current I OL Output Disable, V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V—Output Low VoltageV OL1I OL = 4 mA, V DD = 1.6 V—0.4 VDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceGS8640V18/32/36T-300/250/200/167Notes:1.I DD and I DDQ apply to any combination of V DD and V DDQ operation.2.All parameters listed are worst case scenario.Operating CurrentsParameterTest ConditionsModeSymbol-300-250-200-167Unit0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40to 85°C 0 to 70°C –40to 85°C Operating CurrentDevice Selected; All other inputs ≥V IH o r ≤ V IL Output open(x32/x36)Pipeline I DD I DDQ 4206044060360503805031040330402703529035mA Flow Through I DD I DDQ 3003032030255252752523020250202202024020mA (x18)PipelineI DD I DDQ 3703039030315253352527020290202402026020mA Flow Through I DD I DDQ 2701529015230152501520515225151951521515mA Standby Current ZZ ≥ V DD – 0.2 V —PipelineI SB 100120100120100120100120mA Flow Through I SB 100120100120100120100120mA Deselect CurrentDevice Deselected; All other inputs ≥ V IH or ≤ V IL—Pipeline I DD 150165140155130146125140mA Flow ThroughI DD135150125140120135120135mAGS8640V18/32/36T-300/250/200/167Notes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.AC Electrical CharacteristicsParameter Symbol -300-250-200-167Unit Min Max MinMax MinMax MinMax PipelineClock Cycle Time tKC 3.3— 4.0— 5.0— 6.0—ns Clock to Output ValidtKQ — 2.3— 2.5— 3.0— 3.5ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5— 1.5—ns Setup time tS 1.1— 1.2— 1.4— 1.5—ns Hold time tH 0.1—0.2—0.4—0.5—ns Flow ThroughClock Cycle Time tKC 5.5— 6.5—7.5—8.0—ns Clock to Output ValidtKQ — 5.5— 6.5—7.5—8.0ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.0— 1.3— 1.3— 1.3—ns Clock LOW Time tKL 1.2—1.5—1.5—1.5—ns Clock to Output inHigh-Z tHZ 1 1.5 2.3 1.5 2.5 1.5 3.0 1.5 3.0ns G to Output Valid tOE — 2.3— 2.5— 3.0— 3.5ns G to output in Low-Z tOLZ 10—0—0—0—ns G to output in High-Z tOHZ 1— 2.3— 2.5— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—ns ZZ hold time tZZH 21—1—1—1—ns ZZ recoverytZZR20—20—20—20—nsGS8640V18/32/36T-300/250/200/167Pipeline Mode Timing (SCD)Begin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3ContDeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStHtStHtStStHtStHtStHtSBurst ReadtKCtKL Single Write tKH Single ReadQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E1 masks ADSPE2 and E3 only sampled with ADSP and ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS8640V18/32/36T-300/250/200/167Flow Through Mode Timing (SCD)Begin Read A ContCont Write B Read C Read C+1Read C+2Read C+3Read C Cont DeselecttHZtKQXtKQ tLZtH tStOHZtOEtHtS tHtS tHtStHtS tHtS tHtStHtS tHtS tH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSCADSC initiated readDeselected with E1Fixed HighCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS8640V18/32/36T-300/250/200/167Sleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramtZZRtZZHtZZSHoldSetup tKLtKHtKCCKADSP ADSCZZGS8640V18/32/36T-300/250/200/167TQFP Package Drawing (Package T)D1D E1EPin 1be cLL1A2A1YθNotes:1.All dimensions are in millimeters (mm).2.Package width and length do not include mold protrusion.SymbolDescriptionMin.Nom.MaxA1Standoff 0.050.100.15A2Body Thickness 1.35 1.40 1.45b Lead Width 0.200.300.40c Lead Thickness 0.09—0.20D Terminal Dimension 21.922.022.1D1Package Body 19.920.020.1E Terminal Dimension 15.916.016.1E1Package Body 13.914.014.1e Lead Pitch —0.65—L Foot Length 0.450.600.75L1Lead Length —1.00—Y Coplanarity 0.10θLead Angle0°—7°GS8640V18/32/36T-300/250/200/167Ordering Information for GSI Synchronous Burst RAMs OrgPart Number1TypePackageSpeed 2(MHz/ns)T A 3Status4M x 18GS8640V18T-300Pipeline/Flow Through TQFP 300/5.5C 4M x 18GS8640V18T-250Pipeline/Flow Through TQFP 250/6.5C 4M x 18GS8640V18T-200Pipeline/Flow Through TQFP 200/7.5C 4M x 18GS8640V18T-167Pipeline/Flow Through TQFP 167/8C 2M x 32GS8640V32T-300Pipeline/Flow Through TQFP 300/5.5C 2M x 32GS8640V32T-250Pipeline/Flow Through TQFP 250/6.5C 2M x 32GS8640V32T-200Pipeline/Flow Through TQFP 200/7.5C 2M x 32GS8640V32T-167Pipeline/Flow Through TQFP 167/8C 2M x 36GS8640V36T-300Pipeline/Flow Through TQFP 300/5.5C 2M x 36GS8640V36T-250Pipeline/Flow Through TQFP 250/6.5C 2M x 36GS8640V36T-200Pipeline/Flow Through TQFP 200/7.5C 2M x 36GS8640V36T-167Pipeline/Flow Through TQFP 167/8C 4M x 18GS8640V18T-300I Pipeline/Flow Through TQFP 300/5.5I 4M x 18GS8640V18T-250I Pipeline/Flow Through TQFP 250/6.5I 4M x 18GS8640V18T-200I Pipeline/Flow Through TQFP 200/7.5I 4M x 18GS8640V18T-167I Pipeline/Flow Through TQFP 167/8I 2M x 32GS8640V32T-300I Pipeline/Flow Through TQFP 300/5.5I 2M x 32GS8640V32T-250I Pipeline/Flow Through TQFP 250/6.5I 2M x 32GS8640V32T-200I Pipeline/Flow Through TQFP 200/7.5I 2M x 32GS8640V32T-167I Pipeline/Flow Through TQFP 167/8I 2M x 36GS8640V36T-300I Pipeline/Flow Through TQFP 300/5.5I 2M x 36GS8640V36T-250I Pipeline/Flow Through TQFP 250/6.5I 2M x 36GS8640V36T-200I Pipeline/Flow Through TQFP 200/7.5I 2M x 36GS8640V36T-167I Pipeline/Flow Through TQFP 167/8I 4M x 18GS8640V18GT-250Pipeline/Flow Through Pb-Free TQFP 250/6.5C 4M x 18GS8640V18GT-200Pipeline/Flow Through Pb-Free TQFP 200/7.5C 4M x 18GS8640V18GT-167Pipeline/Flow Through Pb-Free TQFP 167/8C 2M x 32GS8640V32GT-300Pipeline/Flow ThroughPb-Free TQFP300/5.5C2M x 32GS8640V32GT-250Pipeline/Flow Through Pb-Free TQFP 250/6.5C Notes:1.Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8640V18T-300IT.2.The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Eachdevice is Pipeline/Flow Through mode-selectable by the user.3.T A = C = Commercial Temperature Range. T A = I = Industrial Temperature Range.4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which arecovered in this data sheet. See the GSI Technology web site () for a complete listing of current offerings.GS8640V18/32/36T-300/250/200/1672M x 32GS8640V32GT-200Pipeline/Flow Through Pb-Free TQFP 200/7.5C 2M x 32GS8640V32GT-167Pipeline/Flow Through Pb-Free TQFP 167/8C 2M x 36GS8640V36GT-250Pipeline/Flow Through Pb-Free TQFP 250/6.5C 2M x 36GS8640V36GT-200Pipeline/Flow Through Pb-Free TQFP 200/7.5C 2M x 36GS8640V36GT-167Pipeline/Flow Through Pb-Free TQFP 167/8C 4M x 18GS8640V18GT-300I Pipeline/Flow Through Pb-Free TQFP 300/5.5I 4M x 18GS8640V18GT-250I Pipeline/Flow Through Pb-Free TQFP 250/6.5I 4M x 18GS8640V18GT-200I Pipeline/Flow Through Pb-Free TQFP 200/7.5I 4M x 18GS8640V18GT-167I Pipeline/Flow Through Pb-Free TQFP 167/8I 2M x 32GS8640V32GT-300I Pipeline/Flow Through Pb-Free TQFP 300/5.5I 2M x 32GS8640V32GT-250I Pipeline/Flow Through Pb-Free TQFP 250/6.5I 2M x 32GS8640V32GT-200I Pipeline/Flow Through Pb-Free TQFP 200/7.5I 2M x 32GS8640V32GT-167I Pipeline/Flow Through Pb-Free TQFP 167/8I 2M x 36GS8640V36GT-300I Pipeline/Flow Through Pb-Free TQFP 300/5.5I 2M x 36GS8640V36GT-250I Pipeline/Flow Through Pb-Free TQFP 250/6.5I 2M x 36GS8640V36GT-200IPipeline/Flow ThroughPb-Free TQFP200/7.5I2M x 36GS8640V36GT-167I Pipeline/Flow Through Pb-Free TQFP 167/8I Ordering Information for GSI Synchronous Burst RAMs (Continued)OrgPart Number1TypePackageSpeed 2(MHz/ns)T A 3StatusNotes:1.Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8640V18T-300IT.2.The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Eachdevice is Pipeline/Flow Through mode-selectable by the user.3.T A = C = Commercial Temperature Range. T A = I = Industrial Temperature Range.4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which arecovered in this data sheet. See the GSI Technology web site () for a complete listing of current offerings.GS8640V18/32/36T-300/250/200/167 72Mb Sync SRAM Datasheet Revision HistoryDS/DateRev. Code: Old;New Types of ChangesFormat or ContentPage;Revisions;Reason8640Vxx_r1• Creation of new datasheet。

GS881Z36BD-150V中文资料

GS881Z18/32/36B(T/D)-xxxV9Mb Pipelined and Flow ThroughSynchronous NBT SRAM250 MHz–150 MHz 1.8 V or 2.5 V V DD 1.8 V or 2.5 V I/O100-Pin TQFP & 165-Bump BGA Commercial Temp Industrial Temp Features• User-configurable Pipeline and Flow Through mode• NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization• Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs• IEEE 1149.1 JTAG-compatible Boundary Scan• On-chip write parity checking; even or odd selectable • 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply• LBO pin for Linear or Interleave Burst mode • Pin-compatible with 2M, 4M, and 18M devices • Byte write operation (9-bit Bytes)• 3 chip enable signals for easy depth expansion • ZZ pin for automatic power-down • JEDEC-standard packages• RoHS-compliant 100-lead TQFP and 165-bump BGA packages availableFunctional DescriptionThe GS881Z18/32/36B(T/D)-xxxV is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.The GS881Z18/32/36B(T/D)-xxxV may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.The GS881Z18/32/36B(T/D)-xxxV is implemented with GSI's high performance CMOS technology and is available inJEDEC-standard 100-pin TQFP and 165-bump BGA packages.Paramter Synopsis-250-200-150UnitPipeline 3-1-1-1KQ tCycle 4.0 5.0 6.7ns Curr (x18)Curr (x32/x36)200230170195140160mA mA Flow Through 2-1-1-1t KQ tCycle 5.55.5 6.56.57.57.5ns ns Curr (x18)Curr (x32/x36)160185140160128145mA mA807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B FT V DD NC V SS DQ B DQ B6V DD V SS DQ B DQ B DQP BV SS V DDQ V DDQ V SS DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0T M S T D I V S SV D DT D O T C K A A A A A A 1A A E 1E 2 N C N C B BB AE 3C K W C K E VD DV S SG A D V N C A A AA 512K x 18Top View DQP A A NC NC NC NC NC NC NC NCNC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881Z18/32/36B(T/D)-xxxVGS881Z18BT-xxxV 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C FT V DD NC V SS DQ D DQ D2V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0T M S T D I V S SV D DT D O T C K A A A A A AA A E 1E 2 B DB CB BB AE 3C K W C K E VD DV S SG A D V N C A A AA 256K x 32Top View DQB NC DQ B DQ B DQ B DQ A DQ A DQ A DQ A NCDQ C DQ C DQ C DQ D DQ D DQ D NCDQ C NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881Z18/32/36B(T/D)-xxxVGS881Z32BT-xxxV 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C FT V DD NC V SS DQ D DQ D2V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0T M S T D I V S SV D DT D O T C K A A A A A AA A E 1E 2 B DB CB BB AE 3C K W C K E VD DV S SG A D V N C A A AA 256K x 36Top View DQB DQP B DQ B DQ B DQ B DQ A DQ A DQ A DQ A DQP ADQ C DQ C DQ C DQ D DQ D DQ D DQP DDQ C DQP C 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881Z18/32/36B(T/D)-xxxVGS881Z36BT-xxxV 100-Pin TQFP Pinout (Package T)100-Pin TQFP Pin DescriptionsSymbolTypeDescriptionA 0, A 1In Burst Address Inputs; Preload the burst counterA In Address Inputs CK In Clock Input SignalB A In Byte Write signal for data inputs DQ A1–DQ A9; active low B B In Byte Write signal for data inputs DQ B1–DQ B9; active low BC In Byte Write signal for data inputs DQ C1–DQ C9; active low BD In Byte Write signal for data inputs DQ D1–DQ D9; active lowW In Write Enable; active low E 1In Chip Enable; active lowE 2In Chip Enable—Active High. For self decoded depth expansion E 3In Chip Enable—Active Low. For self decoded depth expansionG In Output Enable; active lowADV In Advance/Load; Burst address counter control pinCKE In Clock Input Buffer Enable; active lowNC —No ConnectDQ A I/O Byte A Data Input and Output pins DQ B I/O Byte B Data Input and Output pins DQ C I/O Byte C Data Input and Output pins DQ D I/O Byte D Data Input and Output pins ZZ In Power down control; active high FT In Pipeline/Flow Through Mode Control; active lowLBO InLinear Burst Order; active low.TMS Scan Test Mode Select TDI Scan Test Data In TDO Scan Test Data Out TCK Scan Test Clock V DD In Core power supplyV SS In GroundV DDQInOutput driver power supplyGS881Z18/32/36B(T/D)-xxxVGS881Z18/32/36B(T/D)-xxxV165 Bump BGA—x18 Commom I/O—Top View 1234567891011A NC A E1BB NC E3CKE ADV A17A A A B NC A E2NC BA CK W G NC A NC B C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQA C D NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA D E NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA E F NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA F G NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA G H FT MCH NC V DD V SS V SS V SS V DD NC NC ZZ H J DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC J K DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC K L DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC L M DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC M N DQB NC V DDQ V SS NC NC NC V SS V DDQ NC NC N P NC NC A A TDI A1TDO A A A NC P RLBONCAATMSA0TCKAAAAR11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch(Package D)GS881Z18/32/36B(T/D)-xxxV165 Bump BGA—x32 Common I/O—Top View 1234567891011A NC A E1BC BB E3CKE ADV A17A NC A B NC A E2BD BA CK W G NC A NC B C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC NC C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCH NC V DD V SS V SS V SS V DD NC NC ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N NC NC V DDQ V SS NC NC NC V SS V DDQ NC NC N P NC NC A A TDI A1TDO A A A NC P RLBONCAATMSA0TCKAAAAR11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch(Package D)GS881Z18/32/36B(T/D)-xxxV165 Bump BGA—x36 Common I/O—Top View 1234567891011A NC A E1BC BB E3CKE ADV A A NC A B NC A E2BD BA CK W G NC A NC B C DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCH NC V DD V SS V SS V SS V DD NC NC ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N DQPD NC V DDQ V SS NC NC NC V SS V DDQ NC DQPA N P NC NC A A TDI A1TDO A A A NC P RLBONCAATMSA0TCKAAAAR11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch(Package D)GS881Z18/32/36D-xxxV165-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsA I Address Inputs DQ A DQB DQC DQD I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active lowNC —No ConnectCK I Clock Input Signal; active high CKE I Clock Enable; active low W I Write Enable; active low E 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active highZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowTMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCH —Must Connect High DNU —Do Not Use V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS881Z18/32/36B(T/D)-xxxVK18S A 1S A 0Bu r s t C o u n t e rL B OA D VM e m o r y A r r a yGC KC K ED QF TN CN CD Q a –D Q nKS A 1’S A 0’D QM a t c hW r i t e A d d r e s sR e g i s t e r 2W r i t e A d d r e s sR e g i s t e r 1W r i t e D a t aR e g i s t e r 2W r i t e D a t aR e g i s t e r 1KKKKKKS e n s e A m p sW r i t e D r i v e r sR e a d , W r i t e a n dD a t a C o h e r e n c yC o n t r o l L o g i cD QKP a r i t y C h e c kF TA 0–A nE 3E 2E 1WB DB CB BB AGS881Z18/32/36B(T/D)-xxxVGS881Z18/32/36B(T/D)-xxxV NBT SRAM Functional Block DiagramGS881Z18/32/36B(T/D)-xxxVFunctional DetailsClockingDeassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.Pipeline Mode Read and Write OperationsAll inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E 1, E 2 and E 3). Deassertion of any one of the Enable inputs will deactivate the device. Function W B A B B B C B D Read H X X X X Write Byte “a”L L H H H Write Byte “b”L H L H H Write Byte “c”L H H L H Write Byte “d”L H H H L Write all Bytes L L L L L Write Abort/NOPLHHHHRead operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E 1, E 2, and E 3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (B A , B B , B C & B D ) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.Flow Through Mode Read and Write OperationsOperation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.Synchronous Truth TableOperationType Address CK CKE ADV W Bx E 1E 2E 3G ZZDQNotesRead Cycle, Begin Burst R External L-H L L H X L H L L L Q Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3Write Cycle, Continue Burst B Next L-H L H X L X X X X L D1,3,10Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z Deselect Cycle D None L-H L L L H L H L X L High-Z 1Deselect Cycle, Continue DNone L-H L H X X X X X X L High-Z 1Sleep ModeNone X X X X X X X X X H High-Z Clock Edge Ignore, StallCurrentL-HHXXXXXXXL-4Notes:1.Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-lect cycle is executed first.2.Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the Wpin is sampled low but no Byte Write pins are active so no write operation is performed.3.G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off duringwrite cycles.4.If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the buswill remain in High Z.5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Writesignals are Low6.All inputs, except G and ZZ must meet setup and hold times of rising clock edge.7.Wait states can be inserted by setting CKE high.8.This device contains circuitry that ensures all outputs are in High Z during power-up.9. A 2-bit burst counter is incorporated.10.The address counter is incriminated for all Burst continue cycles.GS881Z18/32/36B(T/D)-xxxVGS881Z18/32/36B(T/D)-xxxVDeselectNew ReadNew WriteBurst ReadBurst WriteWRBRBWDDBBWRD BWRDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input commandcodes as indicated in the Synchronous Truth Table.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipelined and Flow Through Read/Write Control State DiagramWRPipelined and Flow Through Read Write Control State DiagramGS881Z18/32/36B(T/D)-xxxVIntermediateIntermediateIntermediateIntermediateIntermediateIntermediateHigh Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)TransitionƒInput Command CodeKeyTransitionIntermediate State (N+1)Notes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateIntermediate ƒn n+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipeline Mode Data I/O State DiagramNext StateStatePipeline Mode Data I/O State DiagramGS881Z18/32/36B(T/D)-xxxVFlow Through Mode Data I/O State Diagram High Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for: Pipeline and Flow through Read Write Control State DiagramGS881Z18/32/36B(T/D)-xxxVBurst CyclesAlthough NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.Burst OrderThe burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have beenaccessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details.Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down ControlZZL or NC Active HStandby, I DD = I SBNote:There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table.Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS881Z18/32/36B(T/D)-xxxVSleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramtZZRtZZHtZZStKLtKHtKCCKZZDesigning for CompatibilityThe GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V DD or V DDQ on pipelined parts and V SS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.Pin 66, a No Connect (NC) on GSI’s GS8160Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36B NBT SRAM, is often marked as a power pin on other vendor’s NBT compatible SRAMs. Specifically, it is marked V DD or V DDQ on pipelined parts and V SS on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity feature may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline modeapplications or tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage on V DDQ Pins –0.5 to V DDV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCGS881Z18/32/36B(T/D)-xxxVNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges (1.8 V/2.5 V Version)ParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD1 1.7 1.82.0V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 1.8 V V DDQ I/O Supply Voltage V DDQ1 1.7 1.8V DD V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.5V DDVNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS881Z18/32/36B(T/D)-xxxVV DDQ2 & V DDQ1 Range Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low VoltageV IL–0.3—0.3*V DDV1Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceFigure 1Input high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS881Z18/32/36B(T/D)-xxxVDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA FT, ZZ Input Current I IN V DD ≥ V IN ≥ 0 V –100 uA 100 uA Output Leakage CurrentI OLOutput Disable, V OUT = 0 to V DD–1 uA1 uADC Output Characteristics (1.8 V/2.5 V Version)ParameterSymbolTest ConditionsMinMax1.8 V Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V —2.5 V Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V1.7 V —1.8 V Output Low Voltage V OL1I OL = 4 mA —0.4 V2.5 V Output Low VoltageV OL2I OL = 8 mA—0.4 VGS881Z18/32/36B(T/D)-xxxVOperating CurrentsParameterTest ConditionsModeSymbol-250-200-150Unit0to 70°C–40 to 85°C0to 70°C –40to 85°C 0 to 70°C –40to 85°COperating CurrentDevice Selected; All other inputs ≥V IH o r ≤ V IL Output open(x32/x36)PipelineI DD I DDQ 200302203017025190251402016020mA Flow Through I DD I DDQ 160251802514020160201301515015mA (x18)PipelineI DD I DDQ 185152051515515175151301015010mA Flow ThroughI DD I DDQ 1451516515130101501012081408mA Standby Current ZZ ≥ V DD – 0.2 V —Pipeline I SB 405040504050mA Flow Through I SB 405040504050mA Deselect CurrentDevice Deselected; All other inputs ≥ V IH or ≤ V IL—PipelineI DD 859075806065mA Flow Through I DD606550555055mA1.I DD and I DDQ apply to any combination of V DD1, V DD2, V DDQ1, and V DDQ2 operation.2.All parameters listed are worst case scenario.。

GS88236AD-150中文资料

GS88218/36AB/D-250/225/200/166/150/133512K x 18, 256K x 369Mb SCD/DCD Sync Burst SRAMs 250 MHz –133MHz 2.5 V or 3.3 V V DD 2.5 V or 3.3 V I/O119- and 165-Bump BGA Commercial Temp Industrial Temp Features• FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable• IEEE 1149.1 JTAG-compatible Boundary Scan• On-chip read parity checking; even or odd selectable • ZQ mode pin for user-selectable high/low output drive • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications • JEDEC-standard 119- and 165-bump BGA packagesFunctional DescriptionApplicationsThe GS88218/36A is a 9,437,184-bit high performancesynchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.ControlsAddresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM inPipeline mode, activating the rising-edge-triggered Data Output Register.SCD and DCD Pipelined ReadsThe GS88218/36A is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.FLXDrive™The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.Sleep ModeLow power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS88218/36A operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.Parameter Synopsis-250-225-200-166-150-133Unit Pipeline 3-1-1-1KQ tCycle 4.0 4.4 5.0 6.0 6.77.5ns Curr (x18)Curr (x32/x36)280330255300230270200230185215165190mA mA Flow Through 2-1-1-1t KQ tCycle 5.55.5 6.06.0 6.56.57.07.07.57.58.58.5ns ns Curr (x18)Curr (x32/x36)175200165190160180150170145165135150mA mAGS88218/36AB/D-250/225/200/166/150/133 165 Bump BGA—x18 Commom I/O—Top View (Package D)1234567891011A NC A E1B B NC E3BW ADSC ADV A A AB NC A E2NC B A CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQA CD NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA DE NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA EF NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA FG NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA GH FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ HJ DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC JK DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC KL DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC LM DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC MN DQB SCD V DDQ V SS NC NC NC V SS V DDQ NC NC NP NC NC A A TDI A1TDO A A A A17PR LBO NC A A TMS A0TCK A A A A R11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump PitchGS88218/36AB/D-250/225/200/166/150/133165 Bump BGA—x36 Common I/O—Top View (Package D)1234567891011A NC A E1BC B B E3BW ADSC ADV A NC AB NC A E2BD B A CK GW G ADSP A NC BC DQC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQB CD DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB DE DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB EF DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB FG DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB GH FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ HJ DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA JK DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA KL DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA LM DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA MN DQD SCD V DDQ V SS NC NC NC V SS V DDQ NC DQA NP NC NC A A TDI A1TDO A A A A17PR LBO NC A A TMS A0TCK A A A A R11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump PitchGS88218/36AB/D-250/225/200/166/150/133 GS88236A Pad Out—119-Bump BGA—Top View (Package B)1234567A V DDQ A A ADSP A A V DDQB NC E2A ADSC A A NCC NC A A V DD A A NCD DQ C DQP C V SS ZQ V SS DQP B DQ BE DQ C DQ C V SS E1V SS DQ B DQ B3F V DDQ DQ C V SSG V SS DQ B V DDQG DQ C D Q C B C ADV B B DQ B DQ BH DQ C DQ C V SS GW V SS DQ B DQ BJ V DDQ V DD NC V DD NC V DD V DDQK DQ D DQ D V SS CK V SS DQ A DQ AL DQ D DQ D B D SCD B A DQ A DQ AM V DDQ DQ D V SS BW V SS DQ A V DDQN DQ D DQ D V SS A1V SS DQ A DQ AP DQ D DQP D V SS A0V SS DQP A DQ AR NC A LBO V DD FT A PET NC NC A A A NC ZZU V DDQ TMS TDI TCK TDO NC V DDQGS88218/36AB/D-250/225/200/166/150/133 GS88218A Pad Out—119-Bump BGA—Top View (Package B)1234567A V DDQ A A ADSP A A V DDQB NC E2A ADSC A A NCC NC A A V DD A A NCD DQ B NC V SS ZQ V SS DQP A NCE NC DQ B V SS E1V SS NC DQ AF V DDQ NC V SSG V SS DQ A V DDQG NC D Q B B B ADV NC NC DQ AH DQ B N C V SS GW V SS DQ A NCJ V DDQ V DD NC V DD NC V DD V DDQK NC DQ B V SS CK V SS NC DQ AL DQ B NC NC SCD B A DQ A NCM V DDQ DQ B V SS BW V SS NC V DDQN DQ B NC V SS A1V SS DQ A NCP NC DQP B V SS A0V SS NC DQ AR NC A LBO V DD FT A PET NC A A NC A A ZZU V DDQ TMS TDI TCK TDO NC V DDQGS88218/36AB/D-250/225/200/166/150/133GS88218/36 BGA Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter Preset InputsAn I Address InputsDQ ADQ BDQ CDQ DI/O Data Input and Output pinsB A, B B, B C, B D I Byte Write Enable for DQ A, DQ B, DQ C, DQ D I/Os; active lowNC—No ConnectNC—No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active lowGW I Global Write Enable—Writes all bytes; active lowE1I Chip Enable; active lowE3I Chip Enable; active lowE2I Chip Enable; active highG I Output Enable; active lowADV I Burst address counter advance enable; active l0w ADSC, ADSP I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep mode control; active highFT I Flow Through or Pipeline mode; active lowPE I9th Bit Enable; active lowLBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])TMS I Scan Test Mode SelectTDI I Scan Test Data InTDO O Scan Test Data OutTCK I Scan Test ClockMCL—Must Connect Low SCD—Single Cycle Deselect/Dual Cyle Deselect Mode Control V DD I Core power supplyV SS I I/O and Core GroundV DDQ I Output driver power supplyGS88218/36AB/D-250/225/200/166/150/133GS88218/36A (PE = 0) Block DiagramA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterD QR e g i s t e rDQ RegisterA0–An LBO ADV CK ADSC ADSP GW BW E 1FT GZZPower Down ControlMemory Array36364AQD DQx1–DQx9NCParity NCParity EncodeCompare3643636432Note: Only x36 version shown for simplicity.SCD3636DQR e g i s t e r 4B AB BB CB DGS88218/36AB/D-250/225/200/166/150/133GS88218/36A (PE = 1) x32 Mode Block DiagramA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–An LBO ADV CK ADSC ADSP GW BW B AB BB CB DE 1FT GZZPower Down ControlMemory Array36364AQD DQx1–DQx8NCParity NC Parity EncodeCompare3243236432Note: Only x36 version shown for simplicity.SCDD QRegisterD QRegisterParity Encode 3243236GS88218/36AB/D-250/225/200/166/150/133Note:There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ and PE pins, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.Burst Counter SequencesBPR 1999.05.188Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, I DD = I SB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance ControlZQ L High Drive (Low Impedance)H or NC Low Drive (High Impedance)9th Bit EnablePEL Activate DQPx I/Os (x18/x36 mode)H or NCDeactivate DQPx I/Os (x16/x32 mode)Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100GS88218/36AB/D-250/225/200/166/150/1331.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C , and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.Byte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytesHLLLLL2, 3, 4Write all bytes L X X X X XGS88218/36AB/D-250/225/200/166/150/133 Synchronous Truth TableOperation Address UsedStateDiagramKey5E1ADSP ADSC ADV W3DQ4Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CW H X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend Burst Current H X H H T D1.X = Don’t Care, H = High, L = Low2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS88218/36AB/D-250/225/200/166/150/133Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWX XWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs andassumes ADSP is tied high and ADV is tied low.GS88218/36AB/D-250/225/200/166/150/133Simplified State Diagram with GFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS88218/36AB/D-250/225/200/166/150/133Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage in V DDQ Pins –0.5 to 4.6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCPower Supply Voltage RangesParameterSymbolMin.Typ.Max.UnitNotes3.3 V Supply Voltage V DD3 3.0 3.3 3.6V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 3.3 V V DDQ I/O Supply Voltage V DDQ3 3.0 3.3 3.6V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.52.7VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS88218/36AB/D-250/225/200/166/150/133V DDQ3 Range Logic LevelsParameter Symbol Min.Typ.Max.Unit Notes V DD Input High Voltage V IH 2.0—V DD + 0.3V1V DD Input Low Voltage V IL–0.3—0.8V1V DDQ I/O Input High Voltage V IHQ 2.0—V DDQ + 0.3V1,3V DDQ I/O Input Low Voltage V ILQ–0.3—0.8V1,3 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.V DDQ2 Range Logic LevelsParameter Symbol Min.Typ.Max.Unit Notes V DD Input High Voltage V IH0.6*V DD—V DD + 0.3V1V DD Input Low Voltage V IL–0.3—0.3*V DD V1V DDQ I/O Input High Voltage V IHQ0.6*V DD—V DDQ + 0.3V1,3V DDQ I/O Input Low Voltage V ILQ–0.3—0.3*V DD V1,3 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.Recommended Operating TemperaturesParameter Symbol Min.Typ.Max.Unit Notes Ambient Temperature (Commercial Range Versions)T A02570°C2 Ambient Temperature (Industrial Range Versions)T A–402585°C2 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS88218/36AB/D-250/225/200/166/150/133Note:These parameters are sample tested.Capacitance(T A = 25o C, f = 1 MH Z , V DD = 2.5 V)ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFAC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 1Notes:1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. 50% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing50% tKCV DD + 2.0 V50%V DDV ILDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceGS88218/36AB/D-250/225/200/166/150/133DC Electrical CharacteristicsParameter Symbol Test Conditions Min Max Input Leakage Current(except mode pins)I IL V IN = 0 to V DD–1 uA 1 uAZZ Input Current I IN1V DD≥V IN ≥V IH0 V≤ V IN ≤ V IH–1 uA–1 uA1 uA100 uAFT, SCD, ZQ Input Current I IN2V DD≥V IN ≥V IL0 V≤ V IN ≤ V IL–100 uA–1 uA1 uA1 uAOutput Leakage Current I OL Output Disable, V OUT = 0 to V DD–1 uA 1 uA Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V 1.7 V—Output High Voltage V OH3I OH = –8 mA, V DDQ = 3.135 V 2.4 V—Output Low Voltage V OL I OL = 8 mA—0.4 VGS88218/36AB/D-250/225/200/166/150/133N o t e s : 1.I D D a n d I D D Q a p p l y t o a n y c o m b i n a t i o n o f V D D 3, V D D 2, V D D Q 3, a n d V D D Q 2 o p e r a t i o n .2.A l l p a r a m e t e r s l i s t e d a r e w o r s t c a s e s c e n a r i o .O p e r a t i n g C u r r e n t sP a r a m e t e r T e s t C o n d i t i o n s M o d eS y m b o l -250-225-200-166-150-133U n i t0t o 70°C –40 t o 85°C0t o 70°C–40 t o 85°C 0t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C O p e r a t i n g C u r r e n tD e v i c e S e l e c t e d ; A l l o t h e r i n p u t s ≥V I H o r ≤ V I LO u t p u t o p e n(x 36)P i p e l i n eI D DI D D Q290403004026535275352403025030205252152519025200251702018020m AF l o w T h r o u g hI D DI D D Q180201902017020180201651517515155151651515015160151401015010m A(x 18)P i p e l i n eI D DI D D Q260202702023520245202151522515185151951517015180151551016510m AF l o w T h r o u g hI D DI D D Q165101751015510165101501016010140101501013510145101251013510m AS t a n d b y C u r r e n tZ Z ≥ V D D – 0.2 V—P i p e l i n eI S B 203020302030203020302030m AF l o w T h r o u g hI S B203020302030203020302030m AD e s e l e c t C u r r e n tD e v i c e D e s e l e c t e d ; A l l o t h e r i n p u t s ≥ V I H o r ≤ V I L—P i p e l i n eI D D859080857580647060655055m AF l o w T h r o u g hI D D606560655055505550554550m AGS88218/36AB/D-250/225/200/166/150/133Notes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.AC Electrical CharacteristicsParameter Symbol -250-225-200-166-150-133Unit Min Max Min Max Min Max Min Max Min Max Min Max PipelineClock Cycle Time tKC 4.0— 4.4— 5.0— 6.0— 6.7—7.5—ns Clock to Output ValidtKQ — 2.5— 2.7— 3.0— 3.4— 3.8— 4.0ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Setup time tS 1.2— 1.3— 1.4— 1.5— 1.5— 1.5—ns Hold time tH 0.2—0.3—0.4—0.5—0.5—0.5—ns Flow ThroughClock Cycle Time tKC 5.5— 6.0— 6.5—7.0—7.5—8.5—ns Clock to Output ValidtKQ — 5.5— 6.0— 6.5—7.0—7.5—8.5ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3— 1.3— 1.5— 1.7—ns Clock LOW Time tKL 1.5—1.5—1.5—1.5— 1.7—2—ns Clock to Output inHigh-Z tHZ 1 1.5 2.3 1.5 2.5 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns G to Output Valid tOE — 2.3— 2.5— 3.2— 3.5— 3.8— 4.0ns G to output in Low-Z tOLZ 10—0—0—0—0—0—ns G to output in High-Z tOHZ 1— 2.3— 2.5— 3.0— 3.0— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—20—nsGS88218/36AB/D-250/225/200/166/150/133Pipeline Mode Timing (SCD)Begin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3ContDeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStHtStHtStStHtStHtStHtSBurst ReadtKCtKL Single Write tKH Single ReadQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E1 masks ADSPE2 and E3 only sampled with ADSP and ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS88218/36AB/D-250/225/200/166/150/133Flow Through Timing (SCD)Begin Read A ContCont Write B Read C Read C+1Read C+2Read C+3Read C Cont DeselecttHZtKQXtKQ tLZtH tStOHZtOEtHtS tHtS tHtStHtS tHtS tHtStHtS tHtS tH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSCADSC initiated readDeselected with E1Fixed HighCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS88218/36AB/D-250/225/200/166/150/133Pipeline Mode Timing (DCD)Begin Read A Cont Deselect Deselect Write BRead C Read C+1Read C+2Read C+3Cont Deselect DeselecttHZtKQXtKQtLZtHtStOHZtOEtHtStHtStHtStH tStHtStStHtStHtStHtStKCtKL tKHQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCHi-ZDeselected with E1E2 and E3 only sampled with ADSCADSC initiated readCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdGS88218/36AB/D-250/225/200/166/150/133Flow Through Mode Timing (DCD)Begin Read A ContDeselect Write B Read C Read C+1Read C+2Read C+3Read C DeselecttHZtKQX tLZtH tStOHZtOE tKQtHtS tHtS tHtStH tStHtS tHtStHtS tHtS tH tStH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSP and ADSCE1 masks ADSPADSC initiated readDeselected with E1E1 masks ADSPFixed HighCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdGS88218/36AB/D-250/225/200/166/150/133Sleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramApplication TipsSingle and Dual Cycle DeselectSCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.JTAG Port OperationOverviewThe JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V DD . The JTAG output drivers are powered by V DDQ .Disabling the JTAG PortIt is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V DD or V SS . TDO should be left unconnected.tZZRtZZHtZZSHoldSetup tKLtKHtKCCKADSP ADSCZZ。

GS8322V18E-250I中文资料

PreliminaryGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)2M x 18, 1M x 36, 512K x 7236Mb S/DCD Sync Burst SRAMs250 MHz –133 MHz1.8 V V DD 1.8 V I/O119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp Features• FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable• IEEE 1149.1 JTAG-compatible Boundary Scan• ZQ mode pin for user-selectable high/low output drive • 1.8 V +10%/–10% core power supply • 1.8 V +10%/–10% core power supply • 1.8 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications• JEDEC-standard 119-, 165-, and 209-bump BGA package • Pb-Free packages availableFunctional DescriptionApplicationsThe GS8322V18/36/72 is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.ControlsAddresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count ineither linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM inPipeline mode, activating the rising-edge-triggered Data Output Register.SCD and DCD Pipelined ReadsThe GS8322V18/36/72 is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.FLXDrive™The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.Parameter Synopsis-250-225-200-166-150-133UnitPipeline 3-1-1-1KQ t KQ (x72)tCycle 3.04.0 3.04.4 3.05.0 3.56.0 3.86.7 4.07.5ns ns Curr (x18)Curr (x36)Curr (x72)285350440265320410245295370220260320210240300185215265mA mA mA Flow Through 2-1-1-1t KQ tCycle 6.56.57.07.07.57.58.08.08.58.58.58.5ns ns Curr (x18)Curr (x36)Curr (x72)205235315195225295185210265175200255165190240155175230mA mA mAGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)209-Bump BGA—x72 Common I/O—Top View (Package C)1234567891011A DQ G DQ G A E2ADSP ADSC ADV E3A DQB DQ B AB DQ G DQ G BC BG NC BW A BB BF DQ B DQ B BC DQ G DQ G BH BD NC E1NC BE BA DQ B DQ B CD DQ G DQ G V SS NC NC G GW NC V SS DQ B DQ B DE DQP G DQP C V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQPF DQP B EF DQ C DQ C V SS V SS V SS ZQ V SS V SS V SS DQ F DQ F FG DQ C DQ C V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQ F DQ F GH DQ C DQ C V SS V SS V SS MCL V SS V SS V SS DQ F DQ F H J DQ C DQ C V DDQ V DDQ V DD MCL V DD V DDQ V DDQ DQ F DQ F J K NC NC CK NC V SS MCL V SS NC NC NC NC K L DQ H DQ H V DDQ V DDQ V DD FT V DD V DDQ V DDQ DQ A DQ A L M DQ H DQ H V SS V SS V SS MCL V SS V SS V SS DQ A DQ A M N DQ H DQ H V DDQ V DDQ V DD SCD V DD V DDQ V DDQ DQ A DQ A N P DQ H DQ H V SS V SS V SS ZZ V SS V SS V SS DQ A DQ A P R DQP D DQP H V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQP A DQP E R T DQ D DQ D V SS NC NC LBO NC NC V SS DQ E DQ E T U DQ D DQ D NC A A A A A A DQ E DQ E U V DQ D DQ D A A A A1A A A DQ E DQ E V W DQ D DQ D TMS TDI A A0A TDO TCK DQ E DQ E W11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump PitchGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)GS8322V72 209-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset Inputs.An IAddress InputsDQ A DQ B DQ C DQ D DQ E DQ F DQ G DQ H I/O Data Input and Output pinsB A , B B I Byte Write Enable for DQ A , DQ B I/Os; active low BC ,BD I Byte Write Enable for DQ C , DQ D I/Os; active low BE , BF , BG ,B HI Byte Write Enable for DQ E , DQ F , DQ G , DQ H I/Os; active lowNC —No ConnectCK I Clock Input Signal; active highGW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSCI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowSCD I Single Cycle Deselect/Dual Cycle Deselect Mode ControlMCH IMust Connect High MCL Must Connect Low BW I Byte Enable; active lowZQ I FLXDrive Output Impedance Control(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCKIScan Test ClockGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322V72 209-Bump BGA Pin Description (Continued)SymbolTypeDescriptionGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)165-Bump BGA—x18 Commom I/O—Top View (Package E)1234567891011A NC A E1BB NC E3BW ADSC ADV A A AB NC A E2NC BA CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPA CD NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA DE NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA EF NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA FG NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA GH FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ HJ DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC JK DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC KL DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC LM DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC MN DQPB SCD V DDQ V SS NC A NC V SS V DDQ NC NC NP NC NC A A TDI A1TDO A A A A PR LBO A A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump PitchGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)165-Bump BGA—x36 Common I/O—Top View 1234567891011A NC A E1BC BB E3BW ADSC ADV A NC A B NC A E2BD BA CK GW G ADSP A NC B C DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N DQPD SCD V DDQ V SS NC A NC V SS V DDQ NC DQPA N P NC NC A A TDI A1TDO A A A A P RLBOAAATMSA0TCKAAAAR11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch(Package E)GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)GS8322V18/36 165-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsAn I Address Inputs DQ A DQ B DQ C DQ D I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active low (x36 Version)NC —No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active l0w ADSC, ADSPI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCL —Must Connect LowSCD —Single Cycle Deselect/Dual Cyle Deselect Mode ControlV DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)119-Bump BGA—x36 Common I/O—Top View1234567A V DDQ A A ADSP A A V DDQ A B NC A A ADSC A A NC B C NC A A V DD A A NC C D DQ DQP V SS ZQ V SS DQP B DQ B D E DQ DQ V SS E1V SS DQ B DQ B E F V DDQ DQ V SS G V SS DQ B V DDQ F G DQ DQ BC ADV BB DQ B DQ B G H DQ DQ V SS GW V SS DQ B DQ B H J V DDQ V DD NC V DD NC V DD V DDQ J K DQ D DQ D V SS CK V SS DQ A DQ A K L DQ D DQ D BD SCD BA DQ A DQ A L M V DDQ DQ D V SS BW V SS DQ A V DDQ M N DQ D DQ D V SS A1V SS DQ A DQ A N P DQ D DQP D V SS A0V SS DQP A DQ A P R NC A LBO V DD FT A NC R T NC NC A A A A ZZ T UV DDQTMSTDITCKTDONCV DDQU7 x 17 Bump BGA—14 x 22 mm 2 Body—1.27 mm Bump PitchC C C C C C2C C CGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)119-Bump BGA—x18 Common I/O—Top View1234567A V DDQ A A ADSP A A V DDQ AB NC A A ADSC A A NC BC NC A A V DD A A NC CD DQ B NC V SS ZQ V SS DQP A NC DE NC DQ B V SS E1V SS NC DQ A EF V DDQ NC V SSG V SS DQ A V DDQ FG NC DQ B BB ADV NC NC DQ A GH DQ B NC V SS GW V SS DQ A NC HJ V DDQ V DD NC V DD NC V DD V DDQ JK NC DQ B V SS CK V SS NC DQ A KL DQ B NC NC SCD BA DQ A NC LM V DDQ DQ B V SS BW V SS NC V DDQ MN DQ B NC V SS A1V SS DQ A NC NP NC DQP B V SS A0V SS NC DQ A PR NC A LBO V DD FT A NC RT NC A A A A A ZZ TU V DDQ TMS TDI TCK TDO NC V DDQ U7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump PitchGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)GS8322V18/36 119-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsAn I Address Inputs DQ A DQ B DQ C DQ D I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active lowNC —No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low G I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSCI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])SCD I Single Cycle Deselect/Dual Cyle Deselect Mode ControlTMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock V DD I Core power supply V SS I I/O and Core Ground V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)A1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–An LBO ADV CK ADSC ADSP GW BW E 1FT GZZPower Down ControlMemory Array36364AQD DQx1–DQx93636Note: Only x36 version shown for simplicity.SCD3636B AB BB CB DGS8322V18/36 Block DiagramMode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, I DD = I SB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance ControlZQL High Drive (Low Impedance)H or NCLow Drive (High Impedance)GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Note:There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.The burst counter wraps to initial state on the 5th clock.The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110I nterleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Byte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytes H L L L L L 2, 3, 4Write all bytesLXXXXX1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C , and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.Synchronous Truth TableOperationAddress UsedState Diagram Key 5E 1ADSPADSCADVW 3DQ 4Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CWH X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend BurstCurrentHXHHTDNotes:1.X = Don’t Care, H = High, L = Low2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)First WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs andassumes ADSP is tied high and ADV is tied low.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Simplified State Diagram with GAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 3.6V V DDQ Voltage in V DDQ Pins –0.5 to 3.6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 3.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 3.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage RangesParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD 1.6 1.82.0V 1.8 V V DDQ I/O Supply VoltageV DDQ1.61.82.0VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.3*V DD V 1V DDQ I/O Input High Voltage V IHQ 0.6*V DD —V DDQ + 0.3V 1,3V DDQ I/O Input Low VoltageV ILQ–0.3—0.3*V DDV1,3Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)DQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA ZZ Input Current I IN1V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH –1 uA –1 uA 1 uA 100 uA FT, SCD, and ZQ Input Current I IN2V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL–100 uA –1 uA 1 uA 1 uA Output Leakage Current I OL Output Disable, V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V—Output Low VoltageV OL1I OL = 4 mA, V DD = 1.6 V—0.4 VGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)O p e r a t i n g C u r r e n t sP a r a m e t e r T e s t C o n d i t i o n s M o d eS y m b o l -250-225-200-166-150-133U n i t0t o 70°C –40 t o 85°C0t o 70°C–40 t o 85°C 0t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C O p e r a t i n g C u r r e n tD e v i c e S e l e c t e d ; A l l o t h e r i n p u t s ≥V I H o r ≤ V I LO u t p u t o p e n(x 72)P i p e l i n eI D DI D D Q380604006035060370603205034050280403004026040280402353025530m AF l o w T h r o u g hI D DI D D Q275402854025540265402353024530225302353021030220302102022020m A(x 36)P i p e l i n eI D DI D D Q300503205027545295452554027540225352453521030230301902521025m AF l o w T h r o u g hI D DI D D Q210252202520025210251902020020180201902017020180201601517015m A(x 18)P i p e l i n eI D DI D D Q260252802524025260252252024520200202202019020210201701519015m AF l o w T h r o u g hI D DI D D Q190152001518015190151701518015160151701515015160151401515015m AS t a n d b y C u r r e n tZ Z ≥ V D D – 0.2 V—P i p e l i n eI S B 608060806080608060806080m AF l o w T h r o u g hI S B608060806080608060806080m AD e s e l e c t C u r r e n tD e v i c e D e s e l e c t e d ; A l l o t h e r i n p u t s ≥ V I H o r ≤ V I L—P i p e l i n eI D D100115951109010585100851008095m AF l o w T h r o u g hI D D85100851008095809575907085m AN o t e s : 1.I D D a n d I D D Q a p p l y t o a n y c o m b i n a t i o n o f V D D 3, V D D 2, V D D Q 3, a n d V D D Q 2 o p e r a t i o n .2.A l l p a r a m e t e r s l i s t e d a r e w o r s t c a s e s c e n a r i o .AC Electrical CharacteristicsParameterSymbol-250-225-200-166-150-133UnitMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxPipelineClock Cycle Time tKC 4.0— 4.4— 5.0— 6.0— 6.7—7.5—ns Clock to Output Valid (x18/x36)tKQ — 2.5— 2.7— 3.0— 3.5— 3.8— 4.0ns Clock to Output Valid (x72)tKQ — 3.0— 3.0— 3.0— 3.5— 3.8— 4.0ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Setup time tS 1.2— 1.3— 1.4— 1.5— 1.5— 1.5—ns Hold time tH 0.2—0.3—0.4—0.5—0.5—0.5—ns Flow ThroughClock Cycle Time tKC 6.5—7.0—7.5—8.0—8.5—8.5—ns Clock to Output ValidtKQ — 6.5—7.0—7.5—8.0—8.5—8.5ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3— 1.3— 1.5— 1.7—ns Clock LOW Time tKL 1.5— 1.5— 1.5— 1.5— 1.7—2—ns Clock to Output in High-Z (x18/x36)tHZ 1 1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns Clock to Output in High-Z (x72)tHZ 1 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns G to Output Valid (x18/x36)tOE — 2.5— 2.7— 3.0— 3.5— 3.8— 4.0ns G to Output Valid(x72)tOE — 3.0— 3.0— 3.0— 3.5— 3.8— 4.0ns G to output in Low-Z tOLZ 10—0—0—0—0—0—ns G to output in High-Z (x18/x36)tOHZ 1— 2.5— 2.7— 3.0— 3.0— 3.0— 3.0ns G to output in High-Z (x72)tOHZ 1— 3.0— 3.0— 3.0— 3.0— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—20—nsGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Notes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Pipeline Mode Timing (SCD)Begin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3ContDeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStHtStHtStStHtStHtStHtSBurst ReadtKCtKL tKH Single Write Single ReadQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E1 masks ADSPE2 and E3 only sampled with ADSP and ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Flow Through Mode Timing (SCD)Begin Read A ContCont Write B Read C Read C+1Read C+2Read C+3Read C Cont DeselecttHZtKQXtKQ tLZtH tStOHZtOEtHtS tHtS tHtStHtS tHtS tHtStHtS tHtS tH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSCADSC initiated readDeselected with E1Fixed HighCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQd。

GS8662D36E-200中文资料

GS8662D08/09/18/36E-333/300/250/200/16772Mb SigmaQuad-II Burst of 4 SRAM333 MHz–167 MHz1.8 V V DD1.8 V and 1.5 V I/O165-Bump BGA Commercial Temp Industrial Temp Features• Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface• Byte Write controls sampled at data-in time • Burst of 4 Read and Write• 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation• Fully coherent read and write pipelines• ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan• Pin-compatible with present 9Mb, 18Mb, and 36Mb and future 144Mb devices• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package availableSigmaQuad ™ Family OverviewThe GS8662D08/09/18/36E are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662D08/18/36E SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed toimplement economical high performance networking systems.Clocking and Addressing SchemesThe GS8662D08/09/18/36E SigmaQuad-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate theoutput register clock inputs quasi independently with the C andC clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead.Because Separate I/O SigmaQuad-II B4 RAMs always transfer data in four packets, A0 and A1 are internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfers. Because the LSBs are tied off internally, the address field of a SigmaQuad-II B4 RAM is always two address pins less than the advertised index depth (e.g., the 4M x 18 has a 1024K addressable index).Parameter Synopsis- 333-300-250-200-167tKHKH 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns tKHQV0.45 ns0.45 ns0.45 ns0.45 ns0.50 ns165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump ArrayBottom View2M x 36 SigmaQuad-II SRAM—Top View1234567891011ACQ MCL/SA (288Mb)SA W BW2K BW1R SA MCL/SA (144Mb)CQ B Q27Q18D18SA BW3K BW0SA D17Q17Q8C D27Q28D19V SS SA NC SA V SS D16Q7D8D D28D20Q19V SS V SS V SS V SS V SS Q16D15D7E Q29D29Q20 V DDQ V SS V SS V SS V DDQ Q15D6Q6F Q30Q21D21 V DDQ V DD V SS V DD V DDQ D14Q14Q5G D30D22Q22 V DDQ V DD V SS V DD V DDQ Q13D13D5H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J D31Q31D23 V DDQ V DD V SS V DD V DDQ D12Q4D4K Q32D32Q23V DDQ V DD V SS V DD V DDQ Q12D3Q3L Q33Q24D24 V DDQ V SS V SS V SS V DDQ D11Q11Q2M D33Q34D25 V SS V SS V SS V SS V SS D10Q1D2N D34D26Q25 V SS SA SA SA V SS Q10D9D1P Q35D35Q26SA SA C SA SA Q9D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D352.MCL = Must Connect LowGS8662D08/09/18/36E-333/300/250/200/1674M x 18 SigmaQuad-II SRAM—Top View1234567891011ACQ MCL/SA (144Mb)SA W BW1K NC R SA SA CQ B NC Q9D9SA NC K BW0SA NC NC Q8C NC NC D10V SS SA NC SA V SS NC Q7D8D NC D11Q10V SS V SS V SS V SS V SS NC NC D7E NC NC Q11 V DDQ V SS V SS V SS V DDQ NC D6Q6F NC Q12D12 V DDQ V DD V SS V DD V DDQ NC NC Q5G NC D13Q13 V DDQ V DD V SS V DD V DDQ NC NC D5H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC D14 V DDQ V DD V SS V DD V DDQ NC Q4D4K NC NC Q14V DDQ V DD V SS V DD V DDQ NC D3Q3L NC Q15D15 V DDQ V SS V SS V SS V DDQ NC NC Q2M NC NC D16 V SS V SS V SS V SS V SS NC Q1D2N NC D17Q16 V SS SA SA SA V SS NC NC D1P NC NC Q17SA SA C SA SA NC D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.2.MCL = Must Connect LowGS8662D08/09/18/36E-333/300/250/200/1678M x 9 SigmaQuad-II SRAM—Top View1234567891011ACQ SA SA W NC K NC R SA SA CQ B NC NC NC SA NC K BW0SA NC NC Q4C NC NC NC V SS SA NC SA V SS NC NC D4D NC D5NC V SS V SS V SS V SS V SS NC NC NC E NC NC Q5 V DDQ V SS V SS V SS V DDQ NC D3Q3F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC D6Q6 V DDQ V DD V SS V DD V DDQ NC NC NC H D off V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC Q2D2K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC Q7D7 V DDQ V SS V SS V SS V DDQ NC NC Q1M NC NC NC V SS V SS V SS V SS V SS NC NC D1N NC D8NC V SS SA SA SA V SS NC NC NC P NC NC Q8SA SA C SA SA NC D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to D0:D8.2.MCL = Must Connect LowGS8662D08/09/18/36E-333/300/250/200/1678M x 8 SigmaQuad-II SRAM—Top View1234567891011ACQ SA SA W NW1K NC R SA SA CQ B NC NC NC SA NC K NW0SA NC NC Q3C NC NC NC V SS SA NC SA V SS NC NC D3D NC D4NC V SS V SS V SS V SS V SS NC NC NC E NC NC Q4 V DDQ V SS V SS V SS V DDQ NC D2Q2F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC D5Q5 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC Q1D1K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC Q6D6 V DDQ V SS V SS V SS V DDQ NC NC Q0M NC NC NC V SS V SS V SS V SS V SS NC NC D0N NC D7NC V SS SA SA SA V SS NC NC NC P NC NC Q7SA SA C SA SA NC NC NC RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.2.MCL = Must Connect LowGS8662D08/09/18/36E-333/300/250/200/167Pin Description TableSymbolDescriptionTypeCommentsSA Synchronous Address InputsInput —NC No Connect ——R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0–BW3Synchronous Byte Writes Input Active Low x9/x18/x36 only NW0–NW1Nybble Write Control PinInput Active Low x8 only K Input Clock Input Active High K Input Clock Input Active Low C Output Clock Input Active High C Output Clock Input Active LowTMS Test Mode Select Input —TDI Test Data Input Input —TCK Test Clock Input Input —TDO Test Data Output Output —V REF HSTL Input Reference Voltage Input —ZQ Output Impedance Matching Input Input —Qn Synchronous Data Outputs Output Dn Synchronous Data Inputs Input D off Disable DLL when low Input Active LowCQ Output Echo Clock Output —CQ Output Echo Clock Output —V DD Power Supply Supply 1.8 V Nominal V DDQ Isolated Output Buffer Supply Supply 1.5 or 1.8 V NominalV SSPower Supply: GroundSupply—GS8662D08/09/18/36E-333/300/250/200/167Note:NC = Not Connected to die or any other pinGS8662D08/09/18/36E-333/300/250/200/167BackgroundSeparate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the RAM’s bandwidth in half.Alternating Read-Write OperationsSigmaQuad-II SRAMs follow a few simple rules of operation.- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.- Read or Write data transfers in progress may not be interrupted and re-started. - R and W high always deselects the RAM.- All address, data, and control inputs are sampled on clock edges.In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details.SigmaQuad-II B4 SRAM DDR ReadThe status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), after the following rising edge of K with a rising edge of C (or by K if C and C are tied high), after the next rising edge of K with a rising edge of C, and after the following rising edge of K with a rising edge of C. Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle.SigmaQuad-II B4 Double Data Rate SRAM Read FirstRead ANOPRead BWrite CRead DWrite ENOPABCDEC C+1C+2C+3E E+1CC+1C+2C+3EE+1AA+1A+2A+3BB+1B+2B+3DD+1D+2K K AddressR W BWx D C C Q CQ CQGS8662D08/09/18/36E-333/300/250/200/167SigmaQuad-II B4 SRAM DDR WriteThe status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and finally by the next rising edge of K. and by the rising edge of the K that follows.SigmaQuad-II B4 Double Data Rate SRAM Write FirstWrite ANOPRead BWrite CRead DWrite ENOPABCDEA A+1A+2A+3C C+1C+2C+3E E+1E+AA+1A+2A+3CC+1C+2C+3EE+1E+BB+1B+2B+3DD+1D+2K K AddressR W BWx D C C Q CQ CQGS8662D08/09/18/36E-333/300/250/200/167Power-Up Sequence for SigmaQuad-II SRAMsSigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.Power-Up Sequence1. Power-up and maintain Doff at low state.1a.Apply V DD .1b. Apply V DDQ .1c. Apply V REF (may also be applied at the same time as V DDQ ).2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.Note:If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become stablized.DLL Constraints•The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t KCVar on page 21).•The DLL cannot operate at a frequency lower than 119 MHz.•If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage.Power-Up Sequence (Doff controlled)Power UP IntervalUnstable Clocking IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoffPower-Up Sequence (Doff tied High)Power UP IntervalUnstable Clocking IntervalStop Clock IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoff30ns MinNote:If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.GS8662D08/09/18/36E-333/300/250/200/167Special FunctionsByte Write and Nybble Write ControlByte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence.Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18 version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence.Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NBx” may be substituted in all the discussion above.Example x18 RAM Write Sequence using Byte Write EnablesData In SampleTimeBW0BW1D0–D8D9–D17Beat 101Data In Don’t CareBeat 210Don’t Care Data InBeat 300Data In Data InBeat 410Don’t Care Data InResulting Write OperationByte 1 D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Written Unchanged Unchanged Written Written Written Unchanged Written Beat 1Beat 2Beat 3Beat 4Output Register ControlSigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM.A K RW A 0–AnK W 0D 1–D nBank 0Bank 1Bank 2Bank 3R 0D A K W D A K W D A K W D R R R QQQQCCCCQ 1–Q nC W 1R 1W 2R 2W 3R 3Note:For simplicity BWn, NWn, K, and C are not shown.CQ CQ CQ CQ CQ 0CQ 1CQ 2CQ 3GS8662D08/09/18/36E-333/300/250/200/167Example Four Bank Depth Expansion SchematicΣ2x 2B 4 S i g m a Q u a d-I IS R A M D e p t h E x p a n s i o nR e a d AW r i t e B R e a d C W r i t e D R e a d E W r i t e F N O PAB C D E FDD +1D +2D +3DD +1D +2D +3BB +1B +2B +3FF +1FB B +1B +2B +3FF +1FA A +1A +2A +3E E +1E +2C C +1C +2C +3KKA d d r e s s R (1)R (2)W (1)W (2)B W x (1)D (1)B W x (2)D (2)C [1]C [1]Q (1)C Q (1)C Q [1]C [2]C [2]Q (2)C Q [2]C Q [2]GS8662D08/09/18/36E-333/300/250/200/167GS8662D08/09/18/36E-333/300/250/200/167FLXDrive-II Output Driver Impedance ControlHSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver isimplemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.Separate I/O SigmaQuad-II B4 SRAM Truth Table Previous OperationARWCurrent OperationDDDDQQQQK ↑(t n-1)K ↑(t n )K ↑(t n )K ↑(t n )K ↑(t n )K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)Deselect X 11Deselect X X ——Hi-Z Hi-Z ——Write X 1X Deselect D2D3——Hi-Z Hi-Z ——Read X X 1Deselect X X ——Q2Q3——Deselect V 10Write D0D1D2D3Hi-Z Hi-Z ——Deselect V 0X Read X X ——Q0Q1Q2Q3Read V X 0Write D0D1D2D3Q2Q3——WriteVXReadD2D3——Q0Q1Q2Q3Notes:1.“1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”2.“—” indicates that the input requirement or output state is determined by the next operation.3.Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.4.D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.5.Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-ceded by a Read command.ers should not clock in metastable addresses.Byte Write Clock Truth TableBWBWBWBWCurrent OperationDDDDK ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)K ↑(t n )K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)T T T TWriteDx stored if BWn = 0 in all four data transfers D0D2D3D4T F F F WriteDx stored if BWn = 0 in 1st data transfer only D0X X XF T F F WriteDx stored if BWn = 0 in 2nd data transfer only X D1X XF F T F WriteDx stored if BWn = 0 in 3rd data transfer only X X D2XF F F T WriteDx stored if BWn = 0 in 4th data transfer only X X X D3F F F F Write AbortNo Dx stored in any of the four data transfersX X X XNotes:1.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.2.If one or more BWn = 0, then BW = “T”, else BW = “F”.GS8662D08/09/18/36E-333/300/250/200/167x36 Byte Write Enable (BWn) Truth TableBW0BW1BW2BW3D0–D8D9–D17D18–D26D27–D351111Don’t Care Don’t Care Don’t Care Don’t Care 0111Data In Don’t Care Don’t Care Don’t Care 1011Don’t Care Data In Don’t Care Don’t Care 0011Data In Data In Don’t Care Don’t Care 1101Don’t Care Don’t Care Data In Don’t Care 0101Data In Don’t Care Data In Don’t Care 1001Don’t Care Data In Data In Don’t Care 0001Data In Data In Data In Don’t Care 1110Don’t Care Don’t Care Don’t Care Data In 0110Data In Don’t Care Don’t Care Data In 1010Don’t Care Data In Don’t Care Data In 0010Data In Data In Don’t Care Data In 1100Don’t Care Don’t Care Data In Data In 0100Data In Don’t Care Data In Data In 1000Don’t Care Data In Data In Data In 0Data InData InData InData Inx18 Byte Write Enable (BWn) Truth Table BW0BW1D0–D8D9–D1711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData Inx09 Byte Write Enable (BWn) Truth TableBW0D0–D81Don’t Care 0Data In 1Don’t Care 0Data InGS8662D08/09/18/36E-333/300/250/200/167Nybble Write Clock Truth TableNWNWNWNWCurrent OperationDDDDK ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)K ↑(t n )K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)T T T TWriteDx stored if NWn = 0 in all four data transfers D0D2D3D4T F F F WriteDx stored if NWn = 0 in 1st data transfer only D0X X XF T F F WriteDx stored if NWn = 0 in 2nd data transfer only X D1X XF F T F WriteDx stored if NWn = 0 in 3rd data transfer only X X D2XF F F T WriteDx stored if NWn = 0 in 4th data transfer only X X X D3F F F F Write AbortNo Dx stored in any of the four data transfersX X X XNotes :1.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.2.If one or more NWn = 0, then NW = “T”, else NW = “F”.x8 Nybble Write Enable (NWn) Truth Table NW0NW1D0–D3D4–D711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData InGS8662D08/09/18/36E-333/300/250/200/167GS8662D08/09/18/36E-333/300/250/200/167State DiagramPower-UpRead NOPLoad New Read Address D Count = 0DDR ReadD Count = D Count + 1Write NOPLoad New Write Address D Count = 0DDR WriteD Count = D Count + 1WRITEREAD READ D Count = 2WRITE D Count = 2READ WRITEAlwaysAlwaysREAD D Count = 2Notes:1.Internal burst counter is fixed as 2-bit linear (i.e., when first address is A0+0, next internal burst address is A0+1.2.“READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same istrue for “WRITE” and “WRITE”.3.Read and write state machine can be active simultaneously.4.State machine control timing sequence is controlled by K.READ D Count = 1Always Increment Read Address WRITE D Count = 2Increment Write AddressWRITE D Count = 1AlwaysAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 2.9V V DDQ Voltage in V DDQ Pins –0.5 to V DD V V REF Voltage in V REF Pins –0.5 to V DDQV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V V IN Voltage on Other Input Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V I IN Input Current on Any Pin +/–100mA dc I OUT Output Current on Any I/O Pin +/–100mA dcT J Maximum Junction Temperature125o C T STGStorage Temperature–55 to 125oCNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.GS8662D08/09/18/36E-333/300/250/200/167Recommended Operating ConditionsPower SuppliesParameterSymbolMin.Typ.Max.UnitSupply Voltage V DD 1.7 1.8 1.9V I/O Supply Voltage V DDQ 1.4 1.5V DD V Reference VoltageV REF0.68—0.95VNotes:1.The power supplies need to be powered up simultaneously or in the following sequence: V DD , V DDQ , V REF , followed by signalinputs. The power down sequence must be the reverse. V DDQ must not exceed V DD .2.Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. Thepart number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.Operating TemperatureParameterSymbolMin.Typ.Max.UnitAmbient Temperature (Commercial Range Versions)T A 02570°C Ambient Temperature (Industrial Range Versions)T A–402585°CGS8662D08/09/18/36E-333/300/250/200/167HSTL I/O DC Input CharacteristicsParameterSymbolMinMaxUnitsNotesDC Input Logic High V IH (dc)V REF + 0.1V DD + 0.3 V 1DC Input Logic LowV IL (dc)–0.3V REF – 0.1V1Notes:patible with both 1.8 V and 1.5 V I/O drivers2.These are DC test criteria. DC design criteria is V REF ± 50 mV. The AC V IH /V IL levels are defined separately for measuring timing param-eters.3.V IL (Min)DC = –0.3 V, V IL (Min)AC = –1.5 V (pulse width ≤ 3 ns).4.V IH (Max)DC = V DDQ + 0.3 V, V IH (Max)AC = V DDQ + 0.85 V (pulse width ≤ 3 ns).HSTL I/O AC Input CharacteristicsParameterSymbolMinMaxUnitsNotesAC Input Logic High V IH (ac)V REF + 200—mV 3,4AC Input Logic LowV IL (ac)—V REF – 200mV 3,4V REF Peak to Peak AC VoltageV REF (ac)—5% V REF (DC)mV1Notes:1.The peak to peak AC component superimposed on V REF may not exceed 5% of the DC component of V REF .2.To guarantee AC characteristics, V IH ,V IL , Trise, and Tfall of inputs and clocks must be within 10% of each other.3.For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.20% tKHKHV SS – 1.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKHKHV DD + 1.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DDParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Output Capacitance C OUT V OUT = 0 V 67pF Clock CapacitanceC CLKV IN = 0 V56pFNote:This parameter is sample tested.GS8662D08/09/18/36E-333/300/250/200/167AC Test ConditionsParameterConditionsInput high level 1.25 V Input low level 0.25 V Max. input slew rate 2 V/ns Input reference level 0.75 V Output reference levelV DDQ /2Note:Test conditions as specified with output loading as shown unless otherwise noted.DQVT = V DDQ /250ΩRQ = 250 Ω (HSTL I/O)V REF = 0.75 VAC Test Load DiagramInput and Output Leakage CharacteristicsParameterSymbolTest ConditionsMin.MaxNotesInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –2 uA 2 uA DoffI INDOFF V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL –2 uA –2 uA 2 uA 2 uA Output Leakage CurrentI OLOutput Disable,V OUT = 0 to V DDQ–2 uA2 uA(T A = 25= 1.8 V)GS8662D08/09/18/36E-333/300/250/200/167Programmable Impedance HSTL Output Driver DC Electrical CharacteristicsParameterSymbolMin.Max.UnitsNotesOutput High Voltage V OH1 V DDQ /2 – 0.12V DDQ /2 + 0.12V 1, 3Output Low Voltage V OL1 V DDQ /2 – 0.12V DDQ /2 + 0.12V 2, 3Output High Voltage V OH2 V DDQ – 0.2V DDQ V 4, 5Output Low VoltageV OL2Vss0.2V4, 6Notes:1. I OH = (V DDQ /2) / (RQ/5) +/– 15% @ V OH = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).2. I OL = (V DDQ /2) / (RQ/5) +/– 15% @ V OL = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).3.Parameter tested with RQ = 250Ω and V DDQ = 1.5 V or 1.8 V4.Minimum Impedance mode, ZQ = V SS5.I OH = –1.0 mA6.I OL = 1.0 mAOperating CurrentsParameterSymbolTest Conditions-333-300-250-200-167Notes0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C Operating Current (x36): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBDTBDTBDTBDTBDTBDTBDTBDTBDTBD2, 3Operating Current (x18): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x9): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x8): DDR I DDV DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Standby Current (NOP): DDR I SB1Device deselected,IOUT = 0 mA, f = Max,All Inputs ≤ 0.2 V or ≥ V DD – 0.2 VTBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 4Notes:1.Power measured with output pins floating.2.Minimum cycle, I OUT = 0 mA3.Operating current is calculated with 50% read cycles and 50% write cycles.4.Standby Current is only after all pending read and write burst operations are completed.GS8662D08/09/18/36E-333/300/250/200/167AC Electrical CharacteristicsParameter Symbol-333-300-250-200-167Units Notes Min Max Min Max Min Max Min Max Min MaxClockK, K Clock Cycle Time C, C Clock Cycle Time t KHKHt CHCH3.0 3.5 3.34.2 4.0 6.35.07.886.08.4nstKC Variable t KCVar—0.2—0.2—0.2—0.2—0.2ns5K, K Clock High Pulse Width C, C Clock High Pulse Width t KHKLt CHCL1.2— 1.32— 1.6—2.0— 2.4—nsK, K Clock Low Pulse Width C, C Clock Low Pulse Width t KLKHt CLCH1.2— 1.32— 1.6—2.0— 2.4—nsK to K HighC to C Hight KHKH 1.35— 1.49— 1.8— 2.2— 2.7—nsK, K Clock High to C, C Clock High t KHCH0 1.300 1.450 1.80 2.30 2.8nsDLL Lock Time t KCLock1024—1024—1024—1024—1024—cycle6 K Static to DLL reset t KCReset30—30—30—30—30—ns Output TimesK, K Clock High to Data Output Valid C, C Clock High to Data Output Valid t KHQVt CHQV—0.45—0.45—0.45—0.45—0.5ns3K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold t KHQXt CHQX–0.45—–0.45—–0.45—–0.45—–0.5—ns3K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid t KHCQVt CHCQV—0.45—0.45—0.45—0.45—0.5nsK, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold t KHCQXt CHCQX–0.45—–0.45—–0.45—–0.45—–0.5—nsCQ, CQ High Output Valid t CQHQV—0.25—0.27—0.30—0.35—0.40ns7 CQ, CQ High Output Hold t CQHQX–0.25—–0.27—–0.30—–0.35—–0.40—ns7K Clock High to Data Output High-Z C Clock High to Data Output High-Z t KHQZt CHQZ—0.45—0.45—0.45—0.45—0.5ns3K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z t KHQX1t CHQX1–0.45—–0.45—–0.45—–0.45—–0.5—ns3Setup TimesAddress Input Setup Time t AVKH0.4—0.4—0.5—0.6—0.7—ns Control Input Setup Time t IVKH0.4—0.4—0.5—0.6—0.7—ns2 Data Input Setup Time t DVKH0.28—0.3—0.35—0.4—0.5—ns。

GS8162Z18D-166资料

© 1999, GSI Technology
The x18 and x36 parts in this specification are Not Recommended for New Design.
元器件交易网
GS8162Z72 BGA Pin Description
Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.

GS8662R18GE-167I中文资料

GS8662R08/09/18/36E-333/300/250/200/16772Mb SigmaCIO DDR-II Burst of 4 SRAM333 MHz–167 MHz1.8 V V DD1.8 V and 1.5 V I/O165-Bump BGA Commercial Temp Industrial Temp Features• Simultaneous Read and Write SigmaCIO™ Interface • Common I/O bus• JEDEC-standard pinout and package • Double Data Rate interface• Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 4 Read and Write• 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface• Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines• ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan• Pin-compatible with present 9Mb, 18Mb, 36Mb and future 144Mb devices• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package availableSigmaCIO ™ Family OverviewThe GS8662R08/09/18/36E are built in compliance with the SigmaCIO DDR-II SRAM pinout standard for Common I/O synchronous SRAMs. They are 75,497,472-bit (72Mb)SRAMs. The GS8662R08/09/18/36E SigmaCIO SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed toimplement economical high performance networking systems.Clocking and Addressing SchemesThe GS8662R08/09/18/36E SigmaCIO DDR-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate theoutput register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-endedclock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead.Common I/O x36 and x18 SigmaCIO DDR-II B4 RAMs always transfer data in four packets. When a new address is loaded, A0 and A1 preset an internal 2 bit linear addresscounter. The counter increments by 1 for each beat of a burst of four data transfer. The counter always wraps to 00 after reaching 11, no matter where it starts.Common I/O x8 SigmaCIO DDR-II B4 RAMs always transfer data in four packets. When a new address is loaded, the LSBs are internally set to 0 for the first read or write transfer, and incremented by 1 for the next 3 transfers. Because the LSBs are tied off internally, the address field of a x8 SigmaCIO DDR-II B4 RAM is always two address pins less than the advertised index depth (e.g., the 4M x 18 has a 1024K addressable index).Parameter Synopsis-333-300-250-200-167tKHKH 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns tKHQV0.45 ns0.45 ns0.45 ns0.45 ns0.5 ns165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump ArrayBottom View2M x 36 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ MCL/SA (144Mb)SA R/W BW2K BW1LD SA SA CQ B NC DQ27DQ18SA BW3K BW0SA NC NC DQ8C NC NC DQ28V SS SA SA0SA1V SS NC DQ17DQ7D NC DQ29DQ19V SS V SS V SS V SS V SS NC NC DQ16E NC NC DQ20 V DDQ V SS V SS V SS V DDQ NC DQ15DQ6F NC DQ30DQ21 V DDQ V DD V SS V DD V DDQ NC NC DQ5G NC DQ31DQ22 V DDQ V DD V SS V DD V DDQ NC NC DQ14H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC DQ32 V DDQ V DD V SS V DD V DDQ NC DQ13DQ4K NC NC DQ23V DDQ V DD V SS V DD V DDQ NC DQ12DQ3L NC DQ33DQ24 V DDQ V SS V SS V SS V DDQ NC NC DQ2M NC NC DQ34 V SS V SS V SS V SS V SS NC DQ11DQ1N NC DQ35DQ25 V SS SA SA SA V SS NC NC DQ10P NC NC DQ26SA SA C SA SA NC DQ9DQ0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes toDQ27:DQ352.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/1674M x 18 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ SA SA R/W BW1K NC LD SA SA CQ B NC DQ9NC SA NC K BW0SA NC NC DQ8C NC NC NC V SS SA SA0SA1V SS NC DQ7NC D NC NC DQ10V SS V SS V SS V SS V SS NC NC NC E NC NC DQ11 V DDQ V SS V SS V SS V DDQ NC NC DQ6F NC DQ12NC V DDQ V DD V SS V DD V DDQ NC NC DQ5G NC NC DQ13 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC DQ4NC K NC NC DQ14V DDQ V DD V SS V DD V DDQ NC NC DQ3L NC DQ15NC V DDQ V SS V SS V SS V DDQ NC NC DQ2M NC NC NC V SS V SS V SS V SS V SS NC DQ1NC N NC NC DQ16 V SS SA SA SA V SS NC NC NC P NC NC DQ17SA SA C SA SA NC NC DQ0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ172.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/1678M x 9 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ SA SA R/W NC K NC LD SA SA CQ B NC NC NC SA NC K BW SA NC NC DQ4C NC NC NC V SS SA NC SA V SS NC NC NC D NC NC NC V SS V SS V SS V SS V SS NC NC NC E NC NC DQ5 V DDQ V SS V SS V SS V DDQ NC NC DQ3F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC NC DQ6 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC DQ2NC K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC DQ7NC V DDQ V SS V SS V SS V DDQ NC NC DQ1M NC NC NC V SS V SS V SS V SS V SS NC NC NC N NC NC NC V SS SA SA SA V SS NC NC NC P NC NC DQ8SA SA C SA SA NC NC DQ0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to0 at the beginning of each access.2.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/1678M x 8 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ SA SA R/W NW1K NC LD SA SA CQ B NC NC NC SA NC K NW0SA NC NC DQ3C NC NC NC V SS SA NC SA V SS NC NC NC D NC NC NC V SS V SS V SS V SS V SS NC NC NC E NC NC DQ4 V DDQ V SS V SS V SS V DDQ NC NC DQ2F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC NC DQ5 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC DQ1NC K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC DQ6NC V DDQ V SS V SS V SS V DDQ NC NC DQ0M NC NC NC V SS V SS V SS V SS V SS NC NC NC N NC NC NC V SS SA SA SA V SS NC NC NC P NC NC DQ7SA SA C SA SA NC NC NC RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to0 at the beginning of each access.2.NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ73.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/167Pin Description TableSymbolDescriptionTypeCommentsSA Synchronous Address InputsInput —NC No Connect ——R Synchronous Read Input Active High W Synchronous Write Input Active Low BW0–BW3Synchronous Byte Writes Input Active Low x18/x36 only NW0–NW1Nybble Write Control Pin Input Active Low x8 only LD Synchronous Load PinInput Active Low K Input Clock Input Active High K Input Clock Input Active Low C Output Clock Input Active High C Output Clock Input Active LowTMS Test Mode Select Input —TDI Test Data Input Input —TCK Test Clock Input Input —TDO Test Data Output Output —V REF HSTL Input Reference Voltage Input —ZQ Output Impedance Matching InputInput —MCL Must Connect Low——DQ Data I/O Input/Output Three State Doff Disable DLL when low Input Active LowCQ Output Echo Clock Output —CQ Output Echo Clock Output —V DD Power Supply Supply 1.8 V Nominal V DDQ Isolated Output Buffer Supply Supply 1.5 V NominalV SSPower Supply: GroundSupply—GS8662R08/09/18/36E-333/300/250/200/167Note:NC = Not Connected to die or any other pinGS8662R08/09/18/36E-333/300/250/200/167BackgroundCommon I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications. Therefore, the SigmaCIO DDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed Common I/O SRAM data bandwidth in half.Burst OperationsRead and write operations are “burst” operations. In every case where a read or write command is accepted by the SRAM, it will respond by issuing or accepting four beats of data, executing a data transfer on subsequent rising edges of K and K#, as illustrated in the timing diagrams. It is not possible to stop a burst once it starts. Four beats of data are always transferred. This means that it is possible to load new addresses every other K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are inserted.Deselect CyclesChip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the four beat read data transfer and then execute the deselect command, returning the output drivers to high-Z.A high on the LD# pin prevents the RAM from loading read or write commandinputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer operations.SigmaCIO DDR-II B4 SRAM Read CyclesThe status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst transfer inresponse to a read command, if the previous command captured was a read or write command, the Address, LD# and R/W# pins are ignored. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes pipelined reads. The read command is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM produces data out in response to the next rising edge of C# (or the next rising edge of K#, if C and C# are tied high). The second beat of data is transferred on the next rising edge of C, then on the next rising edge of C# and finally on the next rising edge of C, for a total of four transfers per address load.SigmaCIO DDR-II B4 SRAM Write CyclesThe status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst transfer in response to a write command, if the previous command captured was a read or write command, the Address, LD# and R/ W# pins are ignored at the next rising edge of K. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes “late write” data transfers. Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command and the write address. To complete the remaining three beats of the burst of four write transfer the SRAM captures data in on the next rising edge of K#, the following rising edge of K and finally on the next rising edge of K#, for a total of four transfers per address load.GS8662R08/09/18/36E-333/300/250/200/167Power-Up Sequence for SigmaQuad-II SRAMsSigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.Power-Up Sequence1. Power-up and maintain Doff at low state.1a.Apply V DD .1b. Apply V DDQ .1c. Apply V REF (may also be applied at the same time as V DDQ ).2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.Note:If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become stablized.DLL Constraints•The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t KCVar on page 20).•The DLL cannot operate at a frequency lower than 119 MHz.•If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage.Power-Up Sequence (Doff controlled)Power UP IntervalUnstable Clocking IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoffPower-Up Sequence (Doff tied High)Power UP IntervalUnstable Clocking IntervalStop Clock IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoff30ns MinNote:If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.GS8662R08/09/18/36E-333/300/250/200/167Special FunctionsByte Write and Nybble Write ControlByte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence.Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18 version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence.Nybble Write (4-bit) write control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NBx” may be substituted in all the discussion above.Example x18 RAM Write Sequence using Byte Write EnablesData In SampleTimeBW0BW1D0–D8D9–D17Beat 101Data In Don’t CareBeat 210Don’t Care Data InBeat 300Data In Data InBeat 410Don’t Care Data InResulting Write OperationByte 1 D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Written Unchanged Unchanged Written Written Written Unchanged Written Beat 1Beat 2Beat 3Beat 4Output Register ControlSigmaCIO DDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs isare tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM.A K R/W LDA 0–A nKBank 0Bank 1Bank 2Bank 3A KLD A K LD A K LD R/W R/W R/W DQDQDQ DQCC CCDQ 1–C R/WLD 0LD 1LD 2LD 3Note:For simplicity BWn (or NWn), K, and C are not shown.CQ CQ CQ CQ CQGS8662R08/09/18/36E-333/300/250/200/167Example Four Bank Depth Expansion SchematicGS8662R08/09/18/36E-333/300/250/200/167FLXDrive-II Output Driver Impedance ControlHSTL I/O SigmaCIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver isimplemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.Common I/O SigmaCIO DDR-II B4 SRAM Truth TableK nLDR/WDQOperationA + 0A + 1A + 2A + 3↑1X Hi-Z Hi-Z Hi-Z Hi-Z Deselect ↑00D@K n+1D@K n+1D@K n+2D@K n+2Write ↑1Q@K n+1or C n+1Q@K n+2or C n+2Q@K n+2or C n+2Q@K n+3or C n+3ReadNote:Q is controlled by K clocks if C clocks are not used.B4 Byte Write Clock Truth TableBW BW BW BW Current OperationD D D D K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)K ↑(t n )K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)TTTTWriteDx stored if BWn = 0 in all four data transfers D0D2D3D4T F F F WriteDx stored if BWn = 0 in 1st data transfer only D0X X XF T F F WriteDx stored if BWn = 0 in 2nd data transfer only X D1X XF F T F WriteDx stored if BWn = 0 in 3rd data transfer only X X D2XF F F T WriteDx stored if BWn = 0 in 4th data transfer only X X X D3F F F F Write AbortNo Dx stored in any of the four data transfersX X X XNotes:1.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.2.If one or more BWn = 0, then BW = “T”, else BW = “F”.GS8662R08/09/18/36E-333/300/250/200/167*Assuming stable conditions, the RAM can achieve optimum impedance within 1024 cycles.B4 Nybble Write Clock Truth TableNW NW NW NW Current OperationD D D D K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)K ↑(t n )K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)TTTTWriteDx stored if NWn = 0 in all four data transfers D0D2D3D4T F F F WriteDx stored if NWn = 0 in 1st data transfer only D0X X XF T F F WriteDx stored if NWn = 0 in 2nd data transfer only X D1X XF F T F WriteDx stored if NWn = 0 in 3rd data transfer only X X D2XF F F T WriteDx stored if NWn = 0 in 4th data transfer only X X X D3F F F F Write AbortNo Dx stored in any of the four data transfersX X X XNotes:1.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.2.If one or more NWn = 0, then NW = “T”, else NW = “F”.GS8662R08/09/18/36E-333/300/250/200/167x36 Byte Write Enable (BWn) Truth TableBW0BW1BW2BW3D0–D8D9–D17D18–D26D27–D351111Don’t Care Don’t Care Don’t Care Don’t Care 0111Data In Don’t Care Don’t Care Don’t Care 1011Don’t Care Data In Don’t Care Don’t Care 0011Data In Data In Don’t Care Don’t Care 1101Don’t Care Don’t Care Data In Don’t Care 0101Data In Don’t Care Data In Don’t Care 1001Don’t Care Data In Data In Don’t Care 0001Data In Data In Data In Don’t Care 1110Don’t Care Don’t Care Don’t Care Data In 0110Data In Don’t Care Don’t Care Data In 1010Don’t Care Data In Don’t Care Data In 0010Data In Data In Don’t Care Data In 1100Don’t Care Don’t Care Data In Data In 0100Data In Don’t Care Data In Data In 1000Don’t Care Data In Data In Data In 0Data InData InData InData Inx18 Byte Write Enable (BWn) Truth Table BW0BW1D0–D8D9–D1711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData Inx8 Nybble Write Enable (NWn) Truth Table NW0NW1D0–D3D4–D711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData InGS8662R08/09/18/36E-333/300/250/200/167GS8662R08/09/18/36E-333/300/250/200/167B4 State DiagramPower-UpNOPLoad New AddressDDR Read DDR WriteLOADREAD WRITE LOADLOADLOADLOADNotes:1.The internal burst address counter is a 4-bit linear counter (i.e., when first address is A0, next internal burst address is A0+1).2.“READ” refers to read active status with R/W = High, “WRITE” refers to write inactive status with R/W = Low.3.“LOAD” refers to read new address active status with LD = Low, “LOAD” refers to read new address inactive status with LD = High.LOAD Increment Read Address Increment Write AddressAlwaysAlwaysREADWRITEAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 2.9V V DDQ Voltage in V DDQ Pins –0.5 to V DD V V REF Voltage in V REF Pins –0.5 to V DDQV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V V IN Voltage on Other Input Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V I IN Input Current on Any Pin +/–100mA dc I OUT Output Current on Any I/O Pin +/–100mA dcT J Maximum Junction Temperature125o C T STGStorage Temperature–55 to 125oCNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.GS8662R08/09/18/36E-333/300/250/200/167Recommended Operating ConditionsPower SuppliesParameterSymbolMin.Typ.Max.UnitSupply Voltage V DD 1.7 1.8 1.9V I/O Supply Voltage V DDQ 1.7 1.8 1.9V Reference VoltageV REF0.68—0.95VNotes:1.Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ V DDQ ≤ 1.6 V (i.e., 1.5 V I/O)and 1.7 V ≤ V DDQ ≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.2.The power supplies need to be powered up simultaneously or in the following sequence: V DD , V DDQ , V REF , followed by signal inputs. Thepower down sequence must be the reverse. V DDQ must not exceed V DD ..Operating TemperatureParameterSymbolMin.Typ.Max.UnitAmbient Temperature (Commercial Range Versions)T A 02570°C Ambient Temperature (Industrial Range Versions)T A–402585°CGS8662R08/09/18/36E-333/300/250/200/167HSTL I/O DC Input CharacteristicsParameterSymbolMinMaxUnitsNotesDC Input Logic High V IH (dc)V REF + 0.10V DD + 0.3 V V 1DC Input Logic LowV IL (dc)–0.3 VV REF – 0.10V1Notes:patible with both 1.8 V and 1.5 V I/O drivers2.These are DC test criteria. DC design criteria is V REF ± 50 mV. The AC V IH /V IL levels are defined separately for measuring timing parame-ters.3.V IL (Min) DC = –0.3 V, V IL (Min) AC = –1.5 V (pulse width ≤ 3 ns).4.V IH (Max) DC = V DDQ + 0.3 V, V IH (Max) AC = V DDQ + 0.85 V (pulse width ≤ 3 ns).HSTL I/O AC Input CharacteristicsParameterSymbolMinMaxUnitsNotesAC Input Logic High V IH (ac)V REF + 0.20—V 3,4AC Input Logic LowV IL (ac)—V REF – 0.20V 3,4V REF Peak to Peak AC VoltageV REF (ac)—5% V REF (DC)V1Notes:1.The peak to peak AC component superimposed on V REF may not exceed 5% of the DC component of V REF .2.To guarantee AC characteristics, V IH ,V IL , Trise, and Tfall of inputs and clocks must be within 10% of each other.3.For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.20% tKHKHV SS – 1.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKHKHV DD + 1.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DDParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Output Capacitance C OUT V OUT = 0 V67pF Clock CapacitanceC CLK—56pFNote:This parameter is sample tested.GS8662R08/09/18/36E-333/300/250/200/167AC Test ConditionsParameterConditionsInput high level V DDQ Input low level 0 V Max. input slew rate 2 V/ns Input reference level V DDQ /2Output reference levelV DDQ /2Note:Test conditions as specified with output loading as shown unless otherwise noted.DQVT = V DDQ /250ΩRQ = 250 Ω (HSTL I/O)V REF = 0.75 VAC Test Load DiagramInput and Output Leakage CharacteristicsParameterSymbolTest ConditionsMin.MaxNotesInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –2 uA 2 uA DoffI INDOFF V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL –100 uA –2 uA 2 uA 2 uA Output Leakage CurrentI OLOutput Disable,V OUT = 0 to V DDQ–2 uA2 uA(T A = 25= 3.3 V)GS8662R08/09/18/36E-333/300/250/200/167Programmable Impedance HSTL Output Driver DC Electrical CharacteristicsParameterSymbolMin.Max.UnitsNotesOutput High Voltage V OH1 V DDQ /2V DDQ V 1, 3Output Low Voltage V OL1 Vss V DDQ /2V 2, 3Output High Voltage V OH2 V DDQ – 0.2V DDQ V 4, 5Output Low VoltageV OL2Vss0.2V4, 6Notes:1. I OH = (V DDQ /2) / (RQ/5) +/– 15% @ V OH = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).2. I OL = (V DDQ /2) / (RQ/5) +/– 15% @ V OL = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).3.Parameter tested with RQ = 250Ω and V DDQ = 1.5 V or 1.8 V4.Minimum Impedance mode, ZQ = V SS5.I OH = –1.0 mA6.I OL = 1.0 mAOperating CurrentsParameterSymbolTest Conditions-333-300-250-200-167Notes0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C Operating Current (x36):DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBDTBDTBDTBDTBDTBDTBDTBDTBDTBD2, 3Operating Current (x18):DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x9):DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x8):DDR I DDV DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Standby Current (NOP):DDRI SB1Device deselected,I OUT = 0 mA, f = Max,All Inputs ≤ 0.2 V or ≥ V DD – 0.2 VTBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 4Notes:1.Power measured with output pins floating.2.Minimum cycle, I OUT = 0 mA3.Operating current is calculated with 50% read cycles and 50% write cycles.4.Standby Current is only after all pending read and write burst operations are completed.GS8662R08/09/18/36E-333/300/250/200/167AC Electrical CharacteristicsParameterSymbol-333-300-250-200-167UnitsN o t e sMin Max Min Max Min Max Min Max Min MaxClockK, K Clock Cycle Time C, C Clock Cycle Time t KHKH t CHCH 3.0 3.5 3.3 4.2 4.0 6.3 5.07.88 6.08.4ns tTKC Variablet KCVar —0.2—0.2—0.2—0.2—0.2ns 5K, K Clock High Pulse Width C, C Clock High Pulse Width t KHKL t CHCL 1.2— 1.32— 1.6— 2.0— 2.4—ns K, K Clock Low Pulse Width C, C Clock Low Pulse Width t KLKH t CLCH 1.2— 1.32— 1.6— 2.0— 2.4—ns K to K High C to C Hight KHKH 1.35— 1.49— 1.8— 2.2— 2.7—ns K, K Clock High to C, C Clock High t KHCH 0 1.30 1.450 1.80 2.30 2.8ns DLL Lock Time t KCLock 1024—1024—1024—1024—1024—cycle 6K Static to DLL resett KCReset 30—30—30—30—30—nsOutput TimesK, K Clock High to Data Output Valid C, C Clock High to Data Output Valid t KHQV t CHQV —0.45—0.45—0.45—0.45—0.5ns 3K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold t KHQX t CHQX –0.45—–0.45—–0.45—–0.45—–0.5—ns 3K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid t KHCQV t CHCQV —0.45—0.45—0.45—0.45—0.5ns K, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold t KHCQX t CHCQX –0.45—–0.45—–0.45—–0.45—–0.5—ns CQ, CQ High Output Valid t CQHQV —0.25—0.27—0.30—0.35—0.40ns 7CQ, CQ High Output Hold t CQHQX –0.25—–0.27—–0.30—–0.35—–0.40—ns 7K Clock High to Data Output High-Z C Clock High to Data Output High-Z t KHQZ t CHQZ —0.45—0.45—0.45—0.45—0.5ns 3K Clock High to Data Output Low-Z C Clock High to Data Output Low-Zt KHQX1t CHQX1–0.45—–0.45—–0.45—–0.45—–0.5—ns3Setup TimesAddress Input Setup Time t AVKH 0.4—0.4—0.5—0.6—0.7—ns Control Input Setup Time t IVKH 0.4—0.4—0.5—0.6—0.7—ns 2Data Input Setup Timet DVKH0.28—0.3—0.35—0.4—0.5—ns。

GS8662R36E-250I中文资料

GS8662R08/09/18/36E-333/300/250/200/16772Mb SigmaCIO DDR-II Burst of 4 SRAM333 MHz–167 MHz1.8 V V DD1.8 V and 1.5 V I/O165-Bump BGA Commercial Temp Industrial Temp Features• Simultaneous Read and Write SigmaCIO™ Interface • Common I/O bus• JEDEC-standard pinout and package • Double Data Rate interface• Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 4 Read and Write• 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface• Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines• ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan• Pin-compatible with present 9Mb, 18Mb, 36Mb and future 144Mb devices• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package availableSigmaCIO ™ Family OverviewThe GS8662R08/09/18/36E are built in compliance with the SigmaCIO DDR-II SRAM pinout standard for Common I/O synchronous SRAMs. They are 75,497,472-bit (72Mb)SRAMs. The GS8662R08/09/18/36E SigmaCIO SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed toimplement economical high performance networking systems.Clocking and Addressing SchemesThe GS8662R08/09/18/36E SigmaCIO DDR-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate theoutput register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-endedclock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead.Common I/O x36 and x18 SigmaCIO DDR-II B4 RAMs always transfer data in four packets. When a new address is loaded, A0 and A1 preset an internal 2 bit linear addresscounter. The counter increments by 1 for each beat of a burst of four data transfer. The counter always wraps to 00 after reaching 11, no matter where it starts.Common I/O x8 SigmaCIO DDR-II B4 RAMs always transfer data in four packets. When a new address is loaded, the LSBs are internally set to 0 for the first read or write transfer, and incremented by 1 for the next 3 transfers. Because the LSBs are tied off internally, the address field of a x8 SigmaCIO DDR-II B4 RAM is always two address pins less than the advertised index depth (e.g., the 4M x 18 has a 1024K addressable index).Parameter Synopsis-333-300-250-200-167tKHKH 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns tKHQV0.45 ns0.45 ns0.45 ns0.45 ns0.5 ns165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump ArrayBottom View2M x 36 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ MCL/SA (144Mb)SA R/W BW2K BW1LD SA SA CQ B NC DQ27DQ18SA BW3K BW0SA NC NC DQ8C NC NC DQ28V SS SA SA0SA1V SS NC DQ17DQ7D NC DQ29DQ19V SS V SS V SS V SS V SS NC NC DQ16E NC NC DQ20 V DDQ V SS V SS V SS V DDQ NC DQ15DQ6F NC DQ30DQ21 V DDQ V DD V SS V DD V DDQ NC NC DQ5G NC DQ31DQ22 V DDQ V DD V SS V DD V DDQ NC NC DQ14H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC DQ32 V DDQ V DD V SS V DD V DDQ NC DQ13DQ4K NC NC DQ23V DDQ V DD V SS V DD V DDQ NC DQ12DQ3L NC DQ33DQ24 V DDQ V SS V SS V SS V DDQ NC NC DQ2M NC NC DQ34 V SS V SS V SS V SS V SS NC DQ11DQ1N NC DQ35DQ25 V SS SA SA SA V SS NC NC DQ10P NC NC DQ26SA SA C SA SA NC DQ9DQ0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes toDQ27:DQ352.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/1674M x 18 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ SA SA R/W BW1K NC LD SA SA CQ B NC DQ9NC SA NC K BW0SA NC NC DQ8C NC NC NC V SS SA SA0SA1V SS NC DQ7NC D NC NC DQ10V SS V SS V SS V SS V SS NC NC NC E NC NC DQ11 V DDQ V SS V SS V SS V DDQ NC NC DQ6F NC DQ12NC V DDQ V DD V SS V DD V DDQ NC NC DQ5G NC NC DQ13 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC DQ4NC K NC NC DQ14V DDQ V DD V SS V DD V DDQ NC NC DQ3L NC DQ15NC V DDQ V SS V SS V SS V DDQ NC NC DQ2M NC NC NC V SS V SS V SS V SS V SS NC DQ1NC N NC NC DQ16 V SS SA SA SA V SS NC NC NC P NC NC DQ17SA SA C SA SA NC NC DQ0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ172.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/1678M x 9 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ SA SA R/W NC K NC LD SA SA CQ B NC NC NC SA NC K BW SA NC NC DQ4C NC NC NC V SS SA NC SA V SS NC NC NC D NC NC NC V SS V SS V SS V SS V SS NC NC NC E NC NC DQ5 V DDQ V SS V SS V SS V DDQ NC NC DQ3F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC NC DQ6 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC DQ2NC K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC DQ7NC V DDQ V SS V SS V SS V DDQ NC NC DQ1M NC NC NC V SS V SS V SS V SS V SS NC NC NC N NC NC NC V SS SA SA SA V SS NC NC NC P NC NC DQ8SA SA C SA SA NC NC DQ0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to0 at the beginning of each access.2.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/1678M x 8 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ SA SA R/W NW1K NC LD SA SA CQ B NC NC NC SA NC K NW0SA NC NC DQ3C NC NC NC V SS SA NC SA V SS NC NC NC D NC NC NC V SS V SS V SS V SS V SS NC NC NC E NC NC DQ4 V DDQ V SS V SS V SS V DDQ NC NC DQ2F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC NC DQ5 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC DQ1NC K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC DQ6NC V DDQ V SS V SS V SS V DDQ NC NC DQ0M NC NC NC V SS V SS V SS V SS V SS NC NC NC N NC NC NC V SS SA SA SA V SS NC NC NC P NC NC DQ7SA SA C SA SA NC NC NC RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to0 at the beginning of each access.2.NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ73.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/167Pin Description TableSymbolDescriptionTypeCommentsSA Synchronous Address InputsInput —NC No Connect ——R Synchronous Read Input Active High W Synchronous Write Input Active Low BW0–BW3Synchronous Byte Writes Input Active Low x18/x36 only NW0–NW1Nybble Write Control Pin Input Active Low x8 only LD Synchronous Load PinInput Active Low K Input Clock Input Active High K Input Clock Input Active Low C Output Clock Input Active High C Output Clock Input Active LowTMS Test Mode Select Input —TDI Test Data Input Input —TCK Test Clock Input Input —TDO Test Data Output Output —V REF HSTL Input Reference Voltage Input —ZQ Output Impedance Matching InputInput —MCL Must Connect Low——DQ Data I/O Input/Output Three State Doff Disable DLL when low Input Active LowCQ Output Echo Clock Output —CQ Output Echo Clock Output —V DD Power Supply Supply 1.8 V Nominal V DDQ Isolated Output Buffer Supply Supply 1.5 V NominalV SSPower Supply: GroundSupply—GS8662R08/09/18/36E-333/300/250/200/167Note:NC = Not Connected to die or any other pinGS8662R08/09/18/36E-333/300/250/200/167BackgroundCommon I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications. Therefore, the SigmaCIO DDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed Common I/O SRAM data bandwidth in half.Burst OperationsRead and write operations are “burst” operations. In every case where a read or write command is accepted by the SRAM, it will respond by issuing or accepting four beats of data, executing a data transfer on subsequent rising edges of K and K#, as illustrated in the timing diagrams. It is not possible to stop a burst once it starts. Four beats of data are always transferred. This means that it is possible to load new addresses every other K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are inserted.Deselect CyclesChip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the four beat read data transfer and then execute the deselect command, returning the output drivers to high-Z.A high on the LD# pin prevents the RAM from loading read or write commandinputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer operations.SigmaCIO DDR-II B4 SRAM Read CyclesThe status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst transfer inresponse to a read command, if the previous command captured was a read or write command, the Address, LD# and R/W# pins are ignored. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes pipelined reads. The read command is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM produces data out in response to the next rising edge of C# (or the next rising edge of K#, if C and C# are tied high). The second beat of data is transferred on the next rising edge of C, then on the next rising edge of C# and finally on the next rising edge of C, for a total of four transfers per address load.SigmaCIO DDR-II B4 SRAM Write CyclesThe status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst transfer in response to a write command, if the previous command captured was a read or write command, the Address, LD# and R/ W# pins are ignored at the next rising edge of K. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes “late write” data transfers. Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command and the write address. To complete the remaining three beats of the burst of four write transfer the SRAM captures data in on the next rising edge of K#, the following rising edge of K and finally on the next rising edge of K#, for a total of four transfers per address load.GS8662R08/09/18/36E-333/300/250/200/167Power-Up Sequence for SigmaQuad-II SRAMsSigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.Power-Up Sequence1. Power-up and maintain Doff at low state.1a.Apply V DD .1b. Apply V DDQ .1c. Apply V REF (may also be applied at the same time as V DDQ ).2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.Note:If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become stablized.DLL Constraints•The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t KCVar on page 20).•The DLL cannot operate at a frequency lower than 119 MHz.•If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage.Power-Up Sequence (Doff controlled)Power UP IntervalUnstable Clocking IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoffPower-Up Sequence (Doff tied High)Power UP IntervalUnstable Clocking IntervalStop Clock IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoff30ns MinNote:If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.GS8662R08/09/18/36E-333/300/250/200/167Special FunctionsByte Write and Nybble Write ControlByte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence.Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18 version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence.Nybble Write (4-bit) write control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NBx” may be substituted in all the discussion above.Example x18 RAM Write Sequence using Byte Write EnablesData In SampleTimeBW0BW1D0–D8D9–D17Beat 101Data In Don’t CareBeat 210Don’t Care Data InBeat 300Data In Data InBeat 410Don’t Care Data InResulting Write OperationByte 1 D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Written Unchanged Unchanged Written Written Written Unchanged Written Beat 1Beat 2Beat 3Beat 4Output Register ControlSigmaCIO DDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs isare tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM.A K R/W LDA 0–A nKBank 0Bank 1Bank 2Bank 3A KLD A K LD A K LD R/W R/W R/W DQDQDQ DQCC CCDQ 1–C R/WLD 0LD 1LD 2LD 3Note:For simplicity BWn (or NWn), K, and C are not shown.CQ CQ CQ CQ CQGS8662R08/09/18/36E-333/300/250/200/167Example Four Bank Depth Expansion SchematicGS8662R08/09/18/36E-333/300/250/200/167FLXDrive-II Output Driver Impedance ControlHSTL I/O SigmaCIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver isimplemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.Common I/O SigmaCIO DDR-II B4 SRAM Truth TableK nLDR/WDQOperationA + 0A + 1A + 2A + 3↑1X Hi-Z Hi-Z Hi-Z Hi-Z Deselect ↑00D@K n+1D@K n+1D@K n+2D@K n+2Write ↑1Q@K n+1or C n+1Q@K n+2or C n+2Q@K n+2or C n+2Q@K n+3or C n+3ReadNote:Q is controlled by K clocks if C clocks are not used.B4 Byte Write Clock Truth TableBW BW BW BW Current OperationD D D D K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)K ↑(t n )K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)TTTTWriteDx stored if BWn = 0 in all four data transfers D0D2D3D4T F F F WriteDx stored if BWn = 0 in 1st data transfer only D0X X XF T F F WriteDx stored if BWn = 0 in 2nd data transfer only X D1X XF F T F WriteDx stored if BWn = 0 in 3rd data transfer only X X D2XF F F T WriteDx stored if BWn = 0 in 4th data transfer only X X X D3F F F F Write AbortNo Dx stored in any of the four data transfersX X X XNotes:1.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.2.If one or more BWn = 0, then BW = “T”, else BW = “F”.GS8662R08/09/18/36E-333/300/250/200/167*Assuming stable conditions, the RAM can achieve optimum impedance within 1024 cycles.B4 Nybble Write Clock Truth TableNW NW NW NW Current OperationD D D D K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)K ↑(t n )K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)TTTTWriteDx stored if NWn = 0 in all four data transfers D0D2D3D4T F F F WriteDx stored if NWn = 0 in 1st data transfer only D0X X XF T F F WriteDx stored if NWn = 0 in 2nd data transfer only X D1X XF F T F WriteDx stored if NWn = 0 in 3rd data transfer only X X D2XF F F T WriteDx stored if NWn = 0 in 4th data transfer only X X X D3F F F F Write AbortNo Dx stored in any of the four data transfersX X X XNotes:1.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.2.If one or more NWn = 0, then NW = “T”, else NW = “F”.GS8662R08/09/18/36E-333/300/250/200/167x36 Byte Write Enable (BWn) Truth TableBW0BW1BW2BW3D0–D8D9–D17D18–D26D27–D351111Don’t Care Don’t Care Don’t Care Don’t Care 0111Data In Don’t Care Don’t Care Don’t Care 1011Don’t Care Data In Don’t Care Don’t Care 0011Data In Data In Don’t Care Don’t Care 1101Don’t Care Don’t Care Data In Don’t Care 0101Data In Don’t Care Data In Don’t Care 1001Don’t Care Data In Data In Don’t Care 0001Data In Data In Data In Don’t Care 1110Don’t Care Don’t Care Don’t Care Data In 0110Data In Don’t Care Don’t Care Data In 1010Don’t Care Data In Don’t Care Data In 0010Data In Data In Don’t Care Data In 1100Don’t Care Don’t Care Data In Data In 0100Data In Don’t Care Data In Data In 1000Don’t Care Data In Data In Data In 0Data InData InData InData Inx18 Byte Write Enable (BWn) Truth Table BW0BW1D0–D8D9–D1711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData Inx8 Nybble Write Enable (NWn) Truth Table NW0NW1D0–D3D4–D711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData InGS8662R08/09/18/36E-333/300/250/200/167GS8662R08/09/18/36E-333/300/250/200/167B4 State DiagramPower-UpNOPLoad New AddressDDR Read DDR WriteLOADREAD WRITE LOADLOADLOADLOADNotes:1.The internal burst address counter is a 4-bit linear counter (i.e., when first address is A0, next internal burst address is A0+1).2.“READ” refers to read active status with R/W = High, “WRITE” refers to write inactive status with R/W = Low.3.“LOAD” refers to read new address active status with LD = Low, “LOAD” refers to read new address inactive status with LD = High.LOAD Increment Read Address Increment Write AddressAlwaysAlwaysREADWRITEAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 2.9V V DDQ Voltage in V DDQ Pins –0.5 to V DD V V REF Voltage in V REF Pins –0.5 to V DDQV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V V IN Voltage on Other Input Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V I IN Input Current on Any Pin +/–100mA dc I OUT Output Current on Any I/O Pin +/–100mA dcT J Maximum Junction Temperature125o C T STGStorage Temperature–55 to 125oCNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.GS8662R08/09/18/36E-333/300/250/200/167Recommended Operating ConditionsPower SuppliesParameterSymbolMin.Typ.Max.UnitSupply Voltage V DD 1.7 1.8 1.9V I/O Supply Voltage V DDQ 1.7 1.8 1.9V Reference VoltageV REF0.68—0.95VNotes:1.Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ V DDQ ≤ 1.6 V (i.e., 1.5 V I/O)and 1.7 V ≤ V DDQ ≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.2.The power supplies need to be powered up simultaneously or in the following sequence: V DD , V DDQ , V REF , followed by signal inputs. Thepower down sequence must be the reverse. V DDQ must not exceed V DD ..Operating TemperatureParameterSymbolMin.Typ.Max.UnitAmbient Temperature (Commercial Range Versions)T A 02570°C Ambient Temperature (Industrial Range Versions)T A–402585°CGS8662R08/09/18/36E-333/300/250/200/167HSTL I/O DC Input CharacteristicsParameterSymbolMinMaxUnitsNotesDC Input Logic High V IH (dc)V REF + 0.10V DD + 0.3 V V 1DC Input Logic LowV IL (dc)–0.3 VV REF – 0.10V1Notes:patible with both 1.8 V and 1.5 V I/O drivers2.These are DC test criteria. DC design criteria is V REF ± 50 mV. The AC V IH /V IL levels are defined separately for measuring timing parame-ters.3.V IL (Min) DC = –0.3 V, V IL (Min) AC = –1.5 V (pulse width ≤ 3 ns).4.V IH (Max) DC = V DDQ + 0.3 V, V IH (Max) AC = V DDQ + 0.85 V (pulse width ≤ 3 ns).HSTL I/O AC Input CharacteristicsParameterSymbolMinMaxUnitsNotesAC Input Logic High V IH (ac)V REF + 0.20—V 3,4AC Input Logic LowV IL (ac)—V REF – 0.20V 3,4V REF Peak to Peak AC VoltageV REF (ac)—5% V REF (DC)V1Notes:1.The peak to peak AC component superimposed on V REF may not exceed 5% of the DC component of V REF .2.To guarantee AC characteristics, V IH ,V IL , Trise, and Tfall of inputs and clocks must be within 10% of each other.3.For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.20% tKHKHV SS – 1.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKHKHV DD + 1.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DDParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Output Capacitance C OUT V OUT = 0 V67pF Clock CapacitanceC CLK—56pFNote:This parameter is sample tested.GS8662R08/09/18/36E-333/300/250/200/167AC Test ConditionsParameterConditionsInput high level V DDQ Input low level 0 V Max. input slew rate 2 V/ns Input reference level V DDQ /2Output reference levelV DDQ /2Note:Test conditions as specified with output loading as shown unless otherwise noted.DQVT = V DDQ /250ΩRQ = 250 Ω (HSTL I/O)V REF = 0.75 VAC Test Load DiagramInput and Output Leakage CharacteristicsParameterSymbolTest ConditionsMin.MaxNotesInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –2 uA 2 uA DoffI INDOFF V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL –100 uA –2 uA 2 uA 2 uA Output Leakage CurrentI OLOutput Disable,V OUT = 0 to V DDQ–2 uA2 uA(T A = 25= 3.3 V)GS8662R08/09/18/36E-333/300/250/200/167Programmable Impedance HSTL Output Driver DC Electrical CharacteristicsParameterSymbolMin.Max.UnitsNotesOutput High Voltage V OH1 V DDQ /2V DDQ V 1, 3Output Low Voltage V OL1 Vss V DDQ /2V 2, 3Output High Voltage V OH2 V DDQ – 0.2V DDQ V 4, 5Output Low VoltageV OL2Vss0.2V4, 6Notes:1. I OH = (V DDQ /2) / (RQ/5) +/– 15% @ V OH = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).2. I OL = (V DDQ /2) / (RQ/5) +/– 15% @ V OL = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).3.Parameter tested with RQ = 250Ω and V DDQ = 1.5 V or 1.8 V4.Minimum Impedance mode, ZQ = V SS5.I OH = –1.0 mA6.I OL = 1.0 mAOperating CurrentsParameterSymbolTest Conditions-333-300-250-200-167Notes0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C Operating Current (x36):DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBDTBDTBDTBDTBDTBDTBDTBDTBDTBD2, 3Operating Current (x18):DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x9):DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x8):DDR I DDV DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Standby Current (NOP):DDRI SB1Device deselected,I OUT = 0 mA, f = Max,All Inputs ≤ 0.2 V or ≥ V DD – 0.2 VTBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 4Notes:1.Power measured with output pins floating.2.Minimum cycle, I OUT = 0 mA3.Operating current is calculated with 50% read cycles and 50% write cycles.4.Standby Current is only after all pending read and write burst operations are completed.GS8662R08/09/18/36E-333/300/250/200/167AC Electrical CharacteristicsParameterSymbol-333-300-250-200-167UnitsN o t e sMin Max Min Max Min Max Min Max Min MaxClockK, K Clock Cycle Time C, C Clock Cycle Time t KHKH t CHCH 3.0 3.5 3.3 4.2 4.0 6.3 5.07.88 6.08.4ns tTKC Variablet KCVar —0.2—0.2—0.2—0.2—0.2ns 5K, K Clock High Pulse Width C, C Clock High Pulse Width t KHKL t CHCL 1.2— 1.32— 1.6— 2.0— 2.4—ns K, K Clock Low Pulse Width C, C Clock Low Pulse Width t KLKH t CLCH 1.2— 1.32— 1.6— 2.0— 2.4—ns K to K High C to C Hight KHKH 1.35— 1.49— 1.8— 2.2— 2.7—ns K, K Clock High to C, C Clock High t KHCH 0 1.30 1.450 1.80 2.30 2.8ns DLL Lock Time t KCLock 1024—1024—1024—1024—1024—cycle 6K Static to DLL resett KCReset 30—30—30—30—30—nsOutput TimesK, K Clock High to Data Output Valid C, C Clock High to Data Output Valid t KHQV t CHQV —0.45—0.45—0.45—0.45—0.5ns 3K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold t KHQX t CHQX –0.45—–0.45—–0.45—–0.45—–0.5—ns 3K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid t KHCQV t CHCQV —0.45—0.45—0.45—0.45—0.5ns K, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold t KHCQX t CHCQX –0.45—–0.45—–0.45—–0.45—–0.5—ns CQ, CQ High Output Valid t CQHQV —0.25—0.27—0.30—0.35—0.40ns 7CQ, CQ High Output Hold t CQHQX –0.25—–0.27—–0.30—–0.35—–0.40—ns 7K Clock High to Data Output High-Z C Clock High to Data Output High-Z t KHQZ t CHQZ —0.45—0.45—0.45—0.45—0.5ns 3K Clock High to Data Output Low-Z C Clock High to Data Output Low-Zt KHQX1t CHQX1–0.45—–0.45—–0.45—–0.45—–0.5—ns3Setup TimesAddress Input Setup Time t AVKH 0.4—0.4—0.5—0.6—0.7—ns Control Input Setup Time t IVKH 0.4—0.4—0.5—0.6—0.7—ns 2Data Input Setup Timet DVKH0.28—0.3—0.35—0.4—0.5—ns。

GS88236BB-333I资料

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GS88218/36BB/D-333/300/250/200/150
165 Bump BGA—x18 Commom I/O—Top View (Package D)
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GS88218/36BB/D-333/300/250/200/150
119- and 165-Bump BGA Commercial Temp Industrial Temp
512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by

GS881E36T-11I中文资料

GS881E18/36T-11/11.5/100/80/66512K x 18, 256K x 36 ByteSafe™8Mb Sync Burst SRAMs100 MHz–66 MHz3.3 V V DD 3.3 V and 2.5 V I/O100-Pin TQFP Commercial TempIndustrial Temp1.10 9/2000Featuresoperation• Dual Cycle Deselect (DCD) operation• IEEE 1149.1 JTAG-compatible Boundary Scan• On-chip write parity checking; even or odd selectable• 3.3 V +10%/–5% core power supply• 2.5 V or 3.3 V I/O supply• Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode• Common data inputs and data outputs• Clock Control, registered, address, data, and control• Internal self-timed write cycle• Automatic power-down for portable applications• 100-lead TQFP packageFunctional DescriptionApplicationsThe GS881E18//36T is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controlsand power down control (ZZ) are asynchronous inputs. Burst Burst mode, subsequent burst addresses are generated counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.DCD Pipelined ReadsThe GS881E18//36T is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write control inputs.ByteSafe™ Parity FunctionsThe GS881E18/36T features ByteSafe data security functions. See detailed discussion following.Sleep ModeLow power (Sleep mode) is attained through the assertion (high) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS881E18//36T operates on a 3.3 V power supply, and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (V DDQ) pins are used to decouple output noise from the internal circuit.-11-11.5-100-80-663-1-1-1t KQI DD4.0 ns225 mA4.0 ns225 mA4.0 ns225 mA4.5 ns200 mA5.0 ns185 mAThrough 2-1-1-1KQtCycleI DD15 ns180 mA15 ns180 mA15 ns180 mA15 ns175 mA20 ns165 mAGS881E18/36T-11/11.5/100/80/66GS881E18 100-Pin TQFP Pinout807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B1DQ B2V SS V DDQ DQ B3DQ B4FT V DD DP V SS DQ B5DQ B6V DDQ V SS DQ B7DQ B8DQ B9V SS V DDQ V DDQ V SS DQ A8DQ A7V SS V DDQ DQ A6DQ A5V SS QE V DD ZZ DQ A4DQ A3V DDQ V SS DQ A2DQ A1V SS V DDQ L B O A 5A 4A 3A 2A 1A 0T M S T D I V S SV D DT D O T C K A 10A 11A 12A 13A 14A 16A 6A 7E 1E 2 N C N C B BB AA 17C K G W B W VD DV S SG A D S C A D S P A D V A 8A 9A 15512K X 18Top ViewDQ A9A 18NC NC NC NC NC NC NC NCNC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881E18/36T-11/11.5/100/80/66GS881E36 100-Pin TQFP Pinout807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C4DQ C3V SS V DDQ DQ C2DQ C1FT V DD DP V SS DQ D1DQ D2V DDQ V SS DQ D3DQ D4DQ D5V SS V DDQ V DDQ V SS DQ B4DQ B3V SS V DDQ DQ B2DQ B1V SS QE V DD ZZ DQ A1DQ A2V DDQ V SS DQ A3DQ A4V SS V DDQ L B O A 5A 4A 3A 2A 1A 0T M S T D I V S ST D O T C K A 10A 11A 12A 13A 14A 16A 6A 7E 1E 2 B DB CB BB AA 17C K G W B W VD DV S SG A D S C A D S P A D V A 8A 9A 15256K x 36Top ViewDQ B5DQ B9DQ B7DQ B8DQ B6DQ A6DQ A5DQ A8DQ A7DQ A9DQ C7DQ C8DQ C6DQ D6DQ D8DQ D7DQ D9DQ C5DQ C9100999897969594939291908988878685848382813132333435363738394041424344454647484950V D DGS881E18/36T-11/11.5/100/80/66 TQFP Pin DescriptioPin Location Symbol TypeDescription37, 36A0, A1I Address field LSBs and Address Counter preset Inputs 35, 34, 33, 32, 100, 99, 82, 81, 44, 45,46, 47, 48, 49, 50, 92A2–A17I Address Inputs80A18I Address Inputs63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 13, 12, 9, 8, 7, 6, 3, 2 18, 19, 22, 23, 24, 25, 28, 29DQ A1–DQ A8DQ B1–DQ B8DQ C1–DQ C8DQ D1–DQ D8I/O Data Input and Output pins ( x36 Version)51, 80, 1, 30DQ A9, DQ B9,DQ C9, DQ D9I/O Data Input and Output pins58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24DQ A1–DQ A9DQ B1–DQ B9I/O Data Input and Output pins51, 52, 53, 56, 5775, 78, 79,1, 2, 3, 6, 725, 28, 29, 30NC—No Connect16DP I Parity Input; 1 = Even, 0 = Odd66QE O Parity Error Out; Open Drain Output87BW I Byte Write—Writes all enabled bytes; active low93, 94B A, B B I Byte Write Enable for DQ A, DQ B Data I/Os; active low95, 96B C, B D I Byte Write Enable for DQ C, DQ D Data I/Os; active low ( x36 Version) 95, 96NC—No Connect (x18 Version)89CK I Clock Input Signal; active high88GW I Global Write Enable—Writes all bytes; active low98E1I Chip Enable; active low97E2I Chip Enable; active high86G I Output Enable; active low83ADV I Burst address counter advance enable; active low84, 85ADSP, ADSC I Address Strobe (Processor, Cache Controller); active lowGS881E18/36T-11/11.5/100/80/6664ZZ I Sleep mode control; active high 14FT I Flow Through or Pipeline mode; active low 31LBO I Linear Burst Order mode; active low38TMS I Scan Test Mode Select 39TDI I Scan Test Data In 42TDO O Scan Test Data Out 43TCK I Scan Test Clock 15, 41, 65, 91V DD I Core power supply 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90V SS I I/O and Core Ground 4, 11, 20, 27, 54, 61, 70, 77V DDQIOutput driver power supplyPin LocationSymbolTyp eDescriptionGS881E18/36T-11/11.5/100/80/66GS881E18/36 Block DiagramA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterD QR e g i s t e rDQ RegisterA0–An LBO ADV CK ADSC ADSP GW BW B AB BB CB DFT GZZPower Down ControlMemory Array36364AQD DQx0–DQx9DPParity QEParity EncodeCompare3643636432Note: Only x36 version shown for simplicity.3636DQR e g i s t e r 4E 1E 2GS881E18/36T-11/11.5/100/80/66ByteSafe ™ Parity FunctionsThis SRAM includes a write data parity check that checks the validity of data coming into the RAM on write cycles. In Flow Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are reported one clock cycle later. (See Write Parity Error Output Timing Diagram .) The Data Parity Mode (DP) pin must be tied high to set the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the RAM as data. Validity is best established at the data’s destination. The Parity Error Output is an open drain output and drives low to indicate a parity error. Multiple Parity Error Output pins may share a common pull-up resistor.Write Parity Error Output Timing DiagramBPR 1999.05.18CK D In AD In BD In C D In D D In EtKQ tLZDQQEF l o w T h r o u g h M o d eP i p e l i n e d M o d etKQ tLZDQQED In A D In BD In CD In D D In EErr AErr AErr CErr CtHZ tKQX tHZ tKQXGS881E18/36T-11/11.5/100/80/66Note:There are pull-up devices on the LBO, DP and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table.Burst Counter SequencesBPR 1999.05.18Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H or NC Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, I DD = I SB ByteSafe Data Parity ControlDPL Check for Odd Parity H or NCCheck for Even ParityLinear Burst SequenceNote: The burst counter wraps to initial state on the 5th clock.I nterleaved Burst SequenceNote: The burst counter wraps to initial state on the 5th clock.A[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110A[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100GS881E18/36T-11/11.5/100/80/66Byte Write Truth TableNotes:1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C, and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.FunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytes H L L L L L 2, 3, 4Write all bytesLXXXXXGS881E18/36T-11/11.5/100/80/66 Synchronous Truth TableOperation AddressUsedStateDiagramKey5E1E22(x36only)ADSP ADSC ADV W3DQ4Deselect Cycle, Power Down None X H X X L X X High-Z Deselect Cycle, Power Down None X L F L X X X High-Z Deselect Cycle, Power Down None X L F H L X X High-Z Read Cycle, Begin Burst External R L T L X X X Q Read Cycle, Begin Burst External R L T H L X F Q Write Cycle, Begin Burst External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend Burst Current H X X H H T D Notes:1.X = Don’t Care, H = High, L = Low.2.For x36 Version, E = T (True) if E2 = 1; E = F (False) if E2 = 0.3.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.4.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).5.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.6.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.7.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS881E18/36T-11/11.5/100/80/66First WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWX XWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRSimplified State DiagramNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1 and E2) and Write (B A , B B , B C , B D , BW, and GW) controlinputs, and that ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, andassumes ADSP is tied high and ADV is tied low.GS881E18/36T-11/11.5/100/80/66First WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWSimplified State Diagram with GNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS881E18/36T-11/11.5/100/80/66Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.Notes:1.Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both2.75 V ≤ V DDQ ≤ 2.375 V(i.e., 2.5 V I/O) and 3.6 V ≤ V DDQ ≤ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case. 2.This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.3.Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number ofIndustrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.4.Input Under/overshoot voltage must be –2 V > Vi < V DD +2 V with a pulse width not to exceed 20% tKC.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage in V DDQ Pins –0.5 to V DD V V CK Voltage on Clock Input Pin –0.5 to 6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125o CRecommended Operating ConditionsParameterSymbolMin.Typ.Max.UnitNotesSupply Voltage V DD 3.135 3.3 3.6V I/O Supply Voltage V DDQ 2.375 2.5V DD V 1Input High Voltage V IH 1.7—V DD +0.3V 2Input Low VoltageV IL –0.3—0.8V 2Ambient Temperature (Commercial Range Versions)T A 02570°C 3Ambient Temperature (Industrial Range Versions)T A–402585°C3GS881E18/36T-11/11.5/100/80/66Note: These parameters are sample tested.Notes:1.Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-ature air flow, board density, and PCB thermal resistance.2.SCMI G-38-873.Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1Capacitance(T A = 25o C, f = 1 MH Z , V DD = 3.3 V)ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output CapacitanceC I/OV OUT = 0 V67pFPackage Thermal CharacteristicsRatingLayer BoardSymbolMaxUnitNotesJunction to Ambient (at 200 lfm)single R ΘJA 40°C/W 1,2Junction to Ambient (at 200 lfm)four R ΘJA 24°C/W 1,2Junction to Case (TOP)—R ΘJC9°C/W320% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILGS881E18/36T-11/11.5/100/80/66Notes:1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.3.Output Load 2 for t LZ , t HZ , t OLZ and t OHZ4.Device is deselected as defined by the Truth Table.AC Test ConditionsParameterConditionsInput high level 2.3 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level 1.25 V Output reference level1.25 V Output loadFig. 1& 2DC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA ZZ Input Current I INZZ V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH –1 uA –1 uA 1 uA 300 uA Mode Pin Input Current I INM V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL –300 uA –1 uA 1 uA 1 uA Output Leakage Current I OL Output Disable,V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH I OH = –8 mA, V DDQ = 2.375 V 1.7 V —Output High Voltage V OH I OH = –8 mA, V DDQ = 3.135 V2.4 V —Output Low VoltageV OLI OL = 8 mA—0.4 VDQVT = 1.25 V50Ω30pF *DQ2.5 VOutput Load 1Output Load 2225Ω225Ω5pF ** Distributed Test Jig CapacitanceGS881E18/36T-11/11.5/100/80/66 Operating CurrentsParameter Test Conditions Symbol-11-11.5-100-80-66Unit 0to70°C–40to85°Cto70°C–40to85°Cto70°C–40to85°Cto70°C–40to85°Cto70°C–40to85°COperating Current Device Selected;All other inputs≥V IH o r ≤ V ILOutput openI DDPipeline225235225235225235200210185195mAI DDFlow-Thru180 190 180 190 180190175185165175mAStandbyCurrent ZZ≥ V DD- 0.2VI SBPipeline30 40 30 40 304030403040mAI SBFlow-Thru30 40 30 40304030403040mADeselect Current Device Deselected;All other inputs≥ V IH or≤ V ILI DDPipeline80 90 80 90809070806070mAI DDFlow-Thru65 75 65 75657555655060mAGS881E18/36T-11/11.5/100/80/66AC Electrical CharacteristicsNotes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.Parameter Symbol -11-11.5-100-80-66Unit Min Max MinMax MinMax Min Max Min Max PipelineClock Cycle TimetKC 10—10—10—12.5—15—ns Clock to Output Valid tKQ — 4.0— 4.0— 4.0— 4.5—5ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-Z tLZ 1 1.5— 1.5— 1.5— 1.5— 1.5—ns Flow-ThruClock Cycle TimetKC 15.0—15.0—15.0—15.0—20—ns Clock to Output Valid tKQ —11.0—11.5—12.0—14.0—18ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-Z tLZ 1 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock HIGH Time tKH 1.7— 1.7—2—2— 2.3—ns Clock LOW Time tKL 2—2— 2.2— 2.2— 2.5—ns Clock to Output in High-Z tHZ 1 1.5 4.0 1.5 4.2 1.5 4.5 1.5 4.5 1.5 4.8ns G to Output Valid tOE — 4.0— 4.2— 4.5— 4.5— 4.8ns G to output in Low-Z tOLZ 10—0—0—0—0—ns G to output in High-ZtOHZ 1— 4.0— 4.2— 4.5— 4.5— 4.8ns Setup time tS 1.5— 2.0— 2.0— 2.0— 2.0—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—ns ZZ setup time tZZS 25—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—nsGS881E18/36T-11/11.5/100/80/66CKADSPADSCADVGWBWWR2WR3WR1WR1WR2WR3tKCSingle WriteBurst Write t KLt KH tS tHtS tHtS tHtS tHtS tHtStHtS tHWrite specified byte for 2A and all bytes for 2B , 2C & 2DADV must be inactive for ADSP WriteADSC initiated writeADSP is blocked by E inactiveA 0–A nB A –B DDQ A –DQ DWrite DeselectedWR1WR3Write Cycle TimingE 1tS tHE 2 only sampled with ADSP or ADSCE 1 masks ADSPDeselected with E 2GtS tHD2AD2BD2CD2DD3AD1AHi-ZtS tHE 2GS881E18/36T-11/11.5/100/80/66Q1AQ3AQ2DQ2cQ2BQ2AtKQtLZtOEtOHZtOLZtKQXtHZtKQXCKADSP ADSCBW GGWADVBurst ReadRD2RD3tKLtStHtHtS tHtS tHADSC initiated readSuspend Burst Single ReadADSP is blocked by E inactiveA 0–A nB A –B DtKHtKCtS tHtS tStHDQ A –DQ DRD1Hi-ZSuspend BurstFlow Through Read Cycle TimingtHtHE 1 masks ADSPDeselected with E 2E 1tS tS E 2E 2 only sampled with ADSP or ADSCGS881E18/36T-11/11.5/100/80/66Flow Through Read-Write Cycle TimingCKADSPADVGWBWGQ1AD1AQ2AQ2BQ2cQ2DSingle ReadBurst ReadtOEtOHZtS tHtStHtHtS tHtS tHtKH DQ A –DQ DB A –B DtKLtKCtS Single WriteADSP is blocked by E inactivetKQtStHHi-ZQ2ABurst wrap around to it’s initial stateWR1E 1tS tS tHE 1 masks ADSPE 2 only sampled with ADSP and ADSCtHADSCtS tHADSC initiated readRD1WR1RD2tS tHA 0–A nE 2GS881E18/36T-11/11.5/100/80/66Pipelined DCD Read Cycle TimingQ1AQ3AQ2DQ2cQ2BQ2AtKQtLZtOEtOHZtOLZtKQX tHZtKQX CKADSP ADSCBW GGWADVBurst ReadRD2RD3tKLtHtHtStHtHtS tHtS tHADSC initiated readSuspend BurstE 1 masks ADSPE 2 only sampled with ADSP or ADSCSingle ReadADSP is blocked by E 1 inactiveA 0–A nB A –B DE 1tKH tKCtS tHtS tStHDQ A –DQ DtS tS RD1Hi-ZE 2GS881E18/36T-11/11.5/100/80/66Pipelined DCD Read-Write Cycle TimingCKADSPADVGWBW E 1GWR1Q1AD1aQ2A Q2B Q2c Q2DSingle ReadBurst ReadtOEtOHZtS tStHtStH tStHtHtS tHtS tHtKHE 1 masks ADSPE 2 only sampled with ADSP and ADSCDQ A –DQ DtKLtKC tS tHSingle WriteADSP is blocked by E 1 inactivetKQtS tHHi-ZB A –B DADSCtS tHADSC initiated readRD1WR1RD2tS tHA 0–A nE 2GS881E18/36T-11/11.5/100/80/66Application TipsSingle and Dual Cycle DeselectSCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the outputdrivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.JTAG Port OperationOverviewThe JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Some functions have been modified or eliminated because they can slow the RAM. Nevertheless, the RAM supports 1149.1-1990 TAP (Test Access Port) Controller architecture, and can be expected to function in a manner that does not conflict with the operation of Standard 1149.1 compliant devices. The JTAG Port interfaces with conventional TTL / CMOS logic level signaling.Disabling the JTAG PortIt is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unlessclocked. TCK, TDI, and TMS are designed with internal pull-up circuits. To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V DD or V SS . TDO should be left unconnected.CKADSP ADSCtHtKH tKLtKCtS ZZtZZRtZZHtZZS~~~~~~~~~SnoozeSleep Mode Timing DiagramGS881E18/36T-11/11.5/100/80/66JTAG Port RegistersOverviewThe various JTAG registers, refered to as TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on the next falling edge of TCK. When a register is selected it is placed between the TDI and TDO pins.Instruction RegisterThe Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.Bypass RegisterThe Bypass Register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs JTAG Port to another device in the scan chain with as little delay as possible.Boundary Scan RegisterBoundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. TheBoundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. Two TAP instructions can be used to activate the Boundary Scan Register.JTAG Pin Descriptions PinPin NameI/ODescriptionTCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.TMSTest Mode SelectInThe TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level.TDI Test Data In InThe TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.TDO Test Data Out OutOutput that is active depending on the state of the TAP state machine. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.Note:This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.。

GS881E32BD-200资料

GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)512K x 18, 256K x 32, 256K x 369Mb Sync Burst SRAMs250 MHz –150 MHz 2.5 V or 3.3 V V DD 2.5 V or 3.3 V I/O100-Pin TQFP & 165-bump BGA Commercial Temp Industrial Temp Features• FT pin for user-configurable flow through or pipeline operation• Dual Cycle Deselect (DCD) operation• IEEE 1149.1 JTAG-compatible Boundary Scan • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode• Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications• JEDEC-standard 100-lead TQFP and 165-bump BGA packages• Pb-Free 100-lead TQFP and 165-bump BGA packages availableFunctional DescriptionApplicationsThe GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D) is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.ControlsAddresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may beconfigured to count in either linear or interleave order with theLinear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.DCD Pipelined ReadsThe GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D) is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.Sleep ModeLow power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D) operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.Paramter Synopsis-333-300-250-200-150UnitPipeline 3-1-1-1KQ tCycle 3.0 3.3 4.0 5.0 6.7ns Curr (x18)Curr (x32/x36)250290230265200230170195140160mA mA Flow Through 2-1-1-1t KQ tCycle 4.54.5 5.05.0 5.55.5 6.56.57.57.5ns ns Curr (x18)Curr (x32/x36)200230185210160185140160128145mA mAGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)GS881E18B 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B FT V DD NC V SS DQ B DQ B V DDQ V SS DQ B DQ B DQP BV SS V DDQ V DDQ V SS DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A AA 1A 0T M S T D I V S SV D DT D O T C K A A A A A AA A E 1E 2N C N C B BB AA C K G WB W V D DV S SG A D S C A D S P A D V A AA 512K x 18Top View DQP A A NC NC NC NC NC NC NC NCNC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)GS881E32B 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C FT V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A 2A A 0V S SV D DA A A A A AA A E 1E 2B DB CB BB AA C K G WB W V D DV S SG A D S C A D S P A D V A AA 256K x 32Top View DQB NC DQ B DQ B DQ B DQ A DQ A DQ A DQ A NCDQ C DQ C DQ C DQ D DQ D DQ D NCDQ C NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950T M S T D I T D O T C KGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)GS881E36B 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C FT V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A 2A A 0V S SV D DA A A A A AA A E 1E 2B DB CB BB AA C K G WB W V D DV S SG A D S C A D S P A D V A AA 256K x 36Top View DQB DQP B DQ B DQ B DQ B DQ A DQ A DQ A DQ A DQP ADQ C DQ C DQ C DQ D DQ D DQ D DQP DDQ C DQP C 100999897969594939291908988878685848382813132333435363738394041424344454647484950T M S T D I T D O T C KGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)TQFP Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter preset InputsA I Address InputsDQ ADQ BI/O Data Input and Output pinsDQ CDQ DNC—No ConnectBW I Byte Write—Writes all enabled bytes; active lowB A, B B, B C, B D I Byte Write Enable for DQ Data I/Os; active lowNC—No ConnectCK I Clock Input Signal; active highGW I Global Write Enable—Writes all bytes; active lowE2I Chip Enable; active highE1I Chip Enable; active lowG I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active highLBO I Linear Burst Order mode; active lowV DD I Core power supplyV SS I I/O and Core GroundV DDQ I Output driver power supplyGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D) 165 Bump BGA—x18 Commom I/O—Top View (Package D)1234567891011A NC A E1BB NC E3BW ADSC ADV A A AB NC A E2NC BA CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQA CD NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA DE NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA EF NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA FG NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA GH FT MCL NC V DD V SS V SS V SS V DD NC NC ZZ HJ DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC JK DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC KL DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC LM DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC MN DQB NC V DDQ V SS NC NC NC V SS V DDQ NC NC NP NC NC A A TDI A1TDO A A A A PR LBO NC A A TMS A0TCK A A A A R11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump PitchGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D) 165 Bump BGA—x32 Common I/O—Top View (Package D)1234567891011A NC A E1BC BB E3BW ADSC ADV A NC AB NC A E2BD BA CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC NC CD DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB DE DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB EF DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB FG DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB GH FT MCL NC V DD V SS V SS V SS V DD NC NC ZZ HJ DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA JK DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA KL DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA LM DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA MN NC NC V DDQ V SS NC NC NC V SS V DDQ NC NC NP NC NC A A TDI A1TDO A A A A PR LBO NC A A TMS A0TCK A A A A R11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump PitchGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D) 165 Bump BGA—x36 Common I/O—Top View (Package D)1234567891011A NC A E1BC BB E3BW ADSC ADV A NC AB NC A E2BD BA CK GW G ADSP A NC BC DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB CD DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB DE DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB EF DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB FG DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB GH FT MCL NC V DD V SS V SS V SS V DD NC NC ZZ HJ DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA JK DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA KL DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA LM DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA MN DQPD NC V DDQ V SS NC NC NC V SS V DDQ NC DQPA NP NC NC A A TDI A1TDO A A A A PR LBO NC A A TMS A0TCK A A A A R11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump PitchGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)GS881E18/32/36BD 165-Bump BGA Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter Preset InputsA I Address InputsDQ ADQ BI/O Data Input and Output pinsDQ CDQ DB A, B B, B C, B D I Byte Write Enable for DQ A, DQ B, DQ C, DQ D I/Os; active lowNC—No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active lowGW I Global Write Enable—Writes all bytes; active lowE1I Chip Enable; active lowE3I Chip Enable; active lowE2I Chip Enable; active highG I Output Enable; active lowADV I Burst address counter advance enable; active l0w ADSC, ADSP I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep mode control; active highFT I Flow Through or Pipeline mode; active lowLBO I Linear Burst Order mode; active lowTMS I Scan Test Mode SelectTDI I Scan Test Data InTDO O Scan Test Data OutTCK I Scan Test ClockMCL—Must Connect LowV DD I Core power supplyV SS I I/O and Core GroundV DDQ I Output driver power supplyGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)GS881E18/32/36B Block DiagramA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–AnLBO ADV CK ADSC ADSP GW BW E 1GZZPower Down ControlMemory Array36364AQDE 2E 3DQx1–DQx9Note: Only x36 version shown for simplicity.1B AB BB CB DFTGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)Note:There is a pull-up device onthe FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables.Burst Counter SequencesBPR 1999.05.18Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, I DD = I SB FLXDrive Output Impedance ControlZQL High Drive (Low Impedance)H or NCLow Drive (High Impedance)Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.Byte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytesHLLLLL2, 3, 4Write all bytes L X X X X XGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)Synchronous Truth TableOperation AddressUsedStateDiagramKey5E1E2ADSP ADSC ADV W3DQ4Deselect Cycle, Power Down None X H X X L X X High-Z Deselect Cycle, Power Down None X L F L X X X High-Z Deselect Cycle, Power Down None X L F H L X X High-Z Read Cycle, Begin Burst External R L T L X X X Q Read Cycle, Begin Burst External R L T H L X F Q Write Cycle, Begin Burst External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend Burst Current H X X H H T D1.X = Don’t Care, H = High, L = Low2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 13.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.4.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).5.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.6.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.7.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWX XWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, andassumes ADSP is tied high and ADV is tied low.GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)Simplified State Diagram with GFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage in V DDQ Pins –0.5 to 4.6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCPower Supply Voltage RangesParameterSymbolMin.Typ.Max.UnitNotes3.3 V Supply Voltage V DD3 3.0 3.3 3.6V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 3.3 V V DDQ I/O Supply Voltage V DDQ3 3.0 3.3 3.6V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.52.7VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)V DDQ3 Range Logic LevelsParameter Symbol Min.Typ.Max.Unit Notes V DD Input High Voltage V IH 2.0—V DD + 0.3V1V DD Input Low Voltage V IL–0.3—0.8V1V DDQ I/O Input High Voltage V IHQ 2.0—V DDQ + 0.3V1,3V DDQ I/O Input Low Voltage V ILQ–0.3—0.8V1,3 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.V DDQ2 Range Logic LevelsParameter Symbol Min.Typ.Max.Unit Notes V DD Input High Voltage V IH0.6*V DD—V DD + 0.3V1V DD Input Low Voltage V IL–0.3—0.3*V DD V1V DDQ I/O Input High Voltage V IHQ0.6*V DD—V DDQ + 0.3V1,3V DDQ I/O Input Low Voltage V ILQ–0.3—0.3*V DD V1,3 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.Recommended Operating TemperaturesParameter Symbol Min.Typ.Max.Unit Notes Ambient Temperature (Commercial Range Versions)T A02570°C2 Ambient Temperature (Industrial Range Versions)T A–402585°C2 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)Note:These parameters are sample tested.Capacitance(T A = 25o C, f = 1 MH Z , V DD = 2.5 V)ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFAC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 1Notes:1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. 50% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing50% tKCV DD + 2.0 V50%V DDV ILDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)DC Electrical CharacteristicsParameter Symbol Test Conditions Min Max Input Leakage Current(except mode pins)I IL V IN = 0 to V DD–1 uA 1 uAZZ Input Current I IN1V DD≥V IN ≥V IH0 V≤ V IN ≤ V IH–1 uA–1 uA1 uA100 uAFT, SCD, ZQ Input Current I IN2V DD≥V IN ≥V IL0 V≤ V IN ≤ V IL–100 uA–1 uA1 uA1 uAOutput Leakage Current I OL Output Disable, V OUT = 0 to V DD–1 uA 1 uA Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V 1.7 V—Output High Voltage V OH3I OH = –8 mA, V DDQ = 3.135 V 2.4 V—Output Low Voltage V OL I OL = 8 mA—0.4 VGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)Notes:1.I DD and I DDQ apply to any combination of V DD3, V DD2, V DDQ3, and V DDQ2 operation.2.All parameters listed are worst case scenario.Operating CurrentsParameterTest ConditionsModeSymbol-333-300-250-200-150Unit0to 70°C–40 to 85°C0to 70°C–40 to 85°C0to 70°C–40 to 85°C0to 70°C–40to 85°C0 to 70°C–40to 85°COperating CurrentDevice Selected; All other inputs ≥V IH o r ≤ V IL Output open(x32/x36)Pipeline I DD I DDQ 25040270402303525035200302203017025190251402016020mA Flow Through I DD I DDQ 20525225251852520525160251802514020160201301515015mA (x18)PipelineI DD I DDQ 23020250202102023020185152051515515175151301015010mA Flow Through I DD I DDQ 185152051517015190151451516515130101501012081408mA Standby CurrentZZ ≥ V DD – 0.2 V —PipelineI SB 40504050405040504050mA Flow Through I SB 40504050405040504050mA Deselect CurrentDevice Deselected; All other inputs ≥ V IH or ≤ V IL—PipelineI DD 951009095859075806065mA Flow ThroughI DD65606065606550555055mAGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)Notes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.AC Electrical CharacteristicsParameterSymbol-333-300-250-200-150UnitMinMax Min Max Min Max Min Max Min Max PipelineClock Cycle Time tKC 3.0— 3.3— 4.0— 5.0— 6.7—ns Clock to Output Valid tKQ — 2.5— 2.5— 2.5— 3.0— 3.8ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5— 1.5— 1.5—ns Setup time tS 1.0— 1.0— 1.2— 1.4— 1.5—ns Hold time tH 0.1—0.1—0.2—0.4—0.5—ns Flow ThroughClock Cycle Time tKC 4.5— 5.0— 5.5— 6.5—7.5—ns Clock to Output Valid tKQ — 4.5— 5.0— 5.5— 6.5—7.5ns Clock to Output Invalid tKQX 2.0— 2.0— 2.0— 2.0— 2.0—ns Clock to Output in Low-ZtLZ 1 2.0— 2.0— 2.0— 2.0— 2.0—ns Setup time tS 1.3— 1.4— 1.5— 1.5— 1.5—ns Hold time tH 0.3—0.4—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.0— 1.0— 1.3— 1.3— 1.5—ns Clock LOW Time tKL 1.2—1.2—1.5—1.5—1.7—ns Clock to Output inHigh-Z tHZ 1 1.5 2.5 1.5 2.5 1.5 2.5 1.5 3.0 1.5 3.0ns G to Output Valid tOE — 2.5— 2.5— 2.5— 3.0— 3.8ns G to output in Low-Z tOLZ 10—0—0—0—0—ns G to output in High-Z tOHZ 1— 2.5— 2.5— 2.5— 3.0— 3.8ns ZZ setup time tZZS 25—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—nsGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)Pipeline Mode Timing (DCD)Begin Read A Cont Deselect Deselect Write BRead C Read C+1Read C+2Read C+3Cont Deselect DeselecttHZtKQXtKQtLZtHtStOHZtOEtHtStHtStHtStH tStHtStStHtStHtStHtStKCtKL tKHQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCHi-ZDeselected with E1E2 and E3 only sampled with ADSCADSC initiated readCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)Flow Through Mode Timing (DCD)Begin Read A ContDeselect Write B Read C Read C+1Read C+2Read C+3Read C DeselecttHZtKQX tLZtH tStOHZtOE tKQtHtS tHtS tHtStH tStHtS tHtStHtS tHtS tH tStH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSP and ADSCE1 masks ADSPADSC initiated readDeselected with E1E1 masks ADSPFixed HighCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdGS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)Sleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramApplication TipsSingle and Dual Cycle DeselectSCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs (like this one) do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.JTAG Port OperationOverviewThe JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V DD . The JTAG output drivers are powered by V DDQ .tZZRtZZHtZZSHoldSetup tKLtKHtKCCKADSP ADSCZZ。