SN74ALVCH162836VR;SN74ALVCH162836DL;74ALVCH162836GRE4;74ALVCH162836VRE4;中文规格书,Datasheet资料
sn74lv165a原理
sn74lv165a原理SN74LV165A是一种串行输入并行输出的移位寄存器，它可以连接到其他SN74LV165A芯片来扩展输入线。
该芯片可以在微控制器和其他数字电路中起到重要作用。
在此文章中，我们将深入探讨SN74LV165A芯片的工作原理以及其在电路设计中的应用。
SN74LV165A芯片的工作原理SN74LV165A芯片是一种8位移位寄存器，它可以从串行输入线读取数据，并将数据存储在并行输出线中。
该芯片有一个时钟输入端CLK和一个异步清零输入端CLR。
在时钟输入端输入正脉冲时，SN74LV165A芯片将数据从串行输入线读取，并将其存储在内部寄存器中。
当输入完8位数据后，数据将被并行传输到输出线。
SN74LV165A芯片还有一个串行输出端QH'，可以将芯片中的数据通过串行输出线传输出去。
此外，该芯片还具有一个使能输入端，当该端输入低电平时，芯片处于失能状态，此时芯片将不会从串行输入线读取数据，也不会将数据传输到输出线。
SN74LV165A芯片在电路设计中的应用SN74LV165A芯片具有广泛的应用，特别是在数字电路中。
在以下场景中，SN74LV165A芯片被广泛使用：1.扩展输入线：SN74LV165A芯片可以通过串联连接来扩展输入线。
在需要大量输入的应用场景中，SN74LV165A芯片可以通过连接多个芯片来扩展输入线。
2. 计数器：SN74LV165A芯片可以用作计数器的输入接口。
当计数器的计数值达到8时，计数器将停止计数。
在此之后，计数器的输出线可以将计数值传输给其他部件。
3. 时序控制器：在时序控制器中，SN74LV165A芯片可以用作状态机的输入接口。
在时钟输入端输入正脉冲时，状态机将根据当前状态执行不同的操作。
总结SN74LV165A芯片是一种广泛使用的移位寄存器，它可以将串行输入数据转换为并行输出数据。
该芯片可以用于扩展输入线、计数器和时序控制器等应用中。
在电路设计中，SN74LV165A芯片可以提高电路的效率和可靠性，是一种非常有用的电子元件。
sn74lv165a原理
sn74lv165a原理SN74LV165A采用了串行输入、并行输出的设计，它的输入端有一个串行数据输入引脚（SER）和一个时钟输入引脚（CLK）。
通过时钟信号的边沿触发，从串行输入端输入的数据会依次被移位进入移位寄存器中。
移位寄存器内部由8个触发器组成，可以存储8位数据。
当所有数据移入寄存器后，通过并行输出引脚（Q7-Q0）可以同时输出这8位数据。
SN74LV165A的输入端还有一个使能端（CE）和一个清除端（CLR）。
使能端用于控制移位寄存器是否工作，当使能端为高电平时，移位寄存器开始工作；当使能端为低电平时，移位寄存器停止工作，输入数据不再移位。
清除端用于清除移位寄存器内的数据，当清除端为低电平时，寄存器内的数据被清零。
SN74LV165A的时钟输入引脚（CLK）和使能端（CE）可以根据实际需求进行配置。
时钟输入引脚可以选择上升沿触发或下降沿触发，以适应不同的时钟信号；使能端可以选择低电平有效或高电平有效，以满足不同的控制要求。
SN74LV165A具有很多优点，使其在实际应用中得到广泛的应用。
首先，它可以扩展微控制器的输入端口，使其能够同时读取多个输入信号。
其次，它可以实现串行数据的并行输出，提高数据处理的效率。
此外，SN74LV165A的工作电压范围广泛，从2V到5.5V，可以适应不同的电源系统。
在实际应用中，SN74LV165A可以用于数据采集、键盘输入、状态检测等场景。
例如，在一个温度监控系统中，可以使用SN74LV165A从多个温度传感器中读取数据，并将数据传输给微控制器进行处理和显示。
又如，在一个键盘输入系统中，可以使用SN74LV165A来读取用户按下的按键，并将按键数据传输给微控制器进行相应的操作。
SN74LV165A是一种功能强大的串行输入、并行输出的移位寄存器，它具有广泛的应用领域。
通过合理配置时钟输入引脚和使能端，可以实现高效的数据采集和处理。
在实际应用中，SN74LV165A可以用于数据采集、键盘输入、状态检测等场景，为各种系统的设计提供了便利。
低压大电流移相全桥开关电源的研究
低压大电流移相全桥开关电源的研究丁稳房;郜佳辉;杨刚;章子涵【摘要】给出硬件电路系统框图,然后结合采用移相全桥ZVS PWM DC/DC变换器的电路拓扑结构,推导并计算了几个关键的主电路参数,接着给出了产生PWM波相关的硬件电路图,最后在10kW的直流电源样机的环境下进行了实验并得出实验波形.%The paper firstly described the hardware block diagram of circuitry.It then calculated several key parameters of the main circuit combined with the use of phase-shifted full-bridge ZVS PWM DC / DC converter circuit topology.It also presented the relative hardware circuit of the PWM wave generation,Finally,experiments were conducted in the 10KW DC power supply prototype environment and experimental wave forms were obtained.【期刊名称】《湖北工业大学学报》【年(卷),期】2012(027)002【总页数】5页(P40-44)【关键词】移相全桥;DC/DC变换器;PWM【作者】丁稳房;郜佳辉;杨刚;章子涵【作者单位】湖北工业大学电气与电子工程学院,湖北武汉430068;湖北工业大学电气与电子工程学院,湖北武汉430068;湖北工业大学电气与电子工程学院,湖北武汉430068;湖北工业大学电气与电子工程学院,湖北武汉430068【正文语种】中文【中图分类】TM46由于电力电子技术的快速发展，低压大电流直流电源开始越来越多地应用到实际当中去，又由于移相全桥技术可以降低功率开关管的开关损耗，提高变换器的效率以及容易实现软开关等优点，因此移相全桥电路在大功率直流电源中成为首选拓扑结构.移相全桥软开关电路分为零电压开关（ZVS），零电流开关（ZCS），零电压零电流开关（ZVZCS）三种类型［1－3］.相比较而言，移相全桥ZVS电路因为其工作简单可靠，不需要加辅助电路等优点，比较适用于大功率低压大电流的工作场合中.本实验装置采用的是移相全桥ZVS PWM直流变直流技术，其输出电压28.5 V，额定输出电流350 A，本文给出了整个硬件系统框图，主电路参数设计，PWM波相关的硬件设计，最后给出了实验波形.1 系统框图系统框图见图1.图1 硬件系统框图三相电经过12脉波自耦变压器整流出来的电流只含有n次谐波量，n＝12k±1（k ＝1，2，…），减小了输入电流的总谐波含量（THD），提高了系统的兼容性，并且大大减小了12脉波自耦变压器的体积容量.高频变压器采用的是损耗值比较低的铁氧体材料，为了减少开关损耗.输出的电压和电流经过采样后到DSP28335控制板，经过AD转换，再通过SPI进行板间通讯，把数据送到面板显示.2 关键参数的设计移相全桥ZVS变换电路见图2，下面对其中的几个重要参数进行设计计算.图2 移相全桥ZVS变换电路2.1 高频变压器的设计高频变压器设计要求如下：额定输出功率为10kW，允许短时间过载100%（一般为2 min左右），输入三相交流电的电压波动范围为380 V×（1±10%），也就是在342～418 V之间，开关频率为20 k Hz，额定输出直流电压为28.5 V，根据这些要求高频变压器铁芯选取了E28尺寸的R2SKB铁氧体铁芯，根据下面的公式求高频变压器的原边匝数其中：V in为高频变压器的直流输入电压，在这里取最大直流输入电压；K为波形系数，波形系数是指有效值与平均值之比，如果是方波一般为4；f s为开关工作频率（20 k Hz）；B w为变压器的工作磁通密度，一般取它的最大工作磁通密度0.28 T；Ae为铁芯有效截面积，m2，A e ＝A S×K e，K e＝0.97；将参数代入式（1）中可得由于原边是6个变压器串联，在这里就取每个变压器的匝数为6匝.为了提高高频变压器的利用率，减小原边电流以减小开关管的电流应力，降低输出整流块恢复二极管（FRD）的电压应力，从而减小功率损耗，高频变压器的原边与副边的匝数比应尽量大些，但是为了在任何时刻都能得到所要求的输出电压，需要利用高频变压器的副边输出的各种损耗和变压器副边的最大占空比D max来计算高频变压器副边的最大输出电压值其中：V 0为输出电压值；V D为整流输出块恢复二极管上的通态损耗；V L为输出滤波电感上的电压损耗；V R输出电流在输出电缆上的压降损耗.并根据最小输入电压V in（max）来决定变压器的副边匝数.直流电源输出为28.5 V，假设整流输出二极管的通态压降为2 V，输出滤波电感上的电压损耗为1 V，输出电流在输出电缆上的压降损耗为2 V，变换器的最大占空比为0.85，把这些参数代到式（2）中可得变压器的原边与副边的匝数比关系如下：由此可得变压器的副边匝数又由于移相全桥电路的滞后臂工作时占空比丢失比较大，所以取副边匝数为4匝，按以上参数设计的6个变压器实测原边总漏感为12μH.2.2 超前桥臂谐振电容的设计为了实现DC／DC变换器的超前桥臂和滞后桥臂的ZVS软开关，需要根据DC／DC变换器的开关频率和死区时间来确定直流变换器的超前桥臂和滞后桥臂的并联电容和变压器原边串联谐振电感.在移相全桥的超前桥臂工作过程中，输出滤波电感Lf和谐振电感Lr串联，用来抽取超前桥臂上的并联电容的能量以实现ZVS软开关，由于原边等效电感L＝L r＋K 2×L f L r，所以在超前桥臂工作过程中原边等效电感值很大，它的电流可以近似不变，类似一个电流源，为了实现超前臂的ZVS，必须要让Q 1驱动信号和Q3驱动信号的死区时间大于超前桥臂上的并联电容的充放电时间，并联电容电压减少量为t 01是指超前桥臂的并联电容放电由电源电压降到0 V时所需的时间.要实现超前臂的零电压开通，必须要让Q1驱动信号和Q 3驱动信号的死区时间T d大于并联电容的放电时间t 01，所以要满足才能保证零电压开通.由公式可得，如果原边电流变得很小的话，C 3的电压放电到零的时间将变得很长，当t 01＞T d时，将会失去零电压条件，所以选择C 1和C 3的电容值要根据死区时间和要求实现零电压开关的负载范围来确定.由于使用的开关器件是IGBT，所以死区时间不能设置太小，在这里设置超前臂死区时间为2.5μm，DC／DC变换器在大于10%的额定电流能实现零电压开关，即原边电流I 1大于4 A能实现零电压开关，在轻载状态下输入的直流电压为530 V，将这些数据带入式（3）得因为C 1＝C 3，在这里取C 1＝C 3＝4.7 n F，采用的电容是4.7 n F／600 V的CBB聚苯电容.2.3 滞后桥臂谐振电容和谐振电感的设计在滞后桥臂工作的过程中，由于变压器副边上的两个二极管DR1和DR2同时导通，致使变压器原边绕组短接电压为0，所以使得原边等效电感就只是L r L＝L r＋K 2×L f，这就使得滞后桥臂的等效电感远小于超前桥臂的等效电感，因此原边电流就不能看成电流源，而且电流变化大.所以滞后桥臂比超前桥臂难实现零电压开通，要想实现滞后桥臂的零电压开关，要满足以下两个条件.1）串联的谐振电感储存的能量要大于滞后桥臂的电容的储存能量，即其中CTR为变压器的寄生电容，它的值很小，所以上式可以简化为Clag为滞后桥臂的并联电容的平均值，且2）滞后桥臂的死区时间应小于等于谐振周期的四分之一，公式如下：把上式变形一下可得根据这两个约束条件和滞后桥臂大于10 A时能实现零电压开关，就能确定出谐振电感L r和并联电容Clag的参数值.由上述约束条件可得把以知的参数代入公式（4）中由于C 2＝C 4，在这里取Clag＝22 F.由于滞后桥臂的并联谐振电容为22 F，从而可以根据式（5）来确定由于高频变压器的原边总漏感为12μH，所以谐振电感值为45.6μH.在实际的调试过程中，最好把谐振电感设计成可调的，以便让其电感值根据实际的电路来确定.3 PWM硬件电路设计下面主要给出PWM的硬件控制电路和过压过流保护电路，PWM的硬件功能框图和硬件电路如图3.DSP28335输入输出口都是3.3 V，而在设计故障封锁电路时用到的是集成与门CD4081，CD4081的工作电压分别在5 V、10 V、15 V，当工作电压是5 V时，只有当输入电压最低为3.5 V才默认为高电平，所以需要把3.3 V转换成5 V，这里用的电平转换芯片是SN74 ALVC164245，它是16位2.5 V 转为3.3 V或者由3.3 V转为5 V电平的带三态门输出的移位收发器，在这里用的是3.3 V转为5 V电平.硬件电路见图4.电路中2 OE接地，而2DIR接3.3 V，数字2表示第二路，由图4可知只用到第二路，当2 OE为低电平，2DIR为高电平时，A端口处于高阻态，B端口是使能的，所以信号是从A端口到B端口，也就是说PWM波处于输出状态.故障封锁信号如图5所示.图5 故障封锁电路在正常情况下，故障信号BLOCKALL是高电平1，当有故障发生时故障信号BLOCKALL就为低电平0，在更4路PWM相与使得4路输出为0，就把PWM 波封锁了.由于故障信号BLOCKALL牵扯的电路篇幅太大，所以这里给出硬件功能框图以说明硬件设计思想（图6）.在这里需要解释的是：如果有故障信号过来，经过RS触发器后为高电平5 V，高电平5 V是接到三极管的基极来控制三极管的开通，故障显示的电路用的是三极管的共发射极，接法相当于一个开关.所以当信号来时，三极管导通相应的故障灯就亮了.RS触发器出来的故障信号经过集成或门CD4075，是尽量把这么多故障信号转换成一个总的故障信号，再经过一个非门CD4011把故障电平信号反一下变为低电平0，当有故障发生时，也就得到故障信号BLOCKALL为低电平0；没有故障发生时，故障信号BLOCKALL为高电平1.比较电平转换的电路如图7所示.在调试过程中，PWM波参考电压QDVF信号为1 V，PWM波信号QDONE在正常工作时电压有效值为2.1 V，经过比较器L M311出来的电压信号最大为15 V，因为比较器L M311的偏置电压给的是15 V，这样就把PWM波最大为5 V 的信号变成15 V的信号，这里只给出一路PWM波信号，其余三路与此相同.这里出来的PWM波到了IGBT驱动板，再由IGBT驱动板驱动IGBT使其工作.4 实验波形在调试过程中发现高频变压器的原边电压上的尖峰很高，图8是当阻性负载为350 A时的波形，电压尖峰将近400 V，这是谐振电感感应的电压尖峰.为了减小电压尖峰，在谐振电感的两端并上一个耐压值为1 200 V的快恢复二极管，电压波形从图9可以看到，在阻性负载为350 A时的变压器的原边电压尖峰只有100V，电压尖峰消减了300 V，说明此处加上快恢复二极管能起到很好的作用.图10给出的是IGBT的超前桥臂驱动波形，正电压为15 V，负电压为－10 V，负电压是为了让IGBT有效地关断，从图10可以看出，超前臂Q 1和Q 3的驱动信号相反，不存在直通情况.图11是超前桥臂Q 1的GE，CE电压波形，1是驱动信号，2是IGBT的CE的电压波形，由此图看出，当驱动信号关断时，IGBT的CE电压由0开始慢慢上升实现了零电压关断，当驱动信号打开时，IGBT的CE端的电压几乎为0，实现了零电压开通，带轻载时都能实现零电压开通，根据式（3）可知，重载时更容易实现零电压开通.图11 带载35 A时Q1的GE，CE的电压波形最后是突加突减实验波形，突加实验是从电流35 A增加到350 A（图12），突减实验是从电流350 A降到35 A的情况（图13）.图12 从35 A到350 A时的电压突加波形图13 从350 A降到35 A时的电压突减波形5 结论实验证明移相全桥ZVS拓扑结构能够实现零电压开通，减少开关损耗，而且动态性能比较好，适用于大功率的直流电源的软开关电路［4］.［参考文献］［1］孔雪娟，彭力，康勇.模块化移相谐振式DC－DC变流器和并联器［J］.电力电子技术，2002，36（5）：40－43.［2］陈坚.电力电子学［M］.北京：高等教育出版社，2009：291－297. ［3］段善旭，余新颜，康勇.便携式逆变弧焊电源［J］.电焊机，2004，33（12）：28－31.［4］阮新波，严仰光.脉宽调制DC／DC全桥变换器的软开关技术［M］.北京：科学出版社，1999.。
CMOS和TTL电平分析及转换(转载)
ＶＯＨ表示输出高电平的最小值；ＶＯＬ表示输出低电平的最大值。
ＶＩＨ表示输入高电平的最小值；ＶＩＬ表示输入低电平的最大值逻辑标准GND VCC VOH(最小值) VOL（最大值）VIH(最小值) VIL(最大值)3.3V COMS 0.0V 3.3V Vcc-0.1V(3.2V) 0.4V 0.8Vcc(2.64V）0.2Vcc(0.66V) 3.3V TTL 0.0V 3.3V 2.4V 0.4V 2.0V 0.8V5.0V CMOS 0.0V 5.0V 3.5V 0.4V 0.7Vcc(3.5V) 0.3Voc(1.5V) 5.0V TTL 0.0V 5.0V 2.4V 0.4V 2.0V 0.8V（问题一）３３.３Ｖ和５.０Ｖ电平信号的转换在混合电压系统中，不同电源电压的逻辑器件互相接口时存在以下几个问题：第一，加到输入和输出引脚上允许的最大电压限制问题。
器件对加到输入或者输出脚上的电压通常是有限制的。
这些引脚有二极管或者分离元件接到Ｖｃｃ。
如果接入的电压过高，则电流将会通过二极管或者分离元件流向电源。
例如在３．３Ｖ器件的输入端加上５Ｖ的信号，则５Ｖ电源会向３．３Ｖ电源充电。
持续的电流将会损坏二极管和其它电路元件。
第二，两个电源间电流的互串问题。
在等待或者掉电方式时，３．３Ｖ电源降落到０Ｖ，大电流将流通到地，这使得总线上的高电压被下拉到地，这些情况将引起数据丢失和元件损坏。
必须注意的是：不管在３．３Ｖ的工作状态还是在０Ｖ的等待状态都不允许电流流向Ｖｃｃ。
第三，接口输入转换门限问题。
５Ｖ器件和３．３Ｖ器件的接口有很多情况，（问题二）同样ＴＴＬ和ＣＭＯＳ间的电平转换也存在着不同情况。
驱动器必须满足接收器的输入转换电平，并且要有足够的容限以保证不损坏电路元件。
基于上述情况，５Ｖ器件和３．３Ｖ器件是不能直接接口的。
有些半导体器件制造厂家就推出了具有５Ｖ输入容限的３．３Ｖ器件，这种器件输入端具有ＥＳＤ保护电路。
常用电平转换 方案
1.常用的电平转换方案(1)晶体管+上拉电阻法就是一个双极型三极管或MOSFET，C/D极接一个上拉电阻到正电源，输入电平很灵活，输出电平大致就是正电源电平。
(2) OC/OD器件+上拉电阻法跟1)类似。
适用于器件输出刚好为OC/OD的场合。
(3) 74xHCT系列芯片升压(3.3V→5V)凡是输入与5V TTL电平兼容的5V CMOS器件都可以用作3.3V→5V电平转换。
--这是由于3.3V CMOS的电平刚好和5V TTL电平兼容（巧合），而CMOS的输出电平总是接近电源电平的。
廉价的选择如74xHCT(HCT/AHCT/VHCT/AHCT1G/VHCT1G/...)系列(那个字母T就表示TTL 兼容)。
(4)超限输入降压法(5V→3.3V, 3.3V→1.8V, ...)凡是允许输入电平超过电源的逻辑器件，都可以用作降低电平。
这里的“超限”是指超过电源，许多较古老的器件都不允许输入电压超过电源，但越来越多的新器件取消了这个限制(改变了输入级保护电路)。
例如，74AHC/VHC系列芯片，其datasheets明确注明“输入电压范围为0~5.5V”，如果采用3.3V供电，就可以实现5V→3.3V电平转换。
(5)专用电平转换芯片如仙童半导体公司的74LVX4245、TI公司的SN74ALVC164245、SN74ALVC4245。
最著名的就是164245，不仅可以用作升压/降压，而且允许两边电源不同步。
这是最通用的电平转换方案，但是也是很昂贵的(俺前不久买还是￥45/片，虽是零售，也贵的吓人)，因此若非必要，最好用前两个方案。
(6)电阻分压法最简单的降低电平的方法。
5V电平，经1.6k+3.3k电阻分压，就是3.3V。
(7)限流电阻法如果嫌上面的两个电阻太多，有时还可以只串联一个限流电阻。
某些芯片虽然原则上不允许输入电平超过电源，但只要串联一个限流电阻，保证输入保护电流不超过极限(如74HC 系列为20mA)，仍然是安全的。
sn74alvc164245
FEATURESNOTE: New and improved versions of the SN74ALVC164245are available. The new part numbers are SN74LVC16T245 andSN74LVCH16T245 and should be considered for new designs.DESCRIPTION/ORDERING INFORMATIONDGG OR DL PACKAGE(TOP VIEW)1234567891011121314151617181920212223244847464544434241403938373635343332313029282726251DIR1B11B2GND1B31B4(3.3 V, 5 V) V CCB1B51B6GND1B71B82B12B2GND2B32B4(3.3 V, 5 V) V CCB2B52B6GND2B72B82DIR1OE1A11A2GND1A31A4V CCA (2.5 V, 3.3 V)1A51A6GND1A71A82A12A2GND2A32A4V CCA (2.5 V, 3.3 V)2A52A6GND2A72A82OESN74ALVC16424516-BIT2.5-V TO3.3-V/3.3-V TO5-V LEVEL-SHIFTING TRANSCEIVERWITH3-STATE OUTPUTSSCAS416P–MARCH1994–REVISED NOVEMBER2005•Member of the Texas Instruments Widebus™Family•Max t pd of5.8ns at3.3V•±24-mA Output Drive at3.3V•Control Inputs V IH/V IL Levels Are Referencedto V CCA Voltage•Latch-Up Performance Exceeds250mA PerJESD17This16-bit(dual-octal)noninverting bus transceivercontains two separate supply rails.B port has V CCB,which is set to operate at3.3V and5V.A port hasV CCA,which is set to operate at2.5V and3.3V.Thisallows for translation from a 2.5-V to a 3.3-Venvironment,and vice versa,or from a3.3-V to a5-Venvironment,and vice versa.The SN74ALVC164245is designed for asynchronouscommunication between data buses.The controlcircuitry(1DIR,2DIR,1OE,and2OE)is powered byV CCA.To ensure the high-impedance state during power upor power down,the output-enable(OE)input shouldbe tied to V CC through a pullup resistor;the minimumvalue of the resistor is determined by thecurrent-sinking capability of the driver.ORDERING INFORMATIONT A PACKAGE(1)ORDERABLE PART NUMBER TOP-SIDE MARKINGFBGA–GRD74ALVC164245GRDRTape and reel VC4245FBGA–ZRD(Pb-free)74ALVC164245ZRDRTube of25SN74ALVC164245DLSSOP–DL SN74ALVC164245DLR ALVC164245Reel of100074ALVC164245DLRG4–40°C to85°C SN74ALVC164245DGGRReel of200074ALVC164245DGGRG4TSSOP–DGG ALVC164245SN74ALVC164245DGGTReel of25074ALVC164245DGGTE4VFBGA–GQL SN74ALVC164245KRReel of1000VC4245VFBGA–ZQL(Pb-free)74ALVC164245ZQLR(1)Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at/sc/package.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date.Copyright©1994–2005,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.DESCRIPTION/ORDERING INFORMATION (CONTINUED)GQL OR ZQL PACKAGE (TOP VIEW)J H G F E D C B A 213465KGRD OR ZRD PACKAGE(TOP VIEW)JH G F E D C B A 213465SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTSSCAS416P–MARCH 1994–REVISED NOVEMBER 2005The logic levels of the direction-control (DIR)input and the output-enable (OE)input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode.The device transmits data from the A bus to the B bus when the B-port outputs are activated,and from the B bus to the A bus when the A-port outputs are activated.The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess I CC and I CCZ .TERMINAL ASSIGNMENTS (1)(56-Ball GQL/ZQL Package)123456A 1DIR NC NC NC NC 1OE B 1B21B1GND GND 1A11A2C 1B41B3V CCB V CCA 1A31A4D 1B61B5GNDGND1A51A6E 1B81B71A71A8F 2B12B22A22A1G 2B32B4GND GND 2A42A3H 2B52B6V CCB V CCA 2A62A5J 2B72B8GND GND 2A82A7K2DIRNCNCNCNC2OE(1)NC –No internal connectionTERMINAL ASSIGNMENTS (1)(54-Ball GRD/ZRD Package)123456A 1B1NC 1DIR 1OE NC 1A1B 1B31B2NC NC 1A21A3C 1B51B4V CCB V CCA 1A41A5D 1B71B6GND GND 1A61A7E 2B11B8GND GND 1A82A1F 2B32B2GND GND 2A22A3G 2B52B4V CCB V CCA 2A42A5H 2B72B6NC NC 2A62A7J 2B8NC2DIR2OENC2A8(1)NC –No internal connectionFUNCTION TABLE (1)(EACH 8-BIT SECTION)CONTROL INPUTS OUTPUT CIRCUITS OPERATION OE DIR A PORT B PORT L L Enabled Hi-Z B data to A bus L H Hi-Z Enabled A data to B busH XHi-ZHi-ZIsolation(1)Input circuits of the data I/Os always are active.2To Seven Other Channels 1DIR1A11B11OETo Seven Other Channels2DIR2A12B12OEAbsolute Maximum Ratings (1)SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVERWITH 3-STATE OUTPUTSSCAS416P–MARCH 1994–REVISED NOVEMBER 2005LOGIC DIAGRAM (POSITIVE LOGIC)over operating free-air temperature range for V CCB at 5V and V CCA at 3.3V (unless otherwise noted)MINMAX UNIT V CCA –0.5 4.6V CCSupply voltage rangeVV CCB–0.56Except I/O ports (2)–0.56V I Input voltage range I/O port A (3)–0.5V CCA +0.5V I/O port B (2)–0.5V CCB +0.5I IK Input clamp current V I <0–50mA I OK Output clamp current V O <0–50mA I OContinuous output current±50mA Continuous current through each V CC or GND±100mA DGG package70DL package 63θJAPackage thermal impedance (4)°C/W GQL/ZQL package 42GRD/ZRD package36T stg Storage temperature range–65150°C (1)Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)This value is limited to 6V maximum.(3)This value is limited to 4.6V maximum.(4)The package thermal impedance is calculated in accordance with JESD 51-7.3Recommended Operating Conditions (1)Recommended Operating Conditions (1)SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTSSCAS416P–MARCH 1994–REVISED NOVEMBER 2005for V CCB at 3.3V and 5VMINMAX UNIT V CCB Supply voltage 3 5.5V V IH High-level input voltage 2V V CCB =3V to 3.6V 0.7V IL Low-level input voltage V V CCB =4.5V to 5.5V0.8V IB Input voltage 0V CCB V V OB Output voltage0V CCB V I OH High-level output current –24mA I OL Low-level output current 24mA ∆t/∆v Input transition rise or fall rate 10ns/V T A Operating free-air temperature–4085°C(1)All unused inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs ,literature number SCBA004.for V CCA at 2.5V and 3.3VMINMAX UNIT V CCA Supply voltage 2.3 3.6V V CCA =2.3V to 2.7V 1.7V IH High-level input voltage V V CCA =3V to 3.6V 2V CCA =2.3V to 2.7V 0.7V IL Low-level input voltage V V CCA =3V to 3.6V0.8V IA Input voltage 0V CCA V V OA Output voltage0V CCA V V CCA =2.3V –18I OH High-level output current mA V CCA =3V –24V CCA =2.3V 18I OL Low-level output current mA V CCA =3V24∆t/∆v Input transition rise or fall rate 10ns/V T A Operating free-air temperature–4085°C(1)All unused inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs ,literature number SCBA004.4Electrical Characteristics Electrical CharacteristicsSN74ALVC164245 16-BIT2.5-V TO3.3-V/3.3-V TO5-V LEVEL-SHIFTING TRANSCEIVERWITH3-STATE OUTPUTSSCAS416P–MARCH1994–REVISED NOVEMBER2005over recommended operating free-air temperature range for VCCA =2.7V to3.6V and VCCB=4.5V to5.5V(unlessotherwise noted)PARAMETER TEST CONDITIONS V CCA V CCB MIN TYP(1)MAX UNITI OH=–100µA 2.7V to3.6V V CC–0.22.7V 2.2B to A I OH=–12mA3V 2.4I OH=–24mA3V2V OH V4.5V 4.3I OH=–100µA5.5V 5.3A to B4.5V 3.7I OH=–24mA5.5V 4.7I OL=100µA 2.7V to3.6V0.2B to A I OL=12mA 2.7V0.4V OL I OL=24mA3V0.55VI OL=100µA 4.5V to5.5V0.2A to BI OL=24mA 4.5V to5.5V0.55I I Control inputs V I=V CCA/V CCB or GND 3.6V 5.5V±5µAI OZ(2)A or B port V O=V CCA/V CCB or GND 3.6V 5.5V±10µAI CC V I=V CCA/V CCB or GND,I O=0 3.6V 5.5V40µAOne input at V CCA/V CCB–0.6V,∆I CC(3)3V to3.6V 4.5V to5.5V750µA Other inputs at V CCA/V CCB or GNDC i Control inputs V I=V CCA/V CCB or GND 3.3V5V 6.5pFC io A or B port V O=V CCA/V CCB or GND 3.3V 3.3V8.5pF(1)Typical values are measured at V CCA=3.3V and V CCB=5V,T A=25°C.(2)For I/O ports,the parameter I OZ includes the input leakage current.(3)This is the increase in supply current for each input that is at one of the specified TTL voltage levels,rather than at0or the associatedV CC.over recommended operating free-air temperature range for VCCA =2.3V to2.7V and VCCB=3V to3.6V(unless otherwisenoted)PARAMETER TEST CONDITIONS V CCA V CCB MIN MAX UNITI OH=–100µA 2.3V to2.7V3V to3.6V V CCA–0.2B to A I OH=–8mA 2.3V3V to3.6V 1.7V OH I OH=–12mA 2.7V3V to3.6V 1.8VI OH=–100µA 2.3V to2.7V3V to3.6V V CCB–0.2A to BI OH=–18mA 2.3V to2.7V3V 2.2I OL=100µA 2.3V to2.7V3V to3.6V0.2B to AI OL=12mA 2.3V3V to3.6V0.6V OL VI OL=100µA 2.3V to2.7V3V to3.6V0.2A to BI OL=18mA 2.3V3V0.55I I Control inputs V I=V CCA/V CCB or GND 2.3V to2.7V3V to3.6V±5µAI OZ(1)A or B port V O=V CCA/V CCB or GND 2.3V to2.7V3V to3.6V±10µAI CC V I=V CCA/V CCB or GND,I O=0 2.3V to2.7V3V to3.6V20µAOne input at V CCA/V CCB–0.6V,∆I CC(2) 2.3V to2.7V3V to3.6V750µA Other inputs at V CCA/V CCB or GND(1)For I/O ports,the parameter I OZ includes the input leakage current.(2)This is the increase in supply current for each input that is at one of the specified TTL voltage levels,rather than at0or the associatedV CC.5Switching CharacteristicsOperating CharacteristicsSN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTSSCAS416P–MARCH 1994–REVISED NOVEMBER 2005over recommended operating free-air temperature range (unless otherwise noted)(see Figure 1through Figure 4)V CCB =3.3V V CCB =5V ±0.5V ±0.3V FROM TO PARAMETERV CCA =2.5V V CCA =3.3V UNIT(INPUT)(OUTPUT)V CCA =2.7V ±0.2V ±0.3V MINMAX MINMAX MIN MAX A B 7.6 5.91 5.8t pd ns B A 7.6 6.7 1.2 5.8t en OE B 11.59.318.9ns t dis OE B 10.59.2 2.19.5ns t en OE A 12.310.229.1ns t disOEA9.392.98.6ns T A =25°CV CCB =3.3VV CCB =5V PARAMETERTEST CONDITIONSV CCA =2.5VV CCA =3.3VUNITTYPTYP Outputs enabled (B)5556C L =50pF,f =10MHz Outputs disabled (B)276C pdPower dissipation capacitancepF Outputs enabled (A)11856C L =50pF,f =10MHzOutputs disabled (A)5866POWER-UP CONSIDERATIONS(1)SN74ALVC16424516-BIT2.5-V TO3.3-V/3.3-V TO5-V LEVEL-SHIFTING TRANSCEIVERWITH3-STATE OUTPUTSSCAS416P–MARCH1994–REVISED NOVEMBER2005TI level-translation devices offer an opportunity for successful mixed-voltage signal design.A proper power-up sequence always should be followed to avoid excessive supply current,bus contention,oscillations,or other anomalies caused by improperly biased device pins.Take these precautions to guard against such power-up problems:1.Connect ground before any supply voltage is applied.2.Power up the control side of the device(V CCA for all four of these devices).3.Tie OE to V CCA with a pullup resistor so that it ramps with V CCA.4.Depending on the direction of the data path,DIR can be high or low.If DIR high is needed(A data to B bus),ramp it with V CCA.Otherwise,keep DIR low.(1)Refer to the TI application report,Texas Instruments Voltage-Level-Translation Devices,literature number SCEA021.7PARAMETER MEASUREMENT INFORMATION V OHB V OLBC L LOAD CIRCUITCCB = 6 VOpenOutput Control (low-level enabling)Output Waveform 1S1 at 6 V (see Note B)Output Waveform 2S1 at GND (see Note B)0 V0 VV CCAV CCBVOLTAGE WAVEFORMS PROPAGATION DELAY TIMESVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMESt pd t PLZ /t PZL t PHZ /t PZHOpen V CCB = 6 V GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z O = 50 Ω, t r ≤2 ns, t f ≤2 ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTSSCAS416P–MARCH 1994–REVISED NOVEMBER 2005V CCA =2.5V ±0.2V to V CCB =3.3V ±0.3VFigure 1.Load Circuit and Voltage Waveforms8PARAMETER MEASUREMENT INFORMATIONV OHAV OLA From Output Under TestC L LOAD CIRCUITOpen Output Control (low-level enabling)Output Waveform 1S1 at 2 × V CCA (see Note B)Output Waveform 2S1 at GND (see Note B)0 V0 V2.7 VVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMESt pd t PLZ /t PZL t PHZ /t PZHOpen 2 × V CCA GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z O = 50 Ω, t r ≤2 ns, t f ≤2 ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .InputOutputVOLTAGE WAVEFORMS PROPAGATION DELAY TIMES× V CCAV CCASN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVERWITH 3-STATE OUTPUTSSCAS416P–MARCH 1994–REVISED NOVEMBER 2005V CCB =3.3V ±0.3V to V CCA =2.5V ±0.2VFigure 2.Load Circuit and Voltage Waveforms9PARAMETER MEASUREMENT INFORMATIONV OH V OLC L LOAD CIRCUITV CCBOpenOutput Control (low-level enabling)Output Waveform 1S1 at 2 V CCB(see Note B)Output Waveform 2S1 at GND (see Note B)0 V0 V2.7 V≈V CCBVOLTAGE WAVEFORMS PROPAGATION DELAY TIMESVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMESt pd t PLZ /t PZL t PHZ /t PZHOpen 2 V CCB GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω, t r ≤ 2.5 ns, t f ≤ 2.5 ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTSSCAS416P–MARCH 1994–REVISED NOVEMBER 2005V CCA =3.3V ±0.3V to V CCB =5V ±0.5VFigure 3.Load Circuit and Voltage Waveforms10 PARAMETER MEASUREMENT INFORMATION V OHA V OLAC L LOAD CIRCUIT = 6 VOpenOutput Control(low-levelenabling)Output Waveform 1S1 at 6 V (see Note B)Output Waveform 2S1 at GND (see Note B)0 V 0 V 3 V ≈3 V VOLTAGE WAVEFORMSPROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES t pd t PLZ /t PZL t PHZ /t PZH Open V CCA = 6 V GND TEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω, t r ≤ 2.5 ns, t f ≤ 2.5 ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS416P–MARCH 1994–REVISED NOVEMBER 2005V CCB =5V ±0.5V to V CCA =2.7V and 3.3V ±0.3VFigure 4.Load Circuit and Voltage WaveformsPACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)74ALVC164245DGGRE4ACTIVE TSSOP DGG482000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM74ALVC164245DGGRG4ACTIVE TSSOP DGG482000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM74ALVC164245DGGTE4ACTIVE TSSOP DGG48250Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM74ALVC164245DGGTG4ACTIVE TSSOP DGG48250Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM74ALVC164245DLG4ACTIVE SSOP DL4825Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM74ALVC164245DLRG4ACTIVE SSOP DL481000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM74ALVC164245GRDR ACTIVE BGA MICROSTAR JUNIORGRD541000TBD SNPB Level-1-240C-UNLIM74ALVC164245ZQLR ACTIVE BGA MICROSTAR JUNIOR ZQL561000Green(RoHS&no Sb/Br)SNAGCU Level-1-260C-UNLIM74ALVC164245ZRDR ACTIVE BGA MICROSTAR JUNIOR ZRD541000Green(RoHS&no Sb/Br)SNAGCU Level-1-260C-UNLIMSN74ALVC164245DGGR ACTIVE TSSOP DGG482000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74ALVC164245DGGT ACTIVE TSSOP DGG48250Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74ALVC164245DL ACTIVE SSOP DL4825Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74ALVC164245DLR ACTIVE SSOP DL481000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74ALVC164245KR ACTIVE BGA MICROSTAR JUNIORGQL561000TBD SNPB Level-1-240C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.OTHER QUALIFIED VERSIONS OF SN74ALVC164245:•Enhanced Product:SN74ALVC164245-EPNOTE:Qualified Version Definitions:•Enhanced Product-Supports Defense,Aerospace and Medical ApplicationsTAPE AND REELINFORMATION *All dimensions are nominal Device Package Type Package DrawingPinsSPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant 74ALVC164245GRDR BGA MICROSTAR JUNIORGRD 541000330.016.4 5.88.3 1.558.016.0Q174ALVC164245ZQLR BGA MICROSTAR JUNIORZQL 561000330.016.4 4.87.3 1.458.016.0Q174ALVC164245ZRDR BGA MICROSTAR JUNIOR ZRD 541000330.016.4 5.88.3 1.558.016.0Q1SN74ALVC164245DGGR TSSOPDGG 482000330.024.48.615.8 1.812.024.0Q1SN74ALVC164245DGGT TSSOPDGG 48250330.024.48.615.8 1.812.024.0Q1SN74ALVC164245DLRSSOP DL 481000330.032.411.3516.2 3.116.032.0Q1SN74ALVC164245KR BGA MICROSTAR JUNIOR GQL 561000330.016.4 4.87.3 1.458.016.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) 74ALVC164245GRDR BGA MICROSTARJUNIORGRD541000346.0346.033.074ALVC164245ZQLR BGA MICROSTARJUNIORZQL561000346.0346.033.074ALVC164245ZRDR BGA MICROSTARJUNIORZRD541000346.0346.033.0SN74ALVC164245DGGR TSSOP DGG482000346.0346.041.0SN74ALVC164245DGGT TSSOP DGG48250346.0346.041.0SN74ALVC164245DLR SSOP DL481000346.0346.049.0SN74ALVC164245KR BGA MICROSTARJUNIOR GQL561000346.0346.033.0IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale 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SN74LVC1G66YZPR中文资料
SN74LVC1G66 SINGLE BILATERAL ANALOG SWITCH
SCES323H − JUNE 2001 − REVISED SEPTEMBER 2003
D Available in the Texas Instruments D D D D D D D D D
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Control input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port diode current, IIOK (VI/O < 0 or VI/O > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA On-state switch current, IT (VI/O = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 4): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
SN74LVCH16T245-EP 16位双电源总线收发器说明书
DGV PACKAGE(TOP VIEW)1234567891011121314151617181920212223244847464544434241403938373635343332313029282726251DIR1B11B2GND1B31B4V CCB1B51B6GND1B71B82B12B2GND2B32B4V CCB2B52B6GND2B72B82DIR1OE1A11A2GND1A31A4V CCA1A51A6GND1A71A82A12A2GND2A32A4V CCA2A52A6GND2A72A82OESN74LVCH16T245-EP SCES726A–NOVEMBER2008–REVISED NOVEMBER201316-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND3-STATE OUTPUTSCheck for Samples:SN74LVCH16T245-EPFEATURES•Control Inputs V IH/V IL Levels Are Referenced toV CCA Voltage•V CC Isolation Feature–If Either V CC Input Is atGND,All Outputs Are in the High-ImpedanceState•Overvoltage-Tolerant Inputs/Outputs AllowMixed-Voltage-Mode Data Communications•Fully Configurable Dual-Rail Design AllowsEach Port to Operate Over the Full1.65-V to5.5-V Power-Supply Range•Bus Hold on Data Inputs Eliminates the Needfor External Pullup/Pulldown Resistors•I off Supports Partial-Power-Down ModeOperation•Latch-Up Performance Exceeds100mA PerJESD78,Class II•ESD Protection Exceeds JESD22–2000-V Human-Body Model(A114-A)–200-V Machine Model(A115-A)–1000-V Charged-Device Model(C101)SUPPORTS DEFENSE,AEROSPACE,AND MEDICAL APPLICATIONS•Controlled Baseline•One Assembly/Test Site•One Fabrication Site•Available in Military(–55°C/125°C)Temperature Range(1)•Extended Product Life Cycle•Extended Product-Change Notification•Product Traceability(1)Custom temperature ranges availableDESCRIPTIONThis16-bit noninverting bus transceiver uses two separate configurable power-supply rails.The A port is designed to track V CCA.V CCA accepts any supply voltage from1.65V to5.5V.The B port is designed to track V CCB.V CCB accepts any supply voltage from1.65V to5.5V.This allows for universal low-voltage bidirectional translation between any of the1.8-V,2.5-V,3.3-V,and5-V voltage nodes.The SN74LVCH16T245is designed so that the control pins(1DIR,2DIR,1OE,and2OE)are supplied by V CCA.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2008–2013,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasTo Seven Other Channels 1DIR1A11B11OETo Seven Other Channels2DIR2A12B12OESN74LVCH16T245-EPSCES726A –NOVEMBER 2008–REVISED NOVEMBER 2013DESCRIPTION (CONTINUED)The SN74LVCH16T245is designed for asynchronous communication between two data buses.The logic levels of the direction-control (DIR)input and the output-enable (OE)input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode.The device transmits data from the A bus to the B bus when the B-port outputs are activated,and from the B bus to the A bus when the A-port outputs are activated.The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess I CC and I CCZ .Active bus-hold circuitry holds unused or undriven data inputs at a valid logic e of pullup or pulldown resistors with the bus-hold circuitry is not recommended.This device is fully specified for partial-power-down applications using I off .The I off circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.The V CC isolation feature ensures that if either V CC input is at GND,then all outputs are in the high-impedance state.The bus-hold circuitry on the powered-up side always stays active.To ensure the high-impedance state during power up or power down,OE should be tied to V CC through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of the driver.Table 1.ORDERING INFORMATION (1)T APACKAGE (2)ORDERABLE PART NUMBER TOP-SIDE MARKING TVSOP –DGV Tape and reel CLVCH16T245MDGVREP LDHT245MEP –50°C to 125°C TSSOP -DGGTape and reelCLVCH16T245MDGGREP8UT245MEP(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI Web site at .(2)Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at /sc/package .FUNCTION TABLE (1)(EACH 16-BIT SECTION)CONTROL INPUTS OUTPUT CIRCUITS OPERATION OE DIR A PORT B PORT L L Enabled Hi-Z B data to A bus L H Hi-Z Enabled A data to B busH XHi-ZHi-ZIsolation(1)Input circuits of the data I/Os are always active.LOGIC DIAGRAM (POSITIVE LOGIC)2Submit Documentation Feedback Copyright ©2008–2013,Texas Instruments IncorporatedSN74LVCH16T245-EP SCES726A–NOVEMBER2008–REVISED NOVEMBER2013Absolute Maximum Ratings(1)over operating free-air temperature range(unless otherwise noted)MIN MAX UNITV CCASupply voltage range–0.5 6.5VV CCBI/O ports(A port)–0.5 6.5V I Input voltage range(2)I/O ports(B port)–0.5 6.5VControl inputs–0.5 6.5V O Voltage range applied to any output A port–0.5 6.5V in the high-impedance or power-off state(2)B port–0.5 6.5A port–0.5V CCA+0.5V O Voltage range applied to any output in the high or low state(2)(3)VB port–0.5V CCB+0.5I IK Input clamp current V I<0–50mAI OK Output clamp current V O<0–50mAI O Continuous output current±50mAContinuous current through each V CCA,V CCB,and GND±100mAθJA Package thermal impedance(4)58°C/WT stg Storage temperature range–65150°C (1)Stresses beyond those listed under"absolute maximum ratings"may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3)The output positive-voltage rating may be exceeded up to6.5V maximum if the output current rating is observed.(4)The package thermal impedance is calculated in accordance with JESD51-7.Copyright©2008–2013,Texas Instruments Incorporated Submit Documentation Feedback3SN74LVCH16T245-EPSCES726A–NOVEMBER2008–REVISED Recommended Operating Conditions(1)(2)(3)V CCI V CCO MIN MAX UNIT V CCA 1.65 5.5 Supply voltage VV CCB 1.65 5.51.65V to1.95V V CCI×0.652.3V to2.7V 1.7High-levelV IH Data inputs(4)V input voltage3V to3.6V24.5V to5.5V V CCI×0.71.65V to1.95V V CCI×0.352.3V to2.7V0.7Low-levelV IL Data inputs(4)V input voltage3V to3.6V0.84.5V to5.5V V CCI×0.31.65V to1.95V V CCA×0.652.3V to2.7V 1.7High-level Control inputsV IH V input voltage(referenced to V CCA)(5)3V to3.6V24.5V to5.5V V CCA×0.71.65V to1.95V V CCA×0.352.3V to2.7V0.7Low-level Control inputsV IL V input voltage(referenced to V CCA)(5)3V to3.6V0.84.5V to5.5V V CCA×0.3V I Input voltage Control inputs0 5.5VActive state0V CCOV I/O Input/output voltage V3-State0 5.51.65V to1.95V–42.3V to2.7V–8I OH High-level output current mA3V to3.6V–244.5V to5.5V–321.65V to1.95V42.3V to2.7V8I OL Low-level output current mA3V to3.6V244.5V to5.5V321.65V to1.95V202.3V to2.7V20Input transitionΔt/Δv Data inputs ns/V rise or fall rate3V to3.6V104.5V to5.5V5T A Operating free-air temperature–4085°C(1)V CCI is the V CC associated with the data input port.(2)V CCO is the V CC associated with the output port.(3)All unused control inputs of the device must be held at V CCA GND to ensure proper device operation and minimize power consumption.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs,literature number SCBA004.(4)For V CCI values not specified in the data sheet,V IH min=V CCI×0.7V,V IL max=V CCI×0.3V.(5)For V CCA values not specified in the data sheet,V IH min=V CCA×0.7V,V IL max=V CCA×0.3V.4Submit Documentation Feedback Copyright©2008–2013,Texas Instruments IncorporatedSN74LVCH16T245-EP SCES726A–NOVEMBER2008–REVISED NOVEMBER2013Electrical Characteristics(1)(2)over recommended operating free-air temperature range(unless otherwise noted)PARAMETER TEST CONDITIONS V CCA V CCB MIN TYP MAX MIN MAX UNITI OH=–100μA,V I=V IH 1.65V to4.5V 1.65V to4.5V V CCO–0.1I OH=–4mA,V I=V IH 1.65V 1.65V 1.2V OH I OH=–8mA,V I=V IH 2.3V 2.3V 1.9VI OH=–24mA,V I=V IH3V3V 2.4I OH=–32mA,V I=V IH 4.5V 4.5V 3.8I OL=100μA,V I=V IL 1.65V to4.5V 1.65V to4.5V0.1I OL=4mA,V I=V IL 1.65V 1.65V0.45V OL I OL=8mA,V I=V IL 2.3V 2.3V0.3VI OL=24mA,V I=V IL3V3V0.55I OL=32mA,V I=V IL 4.5V 4.5V0.55ControlI I V I=V CCA or GND 1.65V to5.5V 1.65V to5.5V±0.5±1±2μAinputsV I=0.58V 1.65V 1.65V15V I=0.7V 2.3V 2.3V45I BHL(3)μAV I=0.8V3V3V75V I=0.1.35V 4.5V 4.5V100V I=1.07V 1.65V 1.65V–15V I=1.7V 2.3V 2.3V–45I BHH(4)μAV I=2V3V3V–75V I=3.15V 4.5V 4.5V–1001.95V 1.95V2002.7V 2.7V300I BHLO(5)V I=0to V CCμA3.6V 3.6V5005.5V 5.5V9001.95V 1.95V–2002.7V 2.7V–300I BHHO(6)V I=0to V CCμA3.6V 3.6V–5005.5V 5.5V–900A port0V0to5.5V±0.5±1±2I off V I or V O=0to5.5VμAB port0to5.5V0V±0.5±1±2A or BOE=V IH 1.65V to5.5V 1.65V to5.5V±1±2 V O=V CCO orportI OZ GND,μAB port0V 5.5V±1±2OE=don'tV I=V CCI or GNDcareA port 5.5V0V±1±21.65V to5.5V 1.65V to5.5V20I CCA V I=V CCI or GND,I O=05V0V20μA0V5V–21.65V to5.5V 1.65V to5.5V20I CCB V I=V CCI or GND,I O=05V0V–2μA0V5V20I CCA+I CCB V I=V CCI or GND,I O=0 1.65V to5.5V 1.65V to5.5V30μA(1)V CCO is the V CC associated with the output port.(2)V CCI is the V CC associated with the input port.(3)The bus-hold circuit can sink at least the minimum low sustaining current at V IL max.I BHL should be measured after lowering V IN to GNDand then raising it to V IL max.(4)The bus-hold circuit can source at least the minimum high sustaining current at V IH min.I BHH should be measured after raising V IN toV CC and then lowering it to V IH min.(5)An external driver must source at least I BHLO to switch this node from low to high.(6)An external driver must sink at least I BHHO to switch this node from high to low.Copyright©2008–2013,Texas Instruments Incorporated Submit Documentation Feedback5SN74LVCH16T245-EPSCES726A–NOVEMBER2008–REVISED Electrical Characteristics(1)(2)(continued)over recommended operating free-air temperature range(unless otherwise noted)PARAMETER TEST CONDITIONS V CCA V CCB MIN TYP MAX MIN MAX UNIT DIR at V CCA–0.6V,ΔI CCA DIR B port=open,3V to5.5V3V to5.5V50μAA port at V CCA or GNDControlC i V I=V CCA or GND 3.3V 3.3V45pFinputsA or BC io V O=V CCA/B or GND 3.3V 3.3V8.510pFportSwitching Characteristicsover recommended operating free-air temperature range,V CCA=1.8V±0.15V(unless otherwise noted)(see Figure1)V CCB=1.8V V CCB=2.5V V CCB=3.3V V CCB=5VFROM TO±0.15V±0.2V±0.3V±0.5V PARAMETER UNIT (INPUT)(OUTPUT)MIN MAX MIN MAX MIN MAX MIN MAXt PLHA B 1.721.9 1.39.217.40.47.1nst PHLt PLHB A0.923.80.823.80.723.40.723.4nst PHLt PHZOE A 1.529.6 1.529.4 1.529.3 1.429.2ns t PLZt PHZOE B 2.432.2 1.913.1 1.712 1.310.3ns t PLZt PZHOE A0.4240.423.80.423.70.423.7ns t PZLt PZHOE B 1.832 1.518 1.212.60.910.8ns t PZLSwitching Characteristicsover recommended operating free-air temperature range,V CCA=2.5V±0.2V(unless otherwise noted)(see Figure1)V CCB=1.8V V CCB=2.5V V CCB=3.3V V CCB=5VFROM TO±0.15V±0.2V±0.3V±0.5V PARAMETER UNIT (INPUT)(OUTPUT)MIN MAX MIN MAX MIN MAX MIN MAX t PLHA B 1.521.4 1.290.8 6.20.6 4.8nst PHLt PLHB A 1.29.319.118.90.98.8nst PHLt PHZOE A 1.49 1.49 1.49 1.49ns t PLZt PHZOE B 2.329.6 1.811 1.79.30.9 6.9ns t PLZt PZHOE A110.9110.9110.9110.9ns t PZLt PZHOE B 1.728.2 1.512.9 1.29.41 6.9ns t PZL6Submit Documentation Feedback Copyright©2008–2013,Texas Instruments IncorporatedSN74LVCH16T245-EP SCES726A–NOVEMBER2008–REVISED NOVEMBER2013Switching Characteristicsover recommended operating free-air temperature range,V CCA=3.3V±0.3V(unless otherwise noted)(see Figure1)V CCB=1.8V V CCB=2.5V V CCB=3.3V V CCB=5VFROM TO±0.15V±0.2V±0.3V±0.5V PARAMETER UNIT (INPUT)(OUTPUT)MIN MAX MIN MAX MIN MAX MIN MAXt PLHA B 1.621.2 1.18.80.8 6.20.6 4.4nst PHLt PLHB A0.87.20.8 6.20.7 6.10.66nst PHLt PHZOE A 1.68.2 1.68.2 1.68.2 1.68.2ns t PLZt PHZOE B 2.129 1.710.3 1.58.80.8 6.3ns t PLZt PZHOE A0.87.80.88.10.88.10.88.1ns t PZLt PZHOE B 1.827.7 1.412.4 1.18.50.8 6.4ns t PZLSwitching Characteristicsover recommended operating free-air temperature range,V CCA=5V±0.5V(unless otherwise noted)(see Figure1)V CC=1.8V V CC=2.5V V CC=3.3V V CC=5VFROM TO±0.15V±0.2V±0.3V±0.5V PARAMETER UNIT (INPUT)(OUTPUT)MIN MAX MIN MAX MIN MAX MIN MAX t PLHA B 1.521.418.80.760.4 4.2nst PHLt PLHB A0.770.4 4.80.3 4.50.3 4.3nst PHLt PHZOE A0.3 5.40.3 5.40.3 5.40.3 5.4ns t PLZt PHZOE B228.7 1.89.7 1.480.7 5.7ns t PLZt PZHOE A0.7 6.40.7 6.40.7 6.40.7 6.4ns t PZLt PZHOE B 1.527.6 1.311.418.10.96ns t PZLOperating CharacteristicsT A=25�CV CCA=V CCA=V CCA=V CCA=TEST VCCB =1.8V V CCB=2.5V V CCB=3.3V V CCB=5VPARAMETER UNIT CONDITIONSTYP TYP TYP TYPA-port input,B-port output2223C pdA(1)CL =0,B-port input,A-port output18191922f=10MHz,pFA-port input,B-port output18192022t r=t f=1nsC pdB(1)B-port input,A-port output2222(1)Power dissipation capacitance per transceiverCopyright©2008–2013,Texas Instruments Incorporated Submit Documentation Feedback7V OH V OLLOAD CIRCUIT × V CCOOpenOutput Control (low-level enabling)Output Waveform 1S1 at 2 × V CCO (see Note B)Output Waveform 2S1 at GND (see Note B)0 V0 VV CCI0 VV CCAV CCOVOLTAGE WAVEFORMS PROPAGATION DELAY TIMESVOLTAGE WAVEFORMS PULSE DURATIONVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMESInputt pd t PLZ /t PZL t PHZ /t PZHOpen 2 × V CCO GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, Z O = 50 Ω, dv/dt ≥ 1 V/ns,dv/dt ≥1 V/ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .H.V CCI is the V CC associated with the input port.I.V CCO is the V CC associated with the output port.J.All parameters and waveforms are not applicable to all devices.1.8 V ± 0.15 V2.5 V ± 0.2 V3.3 V ± 0.3 V 5 V ± 0.5 V2 k Ω2 k Ω2 k Ω2 k ΩV CCO R L 0.15 V 0.15 V 0.3 V 0.3 VV TP C L 15 pF 15 pF 15 pF 15 pFSN74LVCH16T245-EPSCES726A –NOVEMBER 2008–REVISED NOVEMBER 2013PARAMETER MEASUREMENT INFORMATIONFigure 1.Load Circuit and Voltage Waveforms8Submit Documentation Feedback Copyright ©2008–2013,Texas Instruments IncorporatedPACKAGING INFORMATION(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andAddendum-Page 1continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.OTHER QUALIFIED VERSIONS OF SN74LVCH16T245-EP :•Catalog: SN74LVCH16T245NOTE: Qualified Version Definitions:•Catalog - TI's standard catalog productAddendum-Page 2MECHANICAL DATAMTSS003D – JANUARY 1995 – REVISED JANUARY 1998POST OFFICE BOX 655303 •DALLAS, TEXAS 75265DGG (R-PDSO-G**)PLASTIC SMALL-OUTLINE PACKAGE4040078/F 12/9748 PINS SHOWN0,250,15 NOMGage Plane6,006,208,307,900,750,50Seating Plane250,270,1724A4811,20 MAXM0,080,100,500°–8°5614,1013,9048DIM A MAXA MIN PINS **12,4012,606417,1016,900,150,05NOTES: A.All linear dimensions are in millimeters.B.This drawing is subject to change without notice.C.Body dimensions do not include mold protrusion not to exceed 0,15.D.Falls within JEDEC MO-153IMPORTANT NOTICE AND DISCLAIMERTI PROVIDES TECHNICAL AND RELIABILITY DATA(INCLUDING DATASHEETS),DESIGN RESOURCES(INCLUDING REFERENCE DESIGNS),APPLICATION OR OTHER DESIGN ADVICE,WEB TOOLS,SAFETY INFORMATION,AND OTHER RESOURCES“AS IS”AND WITH ALL FAULTS,AND DISCLAIMS ALL WARRANTIES,EXPRESS AND IMPLIED,INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY,FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products.You are solely responsible for(1)selecting the appropriate TI products for your application,(2)designing,validating and testing your application,and(3)ensuring your application meets applicable standards,and any other safety,security,or other requirements.These resources are subject to change without notice.TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource.Other reproduction and display of these resources is prohibited.No license is granted to any other TI intellectual property right or to any third party intellectual property right.TI disclaims responsibility for,and you will fully indemnify TI and its representatives against,any claims, damages,costs,losses,and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale(/legal/termsofsale.html)or other applicable terms available either on or provided in conjunction with such TI products.TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.Mailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright© 2020,Texas Instruments Incorporated。
模拟器件TI半导体TI数字信号处理德州仪器处理器宽带RFIF和数字音频广播
LM2903DR TI2,500茂百兴LM2903PWR TI2,000茂百兴LM3S1601-IQC50-A2T TI1,000茂百兴LM3S1607-IQR50-A0T TI1,500茂百兴LM3S1911-IQC50-A2T TI1,000茂百兴LM3S1968-IQC50-A2T TI1,000茂百兴LM3S2793-IQC80-C3T TI1,000茂百兴LM3S2965-IQC50-A2T TI1,000茂百兴LM3S3749-IQC50-A0T TI1,000茂百兴LM3S6911-IQC50-A2T TI1,000茂百兴LM3S9B90-IQC80-C3T TI1,000茂百兴LM3S9B92-IQC80-C1TI90茂百兴LM3S9B92-IQC80-C3TI90茂百兴LM4040C50IDBZR TI3,000茂百兴LM4041C12IDCKR TI3,000茂百兴LMV321IDBVR TI3,000茂百兴LMV324IPWR TI2,000茂百兴LMV331IDCKR TI3,000茂百兴LT1013DDR TI2,500茂百兴MAX3221CDBR TI2,000茂百兴MAX3221CPWR TI2,000茂百兴MAX3221IPWR TI2,000茂百兴MAX3223ECDBR TI2,000茂百兴MAX3232CDBR TI2,000茂百兴MAX3232CPWR TI2,000茂百兴MAX3232ECDBR TI2,000茂百兴MAX3232IPWR TI2,000茂百兴MAX3238EIPWR TI2,000茂百兴MAX3243CDBR TI2,000茂百兴MAX3243CPWR TI2,000茂百兴MAX3243ECDBR TI2,000茂百兴MAX3243ECPWR TI2,000茂百兴MSC1211Y5PAGR TI1,500茂百兴MSP430F1232IPWR TI2,000茂百兴MSP430F135IPMR TI1,000茂百兴MSP430F149IPMR TI1,000茂百兴MSP430F1611IPMR TI1,000茂百兴MSP430F1612IPMR TI1,000茂百兴MSP430F169IPMR TI1,000茂百兴MSP430F2001IPWR TI2,000茂百兴MSP430F2011TPWR TI2,000茂百兴MSP430F2132IPMR TI2,000茂百兴MSP430F2232IDAR TI2,000茂百兴MSP430F2252IRHAR TI2,500茂百兴MSP430F413IPMR TI1,000茂百兴MSP430F4250IRGZR TI2,500茂百兴MSP430F5418IPNR TI1,000茂百兴ONET1101LRGER TI3,000茂百兴ONET8501PRGTR TI3,000茂百兴ONET8501VRGPR TI3,000茂百兴OPA2131UA TI2,500茂百兴OPA2132UA TI2,500茂百兴OPA2134UA TI2,500茂百兴OPA2227UA TI2,500茂百兴OPA2244EA TI2,500茂百兴OPA2277UA TI2,500茂百兴OPA2335AIDR TI2,500茂百兴OPA2343EA/2K5TI2,500茂百兴OPA2348AIDCNR TI3,000茂百兴OPA2348AIDR TI3,000茂百兴OPA2349EA/3K TI3,000茂百兴OPA2350UA TI2,500茂百兴OPA2354AIDGKR TI2,500茂百兴OPA2357AIDGSR TI2,500茂百兴OPA2364AIDGKR TI2,500茂百兴OPA2364IDGKR TI2,500茂百兴OPA277AIDRMR TI3,000茂百兴OPA277U TI2,500茂百兴OPA277UA TI2,500茂百兴OPA334AIDBVR TI3,000茂百兴OPA335AIDBVR TI3,000茂百兴OPA336N TI3,000茂百兴OPA340UA/2K5TI2,500茂百兴OPA348AIDBVR TI3,000茂百兴OPA361AIDCKR TI3,000茂百兴OPA374AIDBVR TI3,000茂百兴OPA376AIDBVR TI3,000茂百兴OPA4227UA/2K5TI2,500茂百兴OPA4340UA/2k5TI2,500茂百兴OPA846IDBVR TI3,000茂百兴PCI1510PGE TI60茂百兴PCI1520ZHK TI90茂百兴PCI2040PGE TI60茂百兴PCI2050BIPDV TI36茂百兴PCI2050BIZHK TI450茂百兴PCI2050BPDV TI360茂百兴PCI2050BZHK TI450茂百兴PCI2050IBPDV TI360茂百兴PCI2250PCM TI24茂百兴PCI8402ZHK TI90茂百兴PCI8412ZHK TI90茂百兴PCM1742KE/2K TI2,000茂百兴PCM1753DBQR TI2,000茂百兴PCM1754DBQR TI2,000茂百兴PCM1755DBQR TI2,000茂百兴PCM1808PWR TI2,000茂百兴PCM4104PFBR TI2,000茂百兴PCM4204PAPR TI1,500茂百兴PTH08T220WAZT TI250茂百兴PTH08T260WAZT TI250茂百兴REF3025AIDBZR TI3,000茂百兴REF3030AIDBZR TI3,000茂百兴REF3033AIDBZR TI3,000茂百兴SN65176BDR TI2,500茂百兴SN65220DBVR TI3,000茂百兴SN65240PWR TI2,000茂百兴SN65HVD10DR TI2,500茂百兴SN65HVD11DR TI2,500茂百兴SN65HVD230DR TI2,500茂百兴SN65HVD23DR TI2,500茂百兴SN65HVD251DR TI2,500茂百兴SN65HVD3082EDR TI2,500茂百兴SN65HVD3088EDGKR TI2,500茂百兴SN65HVD33DR TI2,500茂百兴SN65LVDS2DBVR TI3,000茂百兴SN65MLVD200ADR TI2,500茂百兴SN7406DR TI2,500茂百兴SN7407DR TI2,500茂百兴SN74ABTE16246DGGR TI2,000茂百兴SN74AC14PWR TI2,000茂百兴SN74AHC14PWR TI2,000茂百兴SN74AHC1G14DBVR TI3,000茂百兴SN74AHCT08DGVR TI2,000茂百兴SN74AHCT132DR TI2,500茂百兴SN74ALVC164245DLR TI1,000茂百兴SN74ALVCH162244GR TI2,000茂百兴SN74ALVCH162373GR TI2,000茂百兴SN74AUP1G125DCKR TI3,000茂百兴SN74AVC2T45DCUR TI3,000茂百兴SN74CB3Q3257PWR TI2,000茂百兴SN74CBTLV3125PWR TI2,000茂百兴SN74HC14DR TI2,500茂百兴SN74HC164PWR TI2,000茂百兴SN74HC165DR TI2,500茂百兴SN74HC590ADR TI2,500茂百兴SN74HCT541PWR TI2,000茂百兴SN74LV07APWR TI2,000茂百兴SN74LV08APWR TI2,000茂百兴SN74LV14APWR TI2,000茂百兴SN74LV164APWR TI2,000茂百兴SN74LV244ADWR TI2,000茂百兴SN74LV244APWR TI2,000茂百兴SN74LV32APWR TI2,000茂百兴SN74LV595APWR TI2,000茂百兴SN74LV595ARGYR TI1,000茂百兴SN74LVC04ADR TI2,500茂百兴SN74LVC04APWR TI2,000茂百兴SN74LVC08APWR TI2,000茂百兴SN74LVC125APWR TI2,000茂百兴SN74LVC138APWR TI2,000茂百兴SN74LVC14ADR TI2,500茂百兴SN74LVC14APWR TI2,000茂百兴SN74LVC16244ADLR TI1,000茂百兴SN74LVC16245ADGGR TI2,000茂百兴SN74LVC16373ADGGR TI2,000茂百兴SN74LVC1G07DCKR TI3,000茂百兴SN74LVC1G125DCKR TI3,000茂百兴SN74LVC244APWR TI2,000茂百兴SN74LVC245ADGVR TI2,000茂百兴SN74LVC245APWR TI2,000茂百兴SN74LVC2G17DBVR TI3,000茂百兴SN74LVC32APWR TI2,000茂百兴SN74LVC4245APWR TI2,000茂百兴SN74LVC8T245PWR TI2,000茂百兴SN74LVCH162244AGR TI2,000茂百兴SN74LVCH16244ADGGR TI2,000茂百兴SN74LVCH16245ADLR TI1,000茂百兴SN74LVCHR16245AGR TI2,000茂百兴SN74LVTH125PWR TI2,000茂百兴SN74LVTH162244DGGR TI2,000茂百兴SN74LVTH16244ADGGR TI2,000茂百兴SN74LVTH16244ADLR TI1,000茂百兴SN74LVTH16245ADLR TI1,000茂百兴SN74LVTH244APWR TI2,000茂百兴SN75240PWR TI2,000茂百兴SN75ALS1178NSR TI2,000茂百兴SN75LBC176ADR TI2,500茂百兴TAS1020BPFBR TI1,000茂百兴TAS5707PHPR TI1,000茂百兴TFP410PAP TI160茂百兴THS7314DR TI2,500茂百兴THS7316DR TI2,500茂百兴THS7374IPWR TI2,000茂百兴THS8134BCPHP TI250茂百兴THS8200PFP TI96茂百兴TL16C2550PFBR TI1,000茂百兴TL16C550CIPTR TI1,000茂百兴TL16C550CPTR TI1,000茂百兴TL16C550CPTR TI1,000茂百兴TL16C554AFNR TI250茂百兴TL16C554AIPNR TI1,000茂百兴TL16C554APNR TI1,000茂百兴TL16C752BPTR TI1,000茂百兴TL431AIDBVR TI3,000茂百兴TL431IDBVR TI3,000茂百兴TL7705ACDR TI2,500茂百兴TL7712ACDR TI2,500茂百兴TLC1543CDWR TI2,000茂百兴TLC2252AIDR TI2,500茂百兴TLC2252CDR TI2,500茂百兴TLC2254IDR TI2,500茂百兴TLC2262CDR TI2,500茂百兴TLC2272CDR TI2,500茂百兴TLC2274ACDR TI2,500茂百兴TLC2543CDBR TI2,000茂百兴TLC2543CDWR TI2,000茂百兴TLC25M2CDR TI2,500茂百兴TLC3548IDWR TI2,000茂百兴TLC3548IPWR TI2,000茂百兴TLC3702IDR TI2,500茂百兴TLC5510INSR TI2,000茂百兴TLC555CDR TI2,500茂百兴TLC555IDR TI2,500茂百兴TLC5602CDWR TI2,000茂百兴TLC5946RHBR TI3,000茂百兴TLC7701IDR TI2,500茂百兴TLE2062ACDR TI2,500茂百兴TLE2072CDR TI2,500茂百兴TLK1501IRCPR TI1,000茂百兴TLV1543CDWR TI2,000茂百兴TLV2211IDBVR TI3,000茂百兴TLV2231IDBVR TI3,000茂百兴TLV2371IDBVR TI3,000茂百兴TLV2372IDGKR TI2,500茂百兴TLV2432AIDR TI2,500茂百兴TLV2442CDR TI2,500茂百兴TLV2462IDGKR TI2,500茂百兴TLV2556IPWR TI2,000茂百兴TLV272CDR TI2,500茂百兴TLV274CPWR TI2,000茂百兴TLV320AIC1106PWR TI2,000茂百兴TLV320AIC12IDBTR TI2,000茂百兴TLV320AIC3104IRHBR TI3,000茂百兴TLV320AIC31IRHBR TI3,000茂百兴TLV320AIC32IRHBR TI3,000茂百兴TLV320AIC33IZQER TI2,500茂百兴TLV431ACDBVR TI3,000茂百兴TMDS442PNPR TI1,000茂百兴TMP100NA TI3,000茂百兴TMP101NA TI3,000茂百兴TMP20AIDCKR TI3,000茂百兴TMP275AIDR TI2,500茂百兴TMP411ADR TI2,500茂百兴TMP75AIDGKR TI2,500茂百兴TMP75AIDR TI2,500茂百兴TMS320C32PCM50TI24茂百兴TMS320C6205ZHK200TI90茂百兴TMS320C6211BZFN167TI40茂百兴TMS320C6713BGDP225TI40茂百兴TMS320C6713BZDP225TI40茂百兴TMS320C6713BZDP300TI40茂百兴TMS320C6727BZDH300TI90茂百兴TMS320DM355ZCE216TI160茂百兴TMS320DM355ZCE270TI160茂百兴TMS320DM365ZCE27TI160茂百兴TMS320DM365ZCE30TI160茂百兴TMS320DM642AZDK6TI60茂百兴TMS320DM642AZDK7TI60茂百兴TMS320DM642AZNZ7TI40茂百兴TMS320DM6441AZWT TI90茂百兴TMS320DM6446AZWT TI90茂百兴TMS320DM6467TZUT1TI84茂百兴TMS320DM648ZUT9TI84茂百兴TMS320F28015PZA TI90茂百兴TMS320F2802PZA TI90茂百兴TMS320F2806PZA TI90茂百兴TMS320F2808PZA TI90茂百兴TMS320F2810PBKA TI90茂百兴TMS320F2811PBKA TI90茂百兴TMS320F2812GHHA TI160茂百兴TMS320F2812PGFA TI40茂百兴TMS320F28335PGFA TI40茂百兴TMS320LC549PGE-80TI60茂百兴TMS320LF2401AVFA TI250茂百兴TMS320LF2406APZA TI90茂百兴TMS320LF2407APGEA TI60茂百兴TMS320VC33PGE120TI60茂百兴TMS320VC33PGE150TI60茂百兴TMS320VC33PGEA120TI60茂百兴TMS320VC5402PGE100TI60茂百兴TMS320VC5409APGE16TI60茂百兴TMS320VC5409PGE80TI60茂百兴TMS320VC5410APGE16TI60茂百兴TMS32C6713BGDPA200TI40茂百兴TPA2005D1DRBR TI3,000茂百兴TPA2008D2PWPR TI2,000茂百兴TPA2010D1YZFR TI2,500茂百兴TPA2012D2RTJR TI3,000茂百兴TPA2013D1RGPR TI3,000茂百兴TPA3001D1PWPR TI2,000茂百兴TPA3007D1PWR TI2,000茂百兴TPA3100D2PHPR TI1,000茂百兴TPA3101D2PHPR TI1,000茂百兴TPA3110D2PWPR TI2,000茂百兴TPA3113D2PWPR TI2,000茂百兴TPA3120D2PWPR TI2,000茂百兴TPA3121D2PWPR TI2,000茂百兴TPA3123D2PWPR TI2,000茂百兴TPA3123D2PWPR TI2,000茂百兴TPA3124D2PWPR TI2,000茂百兴TPA6011A4PWPR TI2,000茂百兴TPA6110A2DGNR TI2,500茂百兴TPA6111A2DGNR TI2,500茂百兴TPA6111A2DR TI2,500茂百兴TPA6112A2DGQR TI2,500茂百兴TPA6132A2RTER TI3,000茂百兴TPA6204A1DRBR TI3,000茂百兴TPA6211A1DGNR TI2,500茂百兴TPA6211A1DRBR TI3,000茂百兴TPD12S520DBTR TI2,000茂百兴TPIC6595DWR TI2,000茂百兴TPIC6B595DWR TI2,000茂百兴TPS2034DR TI2,500茂百兴TPS2041BDBVR TI3,000茂百兴TPS2041BDR TI2,500茂百兴TPS2042BDGNR TI2,500茂百兴TPS2042BDR TI2,500茂百兴TPS2044BDR TI2,500茂百兴TPS2051BDBVR TI3,000茂百兴TPS2051BDGNR TI2,500茂百兴TPS2051BDR TI2,500茂百兴TPS2052BDR TI2,500茂百兴TPS2061DGN TI80茂百兴TPS2105DBVR TI3,000茂百兴TPS2113APWR TI2,000茂百兴TPS2115PWR TI2,000茂百兴TPS2320IPWR TI2,000茂百兴TPS2331IPWR TI2,000茂百兴TPS2350PW TI2,000茂百兴TPS23750PWPR TI2,000茂百兴TPS23753PWR TI2,000茂百兴TPS23754PWPR TI2,000茂百兴TPS2375DR TI2,500茂百兴TPS23770PWPR TI2,000茂百兴TPS2390DGKR TI2,500茂百兴TPS2391DGKR TI2,500茂百兴TPS2551DRVR TI3,000茂百兴TPS2553DBVR TI3,000茂百兴TPS2553DRVR TI3,000茂百兴TPS2812DR TI2,500茂百兴TPS2814DR TI2,500茂百兴TPS2814PWR TI2,000茂百兴TPS2829DBVR TI3,000茂百兴TPS3106E09DBVR TI3,000茂百兴TPS3106K33DBVR TI3,000茂百兴TPS3305-18DR TI2,500茂百兴TPS3307-18DR TI2,500茂百兴TPS3619-33DGKR TI2,500茂百兴TPS3620-33DGKR TI2,500茂百兴TPS3707-33DR TI2,500茂百兴TPS3801E18DCKR TI3,000茂百兴TPS3801J25DCKR TI3,000茂百兴TPS3801K33DCKR TI3,000茂百兴TPS3803-01DCKR TI3,000茂百兴TPS3808G01DBVR TI3,000茂百兴TPS3808G18DBVR TI3,000茂百兴TPS3808G33DBVR TI3,000茂百兴TPS3809K33DBVR TI3,000茂百兴TPS3820-33DBVR TI3,000茂百兴TPS3823-33DBVR TI3,000茂百兴TPS3824-33DBVR TI3,000茂百兴TPS3825-33DBVR TI3,000茂百兴TPS3828-33DBVR TI3,000茂百兴TPS3828-50DBVR TI3,000茂百兴TPS40001DGQR TI2,500茂百兴TPS40009DGQR TI2,500茂百兴TPS40021PWPR TI2,000茂百兴TPS40041DRBR TI3,000茂百兴TPS40055PWPR TI2,000茂百兴TPS40056PWPR TI2,000茂百兴TPS40057PWPR TI2,000茂百兴TPS40060PWPR TI2,000茂百兴TPS40061PWPR TI2,000茂百兴TPS40071PWPR TI2,000茂百兴TPS40077PWPR TI2,000茂百兴TPS40100RGER TI3,000茂百兴TPS40101RGER TI3,000茂百兴TPS40130DBTR TI2,000茂百兴TPS40190DRCR TI2,500茂百兴TPS40192DRCR TI3,000茂百兴TPS40200DR TI2,500茂百兴TPS40210DGQR TI2,500茂百兴TPS40222DRPR TI3,000茂百兴TPS51100DGQR TI2,500茂百兴TPS51116PWPR TI2,000茂百兴TPS51116RGER TI3,000茂百兴TPS51117RGYR TI3,000茂百兴TPS51120RHBR TI3,000茂百兴TPS51200DRCR TI3,000茂百兴TPS51218DSCR TI3,000茂百兴TPS54010PWPR TI2,000茂百兴TPS5410DR TI2,500茂百兴TPS54110PWPR TI2,000茂百兴TPS54140DGQR TI2,500茂百兴TPS54160DGQR TI2,500茂百兴TPS5420DR TI2,500茂百兴TPS54226PWPR TI2,000茂百兴TPS54231DR TI2,500茂百兴TPS54283PWPR TI2,000茂百兴TPS54286PWPR TI2,000茂百兴TPS54292PWPR TI2,000茂百兴TPS5430DDAR TI2,500茂百兴TPS54310PWPR TI2,000茂百兴TPS54314PWPR TI2,000茂百兴TPS54319RTER TI3,000茂百兴TPS54325PWPR TI2,000茂百兴TPS54331DR TI2,500茂百兴TPS54350PWPR TI2,000茂百兴TPS54357PWPR TI2,000茂百兴TPS54372PWPR TI2,000茂百兴TPS54380PWPR TI2,000茂百兴TPS54383PWPR TI2,000茂百兴TPS54386PWPR TI2,000茂百兴TPS54418RTER TI3,000茂百兴TPS5450DDAR TI2,500茂百兴TPS54550PWPR TI2,000茂百兴TPS54610PWPR TI2,000茂百兴TPS54612PWPR TI2,000茂百兴TPS54614PWPR TI2,000茂百兴TPS54616PWPR TI2,000茂百兴TPS54620RGYR TI3,000茂百兴TPS54672PWPR TI2,000茂百兴TPS54680PWPR TI2,000茂百兴TPS54910PWPR TI2,000茂百兴TPS54972PWPR TI2,000茂百兴TPS60150DRVR TI3,000茂百兴TPS60230RGTR TI3,000茂百兴TPS60231RGTR TI3,000茂百兴TPS60400DBVR TI3,000茂百兴TPS60403DBVR TI3,000茂百兴TPS60500DGSR TI2,500茂百兴TPS61020DRCR TI3,000茂百兴TPS61026DRCR TI3,000茂百兴TPS61030PWPR TI2,000茂百兴TPS61030RSAR TI2,000茂百兴TPS61032PWPR TI2,000茂百兴TPS61040DBVR TI3,000茂百兴TPS61041DBVR TI3,000茂百兴TPS61042DRBR TI3,000茂百兴TPS61045DRBR TI3,000茂百兴TPS61050YZGR TI3,000茂百兴TPS61070DDCR TI3,000茂百兴TPS61080DRCR TI3,000茂百兴TPS61081DRCR TI3,000茂百兴TPS61087DRCR TI3,000茂百兴TPS61090RSAR TI3,000茂百兴TPS61097-33DBVR TI3,000茂百兴TPS61160DRVR TI3,000茂百兴TPS61161DRVR TI3,000茂百兴TPS61165DRVR TI3,000茂百兴TPS62000DGSR TI2,500茂百兴TPS62040DGQR TI2,500茂百兴TPS62040DRCR TI3,000茂百兴TPS62046DGQR TI2,500茂百兴TPS62050DGSR TI2,500茂百兴TPS62060DSGR TI3,000茂百兴TPS62110RSAR TI3,000茂百兴TPS62111RSAR TI3,000茂百兴TPS62200DBVR TI3,000茂百兴TPS62201DBVR TI3,000茂百兴TPS62202DBVR TI3,000茂百兴TPS62203DBVR TI3,000茂百兴TPS62204DBVR TI3,000茂百兴TPS62260DDCR TI3,000茂百兴TPS62260DRVR TI3,000茂百兴TPS62290DRVR TI3,000茂百兴TPS62410DRCR TI3,000茂百兴TPS62510DRCR TI3,000茂百兴TPS62590DRVR TI3,000茂百兴TPS63000DRCR TI3,000茂百兴TPS63001DRCR TI3,000茂百兴TPS63020DSJR TI3,000茂百兴TPS63021DSJR TI3,000茂百兴TPS63030DSKR TI3,000茂百兴TPS63031DSKR TI3,000茂百兴TPS63700DRCR TI3,000茂百兴TPS64200DBVR TI3,000茂百兴TPS64202DBVR TI3,000茂百兴TPS65020RHAR TI2,500茂百兴TPS65021RHAR TI2,500茂百兴TPS65023RSBR TI3,000茂百兴TPS650243RHBR TI3,000茂百兴TPS65053RGER TI3,000茂百兴TPS65120RGTR TI3,000茂百兴TPS65150PWPR TI2,000茂百兴TPS65251RHAR TI2,500茂百兴TPS65920BZCHR TI2,000茂百兴TPS65930BZCHR TI1,000茂百兴TPS6755IDR TI2,500茂百兴TPS70102PWPR TI2,000茂百兴TPS70302PWPR TI2,000茂百兴TPS7101QDR TI2,500茂百兴TPS71501DCKR TI3,000茂百兴TPS71530DCKR TI3,000茂百兴TPS71533DCKR TI3,000茂百兴TPS71550DCKR TI3,000茂百兴TPS71701DCKR TI3,000茂百兴TPS72301DBVR TI3,000茂百兴TPS72501DCQR TI2,500茂百兴TPS72515DCQR TI2,500茂百兴TPS73018DBVR TI3,000茂百兴TPS73033DBVR TI3,000茂百兴TPS73101DBVR TI3,000茂百兴TPS73115DBVR TI3,000茂百兴TPS73130DBVR TI3,000茂百兴TPS73133DBVR TI3,000茂百兴TPS73201DBVR TI3,000茂百兴TPS73601DBVR TI3,000茂百兴TPS73601DCQR TI3,000茂百兴TPS73633DRBR TI3,000茂百兴TPS73701DCQR TI2,500茂百兴TPS73701DRBR TI3,000茂百兴TPS74401RGWR TI3,000茂百兴TPS74701DRCR TI3,000茂百兴TPS74801DRCR TI3,000茂百兴TPS75201QPWPR TI2,000茂百兴TPS76050DBVR TI3,000茂百兴TPS76301DBVR TI3,000茂百兴TPS76318DBVR TI3,000茂百兴TPS76333DBVR TI3,000茂百兴TPS76350DBVR TI3,000茂百兴TPS76633DR TI2,500茂百兴TPS76650DR TI2,500茂百兴TPS76701QPWPR TI2,000茂百兴TPS767D318PWPR TI2,000茂百兴TPS76801QDR TI2,500茂百兴TPS76933DBVR TI3,000茂百兴TPS77601PWPR TI2,000茂百兴TPS77633DR TI2,500茂百兴TPS77701PWPR TI2,000茂百兴TPS77801PWPR TI2,000茂百兴TPS78833DBVR TI3,000茂百兴TPS79101DBVR TI3,000茂百兴TPS79301DBVR TI2,500茂百兴TPS79318DBVR TI3,000茂百兴TPS793285DBVR TI3,000茂百兴TPS79328DBVR TI3,000茂百兴TPS79330DBVR TI3,000茂百兴TPS79333DBVR TI3,000茂百兴TPS79501DCQR TI2,500茂百兴TPS79533DCQR TI2,500茂百兴TPS79633DCQR TI2,500茂百兴TPS79730DCKR TI3,000茂百兴TPS79901DDCR TI3,000茂百兴TS3USB221DRCR TI3,000茂百兴TS5A3167DBVR TI3,000茂百兴TSB12LV26PZT TI90茂百兴TSB43AB22APDT TI90茂百兴TSC2003IPWR TI2,500茂百兴TSC2007IPWR TI2,000茂百兴TSC2007IYZGR TI3,000茂百兴TSC2017IYZGR TI3,000茂百兴TSC2046IPWR TI2,500茂百兴TUSB2046BIVFR TI1,000茂百兴TUSB2046BVFR TI1,000茂百兴TUSB3200ACPAHR TI1,500茂百兴TUSB3410VF TI250茂百兴TVP5150AM1PBSR TI1,000茂百兴TVP5154APNPR TI1,000茂百兴TVP5158IPNPR TI1,000茂百兴TVP5158PNPR TI1,000茂百兴UC2637DWTR TI2,000茂百兴UC2825ADWTR TI2,000茂百兴UC2842AD8TR TI2,500茂百兴UC2843AD8TR TI2,500茂百兴UC2844AD8TR TI2,500茂百兴UC3637DWTR TI2,000茂百兴UC3825ADWTR TI2,000茂百兴UC3843AD8TR TI2,500茂百兴UC3845AD8TR TI2,500茂百兴UC3845AN TI50茂百兴UC3846DWTR TI2,000茂百兴UC3846N TI25茂百兴UC3854AN TI25茂百兴UC3854BDWTR TI2,000茂百兴UC3854N TI25茂百兴UC3902DTR TI2,500茂百兴UCC27223PWPR TI2,000茂百兴UCC27324DGNR TI2,500茂百兴UCC27324DR TI2,500茂百兴UCC27423DR TI2,500茂百兴UCC27424DR TI2,500茂百兴UCC2800DTR TI2,500茂百兴UCC28060DR TI2,500茂百兴UCC28061DR TI2,500茂百兴UCC28070PWR TI2,000茂百兴UCC2808APWTR-2TI2,000茂百兴UCC2809DTR-1TI2,500茂百兴UCC2809PTR-1TI2,500茂百兴UCC2818DTR TI2,500茂百兴UCC28600DR TI2,500茂百兴UCC2891PWR TI2,000茂百兴UCC2894DR TI2,500茂百兴UCC2895DWTR TI2,000茂百兴UCC2897APWR TI2,000茂百兴UCC28C43DR TI2,500茂百兴UCC28C44DR TI2,500茂百兴UCC28C45DR TI2,500茂百兴UCC37324DGNR TI2,500茂百兴UCC3801DTR TI2,500茂百兴UCC3807DTR-3TI2,500茂百兴UCC3808DTR-2TI2,500茂百兴UCC3818PWTR TI2,000茂百兴UCC3895DWTR TI2,000茂百兴UCC3895PWTR TI2,000茂百兴UCC3919DTR TI2,500茂百兴UCC3946DTR TI2,500茂百兴ULN2003ADR TI2,500茂百兴ULN2003AIDR TI2,500茂百兴ULN2003AN TI25茂百兴XIO1100GGB TI160茂百兴XTR116UA/2K5TI2,500茂百兴。
LCD在矿用保护器中的应用
LCD在矿用保护器中的应用【摘要】lcd模块是嵌入式设备常用的显示模块，本文以矿用电力综合保护器为背景，以基于arm体系结构的lpc2292微处理器为平台，以ocmj4*8c 液晶显示模块为对象，设计了嵌入式系统中lcd 的串/并行两种传输模式来实现字符，汉字和图形的显示。
lcd 得到了很好的显示效果，从而证明了该电路的可行性。
【关键词】lpc2292；串行传输；并行传输；lcd；保护器0 引言随着液晶显示技术的发展，lcd（液晶显示器）模块已成为家电、工业控制仪器仪表和其他电子产品的重要组成部分。
矿用电力综合保护器（以下简称保护器）就是一款利用lcd显示中文图形操作界面的仪器，它是煤矿电力开关专用的多功能综合保护装置，放在矿井下，对下属电网和设备起到综合保护作用。
虽然此保护器是装在隔爆型高压配电装置内使用的，但由于其应用环境比较恶劣， lcd 的显示还是会受到一定的影响，所以选择一个高效，稳定的传输方式是很必要的。
保护器采用lpc2292作为核心处理器，本文主要阐述了lpc2292控制lcd显示的串/并行两种传输模式，讨论了两种接口的电平匹配问题，给出了lcd部分显示技巧和常见问题，分析了液晶显示器件串/并行工作时序以及给出了lcd与lpc2292连接的串行接口电路。
1 ocmj4*8c 液晶显示模块的主要特点及引脚定义ocmj4*8c 液晶显示模块是金鹏电子有限公司生产的c系列液晶显示器产品中的一款，其主要特性如下：1）ocmj4*8c 液晶显示模块可以显示字母、数字符号、中文字型及图形；2）ocmj4*8c 液晶显示模块提供三种控制接口，分别是8位微处理器接口，4位微处理器接口及串行接口[1]；3）ocmj4*8c 液晶显示模块具有上/下/左/右移动，当前显示屏幕及清除屏幕等命令；4）ocmj4*8c 液晶显示模块使用+5v单电源，同时由模块内部提供显示驱动负电压，简化了系统电源的设计，该模块还具有led背光源。
常用数字元件
SN74AHC02DR：四2输入正或非门
SN74AHC02N：四2输入正或非门
SN74AHC1G02DBVR：单2输入正或非门
SN74AHC1G02DCKT：单2输入正或非门
SN74AHCT02D：四2输入正或非门
SN74AHCT02DR：四2输入正或非门
SN74AHC00DR：四2输入正与非门
SN74AHC00N：四2输入正与非门
SN74AHC132PW：四2输入施密特触发正与非门
SN74AHC1G00DBVR：单2输入正与非门
SN74AHC1G00DCKR：单2输入正与非门
SN74AHC1G00DCKT：单2输入正与非门
SN74AHCT00D：四2输入正与非门
数字逻辑器件 异或门
CD4070BE：四异或门
SN74AC86D：四2输入异或门
SN74ACT86N：四2输入异或门
SN74AHC1G86DBVR：单2输入异或门
SN74AHC1G86DCKT：单2输入异或门
SN74AHC86D：四2输入异或门
SN74AHC86N：四2输入异或门
SN74HC00N：四2输入正与非门
SN74HC132D：四2输入施密特触发正与非门
SN74HC20N：双4输入正与非门
SN74HCT00D：四2输入正与非门
SN74HCT00N：四2输入正与非门
SN74LVC10AD：三3输入正与非门
SN74LVC1G00DBVR：单2输入正与非门
SN74LVC1G02DCKR：单2输入正或非门
SN74LVC1G02DCKT：单2输入正或非门
电平转换芯片精华版
Part Number Sub Family Vcc range (V) SN10KHT5541 ECL/TTL 转换器SN10KHT5543 ECL/TTL 转换器SN10KHT5574 ECL/TTL 转换器SN10KHT5578 ECL/TTL 转换器SN74GTL2007 GTL/TTL 转换器 3 to 3.6SN74GTL2107 GTL/TTL 转换器 3 to 3.3SN74GTL3004 GTL/TTL 转换器 3 to 3.6SN74AUP1T57 单电源转换器 2.3 to 3.6 SN74AUP1T58 单电源转换器 2.3 to 3.6 SN74AUP1T97 单电源转换器 2.3 to 3.6 SN74AUP1T98 单电源转换器 2.3 to 3.6 CD40109B 双电源转换器CD4504B 双电源转换器CD4504B-EP 双电源转换器SN74ALVC164245 双电源转换器SN74AVC16T245 双电源转换器 1.2 to 3.6 SN74AVC16T245-Q1 双电源转换器 1.2 to 3.6 SN74AVC1T45 双电源转换器 1.2 to 3.6 SN74AVC20T245 双电源转换器 1.2 to 3.6 SN74AVC24T245 双电源转换器SN74AVC2T245 双电源转换器 1.1 to 3.6 SN74AVC2T45 双电源转换器 1.2 to 3.6 SN74AVC32T245 双电源转换器SN74AVC4T245 双电源转换器 1.2 to 3.6 SN74AVC4T245-Q1 双电源转换器 1.2 to 3.6 SN74AVC4T774 双电源转换器 1.2 to 3.6 SN74AVC8T245 双电源转换器 1.2 to 3.6 SN74AVC8T245-Q1 双电源转换器 1.2 to 3.6 SN74AVCA164245 双电源转换器 1.4 to 3.6 SN74AVCAH164245 双电源转换器 1.4 to 3.6 SN74AVCB164245 双电源转换器 1.4 to 3.6 SN74AVCB324245 双电源转换器 1.4 to 3.6 SN74AVCBH164245 双电源转换器 1.4 to 3.6 SN74AVCBH324245 双电源转换器 1.4 to 3.6 SN74AVCH16T245 双电源转换器 1.2 to 3.6 SN74AVCH1T45 双电源转换器 1.2 to 3.6 SN74AVCH20T245 双电源转换器 1.2 to 3.6 SN74AVCH24T245 双电源转换器 1.2 to 3.6 SN74AVCH2T45 双电源转换器 1.2 to 3.6 SN74AVCH32T245 双电源转换器 1.2 to 3.6 SN74AVCH4T245 双电源转换器 1.2 to 3.6 SN74AVCH4T245-EP 双电源转换器 1.2 to 3.6SN74AVCH8T245 双电源转换器 1.2 to 3.6SN74LVC1T45 双电源转换器 1.65 to 5.5SN74LVC1T45-EP 双电源转换器 1.65 to 5.5SN74LVC1T45-Q1 双电源转换器 1.65 to 5.5SN74LVC2T45 双电源转换器 1.65 to 5.5SN74LVC4245A 双电源转换器 SplitRailSN74LVC8T245 双电源转换器 1.65 to 5.5SN74LVC8T245-EP 双电源转换器 1.65 to 5.5SN74LVCC3245A 双电源转换器 SplitRailSN74LVCC4245A 双电源转换器SN74LVCH16T245 双电源转换器 1.65 to 5.5SN74LVCH16T245-EP 双电源转换器 1.65 to 5.5TXB0101 双电源转换器TXB0102 双电源转换器TXB0104 双电源转换器 1.2 to 5.5TXB0104-Q1 双电源转换器 1.2 to 5.5TXB0106 双电源转换器 1.2 to 3.6 (A-port TXB0106-Q1 双电源转换器 1.2 to 3.6 (A-port TXB0108 双电源转换器TXS0101 双电源转换器TXS0102 双电源转换器 1.65 to 3.6 , TXS0104E 双电源转换器 1.65 to 3.6 , TXS0108E 双电源转换器 1.2 to 3.6 , 1 CF4320H 特定应用（CF卡、SD、MMC 和 I2C） -0.5 to 6.5SN74AVC2T872 特定应用（CF卡、SD、MMC 和 I2C） 1.1 to 3.6SN74AVC6T622 特定应用（CF卡、SD、MMC 和 I2C） 1.2 to 3.6SN74AVCA406 特定应用（CF卡、SD、MMC 和 I2C） 1.4 to 3.6SN74AVCA406E 特定应用（CF卡、SD、MMC 和 I2C） 1.2 to 3.6SN74AVCA406L 特定应用（CF卡、SD、MMC 和 I2C） -0.5 to 4.6SN74LV4320A 特定应用（CF卡、SD、MMC 和 I2C） 3 to 5.5TWL1200 特定应用（CF卡、SD、MMC 和 I2C） 1.1 to 3.6 TXS0206 特定应用（CF卡、SD、MMC 和 I2C） 1.1 to 3.6 TXS02612 特定应用（CF卡、SD、MMC 和 I2C） 1.1 to 3.6 TXS03121 特定应用（CF卡、SD、MMC 和 I2C）SN74LVC1T45 电压电平转换 1.65 to 5.5 SN74CB3T16210 转换总线开关 2.3 to 3.6 SN74CB3T16211 转换总线开关 2.3 to 3.6 SN74CB3T16212 转换总线开关 2.3 to 3.6 SN74CB3T1G125 转换总线开关 2.3 to 3.6 SN74CB3T3125 转换总线开关 2.3 to 3.6 SN74CB3T3245 转换总线开关 2.3 to 3.6 SN74CB3T3253 转换总线开关 2.3 to 3.6 SN74CB3T3257 转换总线开关 2.3 to 3.6 SN74CB3T3306 转换总线开关 2.3 to 3.6 SN74CB3T3384 转换总线开关SN74CBTD16210 转换总线开关 4.5 to 5.5 SN74CBTD16211 转换总线开关 4.5 to 5.5 SN74CBTD1G125 转换总线开关SN74CBTD1G384 转换总线开关SN74CBTD3305C 转换总线开关 4.5 to 5.5 SN74CBTD3306 转换总线开关 4.5 to 5.5 SN74CBTD3306C 转换总线开关 4.5 to 5.5 SN74CBTD3384 转换总线开关 4.5 to 5.5 SN74CBTD3384C 转换总线开关 4.5 to 5.5 SN74CBTD3861 转换总线开关 4.5 to 5.5 SN74TVC16222A 转换总线开关SN74TVC3010 转换总线开关SN74TVC3306 转换总线开关Voltage Nodes (V) Description具有三态输出的八路 ECL 至 TTL 转换器具有使能输出的八路 TTL 至 ECL 转换器具有 D 类边沿触发器和三态输出的八路 ECL 至 TTL 转换器具有 D 类边沿触发器和使能输出的八路 TTL 至 ECL 转换器12 位 GTL-/GTL/GTL+ 至 LVTTL 转换器12 位 GTL-/GTL/GTL+ 至 LVTTL 转换器可选 GTL 电压基准2.5,3.3 单电源电压转换器2.5,3.3 单电源电压转换器2.5,3.3 单电源电压转换器2.5,3.3 单电源电压转换器10, 15, 5 CMOS 四路低向高电压位转换器（20V 额定电压）10, 15, 5 用于 TTL 至 CMOS 或 CMOS 至 CMOS 转换的 CMOS 六路电压电平转换器 用于 TTL 到 CMOS 或 CMOS 到 CMOS 操作的 CMOS 六路电压电平转换器 1.8, 2.5, 2.7, 3.3 具有三态输出的 16 位 2.5V 至 3.3V/3.3V 至 5V 电平转换收发器具有可配置电压转换和 3 态输出的 16 位双电源总线收发器1.2, 1.5, 1.8,2.5,3.具有可配置电压转换的汽车类 16 位双电源总线收发器1.2, 1.5, 1.8,2.5,3.3.3 具有可配置电压转换和 3 态输出的单位双电源总线收发器具有可配置电压转换和 3 态输出的 20 位双电源总线收发器具有可配置电压转换和 3 态输出的 24 位双电源总线收发器具有可配置电压转换和三态输出的双位 2-DIR 引脚双电源总线收发器 具有可配置电压转换和 3 态输出的双位双电源总线收发器具有可配置电压转换和 3 态输出的 32 位双电源总线收发器具有可配置电压转换和 3 态输出的 4 位双电源总线收发器1.2, 1.5, 1.8,2.5,3.具有可配置电压转换和 3 态输出的汽车类 4 位双电源总线收发器1.2, 1.5, 1.8,2.5,3.具有可配置电压转换和 3 态输出的 4 位双电源总线收发器具有可配置电压转换和 3 态输出的 8 位双电源总线收发器具有可配置电压转换和三态输出的汽车类 8 位双电源总线收发器1.5, 1.8,2.5,3.3 具有可配置电压转换和 3 态输出的 16 位双电源总线收发器1.5, 1.8,2.5,3.3 具有可配置电压转换的 16 位双电源总线收发器1.5, 1.8,2.5,3.3 16 位双电源总线收发器，具有可配置 转换和三态输出具有可配置电压转换和三态输出的 32 位双电源总线收发器1.5, 1.8,2.5,3.3 16 位双电源总线收发器，具有可配置 电压转换和三态输出具有可配置电压转换和 3 态输出的 32 位双电源总线收发器具有可配置电压转换和 3 态输出的 16 位双电源总线收发器3.3 具有可配置电压转换和 3 态输出的单位双电源总线收发器具有可配置电压转换和三态输出的 20 位双电源总线收发器具有可配置电压转换和 3 态输出的 24 位双电源总线收发器3.3 具有可配置电压转换和 3 态输出的双位双电源总线收发器具有可配置电压转换和 3 态输出的 32 位双电源总线收发器具有可配置电压转换和 3 态输出的 4 位双电源总线收发器1.2, 1.5, 1.8,2.5,3.增强型产品 4 位双电源总线收发器， 具有可配置电压转换 和三态输出1.2, 1.5, 1.8, 2.5, 3.具有可配置电压转换和 3 态输出的 8 位双电源总线收发器具有可配置电压转换和 3 态输出的单位双电源总线收发器1.8,2.5,3.3, 5 增强型产品单比特双电源总线收发器，具有可配置电压转换和 三态输出SN74LVC1T45-Q15 具有可配置电压转换和 3 态输出的双位双电源收发器2.7, 5 /3.3 具有三态输出的八路总线收发器和 3.3V 至 5V 移位器1.8,2.5,3.3, 5 具有可配置电压转换和 3 态输出的 8 位双电源总线收发器1.8,2.5,3.3, 5 增强型产品 8 位双电源总线收发器， 具有可配置电压转换和三态输出5, 3.3 具有可调节输出电压和三态输出的八路总线收发器5, 3.3 具有可调节输出电压和三态输出的八路总线收发器1.8,2.5,3.3, 5 SN74LVCH16T2451.8,2.5,3.3, 5 增强型产品 16 位双电源总线收发器，具有可配置电压转换和三态输出具有自动方向感应和 +/-15kV ESD 保护的 1 位双向电压电平转换器具有自动方向感应和 +/-15kV ESD 保护的 2 位双向电压电平转换器具有自动方向感应和 +/-15kV ESD 保护的 4 位双向电压电平转换器具有自动方向感应和 +/-15kV ESD 保护的汽车类 4 位双向电压电平转换器具有自动方向感应和 +/-15kV ESD 保护的 6 位双向电压电平转换器1.2, 1.5, 1.8,2.5,3.1.2, 1.5, 1.8,2.5,3.具有自动方向感应和 +/-15kV ESD 保护的汽车类 6 位双向电压电平转换具有自动方向感应和 +/-15kV ESD 保护的 8 位双向电压电平转换器用于漏极开路应用的 1 位双向电压电平转换器2-Bit Bidirectional Voltage-Level Translator for Open-Drain Application 用于漏极开路应用的 4 位双向电压电平转换器8 位双向电压电平转换器，适用于漏极开路和推挽应用CompactFlash 总线接口芯片用于 IC-USB 接口的电压电平转换器1.2, 1.5, 1.8,2.5,3.Audio Codec AC'97 Voltage-Translation Transceiver1.2, 1.5, 1.8,2.5, 3,1.5, 1.8,2.5,3.3 MMC、SD、Memory Stick、Smart Media 和 XD-Picture Card 电压转换收发器 1.5, 1.8, 2.5, 3, 3.3 MMC 和 SD 卡电压转换收发器3.3 MMC、SD 卡、记忆棒 (Memory Stick) 电压转换收发器3.3, 5 具有 16 位数据、11 位地址的低功耗、双电源、电平转换 CompactFlash 接口1.2, 1.5, 1.8,2.5,3.SDIO、UART 和音频电压电平收发器具有 ESD 保护和 EMI 滤波的 MMC、SD 卡、记忆棒电压转换收发器1.2, 1.5, 1.8,2.5,3.具有电压电平转换功能的 SDIO 端口扩展器具有输出电压电平转换功能的比较器具有可配置电压转换和 3 态输出的单位双电源总线收发器2.5,3.3 具有 5V 容限电平转换器的 20 位 FET 2.5V/3.3V 低电压总线开关2.5,3.3 具有 5V 容限电平转换器的 24 位 FET 2.5V/3.3V 低电压总线开关2.5,3.3 24 位 FET 总线交换器，具有 5V 容限电平转换器的 2.5V/3.3V 低电压总线开关 2.5, 3.3 具有 5V 容限电平转换器的单路 FET 2.5V/3.3V 低电压总线开关2.5,3.3 具有 5V 容限电平转换器的 3.3V 低电压四路 FET 总线开关2.5,3.3 具有 5V 容限电平转换器的 8 位 FET 2.5V/3.3V 低电压总线开关2.5,3.3 双路 4 选 1 FET 多路复用器/多路解复用器，具有 5V 容限电平转换器的 2.5V/3.2.5,3.3 4位 2 选 1 FET 多路复用器/多路解复用器，具有 5V 容限电平转换器的 2.5V/3.3 2.5, 3.3 双路总线开关电压转换器2.5,3.3 具有 5V 容限电平转换器的 10 位 FET 2.5V/3.3V 低电压总线开关5 具有电平转换功能的 20 位 FET 总线开关5 具有电平转换功能的 24 位 FET 总线开关5 具有电平转换功能的单路 FET 总线开关5 具有电平转换功能的单路 FET 总线开关5 具有 -2V 下冲保护和电平转换的双路 FET 总线开关5 具有电平转换功能的双路 FET 总线开关5 具有电平转换和 -2V 下冲保护的双路 FET 总线开关5 具有电平转换功能的 10 位 FET 总线开关5 具有电平转换和 -2V 下冲保护的 10 位 FET 总线开关5 具有电平转换功能的 10 位 FET 总线开关22 位钳位电压10 位钳位电压双路钳位电压转换器 压电平转换器 换收发器总线收发器 换 和三态输出态输出换和三态输出换和三态输出电平转换器电平转换器电平转换器向电压电平转换器电平转换器向电压电平转换器电平转换器en-Drain Applicationrd 电压转换收发器CompactFlash 接口器总线开关总线开关/3.3V 低电压总线开关限电平转换器的 2.5V/3.3V 低电压总线开关 限电平转换器的 2.5V/3.3V 低电压总线开关 总线开关。
常用电平转换芯片
常用电平转换芯片芯片描述电压范围位数是否双电源SN74AVC1T45 具有可配置电压转换和 3 态输出的单位双电源总线收发器 1.2 3.6 两者兼有 1 双电源SN74LVC1T45 具有可配置电压转换和 3 态输出的单位双电源总线收发器 1.65 5.5 两者兼有 1 双电源SN74AVCH2T45 具有可配置电压转换和 3 态输出的双位双电源总线收发器 1.2 3.6 两者兼有 2 双电源SN74LVC2T45 具有可配置电压转换和 3 态输出的双位双电源收发器 1.65 5.5 两者兼有 2 双电源SN74AVC2T45 具有可配置电压转换和 3 态输出的双位双电源总线收发器 1.2 3.6 两者兼有 2 双电源SN74AVCH4T245 具有可配置电压转换和 3 态输出的 4 位双电源总线收发器 1.2 3.6 两者兼有 4 双电源SN74AVC4T245 具有可配置电压转换和 3 态输出的 4 位双电源总线收发器 1.2 3.6 两者兼有 4 双电源SN74AVCH8T245 具有可配置电压转换和 3 态输出的 8 位双电源总线收发器 1.2 3.6 两者兼有 8 双电源SN74LVC8T245 具有可配置电压转换和 3 态输出的 8 位双电源总线收发器 1.65 5.5 两者兼有 8 双电源SN74AVC8T245 具有可配置电压转换和 3 态输出的 8 位双电源总线收发器 1.2 3.6 两者兼有 8 双电源SN74LVC16T245 具有可配置电压转换和 3 态输出的 16 位双电源总线收发器 1.65 5.5 两者兼有 16 双电源SN74AVC16T245 具有可配置电压转换和 3 态输出的 16 位双电源总线收发器 1.2 3.6 两者兼有 16 双电源SN74AVC20T245 具有可配置电压转换和 3 态输出的 20 位双电源总线收发器 1.2 3.6 两者兼有 20 双电源SN74AVC24T245 具有可配置电压转换和 3 态输出的 24 位双电源总线收发器 1.2 3.6 两者兼有 24 双电源SN74AVC32T245 具有可配置电压转换和 3 态输出的 32 位双电源总线收发器 1.2 3.6 两者兼有 32 双电源SN74TVC3306 双路钳位电压 0.8 5.0 两者兼有 2 FET 开关SN74TVC3010 10 位钳位电压 0.8 5.0 两者兼有 10 FET 开关SN74TVC16222A 22 位钳位电压 0.8 5.0 两者兼有 22 FET 开关。
SN74LV1T04 单电源电源反转CMOS逻辑级转换器说明书
NC A GND V CC Y12345ProductFolderSample &BuyTechnical Documents Tools &SoftwareSupport &CommunitySN74LV1T04SCLS738B –SEPTEMBER 2013–REVISED FEBRUARY 2014SN74LV1T04Single Power Supply Inverter Gate CMOS Logic Level Shifter1Features2Applications•Single-Supply Voltage Translator at •Industrial controllers 5.0/3.3/2.5/1.8V V CC•Telecom•Operating Range of 1.8V to 5.5V •Portable applications •Up Translation•Servers– 1.2V (1)to 1.8V at 1.8V V CC •PC and notebooks – 1.5V (1)to 2.5V at 2.5V V CC •Automotive– 1.8V (1)to 3.3V at 3.3V V CC 3Description– 3.3V to 5.0V at 5.0V V CC SN74LV1T04is a low voltage CMOS gate logic that •Down Translationoperates at a wider voltage range for industrial,– 3.3V to 1.8V at 1.8V V CC portable,telecom,and automotive applications.The – 3.3V to 2.5V at 2.5V V CC output level is referenced to the supply voltage and is able to support 1.8V/2.5V/3.3V/5V CMOS levels.– 5.0V to 3.3V at 3.3V V CCThe input is designed with a lower threshold circuit to •Logic Output is Referenced to V CC match 1.8V input logic at V CC =3.3V and can be used •Output Drivein 1.8V to 3.3V level up translation.In addition,the –8mA Output Drive at 5V 5V tolerant input pins enable down translation (e.g.–7mA Output Drive at 3.3V 3.3V to 2.5V output at V CC =2.5V).The wide V CC range of 1.8V to 5.5V allows generation of desired –3mA Output Drive at 1.8Voutput levels to connect to controllers or processors.•Characterized up to 50MHz at 3.3V V CC The SN74LV1T04is designed with current-drive •5V Tolerance on Input Pinscapability of 8mA to reduce line reflections,•–40°C to 125°C Operating Temperature Range overshoot,and undershoot caused by high-drive •Pb-Free Packages Available:SC-70(DCK)outputs.–2×2.1×0.65mm (Height 1.1mm)Device Information•Latch-Up Performance Exceeds 250mA ORDER NUMBER PACKAGE BODY SIZE Per JESD 17SN74LV1T04DBVR SOT-23(5)2,90mm x 1,60mm •ESD Performance Tested Per JESD 22SN74LV1T04DCKRSC70(5)2,00mm x 1,25mm–2000-V Human-Body Model (A114-B,Class II)DCK or DBV PACKAGE–200-V Machine Model (A115-A)(TOP VIEW)–1000-V Charged-Device Model (C101)•Supports Standard Logic Pinouts•CMOS Output B Compatible with AUP1G and LVC1G Families(1)Refer to the V IH /V IL and output drive for lower V CC condition.SN74LV1T04SCLS738B–SEPTEMBER2013–REVISED Table of Contents4.6Operating Characteristics (7)1Features (1)5Parameter Measurement Information (8)2Applications (1)5.1More Product Selection (8)3Description (1)6Device and Documentation Support (9)4Revision History (2)6.1Trademarks (9)4.1Typical Design Examples (5)6.2Electrostatic Discharge Caution (9)4.2Absolute Maximum Ratings (5)6.3Glossary (9)4.3Recommended Operating Conditions (6)7Mechanical,Packaging,and Orderable4.4Electrical Characteristics (6)Information (9)4.5Switching Characteristics (7)4Revision HistoryNOTE:Page numbers for previous revisions may differ from page numbers in the current version.Changes from Original(September2013)to Revision A Page •Updated V CC values for V IH parameter in the ELECTRICAL CHARACTERISTICS table (6)Changes from Revision A(September2013)to Revision B Page •Updated document formatting (1)2Submit Documentation Feedback Copyright©2013–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LV1T04AY24SN74LV1T04SCLS738B –SEPTEMBER 2013–REVISED FEBRUARY 2014Function TableINPUTOUTPUT (Lower Level Input)(V CC CMOS)A Y H L LHSUPPLY V CC =3.3VAYV IH (min)=1.35V V OH (min)=2.9V V IL (max)=0.8VV OL (max)=0.2V Figure 1.Logic Diagram (NAND Gate)Figure 2.Excellent Signal Integrity (1.8V to 3.3V at 3.3V V CC )Copyright ©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Links:SN74LV1T04SN74LV1T04SCLS738B–SEPTEMBER2013–REVISED Figure3.Excellent Signal Integrity(3.3V to3.3V at3.3V V CC)Figure4.Excellent Signal Integrity(3.3V to1.8V at1.8V V CC)4Submit Documentation Feedback Copyright©2013–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LV1T04VIH minmin= 0.8V= 2.4Vmax= 0.4VVIH= 2.0VVIL= 0.8VVIH= 0.99VVIL= 0.55V5.0V3.3VSystemVcc = 5.0VLV1Txx Logic 5.0VSystemVcc = 1.8V5.0V, 3.3V2.5V, 1.8V1.5V, 1.2VSystemLV1Txx Logic 1.8VSystemSN74LV1T04 SCLS738B–SEPTEMBER2013–REVISED FEBRUARY2014 4.1Typical Design ExamplesFigure5.Switching Thresholds for1.8-V to3.3-V Translation4.2Absolute Maximum Ratings(1)over operating free-air temperature range(unless otherwise noted)MIN MAX UNIT V CC Supply voltage range–0.57.0VV I Input voltage range(2)–0.57.0V Voltage range applied to any output in the high-impedance or power-off state(2)–0.5 4.6VV OVoltage range applied to any output in the high or low state(2)–0.5V CC+0.5VI IK Input clamp current V I<0–20mAI OK Output clamp current V O<0or V O>V CC±20mAI O Continuous output current±25mAContinuous current through VCC or GND±50mADBV package206θJA Package thermal impedance(3)DCK package252°C/W T stg Storage temperature range–65150°C (1)Stresses beyond those listed under"absolute maximum ratings"may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3)The package thermal impedance is calculated in accordance with JESD51-7.Copyright©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Links:SN74LV1T04SN74LV1T04SCLS738B–SEPTEMBER2013–REVISED 4.3Recommended Operating Conditions(1)over operating free-air temperature range(unless otherwise noted)MIN MAX UNITV CC Supply voltage 1.6 5.5VV I Input voltage0 5.5VV O Output voltage0V CC VV CC=1.8V–3V CC=2.5V–5I OH High-level output current mAV CC=3.3V–7V CC=5.0V–8V CC=1.8V3V CC=2.5V5I OL Low-level output current mAV CC=3.3V7V CC=5.0V8V CC=1.8V20Δt/ΔInput transition rise or fall rate V CC=3.3V or2.5V20ns/VvV CC=5.0V20T A Operating free-air temperature–40125°C (1)All unused inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs,literature number SCBA004.4.4Electrical Characteristicsover recommended operating free-air temperature range(unless otherwise noted)T A=25°C T A=–40°C to125°C PARAMETER TEST CONDITIONS V CC UNITMIN TYP MAX MIN MAXV CC=1.65V to1.8V0.94 1.0V CC=2.0V 1.02 1.03V CC=2.25V to2.5V 1.135 1.18V CC=2.75V 1.21 1.23 High-level inputV IH V voltage V=3V to3.3V 1.35 1.37CCV CC=3.6V 1.47 1.48V CC=4.5V to5.0V 2.02 2.03V CC=5.5V 2.1 2.11V CC=1.65V to2.0V0.580.55V CC=2.25V to2.75V0.750.71 Low-level inputV IL V voltage V=3V to3.6V0.80.65CCV CC=4.5V to5.5V0.80.8I OH=–20µA 1.65V to5.5V V CC–0.1V CC–0.1V1.65V 1.28 1.21I OH=–2.0mA V1.8V 1.5 1.45I OH=–2.3mA222.3V VI OH=–3mA2 1.93I OH=–3mA 2.5V 2.25 2.15VV OHI OH=–3.0mA 2.78 2.73.0VI OH=–5.5mA 2.6 2.49VI OH=–5.5mA 3.3V 2.9 2.8I OH=–4mA 4.2 4.14.5VI OH=–8mA 4.1 3.95VI OH=–8mA 5.0V 4.6 4.56Submit Documentation Feedback Copyright©2013–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LV1T04SN74LV1T04 SCLS738B–SEPTEMBER2013–REVISED FEBRUARY2014Electrical Characteristics(continued)over recommended operating free-air temperature range(unless otherwise noted)T A=25°C T A=–40°C to125°C PARAMETER TEST CONDITIONS V CC UNITMIN TYP MAX MIN MAXI OL=20µA 1.65V to5.5V0.10.1I OL=1.9mA 1.65V0.20.25I OH=2.3mA0.10.152.3VI OH=3mA0.150.2V OLI OL=3mA0.10.153.0VI OL=5.5mA0.20.252VI OL=4mA0.150.24.5VI OL=8mA0.30.35I I A input V I=0V or V CC0V,1.8V,2.5V,3.3V,5.5V0.12±1μA5.0V1103.3V110V I=0V or V CC,I CCμAI O=0;open on loading 2.5V1101.8V110One input at0.3V or3.4V,Other inputs at0or V CC, 5.5V 1.35 1.5mAI O=0ΔI CCOne input at0.3V or1.1VOther inputs at0or V CC, 1.8V1010μAI O=0C i V I=V CC or GND 3.3V210210pFC o V O=V CC or GND 3.3V 2.5 2.5pF4.5Switching Characteristicsover recommended operating free-air temperature range(unless otherwise noted)(see Figure7)T A=25°C T A=–65°C to125°CFROM TO FREQUENCYPARAMETER V CC C L UNIT (INPUT)(OUTPUT)(TYP)MIN TYP MAX MIN TYP MAX15pF45455.0V ns30pF 5.57.0 5.57.0DC to50MHz15pF 4.855 5.53.3V ns30pF5 5.5 5.5 6.5 t pd Any In Y15pF6 6.577.5DC to25MHz 2.5V ns30pF 6.57.57.58.515pF10.5111112DC to15MHz 1.8V ns30pF121312144.6Operating CharacteristicsT A=25°CPARAMETER TEST CONDITIONS V CC TYP UNIT1.8V±0.15V102.5V±0.2V10C pd Power dissipation capacitance f=1MHz and10MHz pF3.3V±0.3V105.5V±0.5V10Copyright©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Links:SN74LV1T04From Output Under TestLOAD CIRCUIT1 M ΩVOLTAGE WAVEFORMS PROPAGATION DELAY TIMESINVERTING AND NONINVERTING OUTPUTSV OHV OHV OLV OLV I0 VInputOutputOutputNOTES: A.C L includes probe and jig capacitance.B.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω, slew rate ≥ 1 V/ns.C.The outputs are measured one at a time, with one transition per measurement.D.t PLH and t PHL are the same as t pd .V CC = 2.5 V ± 0.2 V V CC = 3.3 V ± 0.3 V C L V MI V MO5, 10, 15, 30 pFV I /2V CC /25, 10, 15, 30 pFV I /2V CC /2SN74LV1T04SCLS738B –SEPTEMBER 2013–REVISED FEBRUARY 20145Parameter Measurement InformationFigure 6.Load Circuit and Voltage Waveforms5.1More Product SelectionDEVICE PACKAGE DESCRIPTIONSN74LV1T00DCK,DBV 2-Input Positive-NAND Gate SN74LV1T02DCK,DBV 2-Input Positive-NOR Gate SN74LV1T04DCK,DBV Inverter GateSN74LV1T08DCK,DBV 2-Input Positive-AND GateSN74LV1T17DCK,DBV Single Buffer Gate with 3-state Output SN74LV1T14DCK,DBV Single Schmitt-Trigger Inverter Gate SN74LV1T32DCK,DBV 2-Input Positive-OR GateSN74LV1T50DCK,DBV Single Buffer Gate with 3-state Output SN74LV1T86DCK,DBV Single 2-Input Exclusive-Or Gate SN74LV1T125DCK,DBV Single Buffer Gate with 3-state Output SN74LV1T126DCK,DBV Single Buffer Gate with 3-state OutputSN74LV4T125RGY,PWQuadruple Bus Buffer Gate With 3-State Outputs8Submit Documentation FeedbackCopyright ©2013–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LV1T04SN74LV1T04 SCLS738B–SEPTEMBER2013–REVISED FEBRUARY20146Device and Documentation Support6.1TrademarksAll trademarks are the property of their respective owners.6.2Electrostatic Discharge CautionThese devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.6.3GlossarySLYZ022—TI Glossary.This glossary lists and explains terms,acronyms and definitions.7Mechanical,Packaging,and Orderable InformationThe following packaging information and addendum reflect the most current data available for the designated devices.This data is subject to change without notice and revision of this document.Copyright©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Links:SN74LV1T04PACKAGE OPTION ADDENDUM4-Apr-2019Addendum-Page 1PACKAGING INFORMATION(1)The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2)RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.(3)MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.(4)There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.(5)Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.(6)Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andPACKAGE OPTION ADDENDUM 4-Apr-2019Addendum-Page 2continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.TAPE AND REELINFORMATION *All dimensionsare nominal Device Package Type Package DrawingPinsSPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant SN74LV1T04DBVR SOT-23DBV 53000180.08.4 3.23 3.17 1.37 4.08.0Q3SN74LV1T04DBVR SOT-23DBV 53000178.09.2 3.3 3.23 1.55 4.08.0Q3SN74LV1T04DBVR SOT-23DBV 53000178.09.0 3.3 3.2 1.4 4.08.0Q3SN74LV1T04DBVRG4SOT-23DBV 53000178.09.2 3.3 3.23 1.55 4.08.0Q3SN74LV1T04DCKR SC70DCK 53000178.09.0 2.4 2.5 1.2 4.08.0Q3SN74LV1T04DCKR SC70DCK 53000180.08.4 2.47 2.3 1.25 4.08.0Q3SN74LV1T04DCKR SC70DCK 53000178.09.2 2.4 2.4 1.22 4.08.0Q3SN74LV1T04DCKRG4SC70DCK 53000178.09.2 2.4 2.4 1.22 15-Dec-2018*All dimensionsare nominal DevicePackage Type Package Drawing Pins SPQ Length (mm)Width (mm)Height (mm)SN74LV1T04DBVRSOT-23DBV 53000202.0201.028.0SN74LV1T04DBVRSOT-23DBV 53000180.0180.018.0SN74LV1T04DBVRSOT-23DBV 53000180.0180.018.0SN74LV1T04DBVRG4SOT-23DBV 53000180.0180.018.0SN74LV1T04DCKRSC70DCK 53000180.0180.018.0SN74LV1T04DCKRSC70DCK 53000202.0201.028.0SN74LV1T04DCKRSC70DCK 53000180.0180.018.0SN74LV1T04DCKRG4SC70DCK 53000180.0180.018.0 15-Dec-2018PACKAGE OUTLINESOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTORNOTES:1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice.3. Refernce JEDEC MO-178.4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall notexceed 0.15 mm per side.EXAMPLE BOARD LAYOUTSOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTORNOTES: (continued)5. Publication IPC-7351 may have alternate designs.6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.EXAMPLE STENCIL DESIGNSOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTORNOTES: (continued)7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.8. Board assembly site may have different recommendations for stencil design.IMPORTANT NOTICE AND DISCLAIMERTI PROVIDES TECHNICAL AND RELIABILITY DATA(INCLUDING DATASHEETS),DESIGN RESOURCES(INCLUDING REFERENCE DESIGNS),APPLICATION OR OTHER DESIGN ADVICE,WEB TOOLS,SAFETY INFORMATION,AND OTHER RESOURCES“AS IS”AND WITH ALL FAULTS,AND DISCLAIMS ALL WARRANTIES,EXPRESS AND IMPLIED,INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY,FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products.You are solely responsible for(1)selecting the appropriate TI products for your application,(2)designing,validating and testing your application,and(3)ensuring your application meets applicable standards,and any other safety,security,or other requirements.These resources are subject to change without notice.TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource.Other reproduction and display of these resources is prohibited.No license is granted to any other TI intellectual property right or to any third party intellectual property right.TI disclaims responsibility for,and you will fully indemnify TI and its representatives against,any claims, damages,costs,losses,and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale(/legal/termsofsale.html)or other applicable terms available either on or provided in conjunction with such TI products.TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.Mailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2019,Texas Instruments Incorporated。
一种基于TEDS接口的总线适配器的设计与实现
一种基于TEDS接口的总线适配器的设计与实现景俊英;王海瑞;沈三民;李超【摘要】为了解决智能传感器产品由于现场总线种类繁多而引起的互不兼容的问题,实现智能化传感器接口标准化,提出了基于TEDS(transducer el ectronic data sheet)标准的智能传感网络节点中的网络应用处理器NCAP(network capable application processor)的设计方案.该方案以FPGA为核心控制整个系统统一工作,其通过USB接口与上位机通信,而系统内部采用RS485总线完成数据传输,通过严谨的硬件电路设计以及VHDL语言的灵活使用,实现信号可靠性传输.实验测试结果表明,极强的设备接口适应能力以及高可靠性、完备的监控执行能力,为智能传感网络接口设计提供了一种有效的方法.目前,已成功用于某测试系统中.【期刊名称】《科学技术与工程》【年(卷),期】2014(014)011【总页数】5页(P211-215)【关键词】TEDS;NCAP;IEEE1451;总线适配器;智能传感网络【作者】景俊英;王海瑞;沈三民;李超【作者单位】中北大学仪器科学与动态测试教育部重点实验室,电子测试技术国家重点实验室,太原030051;中北大学仪器科学与动态测试教育部重点实验室,电子测试技术国家重点实验室,太原030051;中北大学仪器科学与动态测试教育部重点实验室,电子测试技术国家重点实验室,太原030051;中北大学仪器科学与动态测试教育部重点实验室,电子测试技术国家重点实验室,太原030051【正文语种】中文【中图分类】TP212在复杂测控领域，传统传感器是以点对点或者多路复用的方式与内部设备和控制计算机连接，由于传感器类型复杂、数量庞大、连接电缆错综复杂，整个测控系统十分笨重而且存在很高的风险［1］。
智能传感网络系统作为一种集传感器、通信、计算机为一体的现代分布式测控网络技术，可以有效解决在测控现场布线复杂、仪器设备种类数量庞大的难题。
光自闭环快反镜的控制器设计
光自闭环快反镜的控制器设计刘献之;贾建军;黄迪山;张亮【摘要】As people demand more and more on the precision of laser beam pointing,the requirement of fast steering mirror control technology was also improved.Fast steering mirror controller is mainly composed of control algorithm and hardware circuit.This paper designs optical self closed loop fast steering mirror controller,which take DSP F2812 chip as control core,and H bridge power conversion chip BD6236 as drivecore.Current sampling circuit and spot detection circuit which take CMOS chip as sampling core were coordinated to complete the design of hardware circuit.The incremental discrete incomplete differential PID algorithm was used to suppress the resonance of FSM on working axis,and the bandwidth of control system was improved.The DSP control program was designed,the current and light spot was read,also the multi-loop control system was calculated.Optical self closed loop fast steering mirror was built up,and the positioning accuracy and the control bandwidth were tested.%随着人们对激光束指向精度要求越来越高,对快速反射镜控制技术的要求也相应提高.快反镜控制器主要由控制算法与硬件电路组成.文中设计了光自闭环快反镜的控制器.以DSP F2812芯片为控制核心,DB6236 H桥功率转换芯片为驱动核心.配合电流采样电路以及以CMOS芯片为采样核心的光斑检测电路,完成控制器硬件电路设计.采用增量式离散不完全微分PID算法抑制快反镜工作方向谐振,提高控制器控制带宽.编写DSP控制程序,完成电流读取、光斑质心读取以及多环控制计算.完成快反镜机电系统搭建,并测试其控制误差以及控制带宽.【期刊名称】《仪表技术与传感器》【年(卷),期】2017(000)003【总页数】6页(P37-41,57)【关键词】光自闭环;快反镜;控制器;不完全微分【作者】刘献之;贾建军;黄迪山;张亮【作者单位】中国科学院上海技术物理研究所,上海 200083;上海大学机电工程与自动化学院,上海 200070;中国科学院上海技术物理研究所,上海 200083;上海大学机电工程与自动化学院,上海 200070;中国科学院上海技术物理研究所,上海200083【正文语种】中文【中图分类】TP27快速反射镜在现代光通信、激光武器以及深空探测中发挥着越来越重要的作用[1]。
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FEATURESDESCRIPTIONDGG, DGV, OR DL PACKAGE(TOP VIEW)NC − No internal connection The output port includes equivalent26-Ωseries resistors to reduce overshoot and undershoot.SN74ALVCH16283620-BIT UNIVERSAL BUS DRIVERWITH3-STATE OUTPUTSSCES122F–JULY1997–REVISED OCTOBER2004•Member of the Texas Instruments Widebus™Family•EPIC™(Enhanced-Performance ImplantedCMOS)Submicron Process•Output Port Has Equivalent26-ΩSeriesResistors,So No External Resistors AreRequired•Designed to Comply With JEDEC168-Pin and200-Pin SDRAM Buffered DIMM Specification•ESD Protection Exceeds2000V PerMIL-STD-883,Method3015;Exceeds200VUsing Machine Model(C=200pF,R=0)•Latch-Up Performance Exceeds250mA PerJESD17•Bus Hold on Data Inputs Eliminates the Needfor External Pullup/Pulldown Resistors•Package Options Include Plastic ShrinkSmall-Outline(DL),Thin Shrink Small-Outline(DGG),and Thin Very Small-Outline(DGV)PackagesNOTE:For tape-and-reel order entry,the DGGR package isabbreviated to GR,and the DGVR package is abbreviatedto VR.This20-bit universal bus driver is designed for1.65-Vto3.6-V V CC operation.Data flow from A to Y is controlled by theoutput-enable(OE)input.The device operates in thetransparent mode when the latch-enable(LE)input islow.When LE is high,the A data is latched if theclock(CLK)input is held at a high or low logic level.IfLE is high,the A data is stored in the latch/flip-flop onthe low-to-high transition of CLK.When OE is high,the outputs are in the high-impedance state.To ensure the high-impedance state during power up or power down,OE should be tied to V CC through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of the driver.Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.The SN74ALVCH162836is characterized for operation from-40°C to85°C.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus,EPIC are trademarks of Texas Instruments.PRODUCTION DATA information is current as of publication date.Copyright©1997–2004,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.h t t p://oA1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18OE CLK Y1Y2Y3Y4Y5Y6Y7Y8Y9Y10Y11Y12Y13Y14Y15Y16Y17Y18LEA19A20Y19Y20(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.SN74ALVCH16283620-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTSSCES122F–JULY 1997–REVISED OCTOBER 2004FUNCTION TABLEINPUTSOUTPUTYOE LE CLK A H X X X Z L L X L L L L X H H L H ↑L L L H ↑H H L HL or HXY 0(1)(1)Output level before the indicated steady-state input conditions were establishedLOGIC SYMBOL (1)2ht t p ://oTo 19 Other ChannelsOECLK LEA1Y1ABSOLUTE MAXIMUM RATINGS (1)SN74ALVCH16283620-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTSSCES122F–JULY 1997–REVISED OCTOBER 2004LOGIC DIAGRAM (POSITIVE LOGIC)over operating free-air temperature range (unless otherwise noted)MINMAX UNIT V CC Supply voltage range -0.5 4.6V V I Input voltage range (2)-0.5 4.6V V O Output-voltage range (2)(3)-0.5V CC +0.5V I IK Input clamp current V I <0-50mA I OK Output clamp current V O <0-50mA I OContinuous output current±50mA Continuous current through each V CC or GND±100mADGG package81θJA Package thermal impedance (4)DGV package 86°C/W DL package74T stg Storage temperature range-65150°C (1)Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3)This value is limited to 4.6V maximum.(4)The package thermal impedance is calculated in accordance with JESD 51.3ht t p ://oRECOMMENDED OPERATING CONDITIONS (1)SN74ALVCH16283620-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTSSCES122F–JULY 1997–REVISED OCTOBER 2004MINMAX UNIT V CC Supply voltage1.65 3.6VV CC =1.65V to 1.95V0.65×V CCV IHHigh-level input voltageV CC =2.3V to 2.7V 1.7VV CC =2.7V to 3.6V 2V CC =1.65V to 1.95V0.35×V CCV IL Low-level input voltage V CC =2.3V to 2.7V 0.7V V CC =2.7V to 3.6V0.8V I Input voltage 0V CC V V OOutput voltage0V CC V V CC =1.65V-2V CC =2.3V -6I OHHigh-level output currentmA V CC =2.7V -8V CC =3V -12V CC =1.65V2V CC =2.3V 6I OLLow-level output currentmA V CC =2.7V 8V CC =3V12∆t/∆v Input transition rise or fall rate 10ns/V T A Operating free-air temperature-4085°C (1)All unused control inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs ,literature number SCBA004.4ht t p ://oELECTRICAL CHARACTERISTICSSN74ALVCH162836 20-BIT UNIVERSAL BUS DRIVER WITH3-STATE OUTPUTS SCES122F–JULY1997–REVISED OCTOBER2004over recommended operating free-air temperature range(unless otherwise noted)PARAMETER TEST CONDITIONS V CC MIN TYP(1)MAX UNITI OH=-100µA 1.65V to3.6V V CC-0.2I OH=-2mA 1.65V 1.2I OH=-4mA 2.3V 1.9V OH 2.3V 1.7VI OH=-6mA3V 2.4I OH=-8mA 2.7V2I OH=-12mA3V2I OL=100µA 1.65V to3.6V0.2I OL=2mA 1.65V0.45I OL=4mA 2.3V0.4V OL 2.3V0.55VI OL=6mA3V0.55I OL=8mA 2.7V0.6I OL=12mA3V0.8I I V I=V CC or GND 3.6V±5µAV I=0.58V 1.65V25V I=1.07V 1.65V-25V I=0.7V 2.3V45I I(hold)V I=1.7V 2.3V-45µAV I=0.8V3V75V I=2V3V-75V I=0to3.6V(2) 3.6V±500I OZ V O=V CC or GND 3.6V±10µAI CC V I=V CC or GND,I O=0 3.6V40µA∆I CC One input at V CC-0.6V,Other inputs at V CC or GND3V to3.6V750µA Control inputs 5.5C i V I=V CC or GND 3.3V pFData inputs6C o Outputs V O=V CC or GND 3.3V8pF(1)All typical values are at V CC=3.3V,T A=25°C.(2)This is the bus-hold maximum dynamic current.It is the minimum overdrive current required to switch the input from one state toanother.5 h t t p://oTIMING REQUIREMENTSSWITCHING CHARACTERISTICSOPERATING CHARACTERISTICSSN74ALVCH16283620-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTSSCES122F–JULY 1997–REVISED OCTOBER 2004over recommended operating free-air temperature range (unless otherwise noted)(see Figure 1through Figure 3)V CC =2.5V V CC =3.3V V CC =1.8V V CC =2.7V ±0.2V ±0.3V UNIT MIN MAXMIN MAXMIN MAXMIN MAXf clock Clock frequency (1)150150150MHz LE low(1) 3.3 3.3 3.3t wPulse durationnsCLK high or low (1) 3.3 3.3 3.3Data before CLK ↑(1) 1.4 1.7 1.5t suSetup timeCLK high (1) 1.2 1.6 1.3nsData before LE ↑CLK low(1) 1.4 1.5 1.2Data after CLK ↑(1)0.90.90.9t h Hold time nsData after LE ↑CLK high or low (1)1.11.11.1(1)This information was not available at the time of publication.over recommended operating free-air temperature range (unless otherwise noted)(see Figure 1through Figure 3)V CC =2.5V V CC =3.3V V CC =1.8V V CC =2.7V FROM TO ±0.2V ±0.3V PARAMETERUNIT (INPUT)(OUTPUT)MINTYPMIN MAXMIN MAXMIN MAXf max(1)150150150MHz A(1)1 4.4 4.6 1.24t pd LE Y(1) 1.1 5.8 6.1 1.4 5.1ns CLK (1)1 5.2 5.5 1.15t en OE Y (1) 1.1 6.4 6.5 1.2 5.5ns t disOEY (1)14.75.2 1.75.1ns(1)This information was not available at the time of publication.T A =25°CV CC =1.8VV CC =2.5VV CC =3.3VPARAMETERTEST CONDITIONS UNIT TYPTYP TYP Outputs enabled (1)31.536Power dissipation C pd C L =0,f =10MHzpFcapacitanceOutputs disabled(1)810.5(1)This information was not available at the time of publication.6ht t p ://oPARAMETER MEASUREMENT INFORMATIONV OHV OL From Output Under TestC L LOAD CIRCUITOpen Output Control (low-level enabling)Output Waveform 1S1 at 2 × V CC (see Note B)Output Waveform 2S1 at GND (see Note B)0 V0 VV CC 0 V0 VV CCV CCVOLTAGE WAVEFORMS SETUP AND HOLD TIMESVOLTAGE WAVEFORMS PULSE DURATIONVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMESTiming InputData InputInputt pd t PLZ /t PZL t PHZ /t PZHOpen 2 × V CC GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω, t r ≤ 2 ns, t f ≤ 2 ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .0 VV CCInputOutputVOLTAGE WAVEFORMS PROPAGATION DELAY TIMES× V CCV CCSN74ALVCH16283620-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTSSCES122F–JULY 1997–REVISED OCTOBER 2004V CC =1.8VFigure 1.Load Circuit and Voltage Waveforms7ht t p ://oPARAMETER MEASUREMENT INFORMATIONV OHV OL From Output Under TestC L LOAD CIRCUITOpen Output Control (low-level enabling)Output Waveform 1S1 at 2 × V CC (see Note B)Output Waveform 2S1 at GND (see Note B)0 V0 VV CC 0 V0 VV CCV CCVOLTAGE WAVEFORMS SETUP AND HOLD TIMESVOLTAGE WAVEFORMS PULSE DURATIONVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMESTiming InputData InputInputt pd t PLZ /t PZL t PHZ /t PZHOpen 2 × V CC GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω, t r ≤ 2 ns, t f ≤ 2 ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .0 VV CCInputOutputVOLTAGE WAVEFORMS PROPAGATION DELAY TIMES× V CCV CCSN74ALVCH16283620-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTSSCES122F–JULY 1997–REVISED OCTOBER 2004V CC =2.5V ±0.2VFigure 2.Load Circuit and Voltage Waveforms8ht t p ://oPARAMETER MEASUREMENT INFORMATIONV OH V OLC L LOAD CIRCUITOpenOutput Control (low-level enabling)Output Waveform 1S1 at 6 V (see Note B)Output Waveform 2S1 at GND (see Note B)0 V0 V2.7 V0 V0 V2.7 V0 V2.7 V2.7 V3 VVOLTAGE WAVEFORMS SETUP AND HOLD TIMESVOLTAGE WAVEFORMS PROPAGATION DELAY TIMESVOLTAGE WAVEFORMS PULSE DURATIONVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMESTiming InputData InputInputt pd t PLZ /t PZL t PHZ /t PZHOpen 6 V GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω, t r ≤ 2.5 ns, t f ≤ 2.5 ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .SN74ALVCH16283620-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTSSCES122F–JULY 1997–REVISED OCTOBER 2004V CC =2.7V AND 3.3V ±0.3VFigure 3.Load Circuit and Voltage Waveforms9ht t p ://oPACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)74ALVCH162836DLG4ACTIVE SSOP DL 5620Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74ALVCH162836GRE4ACTIVE TSSOP DGG 562000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74ALVCH162836GRG4ACTIVE TSSOP DGG 562000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74ALVCH162836VRE4ACTIVE TVSOP DGV 562000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74ALVCH162836VRG4ACTIVE TVSOP DGV 562000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74ALVCH162836DGGR OBSOLETE TSSOP DGG 56TBD Call TI Call TI SN74ALVCH162836DGVR OBSOLETE TVSOP DGV 56TBD Call TI Call TISN74ALVCH162836DL ACTIVE SSOP DL 5620Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74ALVCH162836GR ACTIVE TSSOP DGG 562000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74ALVCH162836VRACTIVETVSOPDGV562000Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specifiedlead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM11-Nov-2009Addendum-Page 1/分销商库存信息:TISN74ALVCH162836GR SN74ALVCH162836VR SN74ALVCH162836DL 74ALVCH162836GRE474ALVCH162836VRE474ALVCH162836GRG4 74ALVCH162836VRG474ALVCH162836DLG4SN74ALVCH162836DLR 74ALVCH162836DLRG4。