M65608E_07资料

300
ICCOP (3)
Dynamic operating current
110
100
1.
CS1 > VIH or CS2 < VIL and CS1 < VIL.
2.
CS1 > VCC - 0.3V or, CS2 < GND + 0.3V and CS1 < 0.2V.
3.
F = 1/TAVAV, Iout = 0 mA, W = OE = VIH, Vin = GND or VCC, VCC max.
-1
IOZ(1)
Output leakage current
-1
VOL (2)
Output low voltage
–
VOH (3)
Output high voltage
2.4
1.
GND < Vin < VCC, GND < Vout < VCC Output Disabled.
2.
VCC min. IOL = 8 mA
3.
VCC min. IOH = -4 mA.
Typical –
– – –
Consumption
Symbol
Description
65608E-30
65608E-45
ICCSB (1)
Standby supply current
2
2
ICCSB1 (2)
Standby supply current
300
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Pin Description
Table 1. Pin Names Names A0 - A16 I/O0 - I/O7 CS1 CS2 WE OE VCC GND
Description Address inputs Data Input/Output Chip select 1 Chip select 2 Write Enable Output Enable Power Ground
3. During power up and power-down transitions CS1 and OE must be kept between VCC + 0.3V and 70% of VCC, or with CS2 between GND and GND -0.3V.
4. The RAM can begin operation > TR ns after VCC reaches the minimum operation voltages (4.5V).
Input Pulse Levels: ....................................GND to 3.0V Input Rise/Fall Times: ...............................5 ns Input Timing Reference Levels: ................1.5V Output loading IOL/IOH (see Figure 1 and Figure 2)+30 pF
Deselect/ power-down
Read
Write
Output Disable
3 M65608E
4151M–AERO–07/07
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M65608E
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential:..........................-0.5V + 7.0V DC input voltage: ..............................GND - 0.5V to VCC + 0.5 DC output voltage high Z state: ........GND - 0.5V to VCC + 0.5 Storage temperature: ..................................... -65°C to +150°C Output current into outputs (low): .................................. 20 mA Electro statics discharge voltage: ............................... > 2001V (MIL STD 883D method 3015.3)
Description
The M65608E is a very low power CMOS static RAM organized as 131072 x 8 bits.
Utilizing an array of six transistors (6T) memory cells, the M65608E combines an extremely low standby supply current (Typical value = 0.2 µA) with a fast access time at 30 ns over the full military temperature range. The high stability of the 6T cell provides excellent protection against soft errors due to noise.
Parameter
Description
Cin(1)
Input low voltage
Cout(1)
Output high voltage
Note: 1. Guaranteed but not tested.
Operating Voltage 5V + 10%
Minimum 4.5 0.0
GND - 0.5 2.2
Maximum 1 1 0.4 –
Unit mA µA mA
Unit µA µA V V
Value max max max
5 M65608E
4151M–AERO–07/07
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AC Parameters
AC Test Conditions
AC Test Loads Waveforms
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Features
• Operating Voltage: 5V • Access Time: 30, 45 ns • Very Low Power Consumption
– Active: 600 mW (Max) – Standby: 1 µW (Typ) • Wide Temperature Range: -55°C to +125°C • 400 Mils Width Packages: FP32 and SB32 • TTL Compatible Inputs and Outputs • Asynchronous • No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2 • Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019 • QML Q and V with SMD 5962-89598 • ESCC with Specification 9301/047
The M65608E is processed according to the methods of the latest revision of the MIL PRF 38535 or ESCC 9000.
Rad. Tolerant 128K x 8 5-volts Very Low Power CMOS SRAM
DC Parameters
DC Test Conditions
Table 3. DC Test Conditions TA = -55°C to + 125°C; Vss = 0V; VCC = 4.5V to 5.5V
Symbol
Description
Minimum
IIX (1)
Input leakage current
Military Operating Range
Recommended DC Operating Conditions
Parameter
Description
VCC GND
Supply voltage Ground
VIL
Input low voltage
VIH
Input high voltage
Capacitance
M65608E
Rev. 4151M–AERO–07/07
1
元器件交易网www.cecb2b.com Block Diagram
M65608E
Pin Configuration
32-lead DIL side-brazed 32-lead Flatpack
400 MILS 400 MILS
2
4151M–AERO–07/07
Minimum – –
Typical 5.0 0.0 0.0 –
Typical – –
Operating Temperature -55°C to + 125°C
Maximum
Unit
5.5
V
0.0
V
0.8
V
VCC + 0.5
V
Maximum
Unit
8
pF
8
pF
4
4151M–AERO–07/07
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Table 2. Truth Table
CS1
CS2
W
OE
H
X
X
X
X
L
X
X
L
H
H
L
L
Байду номын сангаас
H
L
X
L
H
H
H
Note: L = low, H = high, X = H or L, Z = high impedance.
Inputs/ Outputs
Z
Z Data Out Data In
Z
Mode
Deselect/ Power-down
6
4151M–AERO–07/07
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Data Retention Characteristics
Typical
Parameter
Description Minimum TA = 25 °C Maximum
Figure 1
Figure 2
Figure 3
M65608E
Data Retention Mode Timing
Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention:
1. During data retention chip select CS1 must be held high within VCC to VCC 0.2V or, chip select CS2 must be held down within GND to GND +0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation.
*NOTE:
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.