FPGA可编程逻辑器件芯片XC2V1000-5FG256I中文规格书

Table 67: IBUFE3, IBUF, and IBUF_IBUFDISABLE Attributes
Attribute
Values Description IBUF_LOW_PWR TRUE, FALSE When set to TRUE, allows for reduced power input standards that require INTERNAL_VREF (for example: HSTL). A setting of FALSE demands more power but delivers higher performance characteristics.
IOSTANDARD See XP IOB Supported Standards Assigns an I/O standard to the element.
USE_IBUFDISABLE TRUE, FALSE
Enables IBUFDISABLE port (IBUFE3, IBUF_IBUFDISABLE only)Table 68: IBUFE3, IBUF, and IBUF_IBUFDISABLE Ports
Port
I/O Description O
Output Buffer output representing the input path to the device.I
Input Input port connection. Connects directly to top-level port in the design.IBUFDISABLE
Input Disables the input buffer and forces the O output to the internal logic to a logic Low when asserted High (IBUFE3, IBUFDISABLE only).OSC[3:0]
Input This is not a supported port and must be left unconnected.OSC_EN[1:0]
Input This is not a supported port and must be left unconnected.VREF Input
Connect to XPIO_VREF (IBUFE3 only).
Single-Ended Bidirectional Buffer Primitives
Figure 40: Single-Ended Bidirectional Buffer Primitives
IOBUF_D_DCIEN
IO
IOBUF
T I O IO IOBUFE3
T OSC_EN
OSC[3:0]
I
O
VREF DCITERMDISABLE
IBUFDISABLE
IO X21624-092318
Chapter 4: XP IOB Resources
Table 69: IOBUFE3, IOBUF, and IOBUF_DCIEN Attributes
Attribute
Values Description IBUF_LOW_PWR TRUE, FALSE When set to TRUE, allows for reduced power input standards that require INTERNAL_VREF (like HSTL). A setting of FALSE demands more power but delivers higher performance characteristics (IOBUFE3,IOBUF_DCIEN only).
DRIVE 2, 4, 8, 12Specifies the drive strength of the output.
SLEW SLOW, FAST, MEDIUM Specifies the slew rate of the output.
IOSTANDARD See XP IOB Supported Standards Assigns an I/O standard to the element.
USE_IBUFDISABLE TRUE, FALSE
Enables IBUFDISABLE (IOBUFE3, IOBUF_DCIEN only).Table 70: IOBUFE3, IOBUF, and IOBUF_DCIEN Ports
Port
I/O Description IO
Inout Inout port connection. Connect directly to top-level port in the design.O
Output Output path of the buffer.I
Input Input port connection. Connect directly to top-level port in the design.T
Input Tristate enable input signifying whether the buffer acts as an input or output.IBUFDISABLE
Input Disables the input buffer and forces the O output to the internal logic to a logic Low when asserted High (IOBUFE3, IOBUF_DCIEN only).DCITERMDISABLE Input Control to enable/disable input termination. This is generally used to reduce power in long periods of an idle state (IOBUFE3, IOBUF_DCIEN only).
OSC[3:0]Input This is not a supported port and must be left unconnected.
OSC_EN[1:0]
Input This is not a supported port and must be left unconnected.
VREF Input Connect to XPIO_VREF (IBUFE3 only).Single-Ended Output Buffer Primitives
Figure 41: Single-Ended Output Buffer Primitives
I OBUF
Output to Device Pad I O OBUFT
T Output to
Device Pad
X21622-092318Table 71: OBUF and OBUFT Attributes
Attribute
Values Description SLEW
SLOW, FAST, MEDIUM Specifies the slew rate of the output.DRIVE 2, 4, 8, 12Specifies the drive strength of the output.
Table 71: OBUF and OBUFT Attributes (cont'd)
Attribute Values Description
IOSTANDARD See XP IOB Supported
Standards
Assigns an I/O standard to the element.
Table 72: OBUF and OBUFT Ports
Port I/O Description
O Output Output of OBUF to be connected directly to top-level output port.
I Input Input of OBUF. Connect to the logic driving the output port.
T Input Tristate enable input. (OBUFT only)
XP IOB Supported Differential Standards
DIFF_SSTL
The stub-series terminated logic (SSTL) for 1.5V (DIFF_SSTL15) and 1.35V (DIFF_SSTL135) are differential I/O standards used for general-purpose memory buses. DIFF_SSTL15 is used for DDR3 SDRAM interfaces and is roughly defined (not by name) in the JEDEC standard
JESD79-3E. DIFF_SSTL135 is used for DDR3L SDRAM interfaces and is roughly defined (not by name) in the JEDEC standard JESD79-3-1.
Table 73: Allowed Attributes for DIFF_SSTL15, DIFF_SSTL135 and DIFF_SSTL12 I/O Primitives
Attributes
IBUF/IBUFE3OBUF/OBUFT IOBUF/IOBUFE3 Allowed
Values Default
Allowed
Value Default
Allowed
Values Default
IOSTANDARD DIFF_SSTL15, DIFF_SSTL135,
DIFF_SSTL12DIFF_SSTL15, DIFF_SSTL135,
DIFF_SSTL12
DIFF_SSTL15, DIFF_SSTL135,
DIFF_SSTL12
SLEW N/A FAST,
MEDIUM,
SLOW SLOW FAST, MEDIUM,
SLOW
SLOW
OUTPUT_IMPED ANCE N//A RDRV_40_40,
RDRV_48_48,
RDRV_60_60
RDRV_40_40RDRV_40_40,
RDRV_48_48,
RDRV_60_60
RDRV_40_40
ODT RTT_40, RTT_48,
RTT_60RTT_40N/A RTT_40, RTT_48,
RTT_60
RTT_40
DQS_BIAS
(DIFF_SSTL12
ONLY)
TRUE, FALSE FALSE TRUE, FALSE FALSE
VOH
(DIFF_SSTL15
ONLY)
N/A N/A75, 8075N/A N/A。