781000中文资料

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10408;10409;中文规格书,Datasheet资料

Made in AmericaThe two most important characteristics for successful applicationConductive Acrylic Paint applications are:1. The surface must be clean, dry, dull, and smooth. Heavy dirt or grease build-up should be removed with a stripper or degreaser. Cleaning methods range from: sweeping, vacuuming, wire brush, air-blasting, water jet, steam cleaning, or stripping.2. If the surface is concrete, it must be in good condition.New concrete should cure for a minimum of 28 days beforeConductive Acrylic Paint. Not all concrete is created equal -- concrete surfaces vary widely in physical and chemical qualities due to the way the concrete was formulated,There are several methods to prepare problem concrete. Each method depends on the condition of the concrete. Adhesion properties can be increased by profiling or roughing the surface through acid etching, rotary drum sanding, scarifying, or mechanically scratching the surface.You must test for moisture in the concrete. If moisture is present, the floor should not be coated until the source of the moisture isConductive Acrylic Paint bonds well to clean, dry concrete. However, a standard industrial primer can be used on certain difficult to bond substrates and enhance the adhesion of Conductive Acrylic Paint.PREVIOUSLY PAINTED SURFACES:The surface should be clean and free of dust, grease, wax, and soap residue. Wash with ordinary detergent and water. Rinse thoroughly with clean water and let dry. Glossy surfaces can be dulled by lightly sanding and then vacuuming and cleaning. Cracks and holes should be repaired before applying the Statguard Conductive Acrylic Paint. Adhesion can be improved by using atest area be coated to ensure that the adhesion and electrical of the paint is acceptable. (See Adhesion Testing, Figure 5.) If the 3. Saturate a 1/4” (6.35 mm) fine nap roller or an industrial brush ure must be above 50°F (10°C).Conductive Acrylic Paint is recommended for appropriate static protection.Mix any settled solids to produce a uniform grey color.Saturate a 1/4” fine nap roller with paint, remove excess paint and trapped bine separate cans into a larger A minimum number of strokes from the applicator is recommended.Figure 2. Paint application with roller.Figure 3. Spray paint application Clean UpWash applicators with water immediately after painting. Remove paint spills promptly with a wet cloth. Close container after each use. Keep container from freezing.Drying TimeIt is recommended that Statguard ® Conductive Acrylic Paint be allowed to dry at a temperature in excess of 45°F (7°C) until dry. A minimum of 1 to 2 hours drying time should be allowed before applying the second coat. The finish can be applied after 48-72 hours or until the last coat of paint is cured. Wait a minimum of 12 hours drying time after the last coat before allowing light traffic on the coated area. At high humidity levels, a longer drying time may be necessary. Do not force dry.MaintenanceUse sweeper, vacuum, or broom to remove dirt. Allow two weeks drying time before using a damp mop to clean the coated area. Do not use abrasive cleaners, floor rinse, or scrubbing machine to clean the floor.Finish/SealerDesco Statguard Conductive Acrylic Paint can be overcoated or sealed with Statguard Floor Finish static dissipative coating to increase durability, enhance shine, improve ease of maintenance, and seal out dirt and debris. Desco Statguard ® Conductive Light Grey Acrylic Paint needs the Statguard ® Floor Finish for gloss and ease of maintenance . Statguard ® is a polymer base floor finish/sealer that can be used as a top coat on the Conductive Acrylic Paint. Surface resistivity will then be in the 10E6-10E7 ohms range. Two coats are recommended. Three coats will improve electrical properties, durability and reduce frequency ofLead free, iron oxide, titanium dioxide and extenders 10.27 lbs per gallon (1.0 kilograms per Use a razor to cut into a painted, dried floor.3.Pull the tape off.Apply tape on the precut area.4.Examine the degree of paint separationfrom the concrete.Figure 5. Adhesion test on the painted floor.10E5 ohms/sq. per ASTM D257Static Charge Decay:<0.01 sec. per FTMS 101B, Method 4046Charge Generation:Zero per AATCC Step Test, Method 134-1979RTT:10E5 ohms per ANSI ESD-S7.1RTG:10E5 ohms per ANSI ESD-S7.1TestingTest patch areas should be tested for adhesion and electricalperformance of the paint before applying paint to the entire floor. To best ensure consistent results, the test should be done at various locations.ELECTRICAL PROPERTIES:Test the surface resistivity, point-to-point resistance, and resistance-to-ground properties of coated area per ANSI ESD-S7.1 test method. For quick and easy verification of the paint’s electrical properties, we recommend the use of our a Surface Resistance Test Kit (Figure 4). For more information contact any of the Desco Industries Inc. companies.ADHESION:Allow newly applied paint to dry a minimum of 48 hours before proceeding with the test. At humidity levels over 55% RH, allow 72 hours of drying time before testing. Use a razor to cut a cross or a few perpendicular lines over a 3” by 3” (75 mm by 75 mm) area on several spots of the thoroughly dried area. Use a piece of masking tape to cover the marked area. Make sure the tape is thoroughly adhered to the test area. Pull the tape off the surface and examine the amount of paint which has peeled off during the test. If any significant portion is transferred to the tape, better surface preparation (acid etching, cleaning or sanding) should be done on the substrate to enhance the adhesion.8. EXPOSURE CONTROL/PERSONAL EXPOSUREControl Parameters TLV-value 50 ppm maximum for n-butanol and 25 ppm for Ethylene GlycolMonobutyl EtherOther Regulations NoneMeasures For Technical Control Preferences of technical measure to prevent or control contact with the product.Isolating process and personnel, mechanical ventilation (dilution and localexhaust) and the regulation of process conditions. In case of non-prevention or non-control, a proper protective wearing should be used. Respiratory Protection Not required. Wear MSHA/NIOSH approved respirator where exposure limits areexceeded.Hand Protection Impervious/Neoprene GlovesEye Protection Chemical Splash Goggles (ANSI Z-87.1)Work/Hygienic Practices Wash hands before eating, smoking, or using washroom facilities9. PHYSICAL AND CHEMICAL PROPERTIESForm FluidColor Grey, OpaqueSmell MildpH 8.5Boiling Point at °C >100-101°C (212-214°F)Freezing Point at °C 0.0°C (32.0 °F)Flash Point at °C 65 °CExplosive Limits LEL: 0.8 UEL: 25.0Inflammability Limits N/A(vol.% in air)Solubility in water CompleteVOC per method 24 of EPA 2.3 -2.5 lbs VOC/ galVapor Pressure (mmHg) 92.43 mm @ 20 °CVapor Density (air=1) Heavier than airDensity at 20°C 8.17 lbs./gal or 1.14 g/cm3Specific Gravity (H20=1) 1.21Inflammability Classification according to OSHA and EC-regulations “non-flammable”Ignition Temperature 240.0 °CEvaporation Rate Slower than n-butyl acetate% Volatile by Volume 13.229%10. STABILITY AND REACTIVITYStability/Reactivity Stable product at normal conditionsConditions to avoid Temperatures above 49°C/120°F and below 1°C/34°F, Open flames and sparks. Materials to avoid Strong Oxidizing agents and alkalies.Hazardous Decomposition Oxides of carbon and nitrogen. If involved in fire (from other sources) could conceivably result in release of Carbon Dioxide and Carbon Monoxide fumes.11. TOXICOLOGICAL INFORMATIONIngredient-Material Description PEL TLV (twa) LD50 (mg/kg) LC50 (ppm)mg/m3 ppm (rat) (rbt) (rat)oral dermal inhalEthylene Glycol Monobutyl Ether * 50.0 0.0 25.0 470.0 220.0 0.0Butanol* 50.0 0.0 50.0 0.0 0.0 0.0Mineral Spirits 100.00 0.0 100.0 0.0 0.0 0.02-(2-Butoxyethoxy)ethanol 0.0 0.0 0.0 6560.0 4120.0 0.02-ethyl-1-Hexanol 0.0 0.0 0.0 3730 1970 0.0Ammonium Hydroxide 0.0 35.0 50.0 350.0 0.0 0.0*Listed Chemical Subject To Reporting Requirement of SARA Section 313 of Title III• Acute toxicity• Primary irritant effect:• On the skin: No irritant effect• On the eye: No irritant effect• Sensatization: No sensitizing effects known• Additional toxicological information:The product in not classified according to the calculation method of the General EU Classification guideline for Preparations as issued in the latest version. When used and handled according to specifications, the product does not have any harmful effects to our experience and the information provided to us.12. ECOLOGICAL INFORMATIONGeneral Notes:Water hazard class 1 (German Regulations) (self-assessment): slightly hazardous for water. Do not allow undiluted product or large quantities of it to reach ground water, water course or sewage system.Mobility The product is aqueous and will be separated in aqueous conditions Degradability N/ABioaccumulation Not likelyEcotoxicity None knownReference to BimSchV N/A13. DISPOSAL CONSIDERATIONSProduct Dike and collect material into plastic container. Water rinse and drain, flush smallamounts. Use sanitary landfill d isposal. Follow state and local regulations(RCRA; Subtitle D).Hazardous Waste Number Nonregulated14. TRANSPORT INFORMATIONThis product is not classified for transport under ADR/IMDG regulations.15. REGULATORY INFORMATIONLabeling according To EU guideline: Observe the general safety regulations when handeling chemicals. The product is not subject to identification regulations under EU Directives and the Ordinance on Hazardous Materials (Genman GefStoffV).National Regualtions:Waterhazard class: Water hazard class 1 (Self-assessment): slightly hazard for waterPhysical/Chemical Indication Non-flammableSafety Phrase (S2): keep away from children, (S7): keep containers well closed, (S24/25): avoidcontact with skin and eyes, (S45): in case of accident or if you feel unwell, seekmedical advice immediately, show label where possible, (S53): avoid exposureobtain special instruction before use, (S62): if swallowed, do not induce vomiting;seek medical advice immediately and show this container or label.EU Classification This product does not have to be classified according to the EU Regulations.(67/548/EEC-88/379/EEC)EINECS Status All components are included in the EINECS Inventories except cas #104-76-7 TSCA All ingredients of this product are listed or are excluded from the listing on the U.S. Toxic Substance Control Act (TSCA) Chemical Substance inventory.16. OTHER INFORMATIONFurther Information None KnownDisclaimerThe information given in this publication has been worked up to the best of the knowledge of Desco Industries Inc, as well as taking into consideration the applicable laws and regulations. We cannot anticipate all conditions under which this information and our products or the products of the manufacturers in combination with our products may be used. We accept no responsibility for the results obtained by the application information or the safety and suitability of our product or product combination with other products. Users are advised to make their own tests to determine the safety and suitability of each such product or product combination for their own purposes. Unless otherwise agreed in writing, we sell the products without warranty, and buyers end users assume responsibility and liability for loss or damage arising from the handling and use of our products, whether used alone or in combination with other products.分销商库存信息:DESCO1040810409。

资料(中文)

概述TC1002 是一个高性能细分步进马达控制器。

它包含一个模拟SINE/COSINE信号发生器，完整的数字控制集成在一颗IC中，高集成度减少产品的设计周期。

尽量的减少了外部的分立元件，提供给设计者一个简单但又高效的产品。

在一个完整的细分控制系统上，TC1002全面的控制马达运行状况，14种细分等级，它能在任何时候改变马达状态，没有必要要复位控制器。

它很容易使马达前进使用者设定的固定步数。

另外在“整步”输出上，当马达长时间工作后，它会指出马达是否还处于整步状态上。

TC1002通过输入时钟和方向两种信号就可控制马达，并可以工作在离散状态下。

芯片采用QFP44封装。

特点¾44引脚QFP封装¾高达10MHz时钟¾内部集成模拟SINE/COSINE发生器，DAC¾PWM电流控制，可自动减少电流¾14种细分选择，细分数的改变不会中断马达的运行¾Standalone or Buss 模式¾5V电源供电¾过流保护¾过温保护¾错误输出¾整步输出¾消除共振结构图引脚分布图TC1002引脚分布图引脚描述44脚名称引脚功能37 SCLK 阶跃时钟输入。

一个正边沿能够使电机前进一个增量。

36 RESET 当RESET脚为低时，这一输入会复位芯片。

当重新释放时，控制器会在它的初始状态（OUTA为0，OUTB为峰值）38 DIR 方向输入。

这一输入用来改变电机的方向。

物理位置也和电机线圈连接有关。

12 CSEL 时钟选择输入。

为低时，内部的正弦余弦发生器作为SCLK输入且不依赖于EN输入电平。

为高时，当EN输入为低时，COUT输出将作为SCLK输入，相反地，当EN输入为高时，内部的正弦余弦发生器将作为SCLK信号。

10 RSEL ROM选择脚，为低选择SIN/COS发生器，为高选择外部查找表39 EN 使能输入。

78172中文资料

SPECIFICATIONSFEATURES AND SPECIFICATIONSMolex's new 1.20mm pitch Pico-EZmate™connectors are compact and low profile, with a mated height of 1.40mm for wire-to-board applications.The Pico-EZmate connector design includes secure locking features between the receptacle housing and the PCB header, with an audible click to ensure mating integrity. The receptacle is mated vertically with the header, which allows excellent workability in production lines.The header design also provides sufficient space to allow stable pick-and-place operations in SMT lines. The headers are packed in the embossed tape packing for automatic insertion equipment.Both header and receptacle housings are made from a halogen-free resin with a 94 V-0 rated material. The series also complies to European RoHS directives.•Ultra low profile •Space savings•Easy vertical mating •Excellent workability in production line •Multiple mating cycles •Allows multiple testing cycles •Assembly suction space on header •Stable pick-and-place area •RoHS & halogen free compliance•Environmentally friendlyReference Information Packaging:Embossed Tape UL File No.: TBD CSA File No.: TBD Designed In:mmElectrical Voltage:50V Current:1.5AApplicable wire range: AWG #28 to #30UL3302Contact Resistance:20 milliohms max. Dielectric Withstanding Voltage: 500V AC Insulation Resistance: 100 Megohms minimumPhysicalHousing: LCP, UL94V-0, Black Contact: Copper alloy Plating: GoldOperating Temperature:-25°C to +85°C1.20mm (.047”) Pitch Pico-EZmate™W-to-B Connectors Series 78171Header78172-Receptacle housing-TerminalNotebookMobile PhoneGPSMP3, MP4Any compact mobile device application Ordering InformationAmericas Headquarters 2222 Wellington Ct. Lisle, Illinois 60532 USA 1-800-78MOLEX amerinfo@ Asia Pacific NorthHeadquartersYamato, Kanagawa, Japan81-462-65-2324feninfo@Asia Pacific SouthHeadquartersJurong, Singapore65-6-268-6868fesinfo@European HeadquartersMunich, Germany49-89-413092-0eurinfo@Corporate Headquarters2222 Wellington Ct.Lisle, Illinois 60532 USA630-969-4550Visit our Web site at Markets and ApplicationsOrder No. : 9876501961©2008, Molex1.20mm (.047”) PitchPico-EZmate™W-to-BConnectorsSeries78171Header78172-Receptacle housing-TerminalOrder No.Circuits78171-1002278171-1003378171-1004478171-10055PCB HeaderOrder No.Circuits78172-0002278172-0003378172-0004478172-00055Receptacle HousingReceptacle Crimp TerminalOrder No.Circuits78172-0410N/A。

trf7960

1Introduction1.1Features1.2APPLICATIONS1.3DescriptionTRF7960,TRF7961MULTI-STANDARD FULLY INTEGRATED 13.56-MHZ RFID ANALOG FRONT END AND DATA-FRAMING READER SYSTEMSLOU186E–AUGUST 2006–REVISED JULY 2008–Standby 120µA•Completely Integrated Protocol Handling–Active (Rx only)10mA•Separate Internal High-PSRR Power Supplies •Parallel 8-Bit or Serial 4-Pin SPI Interface With for Analog,Digital,and PA Sections Provide MCU Using 12-Byte FIFONoise Isolation for Superior Read Range and Reliability•Ultrasmall 32-Pin QFN Package (5mm ×5mm)•Dual Receiver Inputs With AM and PM•Available ToolsDemodulation to Minimize Communication –Reference Design/EVM With Development HolesSoftware•Receiver AM and PM RSSI–Source Code Available for MSP430•Reader-to-Reader Anti-Collision•High Integration Reduces Total BOM and Board Area•Secure Access Control –Single External 13.56-MHz Crystal Oscillator•Product Authentication –MCU-Selectable Clock-Frequency Output of –Printer Ink Cartridges RF,RF/2,or RF/4–Blood Glucose Monitors –Adjustable 20-mA,High-PSRR LDO for •Contactless Payment Systems Powering External MCU•Medical Systems•Easy to Use With High Flexibility–Auto-Configured Default Modes for Each Supported ISO Protocol–12User-Programmable Registers The TRF7960/61is an integrated analog front –Selectable Receiver Gain and AGC end and data-framing system for a 13.56-MHz –Programmable Output Power RFID reader system.Built-in programming (100mW or 200mW)options make it suitable for a wide range of –Adjustable ASK Modulation Range applications for proximity and vicinity RFID (8%to 30%)systems.–Built-In Receiver Band-Pass Filter With User-Selectable Corner FrequenciesThe reader is configured by selecting the •Wide Operating Voltage Range of 2.7V to 5.5V desired protocol in the control registers.Direct •Ultralow-Power Modes access to all control registers allows fine tuning –Power Down <1µAof various reader parameters as needed.Table 1-1.PRODUCT SELECTION TABLEPROTOCOLSDEVICEISO14443A/BISO15693Tag-it™ISO18000-3106kbps212kbps424kbps848kbpsTRF7960√√√√√√TRF7961√√Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.Tag-it is a trademark of Texas Instruments Incorporated.PRODUCTION DATA information is current as of publication date.Copyright ©2006–2008,Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.ContentsTRF7960,TRF7961MULTI-STANDARD FULLY INTEGRATED 13.56-MHZ RFIDANALOG FRONT END AND DATA-FRAMING READER SYSTEMSLOU186E–AUGUST 2006–REVISED JULY 20084.4.1Application Schematic for the TRF7960EVM1Introduction ...............................................(Parallel Mode).......................................1.1Features ..............................................4.4.2ApplicationSchematicfortheTRF7961EVM(SPI1.2APPLICATIONS......................................Mode).................................................1.3Description (5)System Description ....................................2Description (continued)................................ 5.1Power Supplies .. (3)Physical Characteristics ............................... 5.2Receiver –Analog Section ..........................3.1Terminal Functions ................................... 5.3Register Descriptions ................................3.1PACKAGING/ORDERING INFORMATION..........5.4Direct Commands From MCU to Reader...........4ELECTRICAL SPECIFICATIONS ...................... 5.5Reader Communication Interface ...................4.1ABSOLUTE MAXIMUM RATINGS ................... 5.6Parallel Interface Communication ...................4.2DISSIPATION RATINGS TABLE .................... 5.7Serial Interface Communication .....................4.3RECOMMENDED OPERATING CONDITIONS ...... 5.8External Power Amplifier Application ................4.4ELECTRICAL CHARACTERISTICS .................2Contents Submit Documentation Feedback2Description (continued)TRF7960,TRF7961MULTI-STANDARD FULLY INTEGRATED 13.56-MHZ RFID ANALOG FRONT END AND DATA-FRAMING READER SYSTEMSLOU186E–AUGUST 2006–REVISED JULY 2008Figure 2-1.Typical ApplicationA parallel or serial interface can be used for communication between the MCU and reader.When hardware encoders and decoders are used (accelerators for different standards),transmit and receive functions use a 12-byte FIFO register.For direct transmit or receive functions,the encoders/decoders can be bypassed so the MCU can process the data in real time.The transmitter has selectable output-power levels of 100mW (20dBm)or 200mW (23dBm)into a 50-Ωload (at 5-V supply)and is capable of ASK or OOK modulation.Integrated voltage regulators ensure power-supply noise rejection for the complete reader system.Data transmission comprises low-level encoding for ISO15693,modified Miller for ISO14443-A,high-bit-rate systems and Tag-it coding systems.Included with the data encoding is automatic generation of SOF,EOF,CRC,and/or parity bits.The receiver system enables AM and PM demodulation using a dual-input architecture.The receiver also includes an automatic gain control option and selectable gain.Also included is a selectable bandwidth to cover a broad range of input subcarrier signal options.The received signal strength for AM and PM modulation is accessible via the RSSI register.The receiver output is selectable among a digitized subcarrier signal and any of ten integrated subcarrier decoders (two for ISO15693low bit rate,two for ISO15693high bit rate,two for ISO14443,three for ISO14443high bit rates and one for Tag-it systems).Selected decoders also deliver bit stream and a data clock as outputs.The receiver system also includes a framing system.This system performs the CRC and/or parity check,removes the EOF and SOF settings,and organizes the data in bytes.Framed data is then accessible to the MCU via a 12-byte FIFO register and MCU interface.The framing supports ISO14443and ISO15693protocols.The TRF7960/61supports data communication levels from 1.8V to 5.5V for the MCU I/O interface while also providing a data synchronization clock.An auxiliary 20-mA regulator (pin 32)is available for additional system circuits.Submit Documentation Feedback Description (continued)33Physical Characteristics3.1Terminal Functions242322212019181723456781109116151413123231302928272625TRF7960,TRF7961MULTI-STANDARD FULLY INTEGRATED 13.56-MHZ RFIDANALOG FRONT END AND DATA-FRAMING READER SYSTEMSLOU186E–AUGUST 2006–REVISED JULY 2008Figure 3-1.TRF796x Pin Assignments (Top View)Table 3-1.Terminal FunctionsTERMINAL TYPE (1)DESCRIPTIONNAME NO.Also can be configured to provide the received analog signal output (ANA_OUT)ASK/OOK 12BID Direct mode,selection between ASK and OOK modulation (0=ASK,1=OOK)BAND_GAP 11OUT Band-gap voltage (1.6V);internal analog voltage reference;must be ac-bypassed to ground.DATA_CLK 26INP Clock input for MCU communication (parallel and serial)EN 28INP Chip enable input (If EN =0,then chip is in power-down mode).Pulse enable and selection of power down mode.If EN2is connected to VIN,then VDD_X is EN225INP active during power down to support the MCU.Pin can also be used for pulse wake-up from power-down mode.I/O_017BID I/O pin for parallel communication I/O_118BID I/O pin for parallel communication I/O_219BID I/O pin for parallel communication I/O_320BID I/O pin for parallel communication I/O_421BID I/O pin for parallel communication I/O pin for parallel communication I/O_522BIDStrobe out clock for serial communication Data clock output in direct mode I/O pin for parallel communicationI/O_623BIDMISO for serial communication (SPI)Serial bit data output in direct mode 1or subcarrier signal in direct mode 0I/O pin for parallel communication.I/O_724BID MOSI for serial communication (SPI)IRQ 13OUT Interrupt requestMOD 14INPDirect mode,external modulation input(1)SUP =Supply,INP =Input,BID =Bi-directional,OUT =OutputPhysical Characteristics4Submit Documentation Feedback3.1PACKAGING/ORDERING INFORMATION(1)TRF7960,TRF7961MULTI-STANDARD FULLY INTEGRATED13.56-MHZ RFIDANALOG FRONT END AND DATA-FRAMING READER SYSTEM SLOU186E–AUGUST2006–REVISED JULY2008Table3-1.Terminal Functions(continued)TERMINALTYPE(1)DESCRIPTIONNAME NO.OSC_IN31INP Crystal oscillator inputOSC_OUT30OUT Crystal oscillator outputRX1_IN18INP RX input,used for AM receptionRX2_IN29INP RX input,used for PM receptionClock for MCU(3.39/6.78/13.56MHz)at EN=1and EN2=don't careSYS_CLK27OUTIf EN=0and EN2=1,then system clock is set to60kHzTX_OUT5OUT RF output(selectable output power,100mW at8Ωor200mW at4Ω,with VDD=5V)VDD_A1OUT Internal regulated supply(2.7V–3.4V)for analog circuitrySupply for I/O communications(1.8V–5.5V).Should be connected to VIN for5-VVDD_I/O16SUPcommunication,VDD_X for3.3-V communication,or any other voltage from1.8V to5.5V.VDD_PA4INP Supply for PA;normally connected externally to VDD_RF(pin3)VDD_RF3OUT Internal regulated supply(2.7V–5V),normally connected to VDD_PA(pin4)VDD_X32OUT Internally regulated supply(2.7V–3.4V)for external circuitry(MCU)VIN2SUP External supply input to chip(2.7V–5.5V)VSS10SUP Chip substrate groundVSS_A15SUP Negative supply for internal analog circuits;normally connected to circuit groundVSS_D29SUP Negative supply for internal digital circuits;normally connected to circuit groundVSS_PA6SUP Negative supply for PA;normally connected to circuit groundVSS_RX7SUP Negative supply for RX inputs;normally connected to circuit groundPACKAGED DEVICES PACKAGE TYPE(2)TRANSPORT MEDIA QUANTITY TRF7960RHBT Tape and reel250RHB-32TRF7960RHBR Tape and reel3000TRF7961RHBT Tape and reel250RHB-32TRF7961RHBR Tape and reel3000(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TIWeb site at .(2)Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at/sc/package.Submit Documentation Feedback Physical Characteristics54ELECTRICAL SPECIFICATIONS4.1ABSOLUTE MAXIMUM RATINGS4.2DISSIPATION RATINGS TABLE4.3RECOMMENDED OPERATING CONDITIONSTRF7960,TRF7961MULTI-STANDARD FULLY INTEGRATED 13.56-MHZ RFIDANALOG FRONT END AND DATA-FRAMING READER SYSTEMSLOU186E–AUGUST 2006–REVISED JULY 2008over operating free-air temperature range (unless otherwise noted)(1)VALUEUNIT VIN Supply voltage 6V I OOutput current150mA Continuous power dissipationSee Dissipation Ratings TableMaximum junction temperature,any condition (2)140°C T J Maximum junction temperature,continuous operation,long-term reliability (2)125°C T stgStorage temperature range–55to 150°C Lead temperature 1,6mm (1/16inch)from case for 10seconds300°C HBM (human body model)2kV ESDS ratingCDM (charged device model)500VMM (machine model)200(1)The absolute maximum ratings under any condition is limited by the constraints of the silicon process.Stresses above these ratings may cause permanent damage.Exposure to absolute maximum conditions for extended periods may degrade device reliability.These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified are not implied.(2)The maximum junction temperature for continuous operation is limited by package constraints.Operation above this temperature may result in reduced reliability and/or lifetime of the device.POWER RATING (2)θJC θJA (1)PACKAGE (°C/W)(°C/W)T A ≤25°C T A =85°C RHB (32)3136.42.7W1.1W(1)This data was taken using the JEDEC standard high-K test PCB.(2)Power rating is determined with a junction temperature of 125°C.This is the point where distortion starts to increase substantially.Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability.over operating free-air temperature range (unless otherwise noted)MINTYP MAX UNIT VIN Supply voltage2.75 5.5V T J Operating virtual junction temperature range –40125°C T AOperating ambient temperature range –4025110°C Load impedance at TX OUT (pin 5)10ΩELECTRICAL SPECIFICATIONS 6Submit Documentation Feedback4.4ELECTRICAL CHARACTERISTICSTRF7960,TRF7961 MULTI-STANDARD FULLY INTEGRATED13.56-MHZ RFIDANALOG FRONT END AND DATA-FRAMING READER SYSTEM SLOU186E–AUGUST2006–REVISED JULY2008over temperature range V S=5V(unless otherwise noted)TYP–40°CPARAMETER CONDITIONS MIN/25°C TO UNITMAX110°CI PD Supply current in power-down mode All systems disabled,including supply-voltage regulators110µA MAXThe reference voltage generator and the VDD_X remainI PD2Supply current in power-down mode2120300µA MAXactive to support external circuitry.Oscillator running,supply-voltage regulators inI STBY Supply current in standby mode 1.54mA MAXlow-consumption modeSupply current without antenna driver Oscillator,regulators,Rx and AGC,are all active.Tx isI ON11016mA MAXcurrent off.Supply current with antenna driver Oscillator,regulators,Rx,AGC,and Tx are all active.I ON270mA MAXcurrent Pout=100mW.Supply current with antenna driver Oscillator,regulators,Rx,AGC,and Tx are all active.I ON3120mA MAXcurrent Pout=200mW.1.4MINBG Band Gap voltage Internal analog reference voltage 1.6V1.7MAX1.4MINV POR Power on reset voltage(POR)2V2.5MAX3.1MINV DD_A Regulated supply for analog circuitry 3.5V3.8MAX4MINV DD_RF Regulated supply for RF circuitry Regulator set for5-V system with250-mV difference. 4.6V5.2MAX3.1MINV DD_X Regulated supply for external circuitry 3.4V3.8MAXThe difference between the external supply and theRejection of external supply noise onP PSRR regulated voltage is higher than250mV.Measured at2620dB MIN the supply VDD_RF regulator212kHz.Half-power mode812ΩMAXR RFOUT ANT driver output resistanceFul-power mode46ΩMAXRX1_IN1and RX2_IN2input5MINR RFIN10kΩresistance20MAXV RFIN Maximum input voltage At RX1_IN1and RX2_IN2inputs 3.5V PP MAXf SUBCARRIER=424kHz 1.2 2.5mV PP MAXV SENS Input sensitivityf SUBCARRIER=848kHz 1.23mV PP MAXt SET_PD Set up time after power down1020ms MAXt SET_STBY Set up time after standby mode30100µs MAXRecovery time after modulationt REC Modulation signal:sine,424-kHz,10-mVpp60µs MAX (ISO14443)30MINf SYS CLK SYS_CLK frequency In PD2mode EN=0and EN2=160kHz120MAX CLK MAX Maximum CLK frequency20MHz MAXV IL Input logic low0.20.2VDD_I/O MAXV IH Input logic high0.8VDD_I/O MINR OUT Output resistance I/O_0to I/O_7low_io=H for VDD_I/O<2.7V400800ΩMAXR SYS CLK Output resistance SYS_CLK low_io=H for VDD_I/O<2.7V200400ΩMAX Submit Documentation Feedback ELECTRICAL SPECIFICATIONS74.4.1Application Schematic for the TRF7960EVM (ParallelMode)50 R +j xTRF7960,TRF7961MULTI-STANDARD FULLY INTEGRATED 13.56-MHZ RFIDANALOG FRONT END AND DATA-FRAMING READER SYSTEMSLOU186E–AUGUST 2006–REVISED JULY 2008ELECTRICAL SPECIFICATIONS8Submit Documentation Feedback4.4.2Application Schematic for the TRF7961EVM (SPIMode)50 R +j xTRF7960,TRF7961MULTI-STANDARD FULLY INTEGRATED 13.56-MHZ RFID ANALOG FRONT END AND DATA-FRAMING READER SYSTEMSLOU186E–AUGUST 2006–REVISED JULY 2008Submit Documentation FeedbackELECTRICAL SPECIFICATIONS 95System Description5.1Power Supplies5.1.1Negative Supply Connections5.1.2Digital I/O InterfaceTRF7960,TRF7961MULTI-STANDARD FULLY INTEGRATED 13.56-MHZ RFIDANALOG FRONT END AND DATA-FRAMING READER SYSTEMSLOU186E–AUGUST 2006–REVISED JULY 2008The positive supply pin,VIN (pin 2)has an input voltage range of 2.7V to 5.5V.The positive supply input sources three internal regulators with output voltages V DD_RF ,V DD_A and V DD_X that use external bypass capacitors for supply noise filtering.These regulators provide enhanced PSRR for the RFID reader system.The regulators are not independent and have common control bits for output voltage setting.The regulators can be configured to operate in either automatic or manual mode.The automatic regulator setting mode ensures an optimal compromise between PSRR and the highest possible supply voltage for RF output (to ensure maximum RF power output).Whereas,the manual mode allows the user to manually configure the regulator settings.V DD_RFThe regulator V DD_RF (pin 3)is used to source the RF output stage.The voltage regulator can be set for either 5-V or 3-V operation.When configured for the 5-V operation range,the output voltage can be set from 4.3V to 5V in 100-mV steps.The current sourcing capability for 5-V operation is 150mA maximum over the adjusted output voltage range.When configured for 3-V operation,the output can be set from 2.7V to 3.4V,also in 100-mV steps.The current sourcing capability for 3-V operation is 100mA maximum over the adjusted output voltage range.V DD_ARegulator V DD_A (pin 1)supplies voltage to analog circuits within the reader chip.The voltage setting is divided in two ranges.When configured for 5-V operation,the output voltage is fixed at 3.5V.When configured for 3-V operation,the output can be set from 2.7V to 3.4V in 100-mV steps.Note that when configured,both V DD_A and V DD_X regulators are configured together (their settings are not independent).V DD_XRegulator V DD_X (pin 32)can be used to source the digital I/O of the reader chip together with other external system components.When configured for 5-V operation,the output voltage is fixed at 3.4V.When configured for 3-V operation,the output voltage can be set from 2.7to 3.4V in 100-mV steps.The total current sourcing capability of the V DD_X regulator is 20mA maximum over the adjusted output range.Note that when configured,both V DD_A and V DD_X regulators are configured together (their settings are not independent).V DD_PAThe V DD_PA pin (pin 4)is the positive supply pin for the RF output stage and is externally connected to the regulator output V DD_RF (pin 3).The negative supply connections are all externally connected together (to GND).The substrate connection is V SS (pin 10),the analog negative supply is V SS_A (pin 15),the logic negative supply is V SS_D (pin 29),the RF output stage negative supply is V SS_TX (pin 6),and the negative supply for the RF receiver input is V SS_RX (pin 7).To allow compatible I/O signal levels,the TRF7960/61has a separate supply input V DD_I/O (pin 16),with an input voltage range of 1.8V to 5.5V.This pin is used to supply the I/O interface pins (I/O_0to I/O_7),IRQ,SYS_CLK,and DATA_CLK pins of the reader.In typical applications,V DD_I/O is connected directly to V DD_X to ensure that the I/O signal levels of the MCU are the same as the internal logic levels of the reader.System Description 10Submit Documentation Feedback5.1.3Supply Regulator ConfigurationThe supply regulators can be automatically or manually configured by the control bits.The available options are shown in Table5-1through Table5-4.Table5-1shows a5-V system and the manual-mode regulator settings.Table5-2shows manual mode for selection of a3-V system.Table5-3and Table5-4 show the automatic-mode gain settings for5-V and3-V systems.The automatic mode is the default configuration.In automatic mode,the regulators are automatically set every time the system is activated by asserting the EN input HIGH.The internal regulators are also automatically reconfigured every time the automatic regulator selection bit is set HIGH(on the rising edge).The user can re-run the automatic mode setting from a state in which the automatic setting bit is already high by changing the automatic setting bit from high to low to high.The regulator-configuration algorithm adjusts the regulator outputs250mV below the V IN level,but not higher than5V for V DD_RF,3.5V for V DD_A,and3.4V for V DD_X.This ensures the highest possible supply voltage for the RF output stage while maintaining an adequate PSRR(power supply rejection ratio).As an example,the user can improve the PSRR if there is a noisy supply voltage from V DD_X by increasing the target voltage difference across the V DD_X regulator as shown for automatic regulator settings in Table5-3and Table5-4.Table5-1.Supply-Regulator Setting–Manual–5-V System Byte Option Bits Setting in Control Register ActionAddress B7B6B5B4B3B2B1B00015-V system0B0Manual regulator setting0B0111V DD_RF=5V,V DD_A=3.5V,and V DD_X=3.4V0B0110V DD_RF=4.9V,V DD_A=3.5V,and V DD_X=3.4V0B0101V DD_RF=4.8V,V DD_A=3.5V,and V DD_X=3.4V0B0100V DD_RF=4.7V,V DD_A=3.5V,and V DD_X=3.4V0B0011V DD_RF=4.6V,V DD_A=3.5V,and V DD_X=3.4V0B0010V DD_RF=4.5V,V DD_A=3.5V,and V DD_X=3.4V0B0001V DD_RF=4.4V,V DD_A=3.5V,and V DD_X=3.4V0B0000V DD_RF=4.3V,V DD_A=3.5V,and V DD_X=3.4VTable5-2.Supply-Regulator Setting–Manual–3-V System Byte Option Bits Setting in Control Register ActionAddress B7B6B5B4B3B2B1B00003V system0B0Manual regulator setting0B0111V DD_RF=3.4V,V DD_A,and V DD_X=3.4V0B0110V DD_RF=3.3V,V DD_A,and V DD_X=3.3V0B0101V DD_RF=3.2V,V DD_A,and V DD_X=3.2V0B0100V DD_R F=3.1V,V DD_A,and V DD_X=3.1V0B0011V DD_RF=3.0V,V DD_A,and V DD_X=3.0V0B0010V DD_RF=2.9V,V DD_A,and V DD_X=2.9V0B0001V DD_RF=2.8V,V DD_A,and V DD_X=2.8V0B0000V DD_RF=2.7V,V DD_A,and V DD_X=2.7VTable5-3.Supply-Regulator Setting–Automatic–5-V System Byte Option Bits Setting in Control Register ActionAddress B7B6B5B4B3B2(1)B1B00015-V system0B1x11Automatic regulator setting≈250-mV difference0B1x10Automatic regulator setting≈350-mV difference0B1x00Automatic regulator setting≈400-mV difference(1)X are don't caresTable5-4.Supply-Regulator Setting–Automatic–3-V System Byte Option Bits Setting in Control Register ActionAddress B7B6B5B4B3B2(1)B1B00003-V system0B1x11Automatic regulator setting≈250-mV difference0B1x10Automatic regulator setting≈350-mV difference0B1x00Automatic regulator setting≈400-mV difference(1)X are don't cares5.1.4Power ModesThe chip has seven power states,which are controlled by two input pins(EN and EN2)and three bits in the chip status control register(00h).The main reader enable input is EN(which has a threshold level of1V minimum).Any input signal level from1.8V to V IN can be used.When EN is set high,all of the reader regulators are enabled,together with the13.56-MHz oscillator,while the SYS_CLK(output clock for external micro controller)is made available.The auxiliary-enable input EN2has two functions.A direct connection from EN2to V IN ensures availability of the regulated supply(V DD_X)and an auxiliary clock signal(60kHz)on the SYS_CLK output(same for the case EN=0).This mode is intended for systems in which the MCU controlling the reader is also being supplied by the reader supply regulator(V DD_X)and the MCU clock is supplied by the SYS_CLK output of the reader.This allows the MCU supply and clock to be available during power-down.A second function of the EN2input is to enable start-up of the reader system from complete power down(EN=0,EN2=0).In this case the EN input is being controlled by the MCU or other system device that is without supply voltage during complete power down(thus unable to control the EN input).A rising edge applied to the EN2input(which has a1-V threshold level)starts the reader supply system and13.56-MHz oscillator(identical to condition EN=1).This start-up mode lasts until all of the regulators have settled and the13.56-MHz oscillator has stabilized.If the EN input is set high by the MCU(or other system device),the reader stays active.If the EN input is not set high within100µs after the SYS_CLK output is switched from auxiliary clock(60kHz)to high-frequency clock(derived from the crystal oscillator),the reader system returns to complete power-down mode.This option can be used to wake the reader system from complete power down by using a pushbutton switch or by sending a single pulse.After the reader EN line is high,the other power modes are selected by control bits.The power mode options and functions are listed in Table5-5.Table5-5.Power ModesByte Option Bits Setting in Chip Status Control Register EN EN2Functionality Current AddressB7B6B5B4B3B2B1B0STBY RFON RF PWR REC ON0000Complete power down<1µA 0001VDD_X available120µASYS_CLK auxiliary frequency60kHz is ON 001x x x1x All supply regulators active and in low power 1.5mAmode13.56-MHz oscillator ONSYS_CLK clock available 0000x01x All supply regulators active 3.5mA13.56-MHz oscillator ONSYS_CLK clock available 0000x11x All supply regulators active10mA13.56-MHz oscillator ONSYS_CLK clock availableReceiver active00011x1x All supply regulators active70mA13.56-MHz oscillator ON(at5V)SYS_CLK clock availableReceiver activeTransmitter active–half-power mode 00010x1x All supply regulators active120mA13.56-MHz oscillator running(at5V)SYS_CLK clock availableReceiver activeTransmitter active–full-power mode During reader inactivity,the TRF7960/61can be placed in power down-mode(EN=0).The power down can be complete(EN=0,EN2=0)with no function running,or partial(EN=0,EN=1)where the regulated supply(V DD_X)and auxiliary clock60kHz(SYS_CLK)are available to the MCU or other system device.When EN is set high(or on rising edge of EN2and then confirmed by EN=1),the supply regulators are activated and the13.56-MHz oscillator started.When the supplies are settled and the oscillator frequency is stable,the SYS_CLK output is switched from the auxiliary frequency of60kHz to the selected frequency derived from the crystal oscillator.At this point,the reader is ready to communicate and perform the required tasks.The control system(MCU)can then write appropriate bits to the chip status control register(address00)and select the operation mode.The STANDBY mode(bit7=1of register00)is the active mode with the lowest current consumption.The reader is capable of recovering from this mode to full operation in100µs.The active mode with RF section disabled(bit5=0and bit1=0of register00)is the next active mode with low power consumption.The reader is capable of recovering from this mode to full operation in25µs.The active mode with only the RF receiver section active(bit1=1of register00)can be used to measure the external RF field(as described in RSSI measurements paragraph)if reader-to-reader anticollision is implemented.The active mode with the entire RF section active(bit5=1of register00)is the normal mode used for transmit and receive operations.5.1.5Timing DiagramsCHIP POWER UP TO CLOCK STARTC001Figure5-1.Power Up[V IN(Blue)to Crystal Start(Red)] CHIP ENABLE TO CLOCK STARTC002Figure5-2.EN2Low and EN High(Blue)to Start of System Clock(Red)。

KA7810中文资料

Rev. 1.0.0Features•Output Current up to 1A •Output V oltages of 5, 6, 8, 9, 10, 12, 15, 18, 24V•Thermal Overload Protection •Short Circuit Protection•Output Transistor Safe Operating Area ProtectionDescriptionThe KA78XX/KA78XXA series of three-terminal positive regulator are available in the TO-220/D-PAK package and with several fixed output voltages, making them useful in a wide range of applications. Each type employs internalcurrent limiting, thermal shut down and safe operating area protection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 1A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltages and currents.TO-220D-PAK1. Input2. GND3. Output11Internal Block DigramKA78XX/KA78XXA3-Terminal 1A Positive Voltage RegulatorKA78XX/KA78XXAAbsolute Maximum RatingsElectrical Characteristics (KA7805/KA7805R)(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =10V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V o due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol Value Unit Input Voltage (for V O = 5V to 18V)(for V O = 24V)V I V I 3540V V Thermal Resistance Junction-Cases (TO-220)R θJC 5°C/WThermal Resistance Junction-Air (TO-220)R θJA 65°C/WOperating Temperature Range (KA78XX/A/R)T OPR 0 ~ +125°C Storage Temperature RangeT STG-65 ~ +150°CParameterSymbolConditionsKA7805UnitMin.Typ.Max.Output VoltageV OT J =+25 o C4.85.0 5.25.0mA ≤Io ≤1.0A, P O ≤15W V I = 7V to 20V 4.75 5.0 5.25 V Line Regulation (Note1)Regline T J =+25 o C V O = 7V to 25V - 4.0100mV V I = 8V to 12V - 1.650Load Regulation (Note1)Regload T J =+25 o C I O = 5.0mA to1.5A -9100mV I O =250mA to 750mA -450Quiescent Current I Q T J =+25 o C - 5.08.0mA Quiescent Current Change ∆I Q I O = 5mA to 1.0A -0.030.5mA V I = 7V to 25V -0.3 1.3Output Voltage Drift ∆V O /∆T I O = 5mA--0.8-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -42-µV/V O Ripple Rejection RR f = 120HzV O = 8V to 18V 6273-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-15-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -230-mA Peak CurrentI PKT J =+25 o C- 2.2-AKA78XX/KA78XXAElectrical Characteristics (KA7806/KA7806R)(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =11V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsKA7806UnitMin.Typ.Max.Output VoltageV OT J =+25 o C5.756.0 6.255.0mA ≤I O ≤1.0A, P O ≤15W V I = 8.0V to 21V 5.7 6.0 6.3 V Line Regulation (Note1)Regline T J =+25 o C V I = 8V to 25V -5120mV V I = 9V to 13V - 1.560Load Regulation (Note1)Regload T J =+25 o C I O =5mA to 1.5A -9120mV I O =250mA to750mA -360Quiescent Current I Q T J =+25 o C - 5.08.0mA Quiescent Current Change ∆I Q I O = 5mA to 1A --0.5mA V I = 8V to 25V -- 1.3Output Voltage Drift ∆V O /∆T I O = 5mA--0.8-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -45-µV/Vo Ripple Rejection RR f = 120HzV I = 9V to 19V 5975-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-19-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -250-mA Peak CurrentI PKT J =+25 o C- 2.2-AKA78XX/KA78XXAElectrical Characteristics (KA7808/KA7808R)(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =14V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsKA7808UnitMin.Typ.Max.Output VoltageV OT J =+25 o C7.78.08.35.0mA ≤ I O ≤1.0A, P O ≤15W V I = 10.5V to 23V 7.68.08.4 V Line Regulation (Note1)ReglineT J =+25 o C V I = 10.5V to 25V - 5.0160mV V I = 11.5V to 17V - 2.080Load Regulation (Note1)Regload T J =+25 o C I O = 5.0mA to 1.5A-10160mV I O = 250mA to 750mA - 5.080Quiescent Current I Q T J =+25 o C - 5.08.0mA Quiescent Current Change ∆I Q I O = 5mA to 1.0A -0.050.5mA V I = 10.5A to 25V -0.5 1.0Output Voltage Drift ∆V O /∆T I O = 5mA--0.8-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -52-µV/Vo Ripple Rejection RR f = 120Hz, V I = 11.5V to 21.5V 5673-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-17-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -230-mA Peak CurrentI PKT J =+25 o C- 2.2-AKA78XX/KA78XXAElectrical Characteristics (KA7809/KA7809R)(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =15V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsKA7809UnitMin.Typ.Max.Output VoltageV OT J =+25 o C8.6599.355.0mA ≤ I O ≤1.0A, P O ≤15W V I = 11.5V to 24V 8.699.4 V Line Regulation (Note1)Regline T J =+25 o C V I = 11.5V to 25V -6180mV V I = 12V to 17V -290Load Regulation (Note1)Regload T J =+25 o C I O = 5mA to 1.5A -12180mV I O = 250mA to 750mA -490Quiescent Current I Q T J =+25 o C - 5.08.0mA Quiescent Current Change ∆I Q I O = 5mA to 1.0A --0.5mA V I = 11.5V to 26V -- 1.3Output Voltage Drift ∆V O /∆T I O = 5mA--1-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -58-µV/Vo Ripple Rejection RR f = 120HzV I = 13V to 23V 5671-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-17-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -250-mA Peak CurrentI PKT J = +25 o C- 2.2-AElectrical Characteristics (KA7810)(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =16V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsKA7810UnitMin.Typ.Max.Output VoltageV OT J =+25 o C9.61010.45.0mA ≤ I O ≤ 1.0A, P O ≤ 15W V I = 12.5V to 25V 9.51010.5 V Line Regulation (Note1)Regline T J =+25 o C V I = 12.5V to 25V -10200mV V I = 13V to 25V -3100Load Regulation (Note1)Regload T J =+25 o C I O = 5mA to 1.5A -12200mV I O = 250mA to 750mA -4400Quiescent Current I Q T J =+25 o C - 5.18.0mA Quiescent Current Change ∆I Q I O = 5mA to 1.0A --0.5mA V I = 12.5V to 29V -- 1.0Output Voltage Drift ∆V O /∆T I O = 5mA--1-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -58-µV/Vo Ripple Rejection RR f = 120HzV I = 13V to 23V 5671-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-17-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -250-mA Peak CurrentI PKT J =+25 o C- 2.2-AElectrical Characteristics (KA7812/KA7812R)(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =19V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsKA7812/KA7812R UnitMin.Typ.Max.Output VoltageV OT J =+25 o C11.51212.55.0mA ≤ I O ≤1.0A, P O ≤15W V I = 14.5V to 27V 11.41212.6 V Line Regulation (Note1)ReglineT J =+25 o CV I = 14.5V to 30V -10240mV V I = 16V to 22V - 3.0120Load Regulation (Note1)Regload T J =+25 o C I O = 5mA to 1.5A -11240mV I O = 250mA to 750mA - 5.0120Quiescent Current I Q T J =+25 o C - 5.18.0mA Quiescent Current Change ∆I Q I O = 5mA to 1.0A -0.10.5mA V I = 14.5V to 30V -0.5 1.0Output Voltage Drift ∆V O /∆T I O = 5mA--1-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -76-µV/Vo Ripple Rejection RR f = 120HzV I = 15V to 25V 5571-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-18-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -230-mA Peak CurrentI PKT J = +25 o C- 2.2-AKA78XX/KA78XXAElectrical Characteristics (KA7815)(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =23V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsKA7815UnitMin.Typ.Max.Output VoltageV OT J =+25 o C14.41515.65.0mA ≤ I O ≤1.0A, P O ≤15W V I = 17.5V to 30V 14.251515.75 V Line Regulation (Note1)Regline T J =+25 o C V I = 17.5V to 30V -11300mV V I = 20V to 26V -3150Load Regulation (Note1)Regload T J =+25 o C I O = 5mA to 1.5A -12300mV I O = 250mA to 750mA -4150Quiescent Current I Q T J =+25 o C - 5.28.0mA Quiescent Current Change ∆I Q I O = 5mA to 1.0A --0.5mA V I = 17.5V to 30V -- 1.0Output Voltage Drift ∆V O /∆T I O = 5mA--1-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -90-µV/Vo Ripple Rejection RR f = 120HzV I = 18.5V to 28.5V 5470-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-19-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -250-mA Peak CurrentI PKT J =+25 o C- 2.2-AKA78XX/KA78XXAElectrical Characteristics (KA7818)(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =27V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsKA7818UnitMin.Typ.Max.Output VoltageV OT J =+25 o C17.31818.75.0mA ≤ I O ≤1.0A, P O ≤15W V I = 21V to 33V 17.11818.9 V Line Regulation (Note1)Regline T J =+25 o C V I = 21V to 33V -15360mV V I = 24V to 30V -5180Load Regulation (Note1)Regload T J =+25 o C I O = 5mA to 1.5A -15360mV I O = 250mA to 750mA - 5.0180Quiescent Current I Q T J =+25 o C - 5.28.0mA Quiescent Current Change ∆I Q I O = 5mA to 1.0A --0.5mA V I = 21V to 33V --1Output Voltage Drift ∆V O /∆T I O = 5mA--1-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -110-µV/Vo Ripple Rejection RR f = 120HzV I = 22V to 32V 5369-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-22-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -250-mA Peak CurrentI PKT J =+25 o C-2.2-AKA78XX/KA78XXAElectrical Characteristics (KA7824)(Refer to test circuit ,0°C < T J < 125°C, I O = 500mA, V I =33V, C I = 0.33µF, C O =0.1µF, unless otherwise specified)Note:1. Load and line regulation are specified at constant junction temperature. Changes in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsKA7824UnitMin.Typ.Max.Output VoltageV OT J =+25 o C2324255.0mA ≤ I O ≤ 1.0A, P O ≤ 15W V I = 27V to 38V 22.82425.25 V Line Regulation (Note1)ReglineT J =+25 o CV I = 27V to 38V -17480mV V I = 30V to 36V -6240Load Regulation (Note1)Regload T J =+25 o C I O = 5mA to 1.5A -15480mV I O = 250mA to 750mA - 5.0240Quiescent Current I Q T J =+25 o C - 5.28.0mA Quiescent Current Change ∆I QI O = 5mA to 1.0A -0.10.5mA V I = 27V to 38V-0.51Output Voltage Drift ∆V O /∆T I O = 5mA --1.5-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz, T A =+25 o C -60-µV/Vo Ripple Rejection RR f = 120HzV I = 28V to 38V 5067-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-28-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -230-mA Peak CurrentI PKT J =+25 o C- 2.2-AKA78XX/KA78XXAElectrical Characteristics (KA7805A)(Refer to the test circuits. 0o C < T J < +125 o C, I o =1A, V I = 10V, C I =0.33µF, C O =0.1µF, unless otherwise speci-fied)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol ConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25 o C4.955.1V I O = 5mA to 1A, P O ≤ 15W V I = 7.5V to 20V 4.85 5.2Line Regulation (Note1)ReglineV I = 7.5V to 25V I O = 500mA-550mV V I = 8V to 12V -350T J =+25 o CV I = 7.3V to 20V -550V I = 8V to 12V- 1.525Load Regulation (Note1)RegloadT J =+25 o CI O = 5mA to 1.5A -9100mV I O = 5mA to 1A -9100I O = 250mA to 750mA -450Quiescent Current I Q T J =+25 o C - 5.0 6.0mA Quiescent Current Change∆I Q I O = 5mA to 1A--0.5mA V I = 8 V to 25V, I O = 500mA --0.8V I = 7.5V to 20V, T J =+25 o C --0.8Output Voltage Drift ∆V/∆T Io = 5mA--0.8-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25 o C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 8V to 18V -68-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-17-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -250-mA Peak CurrentI PKT J = +25 o C- 2.2-AKA78XX/KA78XXAElectrical Characteristics (KA7806A)(Refer to the test circuits. 0o C < T J < +125 o C, I o =1A, V I = 11V, C I =0.33µF, C O =0.1µF, unless otherwise speci-fied)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol ConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25 o C5.5866.12V I O = 5mA to 1A, P O ≤ 15W V I = 8.6V to 21V 5.766 6.24Line Regulation (Note1)ReglineV I = 8.6V to 25V I O = 500mA-560mV V I = 9V to 13V -360T J =+25 o CV I = 8.3V to 21V -560V I = 9V to 13V- 1.530Load Regulation (Note1)RegloadT J =+25 o CI O = 5mA to 1.5A -9100mV I O = 5mA to 1A -4100I O = 250mA to 750mA - 5.050Quiescent Current I Q T J =+25 o C - 4.3 6.0mA Quiescent Current Change ∆I Q I O = 5mA to 1A--0.5mA V I = 9V to 25V, I O = 500mA --0.8V I = 8.5V to 21V, T J =+25 o C --0.8Output Voltage Drift ∆V/∆T I O = 5mA--0.8-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25 o C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 9V to 19V -65-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-17-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -250-mA Peak CurrentI PKT J =+25 o C- 2.2-AKA78XX/KA78XXAElectrical Characteristics (KA7808A)(Refer to the test circuits. 0o C < T J < +125 o C, I o =1A, V I = 14V, C I =0.33µF, C O =0.1µF, unless otherwise speci-fied)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol ConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25 o C7.8488.16V I O = 5mA to 1A, P O ≤15W V I = 10.6V to 23V 7.788.3Line Regulation (Note1)ReglineV I = 10.6V to 25V I O = 500mA-680mV V I = 11V to 17V -380T J =+25 o CV I = 10.4V to 23V -680V I = 11V to 17V-240Load Regulation (Note1)RegloadT J =+25 o CI O = 5mA to 1.5A -12100mV I O = 5mA to 1A -12100I O = 250mA to 750mA -550Quiescent Current I Q T J =+25 o C - 5.0 6.0mA Quiescent Current Change ∆I Q I O = 5mA to 1A--0.5mA V I = 11V to 25V, I O = 500mA --0.8V I = 10.6V to 23V, T J =+25 o C --0.8Output Voltage Drift ∆V/∆T I O = 5mA--0.8-mV/ o C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25 o C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 11.5V to 21.5V -62-dB Dropout Voltage V Drop I O = 1A, T J =+25 o C -2-V Output Resistance r O f = 1KHz-18-m ΩShort Circuit Current I SC V I = 35V, T A =+25 o C -250-mA Peak CurrentI PKT J =+25 o C- 2.2-AKA78XX/KA78XXAElectrical Characteristics (KA7809A)(Refer to the test circuits. 0o C < T J < +125 o C, I o =1A, V I = 15V, C I =0.33µF, C O =0.1µF, unless otherwise speci-fied)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25°C8.829.09.18V I O = 5mA to 1A, P O ≤15W V I = 11.2V to 24V 8.659.09.35Line Regulation (Note1)ReglineV I = 11.7V to 25V I O = 500mA-690mV V I = 12.5V to 19V -445T J =+25°CV I = 11.5V to 24V -690 V I = 12.5V to 19V -245Load Regulation (Note1)RegloadT J =+25°CI O = 5mA to 1.0A -12100mV I O = 5mA to 1.0A -12100I O = 250mA to 750mA -550Quiescent Current I Q T J =+25 °C- 5.0 6.0mA Quiescent Current Change ∆I Q V I = 11.7V to 25V, T J =+25 °C --0.8mA V I = 12V to 25V, I O = 500mA --0.8I O = 5mA to 1.0A --0.5Output Voltage Drift ∆V/∆T I O = 5mA--1.0-mV/ °C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25 °C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 12V to 22V -62-dB Dropout Voltage V Drop I O = 1A, T J =+25 °C - 2.0-V Output Resistance r O f = 1KHz-17-m ΩShort Circuit Current I SC V I = 35V, T A =+25 °C -250-mA Peak CurrentI PKT J =+25°C- 2.2-A(Refer to the test circuits. 0o C < T J < +125 o C, I o =1A, V I = 16V, C I =0.33µF, C O =0.1µF, unless otherwise speci-fied)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbolConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25°C9.81010.2V I O = 5mA to 1A, P O ≤ 15W V I =12.8V to 25V 9.61010.4Line Regulation (Note1)ReglineV I = 12.8V to 26V I O = 500mA-8100mV V I = 13V to 20V -450 T J =+25 °CV I = 12.5V to 25V -8100 V I = 13V to 20V -350Load Regulation (Note1)RegloadT J =+25 °CI O = 5mA to 1.5A -12100mV I O = 5mA to 1.0A -12100 I O = 250mA to 750mA -550Quiescent Current I Q T J =+25 °C- 5.0 6.0mA Quiescent Current Change ∆I QV I = 13V to 26V, T J =+25 °C --0.5mA V I = 12.8V to 25V, I O = 500mA --0.8 I O = 5mA to 1.0A--0.5Output Voltage Drift ∆V/∆T I O = 5mA --1.0-mV/ °C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25 °C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 14V to 24V -62-dB Dropout Voltage V Drop I O = 1A, T J =+25°C - 2.0-V Output Resistance r O f = 1KHz-17-m ΩShort Circuit Current I SC V I = 35V, T A =+25 °C -250-mA Peak CurrentI PKT J =+25 °C- 2.2-A(Refer to the test circuits. 0o C < T J < +125 o C, I o =1A, V I = 19V, C I =0.33µF, C O =0.1µF, unless otherwise speci-fied)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol ConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25 °C11.751212.25V I O = 5mA to 1A, P O ≤15W V I = 14.8V to 27V 11.51212.5Line Regulation (Note1)ReglineV I = 14.8V to 30V I O = 500mA-10120mV V I = 16V to 22V -4120 T J =+25 °CV I = 14.5V to 27V -10120 V I = 16V to 22V-360Load Regulation (Note1)RegloadT J =+25 °CI O = 5mA to 1.5A -12100mV I O = 5mA to 1.0A -12100 I O = 250mA to 750mA -550Quiescent Current I Q T J =+25°C- 5.16.0mA Quiescent Current Change ∆I QV I = 15V to 30V, T J =+25 °C -0.8mA V I = 14V to 27V, I O = 500mA -0.8 I O = 5mA to 1.0A-0.5Output Voltage Drift ∆V/∆T I O = 5mA --1.0-mV/°C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25°C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 14V to 24V -60-dB Dropout Voltage V Drop I O = 1A, T J =+25°C - 2.0-V Output Resistance r O f = 1KHz-18-m ΩShort Circuit Current I SC V I = 35V, T A =+25 °C -250-mA Peak CurrentI PKT J =+25 °C- 2.2-AKA78XX/KA78XXAElectrical Characteristics (KA7815A)(Refer to the test circuits. 0o C < T J < +125 o C, I o =1A, V I =23V, C I =0.33µF, C O =0.1µF, unless otherwise speci-fied)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol ConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25 °C14.71515.3V I O = 5mA to 1A, P O ≤15W V I = 17.7V to 30V 14.41515.6Line Regulation (Note1)ReglineV I = 17.9V to 30V I O = 500mA-10150mV V I = 20V to 26V -5150 T J =+25°CV I = 17.5V to 30V -11150 V I = 20V to 26V-375Load Regulation (Note1)RegloadT J =+25 °CI O = 5mA to 1.5A -12100mV I O = 5mA to 1.0A -12100 I O = 250mA to 750mA -550Quiescent Current I Q T J =+25 °C- 5.2 6.0mA Quiescent Current Change ∆I QV I = 17.5V to 30V, T J =+25 °C --0.8mA V I = 17.5V to 30V, I O = 500mA --0.8 I O = 5mA to 1.0A--0.5Output Voltage Drift ∆V/∆T I O = 5mA --1.0-mV/°C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25 °C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 18.5V to 28.5V -58-dB Dropout Voltage V Drop I O = 1A, T J =+25 °C - 2.0-V Output Resistance r O f = 1KHz-19-m ΩShort Circuit Current I SC V I = 35V, T A =+25 °C -250-mA Peak CurrentI PKT J =+25°C- 2.2-AKA78XX/KA78XXAElectrical Characteristics (KA7818A)(Refer to the test circuits. 0o C < T J < +125 o C, I o =1A, V I = 27V, C I =0.33µF, C O =0.1µF, unless otherwise speci-fied)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol ConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25 °C17.641818.36V I O = 5mA to 1A, P O ≤15W V I = 21V to 33V 17.31818.7Line Regulation (Note1)ReglineV I = 21V to 33V I O = 500mA-15180mV V I = 21V to 33V -5180 T J =+25 °CV I = 20.6V to 33V -15180 V I = 24V to 30V-590Load Regulation (Note1)RegloadT J =+25°CI O = 5mA to 1.5A -15100mV I O = 5mA to 1.0A -15100 I O = 250mA to 750mA -750Quiescent Current I Q T J =+25 °C- 5.2 6.0mA Quiescent Current Change ∆I QV I = 21V to 33V, T J =+25 °C --0.8mA V I = 21V to 33V, I O = 500mA --0.8 I O = 5mA to 1.0A--0.5Output Voltage Drift ∆V/∆T I O = 5mA --1.0-mV/ °C Output Noise Voltage V N f = 10Hz to 100KHz T A =+25°C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 22V to 32V -57-dB Dropout Voltage V Drop I O = 1A, T J =+25°C - 2.0-V Output Resistance r O f = 1KHz-19-m ΩShort Circuit Current I SC V I = 35V, T A =+25°C -250-mA Peak CurrentI PKT J =+25 °C- 2.2-AKA78XX/KA78XXAElectrical Characteristics (KA7824A)(Refer to the test circuits. 0o C < T J < +125 o C, I o =1A, V I = 33V, C I =0.33µF, C O =0.1µF, unless otherwise speci-fied)Note:1. Load and line regulation are specified at constant junction temperature. Change in V O due to heating effects must be takeninto account separately. Pulse testing with low duty is used.ParameterSymbol ConditionsMin.Typ.Max.UnitOutput VoltageV OT J =+25 °C23.52424.5V I O = 5mA to 1A, P O ≤15W V I = 27.3V to 38V 232425Line Regulation (Note1)ReglineV I = 27V to 38V I O = 500mA-18240mV V I = 21V to 33V -6240 T J =+25 °CV I = 26.7V to 38V -18240 V I = 30V to 36V-6120Load Regulation (Note1)RegloadT J =+25 °CI O = 5mA to 1.5A -15100mV I O = 5mA to 1.0A -15100 I O = 250mA to 750mA -750Quiescent Current I Q T J =+25 °C- 5.2 6.0mA Quiescent Current Change ∆I QV I = 27.3V to 38V, T J =+25 °C --0.8mA V I = 27.3V to 38V, I O = 500mA --0.8 I O = 5mA to 1.0A--0.5Output Voltage Drift ∆V/∆T I O = 5mA --1.5-mV/ °C Output Noise Voltage V N f = 10Hz to 100KHz T A = 25 °C-10-µV/Vo Ripple Rejection RR f = 120Hz, I O = 500mA V I = 28V to 38V -54-dB Dropout Voltage V Drop I O = 1A, T J =+25 °C - 2.0-V Output Resistance r O f = 1KHz-20-m ΩShort Circuit Current I SC V I = 35V, T A =+25 °C -250-mA Peak CurrentI PKT J =+25 °C- 2.2-AKA78XX/KA78XXATypical Perfomance CharacteristicsFigure 1.Quiescent Current Figure 3.Output Voltage Figure 2.Peak Output Current Figure 4.Quiescent CurrentITypical ApplicationsInput OutputFigure 5.DC ParametersInput OutputFigure 6.Load RegulationInput OutputFigure 7.Ripple RejectionInput OutputFigure 8.Fixed Output Regulator2122Figure 9.Constant Current RegulatorNotes :(1)To specify an output voltage. substitute voltage value for "XX." A common ground is required between the input and the Outputvoltage. The input voltage must remain typically 2.0V above the output voltage even during the low point on the input ripple voltage.(2)C I is required if regulator is located an appreciable distance from power Supply filter.(3)C O improves stability and transient response.V O = V XX (1+R 2/R 1)+I Q R 2Figure 10.Circuit for Increasing Output VoltageI RI ≥5 I QV O = V XX (1+R 2/R 1)+I Q R 2Figure 11.Adjustable Output Regulator (7 to 30V)InputOutputC ICOInput OutputC IC OI RI 5IQ≥Input OutputC IC O23Figure 12.High Current Voltage RegulatorFigure 13.High Output Current with Short Circuit ProtectionFigure 14.Tracking Voltage RegulatorInputOutputInputOutput24Figure 15.Split Power Supply ( ±15V-1A)Figure 16.Negative Output Voltage CircuitFigure 17.Switching RegulatorInputOutputInput OutputMechanical DimensionsPackageTO-22025Mechancal Dimensions (Continued)PackageD-PAK2627Ordering InformationProduct Number Output Voltage TolerancePackageOperating TemperatureKA7805 / KA7806 ±4%TO-2200 ~ + 125°CKA7808 / KA7809KA7810 KA7812 / KA7815KA7818 / KA7824KA7805A / KA7806A ±2%KA7808A / KA7809A KA7810A / KA7812A KA7815A / KA7818AKA7824A KA7805R / KA7806R ±4%D-PAKKA7808R / KA7809RKA7812R。

XX1000中文资料

Mimix Broadband ’s single ended fed (no external balun required) 7.5-25.0/15.0-50.0 GHz GaAs MMIC doubler has a +15.0 dBm output drive and is an excellent LO doubler that can be used to drive fundamental mixer devices. It is also well suited to drive Mimix's XR1002 receiver device. This MMIC uses Mimix Broadband ’s 0.15 µm GaAs PHEMT device model technology, and is based upon electron beam lithography to ensure high repeatability anduniformity. The chip has surface passivation to protect and provide a rugged part with backside via holes and gold metallization to allow either a conductive epoxy or eutectic solder die attach process. This device is well suited for Millimeter-wavePoint-to-Point Radio, LMDS, SATCOM and VSAT applications.7.5-25.0/15.0-50.0 GHz GaAs MMIC Excellent Broadband Mixer DriverSingle Ended Fed Doubler with Distributed Buffer AmplifierExcellent LO Driver for Mimix Receivers +15 dBm Output Drive100% On-Wafer RF, DC and Output Power Testing 100% Visual Inspection to MIL-STD-883Method 2010FeaturesElectrical Characteristics (Ambient T emperature T = 25 o C)ParameterInput Frequency Range (fin)Output Frequency Range (fout)Input Return Loss (S11)Output Return Loss (S22)Harmonic Gain (fout)Fundamental Rejection (fin) Saturated Output Power (Psat)RF Input Power (RF Pin)Output Power at +0.0 dBm Pin (Pout)Drain Bias Voltage (Vd1,2)Gate Bias Voltage (Vg1)Gate Bias Voltage (Vg2)Supply Current (Id1,2) (Vd=5.0V, Vg1=-0.6V, Vg2=0.0V Typical)Source Voltage (Vss)Source Current (Iss)Units GHz GHz dB dB dB dBc dBm dBm dBm VDC VDC VDC mA VDC mA Min.7.515.0------10.0---1.2-1.2--5.525Typ.--TBD 12.01320+15-+13.0+5.0-0.60.0220-5.050Max.25.050.0-----+10.0-+5.5+0.1+0.1250-2.060Absolute Maximum RatingsSupply Voltage (Vd)Supply Voltage (Vss)Supply Current (Id)Supply Current (Iss)Gate Bias Voltage (Vg)Input Power (RF Pin)Storage Temperature (Tstg)Operating Temperature (Ta)Channel Temperature (Tch)+6.0 VDC -6.0 VDC 300 mA 60 mA +0.3 VDC +12.0 dBm -65 to +165 O C -55 to MTTF Table MTTF Table Chip Device Layout1(1) Channel temperature affects a device's MTTF. It is recommended to keep channel temperature as low as possible for maximum life.1April 2006 - Rev 10-Apr-06General DescriptionDoubler Measurements0458_4_sa mples: Po ut (2xFin) vs. Fin (GHz)Pin=0dBm, VD1=5V, VG1=-0.6V, VS S=-5V, VD2=5V ~150mA, VG2=open101214161820Fin (GHz)Pout(2xFin)0458_4_s amples: Pout (Fin) vs. F in (GHz)Pin=0dBm, VD1=5V, VG1=-0.6V, VS S=-5V, VD2=5V ~150mA, VG2=open-5101520810121416182022Fin (GHz)Pout(Fin)7.5-25.0/15.0-50.0 GHz GaAs MMICHarmonic Gain and Fundamental Rejection vs Output Freq.Pin = 0 dBm XX1000: Po ut (2xFin) an d Po ut (F in) v s. F in (GHz)Pin = -8 to +6 dBm810121416182022Fin (GHz)Pout(dBm)April 2006 - Rev 10-Apr-06Mechanical DrawingBypass Capacitors- See App Note [2] (Note: Engineering designator is 40DBL0458)Units: millimeters (inches) Bond pad dimensions are shown to center of bond pad. Thickness: 0.110 +/- 0.010 (0.0043 +/- 0.0004), Backside is ground, Bond Pad/Backside Metallization: GoldAll Bond Pads are 0.100 x 0.100 (0.004 x 0.004).Bond pad centers are approximately 0.109 (0.004) from the edge of the chip.Dicing tolerance: +/- 0.005 (+/- 0.0002). Approximate weight: 1.566 mg.Bond Pad #1 (RF In) Bond Pad #2 (Vd1)Bond Pad #3 (Vd2)Bond Pad #4 (RF Out)Bond Pad #5 (Vg2)Bond Pad #6 (Vss)Bond Pad #7 (Vg1)7.5-25.0/15.0-50.0 GHz GaAs MMICApril 2006 - Rev 10-Apr-061.620(0.064)0.2950.6950.196(0.035)(0.061)(0.019)(0.012)0.01234567Vd2Vg1App Note [1] Biasing - It is recommended to separately bias each doubler stage Vd1 through Vd2 at Vd(1,2)=5.0V with Id1=80mAand Id2=140mA and Vss=-5.0V with Iss=50mA. XX1000 provides good performance at reduced bias with Vss=-2.0V and Iss=25mA.Maximum output power is achieved with Vss=-5.0V and Iss=50mA. Separate biasing is recommended if the doubler is to be used at high levels of saturation, where gate rectification will alter the effective gate control voltage. It is also recommended to use active biasing to keep the currents constant as the RF power and temperature vary; this gives the most reproducible results. Depending on the supply voltage available and the power dissipation constraints, the bias circuit may be a single transistor or a low power operational amplifier, with a low value resistor in series with the drain supply used to sense the current. The gate of the pHEMT is controlled to maintain correct drain current and thus drain voltage. The typical gate voltages needed to do this are Vg1=-0.6V and Vg2=0.0V. Typically the gate is protected with Silicon diodes to limit the applied voltage. Also, make sure to sequence the applied voltage to ensure negative gate bias is available before applying the positive drain supply.App Note [2] Bias Arrangement -For Individual Stage Bias (Recommended for doubler applications) -- Each DC pad (Vd1, 2, Vss and Vg1, 2) needs to have DC bypass capacitance (~100-200 pF) as close to the device as possible. Additional DC bypass capacitance (~0.01 uF) is also recommended.MTTF T able s (TBD)These numbers were calculated based on accelerated life test information and thermal model analysis received from the fabricating foundry.Backplate Temperature 55 deg Celsius 75 deg Celsius 95 deg CelsiusChannel Temperature deg Celsius deg Celsius deg CelsiusFITs E+E+E+MTTF HoursE+E+E+Rth C/W C/W C/WBias Conditions: Vd1=Vd2=4.0V, Id1=40 mA, Id2=140 mA, Vss=-5.0V, Iss=50mA7.5-25.0/15.0-50.0 GHz GaAs MMICApril 2006 - Rev 10-Apr-06Device SchematicMimix Broadband MMIC-based 18.0-34.0 GHz Doubler/Receiver Block Diagram(Changing LO and IF frequencies as required allows design to operate as high as 34 GHz)T ypical ApplicationXR10027.5-25.0/15.0-50.0 GHz GaAs MMIC April 2006 - Rev 10-Apr-06Handling and Assembly InformationCAUTION! - Mimix Broadband MMIC Products contain gallium arsenide (GaAs) which can be hazardous to the human body and the environment. For safety, observe the following procedures:Do not ingest.Do not alter the form of this product into a gas, powder, or liquid through burning, crushing, or chemical processing as these by-products are dangerous to the human body if inhaled, ingested, or swallowed.Observe government laws and company regulations when discarding this product. This product must be discarded in accordance with methods specified by applicable hazardous waste procedures.Life Support Policy - Mimix Broadband's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President and General Counsel of MimixBroadband. As used herein: (1) Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in asignificant injury to the user. (2) A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.ESD - Gallium Arsenide (GaAs) devices are susceptible to electrostatic and mechanical damage. Die are supplied in antistatic containers, which should be opened in cleanroom conditions at an appropriately grounded anti-static workstation. Devices need careful handling using correctly designed collets, vacuum pickups or, with care,sharp tweezers.Die Attachment - GaAs Products from Mimix Broadband are 0.100 mm (0.004") thick and have vias through to the backside to enable grounding to the circuit. Microstrip substrates should be brought as close to the die as possible. The mounting surface should be clean and flat. If using conductive epoxy, recommended epoxies are Ablestick 84-1LMI or 84-1LMIT cured in a nitrogen atmosphere per manufacturer's cure schedule. Apply epoxy sparingly to avoid getting any on to the top surface of the die. An epoxy fillet should be visible around the total die periphery. If eutectic mounting is preferred, then a fluxless gold-tin (AuSn) preform, approximately 0.001thick, placed between the die and the attachment surface should be used. A die bonder that utilizes a heated collet and provides scrubbing action to ensure total wetting to prevent void formation in a nitrogen atmosphere is recommended. The gold-tin eutectic (80% Au 20% Sn) has a melting point of approximately 280 C (Note: GoldGermanium should be avoided). The work station temperature should be 310 C 10 C. Exposure to these extreme temperatures should be kept to minimum. The collet should be heated, and the die pre-heated to avoidexcessive thermal shock. Avoidance of air bridges and force impact are critical during placement.Wire Bonding - Windows in the surface passivation above the bond pads are provided to allow wire bonding to the die's gold bond pads. The recommended wire bonding procedure uses 0.076 mm x 0.013 mm (0.003" x0.0005") 99.99% pure gold ribbon with 0.5-2% elongation to minimize RF port bond inductance. Gold 0.025 mm (0.001") diameter wedge or ball bonds are acceptable for DC Bias connections. Aluminum wire should beavoided. Thermo-compression bonding is recommended though thermosonic bonding may be used providing the ultrasonic content of the bond is minimized. Bond force, time and ultrasonics are all critical parameters.Bonds should be made from the bond pads on the die to the package or substrate. All bonds should be as short as possible.2+-7.5-25.0/15.0-50.0 GHz GaAs MMIC April 2006 - Rev 10-Apr-06。

109101907资料

AdvisoryJuly 2002 TSI-8 Time-Slot InterchangerIntroductionThis document describes technical issues that are known to exist with the device and/or the documentation of the device.IssuesTXD Buffer StrengthThe TXD[31:00] output buffers are capable of excessive output drive, resulting in excessive overshoot and undershoot.WorkaroundSeries source and termination resistors may be required for TXD[31:00] to achieve acceptable signal integrity.Corrective ActionThis will be corrected in a future respin.TXD Precharge ResistorsTXD[23:00] are not properly equipped with precharge resistors.WorkaroundExternal precharge resistors for TXD[23:00] must be provided if hot insertion is required by the application. Corrective ActionThis will be corrected in a future respin.Copyright © 2002 Agere Systems Inc.All Rights ReservedJuly 2002AY02-027SWCH (Must accompany DS02-121SWCH, DS02-122SWCH, and DS02-123SWCH)Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.For additional information, contact your Agere Systems Account Manager or the following:INTERNET: E-MAIL:docmaster@N. AMERICA:Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-32861-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)ASIA:Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, KowloonTel. (852) 3129-2000, FAX (852) 3129-2020CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen)JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)EUROPE:Tel. (44) 7000 624624, FAX (44) 1344 488 045Advance InformationMay 2002TSI-8 Time-Slot InterchangerHardware Design GuideIntroductionThis document describes the hardware interfaces to Agere Systems Inc. TSI-8 device. Information rele-vant to the use of the device in a board design is cov-ered. Ball descriptions, dc electrical characteristics, timing diagrams, ac timing parameters, packaging, and operating conditions are included.Related DocumentsMore information on the TSI-8 is contained in the fol-lowing documents:s TSI-8 Product Descriptions TSI-8 Register Descriptions TSI-8 Systems Design GuideDescriptionBlock Diagram and High-Level Interface DefinitionFigure 1. Block Diagram and High-Level Interface DefinitionTable of ContentsContentsPageContentsPage2Agere Systems Inc.Advance InformationMay 2002Hardware Design Guide TSI-8 Time-Slot Interchanger Introductions................................................................1Related Documents ..................................................1Description...................................................................1Block Diagram and High-Level Interface Definition ..1Ball Information............................................................3Ball Diagram .............................................................3Package Ball Assignments .......................................4Ball Types.................................................................8Ball Definitions..........................................................8Absolute Maximum Ratings.......................................11Handling Precautions................................................11ESD Tolerance........................................................11Package Thermal Characteristics...........................11Recommended Operating Conditions .......................12dc Electrical Characteristics ......................................12Timing Diagrams and ac Characteristics...................14Outline Diagrams.......................................................25Ordering Information.. (26)Figure PageFigure 1. Block Diagram and High-LevelInterface Definition (1)Figure 2. Package Diagram (Top View)..................... 3Figure 3. CHICLK Timing Specifications.................. 14Figure 4. MPUCLK Timing Specifications ................ 14Figure 5. ac Timing Measurement Specification ...... 15Figure 6. CHI Interface Timing................................. 16Figure 7. Typical Receive CHI Timing with16.384 Mbits/s Data and16.384 MHz CHICLK (17)Figure 8. Transmit CHI Timing with16.384 Mbits/s Data and16.384 MHz CHICLK (17)Figure 9. Typical Receive CHI Timing with8.192 Mbits/s Data and16.384 MHz CHICLK (18)Figure 10. Transmit CHI Timing with8.192 Mbits/s Data and16.384 MHz CHICLK (18)Figure 11. Typical Receive CHI Timing with4.096 Mbits/s Data and16.384 MHz CHICLK (19)Figure 12. Transmit CHI Timing with4.096 Mbits/s Data and16.384 MHz CHICLK (19)Figure 13. Typical Receive CHI Timing with2.048 Mbits/s Data and16.384 MHz CHICLK (20)Figure 14. Transmit CHI Timing with2.048 Mbits/s Data and16.384 MHz CHICLK (20)Figure 15. Typical Receive CHI Timing with8.192 Mbits/s Data and8.192 MHz CHICLK (21)Figure 16. Transmit CHI Timing with8.192 Mbits/s Data and8.192 MHz CHICLK (21)Figure 17. CHI 3-state Output Control...................... 22Figure 18. Microprocessor Port Timing—Read Cycle (23)Figure 19. Microprocessor Port Timing—Write Cycle (24)Table PageTable 1. Package Ball Assignments inSignal Name Order (4)Table 2. Package Ball Assignments inBall Number Order (Top View) (6)Table 3. Package Ball Assignments inBall Number Order (Bottom View) (7)Table 4. Ball Types..................................................... 8Table 5. Timing Port................................................... 8Table 6. Transmit and Receive ConcentrationHighways (9)Table 7. Control Port .................................................. 9Table 8. Initialization and Test Access..................... 10Table 9. Power Balls................................................. 10Table 10. Absolute Maximum Ratings...................... 11Table 11. ESD Tolerance......................................... 11Table 12. Power Consumption................................. 11Table 13. Operating Conditions................................ 12Table 14. CMOS Inputs............................................ 12Table 15. CMOS Outputs......................................... 12Table 16. CMOS Bidirectionals(Excluding TXD[31:00]) (13)Table 17. CMOS Bidirectionals (TXD[31:00])........... 13Table 18. CHICLK Timing Specifications ................. 14Table 19. MPUCLK Timing Specifications................ 14Table 20. ac Timing Measurement Specification...... 15Table 21. CHI Interface Timing................................. 16Table 22. CHI 3-state Output Control....................... 22Table 23. Microprocessor Port Timing—Read Cycle (23)Table 24. Microprocessor Port Timing—Write Cycle (24)Agere Systems Inc.3Advance Information May 2002Hardware Design GuideTSI-8 Time-Slot InterchangerBall InformationBall DiagramThe TSI-8 is housed in a 240-ball plastic ball grid array. Figure 2 shows the ball arrangement viewed from the top of the package. The balls are spaced on a 1.0 mm pitch.Figure 2. Package Diagram (Top View)BCA EFD HJG LMK PRN UVT 2315648710119131412161517184Agere Systems Inc.Advance InformationMay 2002Hardware Design Guide TSI-8 Time-Slot Interchanger Ball Information (continued)Package Ball AssignmentsTable 1. Package Ball Assignments in Signal Name Order Symbol Ball Symbol Ball Symbol Ball Symbol Ball Symbol Ball ADDR00A17DATA13P18RXD11V7TXD08F1V DD15D13ADDR01A16DATA14P17RXD12T8TXD09G3V DD15D14ADDR02A15DATA15P16RXD13U8TXD10G2V DD15G4ADDR03A14DT H17RXD14V8TXD11G1V DD15H4ADDR04A13FSYNC T11RXD15U9TXD12H2V DD15L4ADDR05A12HIZ R17RXD16V9TXD13H1V DD15M4ADDR06A11INT H16RXD17V10TXD14J2V DD15R7ADDR07A10MPUCLK K15RXD18U10TXD15J1V DD15R8ADDR08A9PAR0R18RXD19V11TXD16K1V DD15R11ADDR09A8PAR1P15RXD20U11TXD17K2V DD15R12ADDR10A7R/W J17RXD21V12TXD18L1V DD33C9ADDR11A6RESET H15RXD22U12TXD19L2V DD33C10ADDR12A5RSV1F17RXD23V13TXD20M1V DD33C17ADDR13A4RSV2F18RXD24U13TXD21M2V DD33D9ADDR14A3RSV3E15RXD25V14TXD22N1V DD33D10ADDR15A2RSV4E16RXD26U14TXD23N2V DD33E3AS J16RSV5E17RXD27V15TXD24N3V DD33F3CHICLK R16RSV6D17RXD28U15TXD25P1V DD33F15CKSPD0E18RSV7B18RXD29T15TXD26P2V DD33H3CKSPD1D16RSV8C18RXD30V16TXD27R1V DD33J3CS J18RSV9D18RXD31U16TXD28R2V DD33K16DATA00K18RSV10T18TCK G17TXD29T1V DD33P3DATA01K17RSV11V17TDI G16TXD30T2V DD33R3DATA02L18RXD00V2TDO G18TXD31U1V DD33T5DATA03L17RXD01U3TMS G15V DD15C5V DD33T6DATA04L16RXD02V3TRSTN H18V DD15C6V DD33T9DATA05M18RXD03U4TXD00B1V DD15C7V DD33T10DATA06M17RXD04V4TXD01C2V DD15C12V DD33T14DATA07M16RXD05U5TXD02C1V DD15C13V DD33T17DATA08M15RXD06V5TXD03D2V DD15C14V DDPLL R14DATA09N18RXD07U6TXD04D1V DD15D5V IO K3DATA10N17RXD08V6TXD05E2V DD15D6V PRE T4DATA11N16RXD09T7TXD06E1V DD15D7V SS A1DATA12N15RXD10U7TXD07F2V DD15D12V SSA18TSI-8 Time-Slot Interchanger Advance InformationMay 2002Hardware Design Guide Ball Information (continued)Package Ball Assignments (continued)Table 1. Package Ball Assignments in Signal Name Order (continued)Symbol Ball Symbol Ball Symbol Ball Symbol BallV SS B2V SS C8V SS J9V SS R4V SS B3V SS C11V SS J10V SS R5V SS B4V SS C15V SS J11V SS R6V SS B5V SS C16V SS J15V SS R9V SS B6V SS D3V SS K4V SS R10V SS B7V SS D4V SS K8V SS R15V SS B8V SS D8V SS K9V SS T3V SS B9V SS D11V SS K10V SS T12V SS B10V SS D15V SS K11V SS T13V SS B11V SS E4V SS L3V SS T16V SS B12V SS F4V SS L8V SS U2V SS B13V SS F16V SS L9V SS U17V SS B14V SS H8V SS L10V SS U18V SS B15V SS H9V SS L11V SS V1V SS B16V SS H10V SS L15V SS V18V SS B17V SS H11V SS M3V SSPLL R13V SS C3V SS J4V SS N4V SS C4V SS J8V SS P4Agere Systems Inc.58Agere Systems Inc.Advance InformationMay 2002Hardware Design Guide TSI-8 Time-Slot Interchanger Ball Information (continued)Ball TypesThis table describes each type of input, output, and I/O ball used on the TSI-8.Table 4. Ball TypesThe dc switching and other electrical characteristics are specified later in this document.Ball Definitions This section describes the function of each of the device balls. The balls are listed by ball name. Package ball num-bers are listed in Table 1 of this document. The static parameters (drive currents, switching thresholds, etc.) for each ball type (input, output, etc.) are described in Table 14 through Table 16.Table 5. Timing Port Type LabelDescriptionI CMOS input, TTL switching thresholds.I pd CMOS input, TTL switching thresholds with internal pull-down resistor.I pu CMOS input, TTL switching thresholds with internal pull-up resistor.O CMOSoutput.O od Open drain output.I/O Bidirectional ball; CMOS input with TTL switching thresholds and CMOS output.None Analog inputs for external resistors, capacitors, voltage references, etc.PPower and ground.Ball Name Type Name/DescriptionFSYNCIFrame Synchronization. This signal indicates the beginning of a 125 µs frame event (8kHz). The FSYNC ball can be programmed as active-low or active-high, but its polarity is the same for all concentration highway interfaces (CHI). FSYNC can be sampled on either the positive or negative edge of CHICLK. Time-slot numbers and bit offsets for each CHI are assigned relative to the detection of FSYNC.CHICLKI Clock. This is the master synchronous clock for the transmit and receive concentrationhighways. The frequency can be 8.192 MHz or 16.384 MHz. It must be at least as fast as the highest CHI data rate.CKSPD0I Clock Speed. Static control input that should be tied according to the frequency of CHICLK. IfCHICLK is connected to an 8.192 MHz source, CKSPD0 should be tied to V SS . If CHICLK is connected to a 16.384MHz source, CKSPD0 should be tied to V DD33.CKSPD1I pd Clock Speed. Reserved, leave disconnected. 20 k Ω pull-down resistor.Ball Information (continued)Ball Definitions (continued)Table 6. Transmit and Receive Concentration Highways Table 7. Control Port Ball Name TypeName/DescriptionRXD[31:00]I pd Receive Data [31:00]. Receive concentration highways. These are serial, synchronous datastreams which may be individually programmed to operate at 2.048 Mbits/s, 4.096Mbits/s, 8.192Mbits/s, or 16.384 Mbits/s. They carry 32, 64, 128, or 256 time slots (respectively) each occupying eight contiguous bits. 20 k Ω pull-down resistor.TXD[31:00]I/O Transmit Data [31:00]. Normally these are output concentration highway data streams withdata rate options identical to the RXD inputs. These balls can be configured to operate as bidirectional multiplex ports such as H.110. Further information can be found in the system design guide. 20 k Ω resistor connected to V PRE .Ball Name Type Name/DescriptionMPUCLK I Processor Clock. This clock is used to sample address, data, and control signals from the microprocessor. This clock must be within the range of 0MHz —66 MHz. Required for operation.CS I Chip Select. Active-low chip select. This input is held low for the duration of any read or write access to the TSI-8. Required for operation.ASIAddress Strobe. Active-low address strobe that is one MPUCLK cycle wide at the start of a microprocessor access cycle to the TSI-8. This is used to initiate a microprocessor access. Required for operation.R/W IRead/Write. Cycle selection. R/W is set high during a read cycle, or set low for a write cycle. Required for operation.ADDR [15:00]I pu Address [15:00]. ADDR[15] is the most significant bit and ADDR[00] is the least significant bitfor addressing all the internal registers during microprocessor access cycles. All addresses are 16-bit word addresses; hence, in a typical application ADDR[00] of the TSI-8 device would be connected to address bit 1 of a byte addressable system address bus. Required for operation. 200 k Ω pull-up resistor.Note:The TSI-8 is little-endian; the least significant byte is stored in the lowest address and themost significant byte is stored in the highest address. Care must be exercised in connection to microprocessors that use big-endian byte ordering.DATA [15:00]I/O Data [15:00]. Data bus for all transfers between the microprocessor and the internal registers.The balls are inputs during write cycles and outputs during read cycles. DATA[15] is the most significant bit and DATA[00] is the least significant bit. Required for operation.PAR[1:0]I/O Control Port Parity [1:0]. Byte-wide parity bits for data. PAR[1] is the parity for DATA[15:8], andPAR[0] is the parity for DATA[7:0]. The parity sense (even or odd) is application programmable via a register bit in the TSI-8. Not required for operation.DTOData Transfer Acknowledge. Active-low for one MPUCLK cycle. Indicates that data has been written during write cycles or that data is valid during read cycles. High impedance when CS is a 1 and driven when CS is 0. Required for operation.INTO od Interrupt. This output is asserted low to indicate that an interrupt condition has occurred. Thissignal remains active-low until the interrupt status register has been cleared or masked.Ball Information (continued)Ball Definitions (continued)Table 8. Initialization and Test Access Table 9. Power Balls Ball Name Type Name/DescriptionRESETI pu Reset. Global reset, active-low. Initializes all internal registers to their default state. The resetoccurs asynchronously, but RESET should be held low for at least two CHICLK periods. 20 k Ω pull-up resistor.TCK I pu Test Clock. This signal provides timing for the boundary scan and test access port (TAP)controller. Should be static except during boundary-scan testing. 20 k Ω pull-up resistor.TDI I pu Test Data In. Data input for the boundary scan. Sampled on the rising edge of TCK. 20 k Ω pull-up resistor.TMS I pu Test Mode Select (Active-Low). Controls boundary-scan test operations. TMS is sampled onthe rising edge of TCK. 20 k Ω pull-up resistor TRSTN I pd Test Reset (Active-Low). This signal is an asynchronous reset for the TAP controller. 20k Ωpull-down resistor.TDO OTest Data Out. Updated on the falling edge of TCK. The TDO output is high impedance except when scanning out test data.HIZ I pu Output Enable. All output and bidrectional buffers will be high impedance when this input islow unless boundary scan is enabled (TRSTN = 1). 20k Ω pull-up resistor.RSV[11:1]—Reserved [11:1]. These balls are used by Agere Systems during the manufacturing process. They must be left unconnected.Symbol Type Name/DescriptionV DD33P I/O Power. Power supply balls for the I/O pads (3.3 V ± 5%).V DD15P Core Power. Power supply balls for the core (1.5 V ± 5%).V SS P Ground. Common ground balls for 3.3 V and 1.5 V supplies.V PREPPrecharge. Precharge voltage to support H.110 hot insertion on TXD[31:00]. If the device is used in an H.110 hot insertion applications the signal should be connected to backplane early voltage, otherwise connect this signal to ground.V IO PPCI Buffer Voltage Select. For an H.110 application using TXD[31:00] in a 5 V signaling environment, connect this signal to 5 V. For an H.110 application using TXD[31:00] in a 3 V signaling environment, connect this signal to V DD33. For all other applications connect this signal to V DD33.V DDPLL P PLL Power. 1.5 V power supply for the internal phase-locked loop. Must include local 0.01µF capacitor to V SSPLL .V SSPLLPPLL Ground. Isolated ground for the internal phase-locked loop.Absolute Maximum RatingsStresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.Table 10. Absolute Maximum RatingsHandling PrecautionsAlthough electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC ’s JESD22-A114 (HBM) and JESD22-C101 (CDM) standards.ESD ToleranceTable 11. ESD TolerancePackage Thermal CharacteristicssΘJA = 24.0 °C/W.Table 12. Power ConsumptionParameterMin Max Unit Supply Voltage (V DD33)–0.5 4.2V Supply Voltage (V DD15)–0.5 1.8V Input Voltage: TXD[31:00]All Other Inputs –0.5–0.3 5.5V DD33 + 0.3V Storage Temperature –40125°C Junction Temperature—125°CDevice Voltage TypeTSI-82,000 V HBM (human-body model)500 VCDM (charged-device model)Supply VoltageTyp **MPUCLK = 66 MHz, CHICLK = 16.384 MHz, TA = 25 °C, all CHIs active, all outputs loaded with 50 pF.MaxV DD33100 mW at 3.3 V 150 mW at 3.47 V V DD15275 mW at 1.5 V325 mW at 1.6 VRecommended Operating ConditionsRecommended conditions apply unless otherwise specified.Table 13. Operating Conditionsdc Electrical CharacteristicsThis section describes all the static parameters associated with all the ball types used in the TSI-8 device.Table 14. CMOS Inputs* Excludes current due to pull-up or pull-down resistors.Table 15. CMOS OutputsParameterMin Typ Max Unit Supply Voltage (V DD33) 3.14 3.3 3.47V Supply Voltage (V DD15) 1.4 1.5 1.6V Ambient Temperature–40—85°CParameterSymbol Conditions Min Typ Max Unit Input Leakage Current I IL V SS < V IN < V DD33——1*µA High-input Voltage V IH — 2.0—V DD33 + 0.3V Low-input Voltage V IL —–0.3—0.8V Input CapacitanceC I——2.5—pFParameter Symbol Conditions Min Typ Max Unit Output Voltage Low V OL I OL = –10 mA ——0.4V Output Voltage High V OH I OL = 10 mA2.4——V Output Current Low I OL ———10mA Output Current High I OH ———10mA Output Capacitance C O ——3—pF HIZ Output Leakage CurrentI OZ———10µAdc Electrical Characteristics (continued)Table 16. CMOS Bidirectionals (Excluding TXD[31:00])Table 17. CMOS Bidirectionals (TXD[31:00])Parameter Symbol Conditions Min Typ Max Unit Leakage Current I L V SS < V IN < V DD33——11µA High-input Voltage V IH — 2.0—V DD33 + 0.3V Low-input Voltage V IL —–0.3—0.8V Biput Capacitance C IB —— 5.0—pF Output Voltage Low V OL I OL = –10 mA ——0.4V Output Voltage HighV OHI OL = 10 mA2.4——VParameterSymbol ConditionsMin Max Unit Leakage Current I L V SS < V IN < V DD33—10µA High-input Voltage V IH VIO = 5.0 V VIO = 3.3V 2.00.5 V DD335.5V DD33 + 0.5V Low-input Voltage V IL VIO = 5.0 V VIO = 3.3V–0.5–0.50.80.3 V DD33V Biput Capacitance C IB ——10pF Output Voltage Low V OL I OL = 1.5 mA, VIO = 3.3 V I OL = 6.0 mA, VIO = 5.0 V ——0.1 V DD330.55V Output Voltage High V OH I OL = –0.5 mA, VIO = 3.3 V I OL = –2.0 mA, VIO = 5.0 V0.9 V DD332.4——V Positive-going Threshold V t+ — 1.2 2.0V Negative-going Threshold V t –—0.6 1.6V Hysteresis (V t+ – V t –)V HYS—0.4—VTiming Diagrams and ac Characteristics (continued)Figure 5 shows the ac timing specifications for the TSI-8. All timing parameters are referenced to V IHmin and V ILmax . The reference signal polarity may be inverted for some timing parameters.Figure 5. ac Timing Measurement SpecificationTable 20. ac Timing Measurement SpecificationParameterDescriptiont 9Setup Time t 10Hold Time t 11Output Delayt 12Output 3-State Timet 9V ILV IHV ILt 11t 10t 12REFERENCE SIGNALINPUT SIGNALOUTPUT SIGNALV IH V ILHIZV OH V OLHIZHIZTiming Diagrams and ac Characteristics (continued)Note: This figure assumes TSI-8 is programmed to sample FSYNC on rising edge of CHICLK.Figure 6. CHI Interface TimingTable 21. CHI Interface Timing * Applies if Driver_Enable_Control = 01; see Figure 17, CHI 3-state Output Control, if Driver_Enable_Control = 11.All timing specifications are with respect to V IHmin and V ILmax as shown in Figure 5. All timing specifications also apply under the following conditions:s If FS is active-low.s If the falling edge of CHICLK is specified as the active edge.sAt all RXD and TXD rates (16.384 Mbits/s, 8.192Mbits/s, 4.096Mbits/s, or 2.048 Mbits/s) with a CHICLK frequency of 16.384 MHz or 8.192 MHz.ParameterDescriptionMin Max Unit t 13FSYNC Setup Time to Active CHICLK Edge 10—ns t 14FSYNC Hold Time from Active CHICLK Edge 5—ns t 15RXD Setup to Active CHICLK Edge 10—ns t 16RXD Hold Time from Active CHICLK Edge 5—ns t 17TXD High Z to Data Valid—15ns t 18TXD Propagation Delay from Active CHICLK Edge 210ns t 19Transmit Data High Impedance*—15nst 18t 19TXDCHICLKt 13t 14t 17RXDFSYNCt 15t 1620Agere Systems Inc.22Agere Systems Inc.Timing Diagrams and ac Characteristics (continued)Figure 17. CHI 3-state Output ControlTable 22. CHI 3-state Output ControlControl in the table below refers to bits [6:4] in Transmit_CHI_Global_Configuration register (0x0C84). This only applies if bits 13 and 12 of the corresponding Transmit_CHI_Control register (0x0C00—0x0C3E) are set to 11. See TSI-8 Register Description.Parameter ControlReference Point **Like edge is the reference edge (rising or falling) as defined by the Transmit_Clock_Edge bit in theTransmit_CHI_Global_Configuration (0x0C84) register. See TSI-8 Register Description document for further details.Min ††All timing specifications are with respect to the parameters shown in Figure 5.Max *Unit t 20000After Previous Like Edge in 16 MHz 5059ns 001After Previous Like Edge in 16 MHz 4453ns 010After Previous Like Edge in 16 MHz 3847ns 011After Previous Like Edge in 16 MHz 3241ns t 21000After Previous Opposite Edge in 8 MHz 5059ns 001After Previous Opposite Edge in 8 MHz 4453ns 010After Previous Opposite Edge in 8 MHz 3847ns 011After Previous Opposite Edge in 8 MHz 3241ns t 22100After Previous Like Edge (8 MHz mode only)111120ns 101After Previous Like Edge (8 MHz mode only)105114ns 110After Previous Like Edge (8 MHz mode only)99108ns 111After Previous Like Edge (8 MHz mode only)93102nsCHICLK 16.384 MHzt 20TXD 16.384 Mbits/sCHICLK 8.192 MHzTXD 8.192 Mbits/sCHICLK 8.192 MHzTXD 8.192 Mbits/st 21t 2224Agere Systems Inc.Timing Diagrams and ac Characteristics (continued)Figure 19. Microprocessor Port Timing —Write CycleTable 24. Microprocessor Port Timing —Write Cycle Note:Posted writes follow the same timing shown in Figure 19 and Table 24. A posted write may return a DT priorto the device completing the write cycle. This allows the microprocessor to continue operation while the TSI-8 completes the write.ParameterDescriptionMin **All timing specifications are with respect to the parameters shown in Figure 5.Max *Unit t 37Address setup.5—ns t 38Address hold.1—ns t 39Chip select setup.5—ns t 40Chip select hold 1—ns t 41Address strobe setup.5—ns t 42Address strobe hold.1—ns t 43R/W setup.5—ns t 44R/W hold.1—ns t 45Data setup.5—ns t 46Data hold.1—ns t 47DT high impedance to valid.115ns t 48DT clock to out.17ns t 49DT valid to high impedance.18nsMPUCLKDATA[15:00]PAR[1:0]t 38t 37ADDR[15:00]CSASR/WDTt 39t 41t 42t 43t 45t 48t 47t 40t 44t 46t 48t 49Copyright © 2002 Agere Systems Inc.All Rights ReservedMay 2002DS02-123SWCHAgere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.For additional information, contact your Agere Systems Account Manager or the following:INTERNET: E-MAIL:docmaster@N. AMERICA:Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-32861-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)ASIA:Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, KowloonTel. (852) 3129-2000, FAX (852) 3129-2020CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen)JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)EUROPE:Tel. (44) 7000 624624, FAX (44) 1344 488 045Ordering InformationDevice Part Number Ball CountPackage Comcode TSI-8TTSI008321BL-1240PBGAM1109101907。

1900170中文资料

Extract from the onlinecatalogEMSTB 2,5/13-GFOrder No.: 1900183The figure shows a 10-position version of the producthttp://eshop.phoenixcontact.de/phoenix/treeViewClick.do?UID=1900183Header, nominal current: 12 A, rated voltage: 250 V, pitch: 5.0 mm, no. of positions: 13, mounting: Press inhttp://Please note that the data givenhere has been taken from theonline catalog. For comprehensiveinformation and data, please referto the user documentation. TheGeneral Terms and Conditions ofUse apply to Internet downloads. Technical dataDimensions / positionsPitch 5 mmDimension a55 mmNumber of positions12Pin dimensions1,7 mmHole diameter 1.75 mmTechnical dataInsulating material group IIIaRated surge voltage (III/3) 4 kVRated surge voltage (III/2) 4 kVRated surge voltage (II/2) 4 kVRated voltage (III/2)320 VRated voltage (II/2)400 VConnection in acc. with standard EN-VDENominal current I N12 ANominal voltage U N250 VMaximum load current12 AInsulating material PBTInflammability class acc. to UL 94V0Certificates / ApprovalsApproval logoCULNominal voltage U N300 VNominal current I N10 AULNominal voltage U N300 VNominal current I N10 ACertification CB, CUL, GOST, UL, VDE-PZIAccessoriesItem Designation DescriptionAssembly1877203EMSTB 2,5-SH Stamp holder, for upper and lower stamp1877229EMSTBVA 2,5-SS-2-5,08Stamp set, consisting of an upper and lower stamp, upper stamp:17 to 24-pos., lower stamp: 2 to 24-pos., pitch: 5.08 mm 1755477MSTB-BL Keying cap, for forming sections, plugs onto header pin, greeninsulating materialMarking0804183SK 5/3,8:FORTL.ZAHLEN Marker card, printed horizontally, self-adhesive, 12 identicaldecades marked 1-10, 11-20 etc. up to 91-(99)100, sufficient for120 terminal blocksPlug/Adapter1734401CR-MSTB Coding section, inserted into the recess in the header or theinverted plug, red insulating materialAdditional productsItem Designation DescriptionGeneral1910623FKC 2,5/12-STF Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.0 mm, no. of positions: 12, type of connection: Spring-cage connection1909498FKCT 2,5/11-STF Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.0 mm, no. of positions: 12, type of connection: Spring-cage connection1909980FKCVR 2,5/12-STF Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.0 mm, no. of positions: 12, type of connection: Spring-cage connection1910306FKCVW 2,5/12-STF Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.0 mm, no. of positions: 12, type of connection: Spring-cage connection1779741FRONT-MSTB 2,5/12-STF Plug with screw flange, nominal current: 12 A, rated voltage: 250V, pitch: 5,0 mm, no. of positions: 12, type of connection: Screwconnection1786938MSTB 2,5/12-STF Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.0 mm, no. of positions: 12, type of connection: Screwconnection1835575MVSTBR 2,5/12-STF Plug with screw flange, nominal current: 12 A, rated voltage: 250V, pitch: 5,0 mm, no. of positions: 12, type of connection: Screwconnection1835384MVSTBW 2,5/12-STF Plug component, nominal current: 12 A, rated voltage: 250 V,pitch: 5.0 mm, no. of positions: 12, type of connection: ScrewconnectionDrawingsDrilling diagramDimensioned drawingAddressPHOENIX CONTACT GmbH & Co. KGFlachsmarktstr. 832825 Blomberg,GermanyPhone +49 5235 3 00Fax +49 5235 3 41200http://www.phoenixcontact.de© 2008 Phoenix ContactTechnical modifications reserved;。

7812中文资料

7812
输出电流
输出电阻
17V
证集成稳压器工作在线性区。

请问7812的输入输出端连接电容的目的是什么？
1.滤波，虑除交流噪声是输出电流更平稳；
2.提供储备电流，当需要突发大电流时变压器不够用时电解电容可以补充瞬间的不足。

不连有什么坏处？
与前面说的情况正相反。

还有就是我用220V-12V的变压器输出端连上7812想得到直流12V电源，为什么7812会热得发烫啊？
7812只是稳压电路，前面的整流元件必不可少，7812最大可以提供1.5A电流，而且必须加散热片。

问题补充：像我这样的输入输出需要并多大的电容啊？
这要根据所需电流来选取，一般有2200u足够了，再大浪费，最好在输出端在并连一只220u 电解和一只0.1u电容，这只0.1u小电容对减小电源高频内阻非常有效！。

8002301FA中文资料

Copyright © 1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.PACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)5962-7603701VEA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC 5962-7603701VFA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 5962-7603701VFA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 7603701EA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC 7603701EA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC 7603701FA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 7603701FA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 76038012A ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC 76038012A ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC 7603801EA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC 7603801EA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC 7603801FA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 7603801FA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 8002301EA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC 8002301EA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC 8002301FA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 8002301FA ACTIVE CFP W161TBD Call TI Level-NC-NC-NCJM38510/07906BEA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NCJM38510/07906BEA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NCJM38510/07906BFA ACTIVE CFP W161TBD Call TI Level-NC-NC-NCJM38510/07906BFA ACTIVE CFP W161TBD Call TI Level-NC-NC-NCJM38510/30906B2A ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NCJM38510/30906B2A ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NCJM38510/30906BEA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NCJM38510/30906BEA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NCJM38510/30906BFA ACTIVE CFP W161TBD Call TI Level-NC-NC-NCJM38510/30906BFA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SN54LS257BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54LS257BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54LS258BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54LS258BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54S257J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54S257J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54S258J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54S258J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN74LS257BD ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BD ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BDE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BDE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)SN74LS257BDR ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BDR ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BDRE4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BDRE4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BN ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74LS257BN ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NC SN74LS257BN3OBSOLETE PDIP N16TBD Call TI Call TISN74LS257BN3OBSOLETE PDIP N16TBD Call TI Call TISN74LS257BNE4ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74LS257BNE4ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74LS257BNSR ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BNSR ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BNSRE4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BNSRE4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BD ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BD ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BDE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BDE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BDR ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BDR ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BDRE4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BDRE4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BN ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74LS258BN ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74LS258BN3OBSOLETE PDIP N16TBD Call TI Call TISN74LS258BN3OBSOLETE PDIP N16TBD Call TI Call TISN74LS258BNE4ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74LS258BNE4ACTIVE PDIP N1625Pb-Free CU NIPDAU Level-NC-NC-NCOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)(RoHS)SN74LS258BNSR ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BNSR ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BNSRE4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BNSRE4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S257D ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S257D ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S257DE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S257DE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S257N ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74S257N ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NC SN74S257N3OBSOLETE PDIP N16TBD Call TI Call TISN74S257N3OBSOLETE PDIP N16TBD Call TI Call TISN74S257NE4ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74S257NE4ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NC SN74S258DR OBSOLETE SOIC D16TBD Call TI Call TISN74S258DR OBSOLETE SOIC D16TBD Call TI Call TISN74S258N OBSOLETE PDIP N16TBD Call TI Call TISN74S258N OBSOLETE PDIP N16TBD Call TI Call TISN74S258N3OBSOLETE PDIP N16TBD Call TI Call TISN74S258N3OBSOLETE PDIP N16TBD Call TI Call TISNJ54LS257BFK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54LS257BFK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54LS257BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54LS257BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54LS257BW ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54LS257BW ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54LS258BFK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54LS258BFK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54LS258BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54LS258BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54LS258BW ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54LS258BW ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54S257FK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54S257FK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NCOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)SNJ54S257J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54S257J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54S257W ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54S257W ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54S258FK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54S258FK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54S258J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54S258J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54S258W ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54S258W ACTIVE CFP W161TBD Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS)or Green(RoHS&no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents 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SX1211资料

Block Diagram
V3.0 – august 15th, 2007
Page 1 of 73

元器件交易网
SX1211
ADVANCED COMMUNICATIONS & SENSING
Table of Contents
1. Block Diagram and General Description ........................ 5 1.1. Simplified Block Diagram ............................................ 5 1.2. Pin Diagram ................................................................ 6 1.3. Pin Description............................................................ 7 2. Electrical Characteristics................................................ 8 2.1. ESD Notice ................................................................. 8 2.2. Absolute Maximum Ratings ........................................ 8 2.3. Operating Range......................................................... 8 2.4. Chip Specification ......

CS8900A中文数据手册中文部分翻译

Байду номын сангаас 目录
4.10.11 I/O 模式下轮询 CS8900A....................................................................... 15 5.2 基本接收操作........................................................................................................ 17
5.2.1.1 数据包................................................................................................ 17 5.2.1.2 帧........................................................................................................ 17 5.2.1.3 传送.................................................................................................... 18 5.2.2 接收配置...................................................................................................... 18 5.2.2.1 配置物理接口.................................................................................... 19

CS5180中文资料

1Copyright ©Cirrus Logic,Inc.2002(All Rights Reserved)P.O.Box 17847,Austin,Texas 78760(512)4457222FAX:(512)4457581Preliminary Product InformationCirrus Logic reserves the right to modify this product without notice.CS5180∆ΣModulator &8kHz to 400kHz 16-Bit ADCFeatures16-BitDelta-Sigma A/D ConverterFully Differential Input with 4.0V pp Range Dynamic Range:93dBSpurious Free Dynamic Range:96dBTotal Harmonic Distortion:-95dB @22kHz Up to 400kHz Output Word Rate No Missing CodesNon-Aliasing Low-Pass Digital Filter High Speed 3-Wire Serial Interface Supply Options:-VA+=5V,VD+=5V,690mW -VA+=5V,VD+=3V,368mWModulatorOutput ModePower Down ModeDescriptionCS5180is a fully calibrated high-speed ∆Σanalog-to-digital converter,capable of 400kSamples/second out-put word rate (OWR).The OWR scales with the master clock.It consists of a 5th order ∆Σmodulator,decimation filter,and serial interface.The chip can use the 2.375V on-chip voltage reference,or an external 2.5V refer-ence.The input voltage range is 1.6×VREFIN V pp fully differential.Multiple CS5180s can be fully synchronized in multi-channel applications with a SYNC signal.The part has a power-down mode to minimize power con-sumption at times of system inactivity.The high speed digital I/O lines have complementary signals to help re-duce radiated noise from traces on the PC board.The CS5180can also be operated in modulator-only mode which provides the delta-sigma modulator bitstream as the output.ORDERING INFORMATIONCS5180-CL 0°C to 70°C28-pin PLCCAPR ‘02DS259PP4TABLE OF CONTENTSCHARACTERISTICS/SPECIFICATIONS (4)ANALOG CHARACTERISTICS (4)DYNAMIC CHARACTERISTICS (6)DIGITAL CHARACTERISTICS (6)SWITCHING CHARACTERISTICS (7)RECOMMENDED OPERATING CONDITIONS (8)ABSOLUTE MAXIMUM RATINGS (8)GENERAL DESCRIPTION (9)THEORY OF OPERATION (9)Converter Initialization:Calibration and Synchronization (9)Clock Generator (10)Voltage Reference (10)Analog Input (11)Output Coding (11)Modulator-Only mode (11)Instability Indicator (13)Digital Filter Characteristics (13)Serial Interface (13)Power Supplies/Board Layout (13)Power-down Mode (15)PIN DESCRIPTION (16)PARAMETER DEFINITIONS (19)APPENDIX A:CIRCUIT APPLICATIONS (21)PACKAGE OUTLINE DIMENSIONS (26)Contacting Cirrus Logic SupportFor a complete listing of Direct Sales,Distributor,and Sales Representative contacts,visit the Cirrus Logic web site at: /corporate/contacts/sales.cfmIMPORTANT NOTICE"Preliminary"product information describes products that are in production,but for which full characterization data is not yet available."Advance"product infor-mation describes products that are in development and subject to development changes.Cirrus Logic,Inc.and its subsidiaries("Cirrus")believe that the infor-mation contained in this document is accurate and reliable.However,the information is subject to change without notice and is provided"AS IS"without warranty of any kind(express or implied).Customers are advised to obtain the latest version of relevant information to verify,before placing orders,that information being relied on is current and complete.All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment,including those pertaining to warranty,patent infringement,and limitation of liability.No responsibility is assumed by Cirrus for the use of this information,including use of this information as the basis for manufacture or sale of any items,or for infringement of patents or other rights of third parties.This document is the property of Cirrus and by furnishing this information,Cirrus grants no license,express or implied under any patents,mask work rights,copyrights,trademarks,trade secrets or other intellectual property rights.Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus.This consent does not extend to other copying such as copying for general distribution,advertising or promotional purposes,or for creating any work for resale.An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma-terial and controlled under the"Foreign Exchange and Foreign Trade Law"is to be exported or taken out of Japan.An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH,PERSONAL INJURY,OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE("CRITICAL APPLICATIONS").CIRRUS PRODUCTS ARE NOT DESIGNED,AUTHORIZED,OR WARRANT-ED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.Cirrus Logic,Cirrus,and the Cirrus Logic logo designs are trademarks of Cirrus Logic,Inc.All other brand and product names in this document may be trade-marks or service marks of their respective owners.2LIST OF FIGURESFigure1.Serial Port Timing(not to scale) (7)Figure2.RESET and SYNC logic and timing (9)Figure3.CS5180connection diagram for using the internal voltage reference (10)Figure4.CS5180connection diagram for using an external voltage reference (11)Figure5.Modulator Only Mode Data RTZ Format (12)Figure6.Circuit to ReconstructReturn-to-Zero(RTZ)Data from SDO/SDO into Original Modulator Bitstream.12Figure7.Magnitude versus frequency spectrum of modulatorbitstream(MCLK=25.6MHz) (12)Figure8.Expanded view of the magnitude versus frequency spectrum ofmodulator bitstream(MCLK=25.6MHz) (12)Figure9.CS5180Digital Filter Magnitude Response(MCLK=25.6MHz) (13)Figure10.CS5180Digital Filter Phase Response(MCLK=25.6MHz) (13)Figure11.CS5180System Connection Diagram (14)Figure12.Single amplifier driving only AIN+,AIN-held at steady dc value (21)Figure13.Performance of amplifier of Figure12overdriving AIN+input to theCS5180at4VPP (21)Figure14.Performance of amplifier of Figure12with AIN+driven at2VPP (21)Figure15.AC-coupled driver using two amplifiers (22)Figure16.Performance of amplifier in Figure15 (22)Figure17.Three amplifier driver (23)Figure18.Performance of amplifier in Figure17 (23)Figure19.Four amplifier driver (24)Figure20.Performance of amplifier in Figure19 (24)Figure21.Performance of amplifier in Figure19 (24)Figure22.CS5180Differential Non-linearity plot.(Data taken with repeating ramp) (25)Figure23.Histogram of DNL from Figure22 (25)Figure24.CS5180Noise Histogram,>60,000samples (25)34CHARACTERISTICS/SPECIFICATIONSANALOG CHARACTERISTICS (T A =0°C to 70°C;VA+=5V ±5%,VD+=3V ±10%;AGND =DGND =0V;MCLK =25.6MHz;VREFIN =VREFOUT;MODE =VD+;Analog source impedance =301Ohms with 2200pF to AGND;Full-Scale input sinewave at 22kHz;Unless otherwise noted)Notes: 1.Dynamic range is tested with a 22kHz input signal 60dB below full scale.2.Specification guaranteed by design,characterization,and/or test.3.Full scale fully-differential input span is nominally 1.6X the VREFIN voltage.The peak negativeexcursion of the signals at AIN+or AIN-should not go below AGND for proper operation.4.VREFIN current is less than 1µA under normal operation,but can be as high as ±200µA duringcalibration.5.Drift of the on-chip reference alone is typically about ±30ppm/°C.If using an external reference,totalfull scale drift will be that of the external reference ±20ppm/°C,which is the typical drift of the X1.6buffer.6.Applies after self-calibration at final operating ambient temperature.ParameterSymbolMinTypMaxUnitDynamic Performance Dynamic Range(Note 1)DR 9093-dB Total Harmonic Distortion THD -90-95-dB Signal to (Noise +Distortion)SINAD 8791-dB Spurious Free Dynamic Range SFDR9096-dBcStatic Performance Linearity Error(Note 2)INL -±2-LSB Differential Non-Linearity (Note 2)DNL--±0.5LSB Full Scale Error(Note 6)-±8-LSB Full Scale Drift with Internal Reference (Notes 2and 5)-±50-ppm/°C Offset Error (Note 6)-±8-LSB Offset Drift (Note 2)-±6.0-µV/°CAnalog InputDifferential Input Voltage Range (Note 3)- 1.6X VREFIN-V pp Common Mode Range CMR1-VREFIN +0.25V Input Capacitance- 4.0-pF Differential Input Impedance MCLK =25.6MHz-500-k ΩCommon Mode Rejection Ratio (Note 2)CMRR50--dB Common Mode Input Current MCLK =25.6MHz-±100±200µAReference Input VREFIN 2.25 2.375 2.6V VREFIN Current (Note 4)-1±200µAReference Output VREFOUT Voltage 2.25 2.375 2.5V VREFOUT Output Current --±500µA VREFOUT Impedance-0.1-Ω5ANALOG CHARACTERISTICS (Continued)Notes:7.All outputs unloaded.All digital inputs except MCLK held static at VD+or DGND.8.Power consumption when PWDN =0applies only with no master clock applied (MCLK held high or low).9.Measured with a 100mV pp sine wave on the VA+supplies at a frequency of 100Hz.ParameterSymbolMinTypMaxUnitPower SuppliesPower Supply Current (MODE =1,PWDN =1)(Note 7)VA1+,VA2+=5V VD1+,VD2+=5V VD1+,VD2+=3V---4692465511055mA mA mA Power Supply Current (MODE =1,PWDN =0)(Notes 7,8)VA1+,VA2+=5V VD1+,VD2+=5V VD1+,VD2+=3V --- 3.70.0680.06060.20.2mA mA mA Power Supply Current (MODE =0,PWDN =1)(Note 7)VA1+,VA2+=5V VD1+,VD2+=5V VD1+,VD2+=3V---46158.5552011.0mA mA mA Power Supply Current (MODE =0,PWDN =0)(Notes 7,8)VA1+,VA2+=5V VD1+,VD2+=5V VD1+,VD2+=3V --- 3.70.0680.06060.20.2mA mA mA Power Supply Rejection(Note 9)PSRR-55-dBDYNAMIC CHARACTERISTICSDIGITAL CHARACTERISTICS(TA =0°C to70°C;VA+=5V±5%;AGND=DGND=0V)Parameter Symbol Min Typ Max Unit Modulator Sampling Frequency-MCLK-Hz Output Word Rate-MCLK/64-Hz Filter Characteristics(Note2)-3dB Corner-MCLK/142.3804-Hz Passband Ripple--±0.05dB Stopband Frequency-MCLK/128-Hz Stopband Rejection90--dB Group Delay-2370/MCLK-sParameter Symbol Min Typ Max UnitHigh-Level Input Voltage VD+=5VVD+=3V V IHV IH4.02.0----VVLow-Level Input Voltage VD+=5VVD+=3V V ILV IL----0.80.8VVHigh-Level Output Voltage(I O=-100µA)VD+=5VVD+=3V V OHV OH42.7----VVLow-Level Output Voltage(I O=100µA)VD+=5VVD+=3V V OLV OL----0.40.3VVInput Leakage Current VD+=5VVD+=3V I inI in--±1±1±10±10µAµAInput Capacitance C in-6-pF67SWITCHING CHARACTERISTICS (T A =0°C to 70°C;VA+=5V ±5%,VD+=2.7V to 5.5V;AGND =DGND =0V;MODE =VD+)Notes:10.Rise and Fall times are specified at 10%to 90%points on waveform.11.RESET,SYNC,and PWDN have Schmitt-trigger inputs.12.Specifications applicable to complementary signals and ParameterSymbol Min Typ Max Unit Master Clock Frequency (Note 2)MCLK0.51225.626MHz Master Clock Duty Cycle 45-55%Rise Times(Notes 2,10,and 11)Any Digital Input,Except MCLKMCLKAny Digital Output t rise-----20100.2/MCLK-ns s ns FallTimes(Notes 2,10,and 11)Any Digital Input,Except MCLKMCLKAny Digital Outputt fall-----20100.2/MCLK-ns s ns Calibration/SyncRESET rising to MCLK rising-3-ns RESET rising recognized,to FSO falling -988205/MCLK-s SYNC rising to MCLK rising-3-ns SYNC rising recognized to FSO falling -5161/MCLK -s PWDN rising recognized to FSO falling -5168/MCLK-s SYNC high time 1/MCLK --s RESET low time 1/MCLK--sSerial Port Timing (Note 12)SCLK frequency -MCLK/3-Hz SCLK high time t 1-1/MCLK -s SCLK low timet 2-2/MCLK -s FSO falling to SCLK risingt 3-2/MCLK +2E-9-s SCLK falling to new data bit available t 4- 1.5-ns SCLK rising to FSO risingt 5-1/MCLK -2E-9-sFigure 1.Serial Port Timing (not to scale)8RECOMMENDED OPERATING CONDITIONS (AGND =DGND =0V)ABSOLUTE MAXIMUM RATINGSWARNING:Operation beyond these limits may result in permanent damage to the device.Normal operation is notguaranteed at these extremes.ParameterSymbol Min Typ Max Unit DC Power Supplies Digital AnalogVD+VA+ 2.74.7535 5.55.25V V Analog Reference Voltage VREFIN2.25 2.5 2.6V AGND to DGND Differential -1000100mV Operating Junction TemperatureT j--120°CParameterSymbolMin Max Unit DC Power SuppliesGround Digital Analog AGND/DGND VD+VA+-0.3-0.3-0.30.36.06.0V V V Input Current,Any pin except Supplies I in -±10mA Output CurrentI out -±25mA Power Dissipation (Total)-1000mW Analog Input Voltage and VREFIN voltage V INA -0.3(VA+)+0.3V Digital Input VoltageV IND -0.3(VD+)+0.3V Ambient Operating Temperature T A 070°C Storage T emperatureT stg-65150°CGENERAL DESCRIPTIONThe CS5180is a monolithic CMOS16-bit A/D converter designed to operate in a continuous mode after being reset.The CS5180can operate in a modulator-only mode in which the unfiltered bit stream from the modula-tor is the data output from the device. THEORY OF OPERATIONThe front page of this data sheet illustrates the block diagram of the CS5180.Converter Initialization:Calibration and SynchronizationThe CS5180does not have an internal power-on re-set circuit.Therefore when power is first applied to the device the RESET pin should be held low until power is established and the voltage reference has stabilized.This resets the converter’s logic to a known state.When power is fully established the converter will perform a self-calibration,starting with the first MCLK rising edge after RESET goes high.The converter will use988,205MCLK cycles to complete the calibration and to allow the digital filter to fully settle,after which,it will output fully-settled conversion words.The converter will then continue to output conversion words at an output word rate equal to MCLK/64.Figure2illustrates the RESET and SYNC logic and timing for the con-verter.The CS5180is designed to perform conversions continuously with an output rate that is equivalent to MCLK/64.The conversions are performed and the serial port is updated independent of external controls.The converter is designed to measure dif-ferential bipolar input signals,and unipolar signals, with a common mode voltage of between1.0V and VREF+0.25V.Calibration is performed when the RESET signal to the device is released.If RESET is properly framed to MCLK,the converter can be synchronized to a specific MCLK cycle at the sys-tem level.The SYNC signal can also be used to synchronize multiple converters in a system.When SYNC is used,the converter does not perform calibration. The SYNC signal is recognized on the first rising edge of MCLK after SYNC goes high.SYNC aligns the output conversion to occur every64 MCLK clock cycles after the SYNC signal is rec-ognized and the filter is settled.After the SYNC is initiated by going high,the converter will wait 5,161MCLK cycles for the digital filter to settle before putting out a fully-settled conversion word. To synchronize multiple converters in a system,theFigure2.RESET and SYNC logic and timing.9SYNC pulse should rise on a falling edge of the MCLK signal.This ensures that the SYNC input to all CS5180s in the system will be recognized on the next rising edge of e of the SYNC input is not necessary to make the converter operate properly.If it is unused it should be tied to DGND. Conversion data is output from the SDO and SDO pins of the device.The data is output from the SDO pin MSB first,in two’s complement format.The converter furnishes a serial clock SCLK and its complement SCLK to latch the data bits;and a data framing signal,Frame Sync Output(FSO),which frames the output conversion word.The SCLK output frequency is MCLK/3.Clock GeneratorThe CS5180must be driven from a CMOS-com-patible clock at its MCLK pin.The MCLK input is powered from the VD+supply and its signal input should not exceed this supply.The required MCLK is64×OWR(Output Word Rate).To achieve an Output Word Rate of400kHz,the MCLK frequency must be64×400kHz,or 25.6MHz.A second clock input pin,MCLK,is not actually used inside the device but allows the user to run a fully differential clock to the converter to minimize radiated noise from the PC board lay-out.The CS5180can be operated with MCLK frequen-cies from512kHz up to26MHz.The output word rate scales with the MCLK rate with OWR=MCLK/64.Voltage ReferenceThe CS5180can be configured to operate from ei-ther its internal voltage reference,or from an exter-nal voltage reference.The on-chip voltage reference is2.375V and is ref-erenced to the AGND pin.This2.375V reference is output from the VREFOUT pin.It is then filtered and returned to the VREFIN pin.VREFIN pin is connected to a buffer which has a gain of1.6.This scales the on-chip reference of2.375V to3.8V. This value sets the peak-to-peak input voltage into the AIN pins of the converter.Figure3illustrates the CS5180connected to use the internal voltage refer-ence.Note that a1.0µF and0.1µF capacitor are shown connected to the VREFCAP pin to filter out noise.A larger capacitor can be used,but may re-quire a longer reset period when first applying power to the part to allow for the reference to charge up the capacitors and stabilize before self-calibration be-gins.Figure3.CS5180connection diagram for using the internal voltage reference.10Alternatively,the CS5180can be configured to use an external voltage reference.Figure4illustrates the CS5180connected to use a2.5V external ref-erence.In this case,the peak-to-peak input at the AIN pins is4V.Analog InputThe analog signal to the converter is input into the AIN+and AIN-pins.The input signal is fully dif-ferential with the maximum peak-to-peak ampli-tude of VREFIN X1.6V.The signal needs to have a common mode voltage in a range from1V toVREF+0.25V.A resistor-capacitor filter should be included on the AIN+and AIN-inputs of the converter.This should consist of a20Ωresistor and a2200pF capacitor on each input to ground as illustrated in the system connection diagram(Fig-ure).Output CodingTable1illustrates the output coding for the con-verter when operating with the digital filter (MODE=1).The converter outputs its data from the serial port in twos complement format,MSB first.The chip offers an MFLAG signal to indicate when the modulator has gone unstable.MFLAG is set when an overrange signal forces the modulator into an unstable condition.Under this condition,output codes from the converter will be locked to either plus or minus full scale as is appropriate for the overrange condition.Modulator-Only modeThe CS5180can be operated in modulator-only mode by connecting the MODE pin to a logic0 (DGND).In modulator-only mode the noise-shaped bit-stream from the fifth-order delta-sigma modulator is output from the SDO and SDO(inverse bit-stream)pins.Figure4.CS5180connection diagram for using an external voltage reference.Fully Differential BipolarInput Voltage1Twos Complement>(V FS-1.5LSB)7FFFV FS-1.5LSB7FFF7FFE-0.5LSB 0000 FFFF-V FS+0.5LSB80018000 <(-V FS+0.5LSB)8000 Notes: 1.V FS=VREFIN x1.6Table1.Output Coding.The data from the modulator is output from SDO/SDO in RTZ (Return to Zero)format.The circuit in Figure 6can be used to reconstruct the data so it can be captured with the rising or falling edge of MCLK.Table 2illustrates the magnitude of the input signal into the chip versus the ones density out of the modulator.The table does not take into account the potential offset and gain errors of the modulator and their effect on the ones density.Figure 7and Figure 8illustrate magnitude versus frequency plots of the modulator bitstream when running at 25.6MHz.Fully Differential BipolarInput Voltage 2Modulator OnesDensity 3VFS75%050%-V FS25%Notes: 2.V FS =VREFIN x 1.63.Ones density is approximate;it does nottake offset and gain errors into consideration.Table 2.Modulator-Only Mode OnesDensity.Figure 5.Modulator Only Mode Data RTZ Format.Figure 6.Circuit to Reconstruct Return-to-Zero (RTZ)Data fromSDO/SDO into Original ModulatorBitstream.Figure 7.Magnitude versus frequency spectrum ofmodulator bitstream (MCLK =25.6MHz).Figure 8.Expanded view of the magnitude versus fre-quency spectrum of modulator bitstreamInstability IndicatorThe MFLAG signal is functional in both modes of operation of the part and indicates when the modu-lator has been overdriven into an unstable condi-tion.In the modulator only mode(MODE=0),the MFLAG signal will remain set for3MCLK cycles when the modulator goes unstable,before being re-turned to the reset state.While the input condition causing modulator instability persists,the MFLAG signal will continually get set for3MCLK cycles and then get reset.When the decimation filter on the part is operation-al(MODE=1),the MFLAG signal is set when the modulator goes unstable.In this mode,however, the MFLAG signal stays set until5,120MCLK cy-cles after the input condition causing modulator in-stability is removed.This delay is provided to allow the digital filter time to settle,and the part will output fully settled conversion words after the MFLAG signal goes low.Digital Filter CharacteristicsFigure9illustrates the magnitude versus frequency plot of the converter when operating at400kHz output word rate.The filter is a non-aliasing4265 tap filter with a-3dB corner at0.4495of the output word rate and an out-of-band attenuation of at least90dB at frequencies above one half the output word rate.The passband ripple is less than ±0.05dB up to the-3dB corner frequency. Figure10illustrates the phase response of the dig-ital filter with the converter operating at400kHz output word rate.The filter characteristics change proportional to changes in the MCLK rate.The group delay of the digital filter is2,370MCLK cycles(92.6µs with MCLK=25.6MHz),and the settling time is4,740MCLK cycles(185.2µs). Serial InterfaceThe CS5180has a serial interface through which conversion words are output in a synchronous self-clocking format.The serial port consists of the Se-rial Data Output pin(SDO),and its complement (SDO);Serial Clock(SCLK),and its complement (SCLK);and the Frame Sync Output(FSO).FSO falls at the beginning of an output word.Data is output in twos complement format,MSB first. FSO stays low for16SCLK cycles.SCLK is out-put at a rate equal to MCLK/3.Power Supplies/Board LayoutThe CS5180can be operated with VA+supplies at 5V and VD+supplies at5V;or with VA+at5V and VD+at3V.Figure illustrates the system connection diagram for the chip.For best performance,each ofthe Figure9.CS5180Digital Filter Magnitude Response(MCLK=25.6MHz)Figure10.CS5180Digital Filter Phase Response(MCLK=25.6MHz)supply pins should be bypassed to the nearest ground pin on the chip.The bypass capacitors should be located as close to the chip as possible.If the chip is surface mounted the bypass capacitors should be on the same side of the circuit card as the chip.The CS5180is a high speed component that re-quires adherence to standard high-frequency print-ed circuit board layout techniques to maintain optimum performance.These include the use of ground and power planes,using low noise power supplies in conjunction with proper supply decou-pling,minimizing circuit trace lengths,and physi-cal separation of digital and analog components and circuit traces.It is preferred that any clock oscillator circuitry be located on a ground plane separate from the digital plane in order to ensure that digital noise does not induce clock jitter.For additional insight,see the CDB5180evaluation board for more details.Also refer to Application Note AN18about layout and design rules for data converters.V.used.†Miniature surface mount25.6MHz clock oscillators may be ordered from the CTS Reeves Company.For4.5V to5.5Volt Operation,order P/N974-7725-0000AFor3.0to3.6Volt Operation,order P/N974-7727-0000AFigure11.CS5180System Connection DiagramPower-down ModeThe CS5180has a PWDN(power-down)function. When active low,power to most of the converter’s circuitry will be reduced.If MCLK is to be stopped to save power,it should not be stopped until at least ten clock cycles after PWDN is taken low.The ten clock cycles are required to allow the part to turn off it’s internal circuitry.If the part does not get the full ten clock cycles,it will still go into a power down state,but the power dissipation could be more than is listed in the specifications for the full power down condition.When PWDN is active,the calibration information inside of the converter is maintained.When coming out of the power-down state,the converter is not recalibrated and will start-up similar to when SYNC is initiated.PIN DESCRIPTIONSupply InputsV A1+,V A2+—Positive Analog SupplyInput for positive analog supply is +5V typical when AGND is 0V .AGND —Analog GroundAnalog ground for circuits supplied by V A+.VD1+,VD2+—Positive Digital SupplyInput for positive digital supply is +5V typical when DGND is 0V .DGND —Digital GroundDigital ground for circuits supplied by VD+.Signal and Reference Related Inputs AIN+,AIN-—Differential Analog InputsFully differential signal inputs.VREFIN —Voltage Reference InputVREFOUT or an external reference is connected to VREFIN.Analog input voltage (full scale fully differential peak-to-peak)into the converter is 1.6times this value.Analog Ground AGND Pos.Reference VREF+VA1+Positive Analog Supply Neg.Reference VREF-AIN-Negative Analog Input Reference Output VREFOUT AIN+Positive Analog Input Pos.Reference InputVREFINPWDNPower Down Mode Reference Bypass VREFCAPMODE Modulator Only Mode Analog Ground AGND RESET Reset and CalibrationAnalog Supply VA2+DGND Digital Ground Invalid ConversionMFLAG VD1+Positive Digital Supply Sync.Filter SYNC MCLK Master Clock Digital Ground DGND MCLK Inverse Master Clock Pos.Digital Supply VD2+AGND Analog Ground Inverse Serial ClockSCLK FSO Frame Sync Output Serial ClockSCLKSDO Serial Data Out SDOInverse Serial Data Out\CS518012342827265678910111213141516171920212223242518VREF+—Positive Voltage ReferenceFilter capacitor connection for the reference input buffer.The voltage on this pin equals VREFIN X1.6.VREF-—Negative Voltage ReferenceVREF-is connected to AGND.VREFOUT—Voltage Reference OutputOutput pin for the2.375volt on-chip reference relative to AGND.VREFCAP—Reference BypassFilter capacitor connection for the internal reference.Serial Interface I/O SignalsSCLK,SCLK—Serial Interface ClockSerial Clock Output.A gated serial clock output from the converter at a rate equal to1/3the MCLK clock rate.The SCLK output is a complement of SCLK and helps reduce radiated noise if the two lines are run adjacent on the PC board layout.SDO,SDO—Serial Data OutSerial Data Output.Output pin for16-bit serial data word.The SDO output is the complement of SDO and helps to reduce radiated noise if the two lines are run adjacent on the PC board layout.Output data is output in twos complement format MSB first.FSO—Frame Sync OutputThe Frame Sync Output indicates the beginning of an output word from the SDO pin by falling to a logic low state.FSO remains low until all16bits are clocked out.Control PinsRESET—Reset and CalibrationWhen the RESET pin is pulled to a logic low the converter will perform a reset of its digital logic.When the level on this pin is brought back to a logic high the chip starts normal operation,following a two clock cycle delay period.When MODE=1the chip goes through an internal gain and offset calibration routine following this reset sequence.PWDN—Power Down ModeA logic0on PWDN pin will put the device into a power-down mode.。

中职《会计实务知识》第二学期期末考试试卷(A卷)

《会计实务知识》第二学期期末考试试卷（A 卷）1. 企业财务会计是应用在各类企业（）中的一个会计分支。

A 经济管理活动 B 资金筹集活动 C 资金运用活动 D 企业发展活动 2．企业财务会计服务的对象具有（）。

A 机动性 B 盈利性 C 实践性 D 多样性3．企业财务会计要对企业的业务经营活动实施（）。

A 财务会计监督 B 收支审查监督 C 财经法纪监督 D 经济效益监督4.会计年度、半年度、季度和月度均按（）起讫日期确定。

A 农历 B 公历 C 皇历 D 日历5.外商投资企业的财务会计记录可以同时使用（）。

A 中文记录 B 外国文字记录 C 一种外国文字 D 两种外国文字6．《会计法》明确规定单位负责人必须对会计资料的（）负责。

A 合法性B 真实性C 完整性D 有效性 7．异地托收承付结算每笔的金额起点是（）A 1000元B 10000元C 100000元D 没有起点金额8．现金清查的结果，无论是长款还是短款，在批准之前应通过（）账户核算。

A 营业外收入 B 待处理财产损溢 C 管理费用 D 营业外支出 9．银行汇票一律记名，付款期限为（）A 1个月B 2个月C 3个月D 以上都不对10．10月5日，某公司将一张8月20日签发的90天到期的商业汇票到银行办理贴现手续，则贴现日数是（）。

A 47天 B 46天 C 45天 D 44天11．对逾期未获支付的商业票据，企业应作的账务处理是（）。

A 借：应收账款 B 借：坏账准备贷：应收票据贷：应收票据 C 借：其他应收款 D 都不对贷：应收票据12．下列各项中不应计入存货成本的是（）。

A 买价 B 运费 C 入库前的整理挑选费用 D 超定额损耗 13．企业外购材料入库时应填制（）。

A 收料单 B 领料单 C 限额领料单 D 发料单14．.收到投资者投入的材料，其会计分录是（）。

A 借：原材料 B 借：实收资本贷：实收资本贷：原材料C 借：固定资产D 借：实收资本贷：实收资本贷：固定资产15．一次领用低值易耗品数量不大，金额不高，可采用（） A 分次摊销法 B 一次摊销法 C 五五摊销法 D 净值摊销法专业班级姓名学号16. 凡不符合固定资产确认标准的劳动资料，应将其列为( )。

SJA1000中文资料

64字节的一个窗口可被
CPU访问
CPU在此
FIFO的支持下可以在处理信息的时候接收其它信息
(铅笔注释 Administrator
2010-12-7 9:31:52
空白)
(铅笔注释 Administrator
CMR
6.4.5 状态寄存器
SR
6.4.6 中断寄存器
IR
6.4.7 中断使能寄存器
IER
6.4.8 仲裁丢失捕捉寄存器
ALC
6.4.9 误码捕捉寄存器
ECC
6.4.10 错误报警时序寄存器
EWLR
6.4.11 RX错误计数寄存器
RXERR
VSS1
XTAL1
XTAL2
MODE
VDD3
TX0
TX1
AD5
AD4
AD3
AD2
AD0
VDD1
AD1
VSS2
RX1
RX0
VDD2
RST
INT
VSS3
1
2
3
4
5
6
7
8
9
10
11
12
13
部延时此时连有外部收发电路这种情况下只有RX0是激活
的弱势电平被认为是高而支配电平被认为是低
VSS2 21 输入比较器的接地端
VDD1 22 逻辑电路的5V电压源
注
1 XTAL1 和XTAL2 引脚必须通过15pF 的电容连到VSS1.
AD6
AD7
ALE/AS
CLKOUT

防洪工程数据库资料

附件A 数据字典A1 工程分类与工程分类码（1）防洪工程分类与工程分类码防洪工程数据库收集有18类工程信息，每一类除类型名称外，为方便排序与检索，尚应编制“工程分类码”。

工程分类码：执行行业标准SL 213-98，其中“险点险段”和“城市防洪”在SL 213-98中没有列项，故分别补充赋码“V”和“W”，见表A1.1。

在表A1.1中还给出了部分工程（类）的“中央数据库域定义”，用于限制中央库的数据量，以保证数据库的性能。

表A1.1 工程分类与工程分类码40 .❶设计中只为涵管、倒虹吸设计了表格，如果是排水站、泵站等，建议入机电排灌站。

41.A2 数据类型防洪工程数据库的数据类型定义如表A2.1。

表A2.1 防洪工程数据库中的数据类型A3字段表与同义词汇总除去重复出现的字段，并按照字段在表中出现的先后次序，将防洪工程数据库的所有字段列于表A3.1。

防洪工程数据库中使用了大量的同义词，如“工程名称代码”在不同的地方可能有不同的含义或需要加以约束，因此称谓也不同，见表A3.2。

其他的同义词见表A3.3。

表A3.1 防洪工程数据库字段表42 ..8283 ..8485 ..8687 ..8889 ..9091 ..9293 ..9495 ..9697 ..9899 ..100101 ..102103 ..104105 ..106107 ..108109 ..110111 ..112113 ..114115 ..116117 ..118119 ..120121 ..122123 ..124125 ..126表A3.2 “工程名称代码”的同义词127 .128.表A3.3 其它同义词清单。

1908114资料

CUL Nominal voltage UN Nominal current IN AWG/kcmil UL Nominal voltage UN 125 V 125 V 4A 28-20
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Address
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Tools 1205202 SZS 0,4X2,0 Screwdriver, bladed, matches all screw terminal blocks up to 1.5 mm² connection cross section, blade width: 2.5 mm, without approvals
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Plug component, nominal current: 4 A, rated voltage: 80 V, pitch: 2.5 mm, no. of positions: 7, type of connection: Spring-cage connection

PC847XIJ000F资料

2. Package resin : UL flammability grade (94V-0)
■ Applications
1. I/O isolation for MCUs (Micro Controller Units) 2. Noise suppression in switching circuits 3. Signal transmission between circuits of different po-
ing) 3. High collector-emitter voltage (VCEO : 80V) 4. Current transfer ratio (CTR : MIN. 50% at IF=5mA,
VCE=5V) 5. Several CTR ranks available 6. High isolation voltage between input and output
PC847XI9J00F
PC847X0J000F
PC847XI0J00F
IC [mA] (IF=5mA, VCE=5V, Ta=25˚C)
2.5 to 30.0 4.0 to 13.0 6.5 to 20.0 10.0 to 30.0 4.0 to 20.0 6.0 to 30.0 4.0 to 30.0
1. Through-Hole [ex. PC847XJ0000F]
1.2±0.3
0.6±0.2
16
15 14
13 12 11 10
9
PC847XJ0000F Series
(Unit : mm)
Factory identification mark
Date code
PC817 PC817