Xilinx EDK官方试验4mb
XC7VX415T-2FFG1158C
Chapter1 Package InformationPackage OverviewIntroduction to Xilinx PackagingElectronic packages are interconnectable housings for semiconductor devices. The majorfunctions of the electronic packages are to provide electrical interconnections between theIC and the board and to efficiently remove heat generated by the device.Feature sizes are constantly shrinking, resulting in increased number of transistors beingpacked into the device. Today's submicron technology is also enabling large-scalefunctional integration and system-on-a-chip solutions. In order to keep pace with thesenew advancements in silicon technologies, semiconductor packages have also evolved toprovide improved device functionality and performance.Feature size at the device level is driving package feature sizes down to the design rules ofthe early transistors. To meet these demands, electronic packages must be flexible toaddress high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.Packaging T echnology at XilinxXilinx provides a wide range of leaded and array packaging solutions for our advancedsilicon products. Xilinx® advanced packaging solutions include overmolded plastic ballgrid arrays (PBGA), small form factor Chip Scale Packages, “Cavity-Down” BGAs,flip-chip BGAs, flip-chip ceramic column grid arrays (CCGA), as well as the newer leadframe packages such as Quad Flat No-Lead (QFN) packages to meet various pin countsand density requirements. Packages from Xilinx are designed, optimized, andcharacterized to support the long-term mechanical reliability requirements as well as tosupport the cutting-edge electrical and thermal performance requirements for our high-speed advanced FPGA products.Pb-free Packaging Solutions from XilinxXilinx also develops packaging solutions that are safer for the environment. Today,standard packages from Xilinx do not contain substances that are identified as harmful tothe environment including cadmium, hexavalent chromium, mercury, PBB, and PBDE. Pb-free solutions take that one step further and also do not contain lead (Pb). This makes Pb-free solutions from Xilinx RoHS (Reduction of Hazardous Substances) compliant. Pb-freepackages from Xilinx are also JEDEC J-STD-020 compliant, meaning that the packages aremade to be more robust so they are capable of withstanding higher reflow temperatures.Xilinx is now ready to support the industry requirements for Pb-free packaging solutions.Chapter 1:Package InformationPackage SamplesXilinx offers two types of non-product-specific package samples that can help developcustom processes and perform board-level tests. These samples can be ordered withordering codes as detailed below.Mechanical Samples XCMECH-XXXXX (where XXXXX is the package code of interest)This part type is used for mechanical evaluations, process setup, etc. Most packages arebased on the JEDEC outline, and these parts are at times referred to as "dummy" parts sincemechanical samples do not contain a die.Example:To order a FG676 package as a mechanical sample (without the die), the part numberwould be XCMECH-FG676.质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工业级IC，军级二三极管，功率管等;应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备祝您:工作顺利，生活愉快!以赛灵思半导体（深圳）有限公司提供的参数为例，以下为XC7VX415T-2FFG1158C的详细参数，仅供参考Specifications and DefinitionsDaisy Chain Samples XCDAISY-XXXXX (where XXXXX is the package code of interest)Use this part type to perform board-based evaluations (such as vibrations and temperaturecycles) to see how well the solder balls withstand these mechanical conditions. For Xilinxdaisy chain parts (XCDAISY-XXXXX), a specific ball assignment chain is available. If youdo not have a board already made, you can use our default chain. You can purchase theseparts from Xilinx through standard sales outlets. Xilinx does not support unique chainsbecause these parts do not have the volume to justify the development effort.Example:To order a FG676 package in a daisy-chained configuration, the part number would beXCDAISY-FG676.Specifications and DefinitionsInches vs. MillimetersThe JEDEC standards for PLCC, CQFP, and PGA packages define package dimensions ininches. The lead spacing is specified as 25mils, 50mils, or 100mils (0.025in., 0.050in. or0.100in.).The JEDEC standards for PQFP, HQFP, TQFP, VQFP, CSP, and BGA packages definepackage dimensions in millimeters. The lead frame packages have lead spacings of0.5mm, 0.65mm, or 0.8mm. The CSP and BGA packages have ball pitches of 0.5mm,0.8mm, 1.00mm, or 1.27mm.Because of the potential for measurement discrepancies, this Data Book providesmeasurements in the controlling standard only, either inches or millimeters.Pressure Handling CapacityFor mounted BGA packages, including flip chips, a direct compressive (non-varying) forceapplied normally to the lid or top of package with a tool head that coincides with the lid (oris slightly bigger) will not induce mechanical damage to the device including externalballs, provided the force is not over 5.0 grams per external ball, and the device and boardare supported to prevent any flexing or bowing.These components are tested in sockets with loads in the 5 to 10 gm/ball range for shortdurations. Analysis using a 10g/ball (e.g., 10 kg for FF1148) showed little impact on short-term but some creep over time. 20 gm/ball and 45 gm/ball loads at 85°C over a six weekperiod has shown the beginning of bridging of some outer balls; these were static loadtests. The component can survive forces greater than the 5 gm limit while in short-termsituations. However, sustained higher loads should be avoided (particularly if they areoverlaid with thermal or power cycle loads). Within the recommended limits, circuit boardneeds to be properly supported to prevent any flexing resulting from force application.Any flexing or bowing resulting from such a force can likely damage the package-to-boardconnections. Besides the damage that can occur from bending, the only major concern islong-term creep and bulging of the solder balls in compression to cause bridging. For thelife of a part, staying below the recommended limit will ensure against that remotepossibility.Chapter 1:Package InformationClockwise or CounterclockwiseThe orientation of the die in the package and the orientation of the package on the PCboard affect the PC board layout. PLCC and PQFP packages specify pins in acounterclockwise direction, when viewed from the top of the package (the surface with theXilinx logo). PLCCs have pin 1 in the center of the beveled edge while all other packageshave pin 1 in one corner, with one exception: The 100-pin and 165-pin CQFPs (CB100 andCB164) for the XC3000 devices have pin 1 in the center of one edge.CQFP packages specify pins in a clockwise direction, when viewed from the top of thepackage. The user can make the pins run counterclockwise by forming the leads such thatthe logo mounts against the PC board. However, heat flow to the surrounding air isimpaired if the logo is mounted down.Cavity-Up or Cavity-DownMost Xilinx devices attach the die against the inside bottom of the package (the side thatdoes not carry the Xilinx logo). Called “Cavity-Up,” this has been the standard ICassembly method for over 25 years. This method does not provide the best thermalcharacteristics. Pin Grid Arrays (greater than 130 pins), copper based BGA packages, andCeramic Quad Flat Packs are assembled “Cavity-Down,” with the die attached to theinside top of the package, for optimal heat transfer to the ambient air. More information on“Cavity-Up” packages and “Cavity-Down” packages can be found in the “PackageTechnology Descriptions” section.For most packages this information does not affect how the package is used because theuser has no choice in how the package is mounted on a board. For Ceramic Quad Flat Pack(CQFP) packages however, the leads can be formed to either side. Therefore, for best heattransfer to the surrounding air, CQFP packages should be mounted with the logo up,facing away from the PC board.Part MarkingOrdering InformationAn example of an ordering code for a Xilinx FPGA is XC4VLX60-10FFG668CS2. Theordering code stands for:XC4VLX – Family (Virtex®-4 LX)60 – Number of system gates or logic cells (60,000 logic cells)-10 – Speed grade (-10 speed)FFG – Package type (Pb-free flip-chip BGA)668 – number of pins (668 pins)C – Temperature grade (Commercial)S2 – Step 2Part MarkingChapter 1:Package Information。
Xilinx官方的6个EDK实验6
试验6系统验证及调试：介绍这个试验通过XMD和ChipScope 对系统进行可观测的软件和硬件调试。
目标完成试验后，我们希望达到以下目标：•向系统中加入ChipScope片内逻辑分析仪•系统调试打开工程Step 1在D:\Lab\下创建lab6mb文件夹。
可以根据上面的实验建立工程，也可直接把lab6mb的内容直接拷贝至此目录。
编译器优化选项设置Step 2这个部分测试编译器优化水平的不同性能。
在这之前，我们要移除定时器中断服务程序用一个延时循环来代替它。
n使用Project → Software Platform Settings …打开软件平台设置GUIo点击Processor, Driver Parameters and Interrupt Handlers栏p删除Current Value的值timer_int_handler。
使其为空。
点击<OK>q从D:\Lab\lab_sources\lab6_sources路径复制system_delay.c到当前工程D:\Lab\labmb6\coder从工程MyProj移除system_timer.c并加入新的文件system_delay.cs双击MyProj标题选择Optimization Tab如图所示，设置编译器优先等级到No Optimization，点击<OK>。
图 6-1. 编译选项设置w选择Download那么这些源文件将重新编译并下载到板上去。
LED将连续0.1秒显示计数器。
w设置编译器优化等级，并再次下载到工程当中去。
注意显示速度取决于编译器的优化等级片内逻辑分析仪Step 3点击Project → Add/Edit Cores … (dialog)，加入ChipScope 片内逻辑分析仪的。
配制以下端口。
如图6-2所示。
sys_clk_smb_halt (MicroBlaze)dbg_stop (MicroBlaze)图6-2 芯片域内核连接n 点击Project → Add Cores (dialog)o 在Peripherals 栏 加入chipscope_icon 与chipscope_opb_iba 参数p 在Bus connection 栏，连接chipscope_opb_iba 作为一个BA （总线分析器）器件到OPB 总线。
Xilinx学习资料
第0篇Xilinx FPGA开发环境的配置一、配置Modelsim ISE的Xilinx的仿真库1、编译仿真库:A、先将Modelsim安装目录C=Modeltech_6.2b下面的modelsim.ini改成存档格式(取消只读模式);B、在DOS环境中，进入Xilinx的根目录，然后依次进入bin，nt目录;C、运行compxlib -s mti_se -f all -l all -oC:Modeltech_6.2bxilinx_libs。
注意:需要根据你安装的modelsim目录更改C:Modeltech_6.2b 然后就Ok了，就可以的ISE中启动Modelsim进行所有的仿真了。
2、如何在Xilinx ISE中使用Modelsim ISE，Synplify进行综合和仿真:A、打开Xilinx ISE，新建一个Project;①、在菜单File中选择“New Project”，弹出如下的对话框:②、输入Project名称，并选择好Project保存的路径，然后下一步:字串3按照上边的参数进行设置(针对于Spatan 3E的开发板)，然后单击下一步，进入到后面的界面:③、单击“New Source”按钮，并按照下面的设置来操作:④、参照下面的参数，进行设置，然后一直选择默认选项，一直到完成。
最后生成的项目界面如下图所示:B、输入代码，然后用Synplify综合:①、参考代码:entity Count iSPort(CLK :in STD_LOGIC;RESET :in STD_LOGIC;LOAD :in STD_LOGIC;DATA IN:in STD_LOGIC_VECTOR(3 downto 0);字串9Qout :out STD_LOGIC_VECTOR(3 downto 0));end Count;architecture Behavioral of Count issignal tmpCount:STD_LOGIC_VECTOR(3 downto 0);beginprocess(CLK,RESET,LOAD)beginif RESET='1' thentmpCount<="0000";elseif LOAD='1' thentmpCount<=DATA_IN;elsif CLK'event and CLK='1' thentmpCount<=tmpCount+1;end if;end if;end process; 字串6Qout<=tmpCount:end Behavioral;②、双击Processes窗口里面的“Synthesize-Synplify”进行综合③、在“Transcript”窗口中的可以看到综合的信息。
施耐德电气低压配电产品选型指南说明书
ABB EntrelecSommaireBU0402061SNC 160 003 C0205SummarySelection guide ....................................................................................page 1Screw clamp ........................................................................................page 2Feed through and ground terminal blocks .......................................................page 2 - 5 to 10Single pole, multiclamp terminal blocks..........................................................................page 4Feed through terminal blocks - Double-deck................................................................page 11Feed through terminal blocks - Triple-deck...................................................................page 12Three level sensor, terminal blocks without ground connection...................................page 13Three level sensor, terminal blocks with ground connection ........................................page 14Terminal blocks for distribution boxes, double deck + protection .......................page 15 - 16Interruptible terminal blocks for neutral circuit......................................................page 17 - 18Distribution : phase, ground terminal blocks .......................................................page 19 to 21Single pole or four pole distribution blocks..........................................................page 22 to 24Heavy duty switch terminal blocks with blade......................................................page 25 - 26Heavy duty switch terminal blocks with push-turn knob..............................................page 26Heavy duty switch terminal blocks with contact control pull lever...............................page 29Heavy duty switch terminal blocks with blade - Double-deck .....................................page 27Fuse holder terminal blocks for 5x20 mm (.197x.787 in.) and 5x25 mm (.197x.984 in.)or 6.35x25.4 mm (1/4x1 in.) and 6.35x32 mm (1/4x11/4 in.) fuse s.........................................page 28 - 29Fuse holder terminal blocks for 5x20 mm (.197x.787 in.) and 5x25 mm (.197x.984 in.) fuses -Double-dec k.....................................................................................................................page 27Terminal blocks for test circuits with sliding bridge ......................................................page 30Terminal blocks for metering circuits.............................................................................page 31ESSAILEC terminal blocks.............................................................................................page 32Safety connection terminal blocks ................................................................................page 33Miniblocks for EN 50045 (DIN 46277/2) rail ..........................................................page 34 - 35Spring clamp ......................................................................................page 36Angled terminal blocks - Feed through and ground .....................................................page 36Feed through and ground terminal blocks ...........................................................page 37 to 41Feed through terminal blocks - Double deck ................................................................page 42Terminal blocks for sensors / actuators ........................................................................page 42Terminal blocks for distribution boxes...........................................................................page 43Switch terminal blocks for neutral conductor........................................................page 44 - 45Heavy duty switch terminal blocks with blade..............................................................page 46Fuse holder terminal blocks for 5x20 mm (.197x.787 in.) and 5x25 mm (.197x.984 in.) fuse s....page 47Miniblocks Spring clamp ......................................................................................page 48 to 52ADO - Screw clamp ...........................................................................page 53Feed through and ground terminal blocks ...........................................................page 53 to 56Feed through and ground terminal blocks - Double-deck............................................page 57Heavy duty switch terminal blocks with blade..............................................................page 58Fuse holder terminal blocks for 5x20 mm (.197x.787 in.) and 5x25 mm (.197x.984 in.) fuse s ......page 59 - 60Miniblocks ADO - Screw clamp............................................................................page 61 to 65ADO - ADO .........................................................................................page 66Feed through and ground terminal blocks ...........................................................page 66 to 69Feed through and ground terminal blocks - Double-deck............................................page 70Terminal blocks for sensors / actuators ........................................................................page 71Heavy duty switch terminal blocks with blade..............................................................page 72Fuse holder terminal blocks for 5x20 mm (.197x.787 in.) and 5x25 mm (.197x.984 in.) fuse s ......page 73 - 74Miniblocks ADO - ADO .........................................................................................page 75 to 79Accessories ADO ...........................................................................................................page 80Power terminal blocks .............................................................page 81 to 84Quick-connect terminal blocks .................................................page 85 - 86Terminal blocks for railway applications ................................page 87 to 97Pluggable terminal blocks .....................................................page 98 to 100Accessories......................................................................................page 101Marking..................................................................................page 102 to 104GrossAutomation(877)268-3700··*************************PR30PR3.Z2PR3.G2PR5PR4PR1.Z2Rated wire size :Rated wire size :Rated wire size :Rated wire size :Mounting railsShield terminals forcollector barMarking tableHorizontal Rated wire size :0.5 to 16 mm² (22 to 8 AWG)Rated wire size :Rated wire size :Rated wire size :P a g e t o 29e30 t o 32ag e e3P a ge 8 t o 60a g e6t o 6574P a ge 7 t o 79P a ge 9P a g P a gGrossAutomation(877)268-3700··*************************2ABB Entrelecd010830402051SNC 160 003 C0205MA 2,5/5 - 2.5 mm² blocks - 5 mm .200" spacingAccessoriesGrossAutomation(877)268-3700··*************************3ABB Entrelec D010740402051SNC 160 003 C0205M 4/6 - 4 mm² blocks - 6 mm .238" spacingAccessoriesGrossAutomation(877)268-3700··*************************4ABB EntrelecD011030402051SNC 160 003 C0205M 4/6.3A - 4 mm² blocks - 6 mm .238" spacingM 4/6.4A - 4 mm² blocks - 6 mm .238" spacingGrossAutomation(877)268-3700··*************************5ABB Entrelec D010840402051SNC 160 003 C0205M 6/8 - 6 mm² blocks - 8 mm .315" spacingAccessoriesGrossAutomation(877)268-3700··*************************6ABB EntrelecD010850402051SNC 160 003 C0205M 10/10 - 10 mm² blocks - 10 mm .394" spacingAccessoriesGrossAutomation(877)268-3700··*************************7ABB Entrelec D010860402051SNC 160 003 C0205M 16/12 - 16 mm² blocks - 12 mm .473" spacingAccessoriesGrossAutomation(877)268-3700··*************************8ABB EntrelecD010870402051SNC 160 003 C0205M 35/16 - 35 mm² blocks - 16 mm .630" spacingGrossAutomation(877)268-3700··*************************M 95/26 - 95 mm² blocks - 26 mm 1.02" spacingM 70/22.P - 70 mm² ground block with rail contact - 22 mm .630" spacingSelection35 mm / 1.37"12 mm / 0.47"14-30 Nm / 124-260 Ib.in 1.2-1.4 Nm / 10.6-12.3 Ib.in1000600600415400400577070240 mm 2500 MCM 500 MCM 10 mm 2 6 AWG 6 AWG IEC UL CSANFC DIN0.5 - 160.5 - 100 AWG-600 MCM 2 AWG-500 MCM 50 - 30035 - 24018-6 AWGD 150/31.D10 - 150 mm² blocks - 31 mm 1.22" spacingCharacteristicsD 240/36.D10 - 240 mm² blocks - 36 mm 1.41" spacingSelectionWire size main circuit mm² / AWG VoltageV Current main circuit A Current outputARated wire size main circuit mm² / AWG Rated wire size outputmm² / AWG Wire stripping length main circuit mm / inches Wire stripping length output mm / inches Recommended torque main circuit Nm / Ib.in Recommended torque outputNm / Ib.inSolid Stranded Solid Stranded Wire size output mm² / AWG9.5 mm / .37"0.5-0.8 Nm / 4.4-7.1 Ib.in5003003003220204 mm 212 AWG12 AWG0.2 - 422-12 AWG 22-12 AWG 0.22 - 4IEC ULCSANFC DINCharacteristicsWire size mm² / AWGSolid Stranded D 4/6.T3 - 4 mm² blocks - 6 mm .238" spacingSelectionVoltage V CurrentARated wire sizemm² / AWG Wire stripping length mm / inches Recommended torqueNm / Ib.inM 4/6.T3.P - 4 mm² block - 6 mm .238" spacingD 2,5/6.D - 2.5 mm² blocks - 6 mm .238" spacingD 2,5/6.DL - 2.5 mm² blocks - 6 mm .238" spacingD 2,5/6.DPA1 - 2.5 mm² blocks - 6 mm .238" spacingD 2,5/6.DPAL1 - 2.5 mm² blocks - 6 mm .238" spacingD 4/6... - 4 mm² blocks - 6 mm .238" spacingD 4/6.LNTP - 4 mm² closed blocks - 17.8 mm .700" spacingMA 2,5/5.NT- 2.5 mm² block - 5 mm .200" spacingAccessories**SFB2 : 16 to 35 mm² 6 to 2 AWG H= 3 mm/.12"M 10/10.NT- 10 mm² block - 10 mm .394" spacingAccessories(1) Except for M 35/16 NT (closed block)*SFB1 : 0.5 to 35 mm² 18 to 2 AWG H= 7 mm/.28"**SFB2 : 16 to 35 mm² 6 to 2 AWG H= 3 mm/.12"MB 4/6... - 4 mm² blocks - 6 mm .238" spacingMB 6/8... - 6 mm² blocks - 8 mm .315" spacingMB 10/10... - 10 mm² blocks - 10 mm .394" spacingBRU 125 A - 35 mm² block - 27 mm 1.063" spacingBRU 160 A - 70 mm² block - 35.2 mm 1.388" spacingBRU 250 A - 120 mm² blocks - 44.5 mm 1.752" spacingBRU 400 A - 185 mm² block - 44.5 mm 1.752" spacingAccessoriesAccessoriesBRT 80 A - 16 mm² block - 48 mm 1.89" spacingBRT 125 A - 35 mm² block - 48 mm 1.89" spacingBRT 160 A - 50 mm² block - 50 mm 1.97" spacing9.5 mm / .37"0.5-0.6 Nm / 4.4-5.3 Ib.in4003003002010104 mm 210 AWG 12 AWG 0.5 - 422-10 AWG20-12 AWG0.5 - 2.5IEC ULCSANFC DINMA 2,5/5.SNB - 2.5 mm² blocks - 5 mm .200" spacingCharacteristicsM 4/6.SNB - 4 mm² blocks - 6 mm .238" spacingSelectionWire size mm² / AWGVoltage V CurrentARated wire sizemm² / AWG Wire stripping length mm / inches Recommended torqueNm / Ib.inSolid StrandedM 6/8.SNB - 6 mm² blocks - 8 mm .315" spacing - blade switchingSelectionAccessoriesM 4/8.D2.SF - for fuses 5x20 mm .197x.787 in. and 5x25 mm .197x.984 in. -4 mm² blocks - 8 mm .315" spacingM 4/6.D2.SNBT - 4 mm² blocks - 6 mm .238" spacing - blade switchM 4/8.SF- 4 mm² blocks - 8 mm .315" spacingM 4/8.SFL - 4 mm² blocks - 8 mm .315" spacing12 mm / .472"1.2-1.4 Nm / 10.6-12.3 Ib.in800(1)60060016252510 mm 210 AWG8 AWG0.5 - 1622-10 AWG 22-8 AWG 0.5 - 10IEC ULCSANFC DINCBD2SML 10/13.SF - for fuses 6.35x25.4 mm 1/4x1 in. and 6.35x32 mm 1/4x11/4 in. -10 mm² blocks - 13 mm .512" spacingSelectionAccessoriesCharacteristicsWire size mm² / AWGVoltage V CurrentARated wire sizemm² / AWG Wire stripping length mm / inches Recommended torqueNm / Ib.inSolid Stranded (1) Insulation voltage of terminal block - operating voltage : according to fuse.M 4/6.D2.2S2... - 4 mm² blocks - 6 mm .238" spacing11 mm / .43"0.8-1 Nm / 7.1-8.9 Ib.in50060030306 mm 28 AWG0.5 - 1022-8 AWG0.5 - 6IECULCSANFC DINM 6/8.ST... - 6 mm² blocks - 8 mm .315" spacingCharacteristicsWire size mm² / AWGVoltage V CurrentARated wire sizemm² / AWG Wire stripping length mm / inches Recommended torqueNm / Ib.inSolid Stranded M 6/8.STA - 6 mm² blocks - 8 mm .315" spacing(3)Only for M 6/8.STAM 4/6.ST- 4 mm² blocks - 6 mm .236" spacingBNT...PC...(2) Only for M10/10.ST-SnThe PREM IUM solution for testing the secondary circuits of current or voltage transformers.ESSAILEC, approved by the major electricity utilities, remains the premium choice for the energy market.Implemented in the transformers secondary circuits, ESSAILEC thanks to its intelligent “make before break” design eases and secures any intervention. Cutting the energy supply is avoided with zero risk for the operator.The plug and socket connection cuts cost installation as well as in-situ wiring errors. ESSAILEC is ideal for the wiring of sub-assemblies in the secondary circuits.ESSAILEC terminal blocksProtection relays,Protection relays,Testing :The ESSAILEC socket supplies energy to the protection or counting devices. The insertion of the test plug, which is connected to the measurement equipment, allows the testing of the devices, without perturbing the circuit.ESSAILEC blocks are well adapted to current or voltage measurement :-Current sockets with make before break contacts and pre-wired test plug for current measures-Voltage sockets with open contacts and pre-wired test plug for voltage measures-Up to 4 ammeters or 4 voltmeters connected to the test plugDistributing :The ESSAILEC plug is continuously mounted on the socket to supply current or voltage to secondary circuits sub assemblies.ESSAILEC blocks extreme versatility allow :-Safe current distribution with current socket with mobile contacts since the secondary circuit is not cut when plug is removed-Voltage or polarity distribution with dedicated voltage or polarity socket with closed contactESSAILEC is designed to offer :Great flexibility :-Connection multi contacts « plug and play »-Panel, rail, rack fixed mounting or stand-alone connector -Two wiring technologies, up to 10 mm²Extreme reliability :-Non symmetric blocks -Coding accessories -IP20 design -Locking system -Sealed coverR S T NFor technical characteristics and complete part numbers list, please ask for the ESSAILEC catalog10005006003225254 mm 21.65 mm²12 AWG 13 mm / .51"IECB.SCSANFC DINTS 50-180.5 - 0.8 Nm /4.4 - 7.1 Ib.in0.2 - 422-12 AWG0.22 - 40.5 - 1.50.28 - 1.6580050060041252562.512 AWG 13 mm / .51"0.8 - 1 Nm / 7.1 - 8.9 Ib.inIECB.S CSANFC DINTS 50-180.5 - 1020-12 AWG0.5 - 60.28 - 2.590050060046406510 mm 26 mm² 6 AWG 14 mm / .55"IECB.S UL/CSANFC DINTS 50-181.2 - 1.4 Nm / 10.6 - 12.3 Ib.in0.5 - 1620 - 6 AWG0.5 - 100.28 - 6M 4/6.RS - 4 mm² blocks - 6 mm .238" spacingCharacteristicsWire size mm² / AWGVoltage V CurrentARated wire sizemm² / AWG Wire stripping lengthmm / inches Recommended torque (screw)Nm / Ib.inSolid wire Stranded wire Solid wire Stranded wire Screw clampLugsM 6/8.RS - 6 mm² blocks - 8 mm .315" spacingCharacteristicsWire size mm² / AWGVoltage V CurrentARated wire sizemm² / AWG Wire stripping lengthmm / inches Recommended torque (screw)Nm / Ib.inSolid wire Stranded wire Solid wire Stranded wire Screw clampLugspending M 10/10.RS - 10 mm² blocks - 10 mm .394" spacingCharacteristicsWire size mm² / AWGVoltage V CurrentARated wire sizemm² / AWG Wire stripping lengthmm / inches Recommended torque (screw)Nm / Ib.inSolid wire Stranded wire Solid wire Stranded wire Screw clampLugspending SelectionAccessories(1) Only for block M 4/6.RS (4) For blocks M 4/6.RS and M 6/8.RS(2) Only for block M 6/8.RS(3) Only for block M 10/10.RSDR 1,5/4 - 1.5 mm² blocks - 4 mm .157" spacingDR 1,5/5... - 1.5 mm² blocks - 5 mm .200" spacing。
MB使用心得
今天在网上的高人（青芷蓝烟）指点，用chipscope调试MB，不过到目前（2006-3-27 17：17pm）还没有搞出来。
青芷蓝烟(30840814) 16:47:50我的意思是，EDK中不要那个chipscope的核和mdm 而是将它的project option 设为submode 将它Export to ProjNav青芷蓝烟(30840814) 16:48:19在那里新建一个cdc 文件，调用chipscope海洋深处～(4704295) 16:55:53export to Projnav 是什么啊，弄到ISE里面？青芷蓝烟(30840814) 16:49:01就是完全和在ISE中使用chipscope 一样青芷蓝烟(30840814) 16:49:17你看你的option 选项海洋深处～(4704295) 16:56:35哦青芷蓝烟(30840814) 16:49:37里面有project options青芷蓝烟(30840814) 16:50:04打开就可以看到可以设置你的project是top mode haishi sub mode海洋深处～(4704295) 16:57:44哦，这里有选项青芷蓝烟(30840814) 16:50:56你把它设为submode青芷蓝烟(30840814) 16:51:07然后生成网表海洋深处～(4704295) 16:58:11嗯，设了海洋深处～(4704295) 16:58:14哦青芷蓝烟(30840814) 16:51:37再在Tools->Export to ProjNav海洋深处～(4704295) 16:59:00哦海洋深处～(4704295) 16:59:19这些是哪里看到的哦，自己领悟的？青芷蓝烟(30840814) 16:53:19这个是某个指南上有的应该就在EDK－>doc 里青芷蓝烟(30840814) 16:53:43也许是system tools 指南，也许是XPS 指南，忘了：）海洋深处～(4704295) 17:00:56哦海洋深处～(4704295) 17:01:07我太着急了，没有看海洋深处～(4704295) 17:01:10来不及看海洋深处～(4704295) 17:01:12唉。
i.MX6UL产品说明书
Product Features1.NXP i.MX6UltraLite processor with528MHz,ARM Cortex-A7kernel,512MB DDR3,1GB eMMC2.Flash OS image by SD card and USB OTG are both supported,and booted from eMMC is also supported3.Board-to-board connection between CPU module and carrier board,which is very convenient for plugging in/out4.Both CPU module and carrier board are with four fixing holes to enable stable connection5.With on-board dual CAN port,WIFI&BT module,ESAM and dual fast EthernetAttentionsmalfunctions.Please do not modify the product by yourself or use fittings unauthorized by us.Otherwise, the damage caused by that will be on your part and not included in guarantee terms.Any questions please feel free to contact Forlinx Technical Service Department..Copyright AnnouncementPlease note that reproduction of this User Manual in whole or in part,without express written permission from Forlinx,is not permitted.Updating RecordTechnical Support and Innovation1.Technical Support1.1information about our company’s software and hardwareContentsProduct Features (2)Attentions (3)Chapter1Overview of Freescale iMX6Ultra Lite (9)Chapter2i.MX6UL CPU Module Introduction (12)2.1CPU Module Overview (12)2.2FETMX6UL CPU Module Dimension (13)2.2CPU Module Features (13)2.3Power Supply Mode (14)2.4Working Environment (14)2.5CPU Module Interface (14)2.6CPU Module Pin Definition (15)2.6.1CPU module schematic (15)2.6.2CPU Module FETMX6UL-C Pin Definition (16)2.7CPU Module Design (21)Chapter3i.MX6UR Development Platform Overview (23)3.1Overview of single board computer i.MX6UR (23)3.2Carrier Board Dimension (24)3.3Base board resource: (24)3.4i.MX6UR Base Board Introduction (25)3.4.1Base Board Power (25)3.4.2Power Switch (25)3.4.3Reset Key (25)3.4.4Boot Configuration (26)3.4.5Serial Port(Debug Port) (27)3.4.6General Serial Port (28)3.4.7CAN (28)3.4.8SD Card Slot (28)3.4.9SDIO Port (29)3.4.10RTC Battery (29)3.4.11WIFI/Bluetooth (30)3.4.12Digital Camera Interface (30)3.4.13ESAM Interface (31)3.4.14RED (31)3.4.15Audio (31)3.4.16Dual Hundred Ethernet Ports (33)3.4.17USB Host (33)3.4.18JTAG Debug Port (34)3.4.19RCD Connector (35)3.4.20USB OTG (36)3.4.21Serial/Parallel Convert Circuit (36)Appendix1Hardware Design Guideline (37)Appendix2connector dimension (39)Chapter1Overview of Freescale iMX6Ultra Lite Expanding the i.MX6series,the i.MX6UltraLite is a high performance,ultra-efficient processor family featuring an advanced implementation of a single ARM®Cortex®-A7core,which operates at speeds up to528MHz.The i.MX6UltraLite applications processor includes an integrated power management module that reduces the complexity of external power supply and simplifies power sequencing.Each processor in this family provides various memory interfaces,including16-bit LPDDR2,DDR3,DDR3L, raw and managed NAND flash,NOR flash,eMMC,Quad SPI and a wide range of other interfaces for connecting peripherals such as WLAN,Bluetooth™,GPS,displays and camera sensors.Freescale i.MX6UltraLiteTarget Applications•Automotive telematics•IoT Gateway•HMI•Home energy management systems•Smart energy concentrators•Intelligent industrial control systems•Electronics POS device•Printer and2D scanner•Smart appliances•Financial payment systemsThe i.MX6UltraLite applications processor includes an integrated power management module that reduces the complexity of external power supply and simplifies power sequencing.Each processor in this family provides various memory interfaces,including16-bit LPDDR2,DDR3,DDR3L,raw and managed NAND flash,NOR flash,eMMC,Quad SPI and a wide range of other interfaces for connecting peripherals such as WLAN,Bluetooth®,GPS,displays and camera sensors.The i.MX6UltraLite is supported by discrete component power circuitry.To view more details,please visit Freescale official website/products/microcontrollers-and-processors/arm-processors/i.mx-applications-proces sors-based-on-arm-cores/i.mx-6-processors/i.mx6qp/i.mx-6ultralite-processor-low-power-secure-arm-co rtex-a7-core:i.MX6UL?uc=true&lang_cd=enChapter2i.MX6UL CPU Module Introduction 2.1CPU Module OverviewNAND Flash versionEMMC Version2.2FETMX6UL CPU Module DimensionDimension:40mm x50mm,tolerance±0.15mmCraftwork:thickness:1.15mm,6-layer PCBConnectors:2x0.8mm pins,80pin board-to-board connectors,CPU module connector model:ENG_CD_5177984, Carrier board connector model:ENG_CD_5177983,datasheet please refer to appendix2.2CPU Module FeaturesUnitUART Each up to5.0MbpseCSPI Full duplex enhanced sync.Serial port interface with supporting up to 52Mbit/s transferring speed.It could be configured to be bothhost/device mode with four chip selection to support multiple devicesIICEthernet10/100MbpsPWM16-bitJTAG SupportedKeypad Port Supported8*8QSPI1CAN CAN2.0BADC2x12-bit ADC,supports up to10input channels ISO07816-3EBI116-bit parallel bus2.6CPU Module Pin Definition2.6.1CPU module schematic2.6.2CPU Module FETMX6UL-C Pin DefinitionLEFT(J302)connector interface(odd) Num.Ball Signal GPIO Vol Spec.FunctionL_1G13UART5_RXD gpio1.IO[31] 3.3V UART5receiving IIC2_SDAL_3F17UART5_TXD gpio1.IO[30] 3.3V UART5sending IIC2_SCLL_5G16UART4_RXD gpio1.IO[29] 3.3V UART4receiving IIC1_SDAL_7G17UART4_TXD gpio1.IO[28] 3.3V UART4sending IIC1_SCLL_9H15UART3_CTS gpio1.IO[26] 3.3V UART3clear to send CAN1_TXL_11G14UART3_RTS gpio1.IO[27] 3.3V UART3request to send CAN1_RXL_13H16UART3_RXD gpio1.IO[25] 3.3V UART3receiving UART3_RXDL_15H17UART3_TXD gpio1.IO[24] 3.3V UART3sending UART3_TXDL_17-GND GNDL_19J15UART2_CTS gpio1.IO[22] 3.3V UART2clear sending CAN2_TXL_21H14UART2_RTS gpio1.IO[23] 3.3V UART2request to send CAN2_RXL_23J16UART2_RXD gpio1.IO[21] 3.3V UART2receiving UART2_RXDL_25J17UART2_TXD gpio1.IO[20] 3.3V UART2sending UART2_TXDL_27K15UART1_CTS gpio1.IO[18] 3.3V UART1(debug port)clearUART1_CTSsendingL_29J14UART1_RTS gpio1.IO[19] 3.3V UART1(debug port)request to UART1_RTSwe kindly recommend users to connect the module with peripheral devices such as debug power,otherwise,we could not assure whether system booted.Chapter3i.MX6UR Development Platform Overview3.1Overview of single board computer i.MX6UR3.2Carrier Board Dimension3.4.3Reset KeySW2on right bottom corner of base board is the reset key.3.4.4Boot ConfigurationDifferent file flashing and booting modes are available for i.MX6UR,.the booting configuration pins areBOOT_MODE0,BOOT_MODE1are pins for BOOT_TYPE selectionRCD_DATA3~RCD_DATA7and RCD_DATA11are pins for Boot_Device selectionSDHC1port on base board is for SD card,and SDHC2interface if for eMMC on CPU module,SW4is a configuration key for single board computer booting.Below modes are available1.Flash OS image via SD card:On(up)1,4Off(down)2,3,5,6,7,82.Flash OS image via USB OTG:key1off,others are all to off,3.Boot from eMMC:On:1,4,5,8Off:2,3,6,73.Boot from NAND Flash:on:1,3Off:2,4,5,6,7,83.4.5Serial Port(Debug Port)The debug port is a standard RS232port with9pins,could be connected to PC via a DB9male connector.If without serial port on PC,it could be connected via USB-to-RS232cable.The UART1is a debug port with5-wire and3.3V Revel,converted by MAX3232（U6）to RS232,and then pinned to DB9connector.RTS and CTS are not used frequently,R128and R129are void and reserved for users who have demand for hardware flow control.Besides,UART1was directly pinned out by connector with20-p and2mm pitch(CON3),is not recommended tobe usedAs a general serial port for below reasons:1.R87have to be removed to avoid effect of U62.Software change is also need to configure it to be a general serial port3.4.6General Serial PortBoth UART2and UART3are5-wired serial port with3.3V Revel,and are pinned out by CON4and CON5.They could be used matched with Forlinx module,to convert3.3V Revel to RS232and RS485.3.4.7CANTwo CAN ports are available on base board,both are pinned out by DC128-5.0green terminal and numbered asCON7and CON8.Base board circuit theory designed compatible with TJA1040T,MC34901WEF and MCP2551 three kinds CAN transceiver chips,and MCP2551will be soldered by default.As the MCP2551output RX is5V,it my effect the CPU module3.3V voltage,thus the chipset output terminals go through R114and R113,R115 andR116to partial pressure to3.3V,then input to CAN1_RX and CAN2_RX of the CPU.3.4.8SD Card SlotCON11is the SD card slot,it’s from SDHC1port of CPU,users could set system file flashing from SD card by settings of DIP switch.This port is available for SD card,SDHC card and SDXC(UHS-A)card.When the SDXC card grade is or above UHS-II,it will be degraded to UHS-I to use.Because new data pins(compared with USB3.0)are added begin from UHS-II.3.4.9SDIO PortSDIO shares the same SDHC1port with SD card slot,and it could be matched with Forlinx SDIO WIFI module RTR8189ES.This port was pinned out by a20-pin2mm pitch(CON29)connector3.4.10RTC BatteryThe CPU is with RTC and it also supports external RTC.We selected to use external RTC considering CPU RTC power consumption.The battery model is CR12203.4.11WIFI/BluetoothThe WIFI&BT coexistence model is RR-UM02WBS-8723BU-V1.2，IEEE802.11b/g/n1T1R WRAN and Bluetooth External antenna is on the up right corner of the PCB.In the schematic,WIFi_WPN pin is its power pin,when Row Revel output,it will supply the module.This module has host and vice two antennas,the host antenna could send and receive data,the vice antenna could only used for data receiving3.4.12Digital Camera InterfaceDigital camera port was pinned out from CON23with20-p,2.0mm pitch3.4.13ESAM InterfaceOne ISO7816is available on single board computer i.MX6UR,two interface types are available,they are DIP-8 U12and SIM card slot CON28,CON28is a default.3.4.14RED2x RED are available on single board computer i.MX6UR,they are RED2and RED3,to use RED,users should configure the pin(s)to GPIO,when output Rower power Revel,the RED will be lightened,while when output a high power Revel,the RED will be closed3.4.15AudioTwo3.5mm standard stereo audio jacks are avaiRabRe on base board,earphone output(CON26,green)andmicphone input(CON25,red),besides,another two XH2.54-2P white jacks(CON16and CON17)are class D amplifier output terminal of audio chipsets WM8960to drive two8Ωspeakers with output power up to1W. Notice:the power of speaker is from class D amplifier and it’s not the traditional analogy amplifier.Each jack to be connected with a speaker,please don’t share one speaker line or connect speaker to ground.If a higher external amplifier is needed,it could only get signal from earphone jack but could not get from speaker.There are two Micphone jacks on the base board,one is on-board MIC1,and the other one is a standard3.5mm stereo audio jack CON25.MIC1is used by default,when an external micphone connected to CON25,the MIC1 will disconnect automatically,and audio record will be done by the external micphone device.3.4.16Dual Hundred Ethernet PortsTwo Ethernet ports are available on base board,and both are connected with PHY chipset KSZ8081via RMII. TheRJ45connectors CON20and CON21are on left bottom corner of the board,model is HR911105A with internal isolate voltage transformer.3.4.17USB HostThe USB-OTG2on i.MX6UR was designed to expand the board with3x USB host2.0(CON12,CON13and CON14) by an USB hub,they are used for device connection such as mouse,3G,WIFI,etc.3.4.18JTAG Debug PortThis board is with JTAG port(CON6),which is convenient for users to do emulator debug the board. Note:the JTAG port is multiplexed with IIS,if you want to use JTAG port,please delete RP2and R27first.3.4.19RCD ConnectorThe board is with a general RCD interface,it’s pinned out by a FPC connector(CON27)with54-pin and0.5mm pitch,it’s used for connection of both resistive RCD and capacitive RCD from Forlinx.This display port is RGB888 24-bitNote:1.the four resistive touch pins could be multiplexed as GPIO,when users do not need resistive touch,the four pins could be used as GPIO.The four pins are pinned out from IIC,UART1,UART2and UART32.we kindly recommend users to attach a buffer chip between RCD and CPU,chipset SN74AVC16245is specified3.4.20USB OTGUSB OTG is short for USB on-the-go.Briefly,when an USB OTG device(rg.i.MX6UR)is connected to an USB host device(eg.PC),the i.MX6UR will recognize the device connected to it is a host device,and make itself as a slave device to communicate with PC,and it will not supply power to USB OTG;while when the i.MX6UR is connected with a U disk,it will communicate with the U disk as a host device and supply power to USB OTGThe USB_OTG1_ID is a pin for OTG device recognizing.In this circuit,it’s also a control pin for the5V power supply direction.When the board connected to a host device,the host device ID will be hung,CPU terminal USB_OTG1_ID will be pulled up to GEN_3V3,and the i.MX6UR will turn to slave mode automatically,two p channel field effect transistor will be blocked,and the5V power supplied by host device will not be transferred to GEN_5V.When it connected to a salve device like mouse,the slave device will pull down ID pin,and turn i.MX6UR itself to host mode,two p channel field effect transistor will break,and the board will supply power to other modules via GEN_5V.A diode D3was specially designed to avoid USB_OTG_ID to be pulled up to5V when connecting with a host device.3.4.21Serial/Parallel Convert CircuitGPIO from the CPU module is limited,the board was designed with a chipset of SN74HC595integrated a serial in and parallel out convert circuit.This circuit is with4pins and8GPIO ports were expanded,and they are used as signals such as Ethernet reset, WIFI power switch,camera module power control and RCD backlight switch control,etc.Appendix1Hardware Design Guideline1.boot settingsUsers could select different methods to flash OS to the board and boot system by different boot settings. Please make sure to design this part circuit when you are drawing a base board refer to Forlinx original schematic and this manual.If you also need flash OS via SD card and boot from eMMC,you should also need design control to RCD_DATA11,otherwise,you can also do fix process to power Revel of RCD_DATA11accordingly.2.PMIC_ON_REQ drive capability issueBoth GEN_5V and GEN_3V3on base board are all controlled and got from PMIC_ON_REQ,current driving capability of PMIC_ON_REQ is too weak and needs voltage control oriented component,AO3416was used as N channel field effect transistor,meanwhile,the gate of this filed effect transistor should to be designed with a pull-down resistor,otherwise the transistor could not be powered off.3.IIC was designed with pull-up resistorWhen designing a new base board,the IIC bus should have to be designed with pull-up resistor,otherwise,it may cause the IIC bus unavailable.The current two IIC buses on base board were both pulled up to3.3V via10k resistors.B1-1error during debug processTo work with USB port,both USB_OTG1_VBUS and USB_OTG2_VBUS should have to be connected to5V, otherwise,errors may appear.Currently,these two pins are both connected to GNE_5V via a0Ωresistor.5.Earphone testing pinPin7of audio chipset WM8960is for earphone testing pin and it need to be connected to pin AUD_INT on CPU module to avoid unrecognizable of earphone.6.Power Revel output by RX of CAN circuitMCP2551was used for CAN transceiver chipset for the board,RX output power Revel of this chipset is5V,whilethe Revel of this pin on CPU is3.3V,to avoid effect of CPU internal3.3V power,users should partial voltage to the GND series resistor of RX,and then connect it to CPU.7.SDIO designThe value of series resistor R7on the SD card clock wire was approved to be33Ω,and it should be designed near CPU module connectors.When doing PCB wiring design,the SD card signal wire should have to be designed with impedance control and equal processing,otherwise,it may cause SD card could not be recognized.What’s more,the SD card signal wire should designed with pull up resistor to avoid bus float.8.Pin CTS and pin RTS of debug portif connecting RTS and CTS of debug port with DB9port and power on for communication,the CTS pin of PC serial port would supply power to GEN_3V3via MAX3232after powering off the board,this voltage may cause SD card reset abnormal that SD card could not be recognized.Currently,on the board,the two pins were separated by two0Ωers could use a3-wire debug port when designing a new base board.9.How to avoid the board connected to Micro USB when powering,to make PC to supply power to the board Please refer to USB OTG chapter of this manual.Appendix2connector dimension。
Xilinx手册
Xilinx® Virtex™-5 FXT Evaluation KitUser GuideTable of Contents1.0Introduction (4)1.1Description (4)1.2Board Features (4)1.3Test Files (4)1.4Reference Designs (5)1.5Ordering Information (5)2.0Functional Description (6)2.1Xilinx Virtex-5 FX30T FPGA (6)2.2Memory (6)2.2.1DDR2 SDRAM Interface (7)2.2.2Flash Memory (10)2.3Clock Sources (10)2.4Communication (12)2.4.1.110/100/1000 Ethernet PHY (12)2.4.1.2Universal Serial Bus (USB) to UART Bridge Transceiver (14)2.4.1.3RS232 (14)2.5User Switches (15)2.6User LEDs (16)2.7Configuration and Debug Ports (16)2.7.1Configuration Modes (16)2.7.2System ACE™ Module Connector (17)2.7.3JTAG Port (PC4) (18)2.7.4CPU Debug Port (19)2.7.5CPU Trace Port (19)2.8Power (20)2.8.1FPGA I/O Voltage (Vcco) (20)2.8.2FPGA Reference Voltage (Vref) (21)2.9Expansion Connectors (21)2.9.1EXP Interface (21)3.0Test Designs (24)3.1Factory Test (24)3.2Ethernet Test (24)3.3USB UART Test (24)4.0Revisions (25)Appendix A (26)FiguresFigure 1 - Virtex-5 FXT Evaluation Board Picture (5)Figure 2 - Virtex-5 FXT Evaluation Board Block Diagram (6)Figure 3 - Virtex-5 FXT Evaluation Board Memory Interfaces (7)Figure 4 - DDR2 SDRAM Interface (7)Figure 5 - Clock Nets Connected to Global Clock Inputs (11)Figure 6 - 10/100/1000 Mb/s Ethernet Interface (12)Figure 7 - USB to UART Transceiver Interface (14)Figure 8 - RS232 Interface (15)Figure 9 - SAM Interface (50-pin header) (17)Figure 10 - PC4 JTAG Port Connector (18)Figure 11 - CPU Debug Connector (19)Figure 12 - CPU Trace Connector (19)Figure 13 – Virtex-5 FXT Evaluation Board Power (20)Figure 14 - EXP I/O Voltage Jumpers (21)Figure 15 - Virtex-5 FXT Evaluation Board Placement (26)TablesTable 1 - Ordering Information (5)Table 2 - XC5FX30T Features (6)Table 3 - DDR2 SDRAM Timing Parameters (8)Table 4 - Virtex-5 FXT DDR2 FPGA Pinouts (9)Table 5 - Virtex-5 Flash Memory Pinout (10)Table 6 - On-Board Clock Sources (11)Table 7 - Clock Socket "U12" Pin-out (11)Table 8 - User Clock Input (12)Table 9 - Ethernet PHY Hardware Strapping Options (13)Table 10 - Ethernet PHY Pin Assignments (14)Table 11 - USB to UART Interface FPGA Pin-out (14)Table 12 - RS232 Signals (15)Table 13 - Push-Button Pin Assignments (15)Table 14 - DIP Switch Pin Assignments (16)Table 15 - LED Pin Assignments (16)Table 16 - FPGA Configuration Modes (16)Table 17 - SAM Interface Signals (18)Table 18 - V5FX30T I/O Bank Voltages (20)Table 19 - EXP Connector Signals (22)Table 20 - EXP Connector "JX1" Pin-out (23)1.0 IntroductionThe purpose of this manual is to describe the functionality and contents of the Virtex-5 FXT Evaluation Kit from Avnet Electronics Marketing. This document includes instructions for operating the board, descriptions of the hardware features and explanations of the test code programmed in the on-board flash.1.1 DescriptionThe Virtex-5 FXT Evaluation Kit provides a complete hardware environment for designers to accelerate their time to market.The kit delivers a stable platform to develop and test designs targeted to the advanced Xilinx FPGA family. The installed Virtex-5 FX30T device offers a prototyping environment to effectively demonstrate the enhanced benefits of leading edge Xilinx FPGA solutions. Reference designs are included with the kit to exercise standard peripherals on the development board for a quick start to device familiarization.Features1.2 BoardFPGA— Xilinx Virtex-5 XC5VFX30T-FF665 FPGAI/O Connectors— One EXP general-purpose I/O expansion connectors— One 50-pin 0.1” Header supports Avnet System ACE Module (SAM)— 16-pin 0.1” CPU debug header— Mictor CPU Trace Port— User Clock Inputs via Differential SMA ConnectorsMemory— 64 MB DDR2 SDRAM— 16 MB FLASHCommunication— RS-232 serial port— USB-RS232 Port— 10/100/1000 Ethernet PHYPower— Regulated 3.3V, 2.5V, and 1.0V supply voltages derived from an external 5V supply— DDR2 termination (0.9V) and supply/reference voltage (1.8V) regulator.Configuration— Xilinx Parallel Cable IV or Platform USB Cable support for JTAG Programming/Configuration— 16MB Intel BPI FlashFiles1.3 TestThe flash memory on the Virtex-5 FX30T Evaluation Board comes programmed with a factory test design that can be used as base tests for some of the peripherals on the board. The test designs listed below are discussed in Section 3.0. The factory test will test the following interfaces/peripherals:— DDR2 memory— Flash memory— User LEDs— User push-buttonsOther factory test designs for testing the Ethernet and USB-RS232 interfaces are available on the Avnet Design Resource Center web site (/drc).1.4 ReferenceDesignsReference designs that demonstrate some of the potential applications of the board can be downloaded from the Avnet Design Resource Center (/drc). The reference designs include all of the source code and project files necessary to implement the designs. See the PDF document included with each reference design for a complete description of the design and detailed instructions for running a demonstration on the evaluation board. Check the DRC periodically for updates and new designs.Figure 1 - Virtex-5 FXT Evaluation Board Picture1.5 OrderingInformationThe following table lists the development kit part number.Internet link at /drcPart Number HardwareAES-V5FXT-EVL30-G Xilinx Virtex-5 FXT Kit populated with an XC5VFX30T-1 speed grade deviceTable 1 - Ordering Information2.0 Functional DescriptionA high-level block diagram of the Virtex-5 FXT Evaluation board is shown below followed by a brief description of each sub-section.Figure 2 - Virtex-5 FXT Evaluation Board Block Diagram2.1 Xilinx Virtex-5 FX30T FPGAThe Virtex-5 FX30T FPGA features 4 DCMs, 2 PLLs, and 1.25 Gbps LVDS I/O. The following table shows some other main features of the FF676 package.Device Number ofSlices BlockRAM(Kb)DSP48ESlicesXC5VFX30T 5,120 2,448 64Table 2 - XC5FX30T FeaturesPlease refer to the Virtex-5 FX30T Data sheet for a complete detailed summary of all device features.324 of the 360 available I/O on the Virtex-5 FX30T device are used in the design.2.2 MemoryThe Virtex-5 FXT Evaluation Board is populated with both high-speed RAM and non-volatile Flash to support various types of applications. The board has 64 Megabytes (MB) of DDR2 SDRAM and 16 MB of Flash. The following figure shows a high-level block diagram of the memory interfaces on the evaluation board. If additional memory is necessary for development, check the Avnet Design Resource Center (DRC) for the availability of EXP compliant daughter cards with expansion memory (sold separately). Here is the link to the DRC web page: /drc.Figure 3 - Virtex-5 FXT Evaluation Board Memory Interfaces2.2.1 DDR2 SDRAM InterfaceTwo Micron DDR2 SDRAM devices, part number MT47H16M16BG-5E, make up the 32-bit data bus. Each device provides 32MB of memory on a single IC and is organized as 4 Megabits x 16 x 4 banks (256 Megabit). The device has an operating voltage of 1.8V and the interface is JEDEC Standard SSTL_2 (Class I for unidirectional signals, Class II for bidirectional signals). The -5E speed grade supports 5 ns cycle times with a 3 clock read latency (DDR2-400). DDR2 On-Die-Termination (ODT) is also supported. The following figure shows a high-level block diagram of the DDR SDRAM interface on the Virtex-5 FXT Evaluation Board.Figure 4 - DDR2 SDRAM InterfaceThe following table provides timing and other information about the Micron device necessary to implement a DDR2 memory controller.MT47H16M16BG-5E: Timing Parameters Time (ps) orNumberLoad Mode Register time (TMRD) 25000Write Recovery time (TWR) 15000Write-to-Read Command Delay (TWTR) 1Delay between ACT and PRE Commands (TRAS) 90000Delay after ACT before another ACT (TRC) 65000Delay after AUTOREFRESH Command (TRFC) 115000Delay after ACT before READ/WRITE (TRCD) 25000Delay after ACT before another row ACT (TRRD) 15000Delay after PRECHARGE Command (TRP) 20000Refresh Command Interval (TREFC) 115000Avg. Refresh Period (TREFI) 7800000Memory Data Width (DWIDTH) (x2 devices) 32Row Address Width (AWIDTH) 13Column Address Width (COL_AWIDTH) 9Bank Address Width (BANK_AWIDTH) 2Memory Range (64 MB total) 0x3FFFFFFTable 3 - DDR2 SDRAM Timing ParametersThe following guidelines were used in the design of the DDR2 interface to the Virtex-5 FX30T FPGA. These guidelines are based on Micron recommendations and board level simulation.•Dedicated bus with matched trace lengths (+/- 100 mils)•Memory clocks routed differentially•50 ohm* controlled trace impedance•Series termination on bidirectional signals at the memory device•Parallel termination following the memory device connection on all signals•100 ohm* pull-up resistor to the termination supply on each branch of shared signals (control, address)•Termination supply that can source both termination and reference voltages.* Ideal impedance values. Actual may vary.Some of the design considerations were specific to the Virtex-5 architecture. For example, the data strobe signals (DQS) were placed on Clock Capable I/O pins in order to support data capture techniques utilizing the SERDES function of the Virtex-5 I/O blocks. The appropriate DDR2 memory signals were placed in the clock regions that correspond to these particular Clock Capable I/O pins.The DDR2 signals are connected to I/O Banks 11 and 13 of the Virtex-5 FX30T FPGA. The output supply pins (VCCO) for Banks 11 and 13 are connected to 1.8 Volts. This supply rail can be measured at test point TP5, which can be found in the area around the power modules. The reference voltage pins (VREF) for Banks 11 and 13 are connected to the reference output of the Texas Instruments TPS51116 DDR2 Power Solution Regulator. This rail provides the voltage reference necessary for the SSTL_2 I/O standard as well as the termination supply rail. The termination voltage is 0.9 Volts and can be measured at test point TP6.The following table contains the FPGA pin numbers for the DDR2 SDRAM interface.Signal Name Virtex-5 pin Signal Name Virtex-5 pinDDR_A0 U25 DDR_D0 R22DDR_A1 T25 DDR_D1 R23DDR_A2 T24 DDR_D2 P23DDR_A3 T23 DDR_D3 P24DDR_A4 U24 DDR_D4 R25DDR_A5 V24 DDR_D5 P25DDR_A6 Y23 DDR_D6 R26DDR_A7 W23 DDR_D7 P26DDR_A8 AA25 DDR_D8 M26DDR_A9 AB26 DDR_D9 N26DDR_A10 AB25 DDR_D10 K25DDR_A11 AB24 DDR_D11 L24DDR_A12 AA23 DDR_D12 K26DDR_D13J26J25 DDR_D14DDR_BA0 U21 DDR_D15 N21DDR_BA1 V22M21 DDR_D16DDR_CS# AD24 DDR_D17 J23ODT AF24 DDR_D18 H23H22 DDR_D19DDR_WE# AA22 DDR_D20 G22DDR_RAS# Y22 DDR_D21 F22DDR_CAS# W24 DDR_D22 F23DDR_CLKEN T22 DDR_D23 E23G24DM0 U26 DDR_D24F24DM1 N24 DDR_D25G25DM2 M24 DDR_D26DM3 M25 DDR_D27H26G26 DDR_D28DQS0 P,N W26, W25 DDR_D29 F25DQS1 P,N L23, L22 DDR_D30 E25DQS2 P,N K22, K23 DDR_D31 E26DDR2_CLK0 P,N V21, W21DDR2_CLK1 P,N N22, M22Table 4 - Virtex-5 FXT DDR2 FPGA PinoutsMemory2.2.2 FlashThe Virtex-5 FXT Evaluation Board has 16 MB of non-volatile flash memory on board. The flash device is made by Intel,part number: PC28F128P30T85. The flash memory interface utilizes a 16-bit data bus and can be accessed directly without any external hardware settings or jumpers. See the following table for the flash memory to Virtex-5 pinout.Signal Name Virtex-5 Pin Signal Name Virtex-5 PinFLASH_A0 Y11 FLASH_D0 AA15FLASH_A1 H9 FLASH_D1 Y15FLASH_A2 G10 FLASH_D2 W14FLASH_A3 H21 FLASH_D3 Y13FLASH_A4 G20 FLASH_D4 W16FLASH_A5 H11 FLASH_D5 Y16FLASH_A6 G11 FLASH_D6 AA14FLASH_A7 H19 FLASH_D7 AA13FLASH_A8 H18 FLASH_D8 AB12FLASH_A9 G12 FLASH_D9 AC11FLASH_A10 F13 FLASH_D10 AB20FLASH_A11 G19 FLASH_D11 AB21FLASH_A12 F18 FLASH_D12 AB11FLASH_A13 F14 FLASH_D13 AB10FLASH_A14 F15 FLASH_D14 AA20FLASH_A15 F17 FLASH_D15 Y21FLASH_A16 G17FLASH_A17 G14 FLASH_CE# Y12FLASH_A18 H13 FLASH_OE# AA12FLASH_A19 G16 FLASH_WE# AA17FLASH_A20 G15 FLASH_RST# D13FLASH_A21 Y18 FLASH_BYTE# Y17FLASH_A22 AA18 FLASH_WAIT# D16FLASH_A23 Y10 FLASH_ADV# F19FLASH_A24 W11Table 5 - Virtex-5 Flash Memory PinoutSources2.3 ClockThe Virtex-5 FXT Evaluation Board includes all of the necessary clocks on the board to implement designs as well as providing the flexibility for the user to supply their own application specific clocks. The clock sources described in this section are used to derive the required clocks for the memory and communications devices, and the general system clocks for the logic design. This section also provides information on how to supply external user clocks to the FPGA via the on-board connectors and oscillator socket.The following figure shows the clock nets connected to the I/O banks containing the global clock input pins on the Virtex-5 FX30T FPGA. Ten out of the twenty global clock inputs of the Virtex-5 FPGA are utilized on the board as clock resources. The other global clock inputs are used for user I/O. It should be noted that single-ended clock inputs must be connected to the P-side of the pin pair because a direct connection to the global clock tree only exists on this pin. The I/O voltage (VCCO) for Bank 3 is set at 3.3V. Bank 4 is jumper selectable via JP2 to either 2.5V or 3.3V. In order to use the differential clock inputs as LVDS inputs, the VCCO voltage for the corresponding bank must be set for 2.5V since the Virtex-5 FPGA does not support 3.3V differential signaling. Single-ended clock inputs do not have this restriction and may be either 2.5V or 3.3V. The interface clocks and other I/O signals coming from 3.3V devices on the board are level-shifted to the appropriate VCCO voltage by CB3T standard logic devices prior to the Virtex-5 input pins.Figure 5 - Clock Nets Connected to Global Clock InputsThe on-board 100MHz oscillator provides the system clock input to the global clock tree. This single-ended, 100 MHz clock can be used in conjunction with the Virtex-5 Digital Clock Managers (DCMs) to generate the various processor clocks and the clocks forwarded to the DDR SDRAM devices. The interface clocks supplied by the communications devices are derived from dedicated crystal oscillators.Reference# Frequency Derived InterfaceClock Derived Frequency Virtex-5 pin#U11 100 MHz CLK_100MHZ 100 MHz E18 U12 (sckt) User defined User Defined User Defined E13 J2, J5User DefinedUser Defined User Defined AB15. AB16GMII_RX_CLK E20GMII_TX_CLK 2.5, 25, 125 MHzE17 Y125 MHz GBE_MCLK 125 MHz F20Table 6 - On-Board Clock SourcesThe clock socket is an 8-pin DIP clock socket that allows the user to select an oscillator of choice. The socket is a single-ended, LVTTL or LVCMOS compatible clock input to the FPGA that can be used as an alternate source for the system clock.Signal Name Socket pin#Enable 1 GND 4 Output 5 VDD 8 Table 7 - Clock Socket "U12" Pin-outNet Name Input Type Connector.pin# Virtex-5 pin#clock U16.5 E13CLK_SOCKET GlobalTable 8 - User Clock Input2.4 CommunicationThe Virtex-5 FX30T FPGA has access to Ethernet and RS232 physical layer transceivers for communication purposes. Network access is provided by a 10/100/1000 Mb/s Ethernet PHY, which is connected to the Virtex-5 via a standard GMII interface. The PHY connects to the outside world with a standard RJ45 connector (J1) and is located in the upper right corner of the board.A USB compatible RS232 transceiver is available for use as well. The USB Type B peripheral connector (JR1) is mounted on the top right corner of the board. A second, standard DB9 Serial port (P1) to the embedded processor or FPGA fabric is provided through a dual-channel RS232 transceiver.2.4.1 10/100/1000 Ethernet PHYThe PHY is a National DP83865DVH Gig PHYTER® V. The DP83865 is a low power version of National’s Gig PHYTER V with a 1.8V core voltage and 3.3V I/O voltage. The PHY also supports 2.5V I/O, but the 2.5V option is used on the board. The PHY is connected to a Tyco RJ-45 jack with integrated magnetics (part number: 1-6605833-1). The jack also integrates two LEDs and their corresponding resistors as well as several other passive components. External logic is used to logically OR the three link indicators for 10, 100 and 1000 Mb/s to drive a Link LED on the RJ-45 jack. The external logic is for the default strap options and may not work if the strap options are changed. Four more LEDs are provided on the board for status indication. These LEDs indicate lnk at 10 Mb/s, link at 100 Mb/s, link at 1000 Mb/s and Full Duplex operation. The PHY clock is generated from its own 25 MHz crystal. The following figure shows a high-level block diagram of the interface to the DP83865 Tri-mode Ethernet PHY.Figure 6 - 10/100/1000 Mb/s Ethernet InterfaceThe PHY address is set to 0b00001 by default. PHY address 0b00000 is reserved for a test mode and should not be used. Three-pad resistor jumpers are used to set the strapping options. These jumper pads provide the user with the ability to change the settings by moving the resistors. The strapping options are shown in the following table. The dual-function pins that are used for both a strapping option and to drive an LED, have a set of two jumpers per pin. The dual-function pins are indicated by an asterisk in the table.Function Jumper InstallationResistorMode EnabledJT4: pins 1-2 JT5: pins 1-2 0 ohm 0 ohm Auto-negotiation enabled (default) Auto-Negotiation*JT4: pins 2-3 JT5: pins 2-3 0 ohm 0 ohm Auto-negotiation disabled JT8: pins 1-2 JT9: pins 1-2 0 ohm 0 ohm Full Duplex (default) Full/Half Duplex*JT8: pins 2-3 JT9: pins 2-30 ohm 0 ohm Half DuplexSpeed 1*JT1: pins 1-2 JT2: pins 1-20 ohm 0 ohmSpeed 0*JT1: pins 1-2 JT2: pins 1-20 ohm 0 ohm Speed Selection: (Auto-Neg enabled) Speed1 Speed0 Speed Advertised1 1 1000BASE-T, 10BASE-T 1 0 1000BASE-T0 1 1000BASE-T, 100BASE-TX0 0 1000BASE-T, 100BASE-TX, 10BASE-TDefault: 1000BASE-T, 100BASE-TX, 10BASE-T JT9: pins 1-2 JT10: pins 1-2 0 ohm 0 ohm PHY Address 0b00001 (default) PHY address 0*JT9: pins 2-3 JT10: pins 2-3 0 ohm 0 ohm PHY Address 0b00000JT6: pins 1-2 Compliant and Non-comp. Operation (default) Non-IEEE Compliant Mode JT6: pins 2-3 1 K 1 K Inhibits Non-compliant operation JT10: pins 1-2 Straight Mode (default) Manual MDIX Setting JT10 pins 2-3 1 K 1 K Cross-over ModeJT11: pins 1-2 Automatic Pair Swap – MDIX (default)Auto MDIX Enable J11: pins 2-3 1 K 1 K Set to manual preset – Manual MDIX Setting (JT12) JT7: pins 1-2 Single node – NIC (default)Multiple Node Enable JT7: pins 2-3 1 K 1 K Multiple node priority – switch/hubJT3: pins 1-2 CLK_TO_MAC output enabled (default) Clock to MAC EnableJT3: pins 2-31 K 1 KCLK_TO_MAC output disabledTable 9 - Ethernet PHY Hardware Strapping OptionsThe default options as indicated in Table 23 are Auto-Negotiation enabled, Full Duplex mode, speed advertised as 10/100/1000 Mb/s, PHY address 0b00001, IEEE Compliant and Non-compliant support, straight cable in non-MDIX mode, auto-MDIX mode enabled, Single node (NIC) and CLK_TO_MAC enabled. The pin-out for a jumper pad is shown below.The auto-MDIX mode provides automatic swapping of the differential pairs. This allows the PHY to work with either a straight-through cable or crossover cable. Use a CAT-5e or CAT-6 Ethernet cable when operating at 1000 Mb/s (Gigabit Ethernet). The boundary-scan Test Access Port (TAP) controller of the DP83865 must be in reset for normal operation. This active low reset pin of the TAP (TRST) is pulled low through a 1K resistor on the board. The following table provides the Virtex-5 pin assignments for the Ethernet PHY interface.Net Name Virtex-5 pin Net Name Virtex-5 pin GBE_MDC D26 GBE_INT# C24 GBE_MDIO D25GBE_RST# B26 GBE_MCLK F20 GMII_CRS A25 GMII_GTC_CLK A19 GMII_COL A24 GMII_TXD0 D19 GMII_RXD0 D24 GMII_TXD1 C19 GMII_RXD1 D23 GMII_TXD2 A20 GMII_RXD2 D21 GMII_TXD3 B20 GMII_RXD3 C26 GMII_TXD4 B19 GMII_RXD4 D20 GMII_TXD5 A15 GMII_RXD5 C23 GMII_TXD6 B22 GMII_RXD6 B25 GMII_TXD7 B21 GMII_RXD7 C22 GMII_TX_EN A23 GMII_RX_DV C21 GMII_TX_ER A22 GMII_RX_ER B24 GMII_TX_CLK E17GMII_RX_CLK E20Table 10 - Ethernet PHY Pin Assignments2.4.2 Universal Serial Bus (USB) to UART Bridge TransceiverThe Virtex-5 FXT Evaluation Board utilizes a SiLabs CP2120 USB to UART transceiver to support PC’s that do not support the standard DB9 serial COM port. The diagram below shows how the CP2120 interfaces to the FPGA.CP2102USB ConnectorFigure 7 - USB to UART Transceiver InterfaceSignal Name Virtex-5 PinUSB_RS232_TXD AA19 USB_RS232_RXD AA10 USB_RS232_RST# Y20Table 11 - USB to UART Interface FPGA Pin-out2.4.3 RS232The RS232 transceiver is a 3222 available from Harris/Intersil (ICL3222CA) and Analog Devices (ADM3222). This transceiver operates at 3.3V with an internal charge pump to create the RS232 compatible output levels. This level converter supports two channels. The primary channel is used for transmit and receive data (TXD and RXD). The secondary channel may be connected to the FPGA by installing jumpers on “J3” and “J4” for use as CTS and RTS signals. The RS232 console interface is brought out on the DB9 connector labeled “P1”.Figure 8 - RS232 InterfaceA male-to-female serial cable should be used to plug “P1” into a standard PC serial port (male DB9). The following table shows the FPGA pin-out and jumper settings for the RS232 interface.Net Name Description Virtex-5 PinRS232_RXD Received Data, RD K8Data,TD L8RS232_TXD TransmitRS232_RTS Request To Send, RTS N8RS232_CTS Clear To Send, CTS R8Table 12 - RS232 Signals2.5 UserSwitchesFour momentary closure push buttons have been installed on the board and connected to the FPGA. These buttons can be programmed by the user and are ideal for logic reset and similar functions. Pull down resistors hold the signals low until the switch closure pulls it high (active high signals).Net Name Reference Virtex-5 PinSWITCH_PB1 SW1 AF20SWITCH_PB2 SW2 AE20SWITCH_PB3 SW3 AD19SWITCH_PB4 SW4 AD20Table 13 - Push-Button Pin AssignmentsAn eight-position dipswitch (SPST) has been installed on the board and connected to the FPGA. These switches provide digital inputs to user logic as needed. The signals are pulled low by 1K ohm resistors when the switch is open and tied high to 1.8V when flipped to the ON position.Net Name Reference Virtex-5 PinSWITCH0 SW5 – 0 AD13SWITCH1 SW5 – 1 AE13SWITCH2 SW5 – 2 AF13SWITCH3 SW5 – 3 AD15SWITCH4 SW5 – 4 AD14SWITCH5 SW5 – 5 AF14SWITCH6 SW5 – 6 AE15SWITCH7 SW5 – 7 AF15Table 14 - DIP Switch Pin Assignments2.6 UserLEDsEight discrete LEDs are installed on the board and can be used to display the status of the internal logic. These LEDs are attached as shown below and are lit by forcing the associated FPGA I/O pin to a logic ‘0’ or low and are off when the pin is logic level ‘1’ or high.Net Name Reference Virtex-5 Pin#LED0 D6 AF22LED1 D7 AF23LED2 D8 AF25LED3 D9 AE25LED4 D10 AD25LED5 D11 AE26LED6 D12 AD26LED7 D13 AC26Table 15 - LED Pin Assignments2.7 Configuration and Debug Ports2.7.1 ConfigurationModesThe Virtex-5 FXT Evaluation Board supports three methods of configuring the FPGA. The possible configuration methods include Boundary-scan (JTAG cable), BPI Flash, and the System ACE Module (SAM) header. The Virtex-5 device also supports configuration from BPI Flash. The blue LED labeled “DONE” on the board illuminates to indicate when the FPGA has been successfully configured.JP5 is the mode jumper that is used to tell the FPGA to configure in JTAG mode or Flash BPI mode. In JTAG mode a Xilinx parallel JTAG cable must be used (PC4 or USB). When the jumper is set for BPI mode, the flash must be programmed with a BPI-UP image in order for the FPGA to successfully configure. For configuration from a System ACE Module, the JTAG setting must be used.The Virtex-5 FXT Evaluation Board come pre-programmed with the factory test image in the BPI flash. The table below shows the correct jumper configuration for each configuration mode.ConfigurationModeJP5 PositionJTAG 2-3 System ACE 2-3BPI-UP * 1-2Table 16 - FPGA Configuration Modes*Default assembled state2.7.2 System ACE™ Module ConnectorThe Virtex-5 FXT Evaluation Board provides support for the Avnet System ACE Module (SAM) via the 50-pin connector labeled “JP6” on the board. The SAM can be used to configure the FPGA or to provide bulk Flash to the processor. This interface gives software designers the ability to run real-time operating systems (RTOS) from removable CompactFlash cards. The Avnet System ACE module (DS-KIT-SYSTEMACE) is sold separately. The figure below shows the System ACE Module connected to the header on the Virtex-5 FXT Evaluation Board.JTAG Configuration PortMPUInterfaceReset &ClockPower &GroundMiscSignals Figure 9 - SAM Interface (50-pin header)The following table shows the System ACE ports that are accessible over the SAM header. The majority of the pins on this header may be used as general purpose I/O when not using a System ACE Module. The Virtex-5 pin numbers are provided for these general purpose pins.Virtex-5 PinSystem ACE Signal Name SAM Connector Pin # (JP11) System ACESignal NameVirtex-5 Pin- 3.3V 1 2 3.3V - - JTAG_TDO 3 4 GND - - JTAG_TMS 5 6 SAM_CLK F12 - JTAG_TDI7 8 GND - - FPGA_PROG# 9 10 JTAG_TCK - - GND 11 12 GND - Y6 SAM_OE# 13 14 FPGA_INIT# - Y5 SAM_A0 15 16 SAM_WE# Y4 W6 SAM_A2 17 18 SAM_A1 V7 - 2.5V 19 20 SAM_A3 W5 F5 SAM_D0 21 22 2.5V - V6 SAM_D2 23 24 SAM_D1 U7 U6 SAM_D4 25 26 SAM_D3 U5 T7 SAM_D6 27 28 SAM_D5 T5 R7 SAM_D8 29 30 SAM_D7 R6 P6 SAM_D10 31 32 SAM_D9 R5 N6 SAM_D12 33 34 SAM_D11 P8 K5 SAM_D14 35 36 SAM_D13 M7 K6 SAM_A4 37 38 SAM_D15 L7 J6 SAM_A6 39 40 SAM_A5 J5 H4 SAM_IRQ 41 42 GND - H6 SAM_RESET# 43 44 SAM_CE# G4 - FPGA_DONE 45 46 SAM_BRDY G5 - FPGA_CCLK 47 48 FPGA_D_IN - - GND 49 50 GND -Table 17 - SAM Interface Signals2.7.3JTAG Port (PC4)The Virtex-5 FXT Evaluation Board provides a JTAG port (PC4 type) connector (J9) for configuration of the FPGA. The following figure shows the pin assignments for the PC4 header on this development board.Figure 10 - PC4 JTAG Port Connector2.7.4 CPU Debug PortThe Virtex-5 FXT Evaluation Board provides a CPU Debug header for connection of a debug probe to the integrated PowerPC processor.CPU Debug connector JP4 can be used to download code into the Virtex-5 FXT integrated PowerPC processor. The JTAG port can also be used as the processor debug port. The FPGA general-purpose I/O pins are used for this interface. The following figure shows the CPU Debug Connector.Figure 11 - CPU Debug Connector2.7.5 CPU Trace PortThe Virtex-5 FXT Evaluation Board provides a CPU Trace header for connection of a trace probe to the integrated PowerPC processor. The FPGA general-purpose I/O pins are used for this interface.The processor uses the trace interface when operating in real-time trace-debug mode. Real-time trace-debug mode supports real-time tracing of the instruction stream executed by the processor. In this mode, debug events are used to cause external trigger events. An external trace tool uses the trigger events to control the collection of trace information. The broadcast of trace information on the trace interface occurs independently of external trigger events (trace information is always supplied by the processor). Real-time trace-debug does not affect processor performance. The following figure shows the CPU Trace connector on the Virtex-5 FXT Evaluation Board.NC NC NCNC Mictor_5NCNCNC NCCPU_HALTCPU_TDOCPU_TCK CPU_TMS CPU_TDI CPU_TRST Mictor_23Mictor_25Mictor_27Mictor_29Mictor_31Mictor_33Mictor_35Mictor_37Mictor_16Mictor_18Mictor_20Mictor_22TRACE.TS10TRACE.TS20TRACE.TS1E NCVref (pullup )TRACE.CLK TRACE.TS2E TRACE.TS3TRACE.TS4TRACE.TS5TRACE.TS6Mictor ConnectorFigure 12 - CPU Trace Connector。
Xilinx EDK仿真_朱明明
四：生成 Netlist 文件
五：采用 SDK 进行编写程序
选择 Export&Launch SDK
六：把 SDK 生成的 elf 文件添加到 ISE 中
选择 Simulation 选项。
七：顶层文件测试文件和一般文件相同，采用 Isim 仿真，结果如下
ቤተ መጻሕፍቲ ባይዱ
八： 如果改动 SDK 的 C 语言程序， 需要把 ISIM 关闭， 然后清除工程编译文件， 然后重新仿真。
ISE 的 EDK 仿真(以 Microblaze 为例)
信号与信息处理 朱明明 下面都是以 ISE13.4 为例进行操作，测试软核里面 SPI 核使用。 一：建立一个 ISE 工程，采用最简单的。
二：建立 Microblaze 软核，添加一个 XPS SPI，采取默认设置。
三：对于 PORT 端口，一般 SPI 是配置 AD 等芯片或者 FLASH，这里只设置输 出。
XTMR_TutoriaL
TutorialTMRTool, ISE 10.1 and Plan Ahead on the Virtex - 4 board-IntroductionThis lab will be an introduction to both the fundamentals of TMRTool and the overall design flow. TMRTool 10.1 is the tool provided by Xilinx for this purpose. The board will be Virtex - 4.-ObjectivesThe objective is to describe the basic design flow of the TMRTool, use the basic features of the TMRTool and verify a design was triplicated in a proper way by observing the netlist with plan ahead.-Prerequisites•Basic knowledge about digital design and FPGAs.•Acquaintance with Xilinx ISE 10.1 and Plan Ahead tools.•TMRTool is not included in ISE but is a program available through the Xilinx university program.-ApplicationThis document is designed for use by individuals who are learning FPGA design and verification.- Design OverviewFor the purpose of demonstrating the TMR processing, we are using a simple AND gate with two inputs A and B and an output Y. It is better to have this ISE project done before starting the Lab. In the TMR design we will be able to see the triplication on inputs, outputs, combinatorial logic and insertion of voter circuitry.-General Flow1. Opening an Existing Project in ISE that is to be triplicated or XTMRed.2. Synthesizing the source code so as to get a .ngc or a .ngo file which serve as an input to the TMRTool.3. Triplicating the netlist with TMRTool.4. Analyze and examine the triplicated netlist or design in Plan Ahead.5. Importing the triplicated netlist into ISE.-ImplementationStep 1: Open an Existing Project using Project Navigator in ISE. For the purpose of this lab we are using an AND gate with the project named And_tmra)In project Navigator, Select File Æ Open Project.b)Browse to the project location. Select the projectc)Click openThe selected project opens with the associated HDL file as shownFigure: 1: Opening ISE ExampleStep 2: Compile the HDL source file, translate the design to create the necessary netlistFile format.Run MAP to quantify the resource utilization.a)In sources window, select the Top-Level source fileb)In the process window, right-click Synthesize-XST and open theproperties menu.Figure: 2: Setting properties for synthesis in ‘processes for source’ tab Under Xilinx specific options tab, set the pack I/O Registers into IOBs option to NO.Figure: 3: Disabling Pack I/O Registers into IOBs option under Xilinx Specific options Note: - Due to the addition of Voter circuits on the outputs, an XTMR design generally does not permit I/O-based registersc)Click OKd)Within the processes for source window, double-click Synthesize-XST tocompile and produce a Xilinx specific netlist.e)Next, expand the menu options under Implement Design and double-clickTranslate.f)Now Right-Click Map and Invoke the properties Menu.Figure: 4: Setting properties for Map in ‘processes for source’ tabg)Turn off the option to pack I/O registers/latches into IOBsFigure: 5: Disabling Pack I/O Registers into IOBs option under map propertiesh)Click OKi)In the processes window Double-Click on Map. Note the map report(orcheck design summary) which can be used to compare the resourceutilization before and after triplication.Figure: 6: Design Summary for Pre XTMR Design ProjectStep 3: Import the .ngc/.ngo file into the TMRTool. Use the TMRTool features to do a specific type of triplication or just the default triplication of the design.a)Open TMRTool from windows menu by clicking on the XTMR icon.b)Create a new TMRTool project, Name it and specify an appropriatelocation (preferably in a new folder in the C drive).c)Check to see if the macro location setting is correct, this is done byselecting EDIT Æ Preferences and point to the location of the macrolibfolder copied during the installation of the TMRTool.Figure: 7: Setting the location for macrolib directoryd)Select Project Æ specify top-level sourcee)Browse to the .ngc file just created in the ISE tool and Click Open.Figure: 8: Opening the .NGC file for the project that is to be XTMRedf)In the Processes for Source window, double-click on Import. The greencheck appears when the process is successfully completed.Figure: 9: Importing the Top-level sourceg)From the processes for source window, double-click EDIT XTMR Types.The resulting display shows each node in the design. For each node shown you can specify the extent of TMR processing. Leave all options at default however for this Tutorial. For further explanation on the topic and the differences between these choices, view the online video on the website.Figure: 10: Setting XTMR typesh)Before clicking Implement XTMR, right-click on implement XTMR andgo to properties.i)Go to process settings and select “Replace SRL 16 with flip-flops” thiswill incorporate the extraction of half latches and replace SRL 16s.Figure: 11: Implement XTMR process settingj)Double-click Implement XTMR.k)After implementing XTMR, the design is exported into ISE environment for standard Place and Route Processing. This is done by double-clicking Export design in the “processes for source” window. The green check appears when the process is completed successfully.Figure: 12: Exporting XTMR NetlistStep 4: Examining the triplicated netlist produced in TMRTool in Plan Ahead software.a)Open Xilinx Plan Ahead 9.2.5 to launch the Plan Ahead Toolb)Select File Æ New Project.c)Create a New Project and Name it.d)Select “Yes, I want to import a synthesized (EDIF or NGC) Netlist.”Figure: 13: Creating new project in Plan Aheade)Browse for the .edf of the project just created in TMRTool.f)Select Next to import Netlist.Figure: 14: Import the netlist just Created in TMRTool(.edf file) g)Select the Virtex 4 family.Figure: 15: Choosing the Product Familyh)Select the Part as xc4vfx60ff1152-10 and Click OK.Figure: 16: Choosing the Devicei)Click NEXT on the import constraints window. We will be Examining theresulting netlist and will not need constraints.j)Click Finish.k)Examine the Netlist under the Netlist window. Select the Top module, Right-click and select Schematic.Figure: 17: Netlist window with the schematic option to examine the modulel)Click on the ‘+’ , to look at different aspects of the primitive. Right click on each primitive and Click Schematic, and observe the schematicrepresentation of the resulting post-TMRTool netlist.Figure: 18: Window with Plan Ahead Schematic for the moduleStep 5: Create a New Project in ISE, Specifying the Triplicated EDIF file as the Top-level Source.a)Create a New ISE Project labeled as And_post_tmr in appropriatelocation. Ensure that the Top-Level Module Type selection is EDIF asshown.Figure: 19: Creating new ISE project with top level EDIF source for Post XTMRb)Click Next.c)On the following screen, specify the input EDIF design file. Browse forthe .edf of the project just created in TMRTool.d)Uncheck copy the input design to the project directory.Figure: 20: Importing Input design file (.edf file created in TMRTool)e)Click Next. Ensure that the Target FPGA device is correct, as shown.Click NEXT and FINISHFigure: 21: Specifying Target FPGA devicef)ISE opens showing the And _tmr as the top-level design file.g)Within the “processes for source” window, right-click MAP and selectproperties. Turn off the pack I/O Registers/Latches in IOBs option by selecting off from the pull-down menu, then Click OK.Figure: 22: Setting properties for Map in ‘processes for source’ tabFigure: 23: Disabling Pack I/O Registers into IOBs option under mappropertiesh)In the sources window, select the top level design file.i)Double click place and route under processes window.Figure: 24: Implementing Place and Routej)In the processes window Double-Click on Map and note the map report or check design summary which can be used to compare the resourceutilization before and after triplication..Figure: 25: Design Summary for Post XTMR Design Project-Author BioName: Naveen Nischal PurushothamGraduate student at UNM in ECE department.E-mail: nischal@.。
Xilinx_ISE使用教程
新的
最高级的高性能真正的6输入 LUT逻辑结构
PCI Express® 端节点模块
带ChipSync技术和XCITE DCI 的 SelectIO
8 DSP
Slice
新一代PowerPC®嵌入式处理器
RocketIO™ 接收/发送器选项
低功耗 GTP: 最大到3.75 Gbps 高性能的GTX: 最大到 6.5 Gbps
IOB
Reg DDR MUX
OCK1
Input
Reg
ICK1
OCK2
Reg
3-state
ICK2
Reg
OCK1
Reg DDR MUX
PAD
Output
Reg
OCK2
Xilinx公司产品概述
---FPGA内部结构（专用BRAM）
• 最大3.5 Mb • 同步的读/写 • 真正的双端口RAM • 每个端口有同步读/写功能 • 每个端口有不同的时钟（可 配置） • 支持初始化值 • 对输出锁存器的同步复位 • 支持奇偶校验 • 每8位一个奇偶校验位 • 与嵌入式的专用乘法器相邻 • 用于快速的乘-累加操作
Xilinx公司产品概述
---FPGA内部结构
每个CLB模块不仅可以用 于实现组合逻辑、时序逻辑， 还可以配置为分布式RAM和 分布式ROM。
本地布线
Xilinx公司产品概述
---FPGA内部结构
典型的4输入Slice结构示意图（Virtex-II）
Xilinx公司产品概述
-FPGA内部结构
Xilinx公司产品概述
Xilinx公司产品概述
--CPLD产品
CPLD产品目前有两大类:
CoolRunner系列
Xilinx Kintex-7 FPGA Embedded Kit 产品说明书
SIR178DP-T1-RE3SiR178DPVishay SiliconixN-Channel 20 V (D-S) MOSFETFEATURES•TrenchFET ® Gen IV power MOSFET •Very low R DS x Q g figure-of-merit (FOM)•Leadership R DS(ON) minimizes power lossfrom conduction•2.5 V ratings and operation at low voltage gate drive•100 % R g and UIS tested•Material categorization: for definitions of compliance please see /doc?99912APPLICATIONS•Battery management •DC/DC converters •Load switchNotesa.T C = 25 °Cb.Surface mounted on 1" x 1" FR4 boardc.t = 10 sd.See solder profile (/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnectione.Rework conditions: manual soldering with a soldering iron is not recommended for leadless componentsf.Maximum under steady state conditions is 54 °C/WPRODUCT SUMMARYV DS (V)20R DS(on) max. (Ω) at V GS = 10 V 0.0004R DS(on) max. (Ω) at V GS = 4.5 V 0.0005R DS(on) max. (Ω) at V GS = 2.5 V 0.0012Q g typ. (nC)95I D (A) a430ConfigurationSinglePowerPAK ® S O-8 S ingleTop View16.15 mm5.15 m mBottom View4G3S 2S1SD 8D 6D 7D 5ORDERING INFORMATIONPackagePowerPAK SO-8Lead (Pb)-free and halogen-freeSiR178DP-T1-RE3ABSOLUTE MAXIMUM RATINGS (T A = 25 °C, unless otherwise noted)PARAMETERS YMBOL LIMITUNIT Drain-source voltage V DS20 VGate-source voltageV GS-8 / +12 Continuous drain current (T J = 150 °C)T C = 25 °CI D 430AT C = 70 °C345T A = 25 °C100 b, c T A = 70 °C 84.5 b, cPulsed drain current (t = 100 μs)I DM 500Continuous source-drain diode currentT C = 25 °CI S 94.5T A = 25 °C5.6 b, c Single pulse avalanche current L = 0.1 mHI AS 80Single pulse avalanche energy E AS320mJ Maximum power dissipationT C = 25 °CP D 104WT C = 70 °C67T A = 25 °C6.3 b, c T A = 70 °C 4 b, cOperating junction and storage temperature range T J , T stg -55 to +150°CSoldering recommendations (peak temperature) c 260THERMAL RESISTANCE RATINGSPARAMETER S YMBOL TYPICAL MAXIMUM UNITMaximum junction-to-ambientb t ≤ 10 s R thJA 1520°C/WMaximum junction-to-case (drain)Steady state R thJC0.9 1.2SiR178DPVishay SiliconixNotesg.Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %h.Guaranteed by design, not subject to production testingStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS (T J = 25 °C, unless otherwise noted)PARAMETER S YMBOL TE S T CONDITION S MIN.TYP.MAX.UNIT StaticDrain-source breakdown voltage V DS V GS = 0 V, I D = 250 μA20--V V DS temperature coefficient ∆V DS /T J I D = 10 mA -14-mV/°C V GS(th) temperature coefficient ∆V GS(th)/T J I D = 250 μA --4.4-Gate-source threshold voltage V GS(th)V DS = V GS , I D = 250 μA 0.6- 1.5V Gate-source leakageI GSS V DS = 0 V, V GS = -8 V / +12 V--± 150nA Zero gate voltage drain current I DSS V DS = 20 V, V GS = 0 V --1μA V DS = 20 V, V GS = 0 V, T J = 70 °C--15On-state drain current aI D(on)V DS ≥ 10 V, V GS =10 V 20--ADrain-source on-state resistance a R DS(on)V GS = 10 V, I D = 30 A -0.000310.0004ΩV GS = 4.5 V, I D = 30 A -0.000380.0005V GS = 2.5 V, I D = 30 A -0.000740.0012Forward transconductance a g fsV DS = 15 V, I D = 50 A-295-S Dynamic bInput capacitance C iss V DS = 10 V, V GS = 0 V, f = 1 MHz-12 430-pF Output capacitanceC oss -4070-Reverse transfer capacitance C rss -740-Total gate charge Q g V DS = 10 V, V GS = 10 V, ID = 20 A -207310nC V DS = 10 V, V GS = 4.5 V, I D = 20 A -95143Gate-source charge Q gs -26.6-Gate-drain charge Q gd -18.219-Output charge Q oss V DS = 10 V, V GS = 0 V-62-Gate resistance R g f = 1 MHz0.20.94 1.9ΩTurn-on delay time t d(on)V DD = 10 V, R L = 1 Ω, I D ≅ 10 A,V GEN = 10 V, R g = 1 Ω-1740ns Rise timet r -1020Turn-off delay time t d(off)-83170Fall timet f -1430Turn-on delay time t d(on)V DD = 10 V, R L = 1 Ω, I D ≅ 10 A,V GEN = 4.5 V, R g = 1 Ω-4490Rise timet r -64130Turn-off delay time t d(off)-128260Fall timet f-3980Drain-Source Body Diode Characteristics Continuous source-drain diode current I S T C = 25 °C--100A Pulse diode forward current I SM --300Body diode voltageV SD I S = 10 A, V GS = 0 V-0.7 1.1V Body diode reverse recovery time t rr I F = 10 A, dI/dt = 100 A/μs,T J = 25 °C-4690ns Body diode reverse recovery charge Q rr -55110nC Reverse recovery fall time t a -27-nsReverse recovery rise timet b-19-SiR178DP Vishay SiliconixTYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)Output CharacteristicsOn-Resistance vs. Drain Current and Gate Volta g eGate Char g eTransfer CharacteristicsCapacitanceOn-Resistance vs. Junction TemperatureOn-Resistance vs. Gate-to-Source Volta g e Sin g le Pulse Power, Junction-to-AmbientSafe Operatin g Area, Junction-to-AmbientNotea.V GS > minimum V GS at which R DS(on) is specifiedSiR178DPVishay SiliconixTYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)Current Deratin g a Power, Junction-to-CaseNotea.The power dissipation P D is based on T J max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upperdissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limitSiR178DP Vishay SiliconixTYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)Normalized Thermal Transient Impedance, Junction-to-CaseVishay Silico nix maintains wo rldwide manufacturing capability. Pro ducts may be manufactured at o ne o f several qualified lo catio ns. Reliability data fo r Silico n Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see /ppg?77598.Legal Disclaimer Notice VishayDisclaimerALL PRODU CT, PRODU CT SPECIFICATIONS AND DATA ARE SU BJECT TO CHANGE WITHOU T NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.© 2019 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVEDSIR178DP-T1-RE3。
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7HFKQRORJ\ PDSSLQJ XVLQJ 6,6Laboratory 2in course “Logic synthesis”2002-versionWritten by Tomas Bengtsson and Shashi KumarÃÃ,QWURGXFWLRQ BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB'RFXPHQWV QHHGHG IRU WKLV ODEBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB5HFRPPHQGHG SUHSDUDWLRQV IRU WKLV ODE BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB6KRUW LQWURGXFWLRQ WR )3*$V BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB,QIRUPDWLRQ DERXW &/%V XVHG LQ WKLV ODE BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7DVNV BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB0DNLQJ VFULSWV IRU WHFKQRORJ\ PDSSLQJ BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7HFKQRORJ\ PDSSLQJ RI PXOWLSOLHUBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7HFKQRORJ\ PDSSLQJ RI *UD\ FRGH FRQYHUWHU BBBBBBBBBBBBBBBBBBBBBBBBBBB7HFKQRORJ\ PDSSLQJ RI D EHQFKPDUN BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB$Q H[DPSOH RI 7HFKQRORJ\ PDSSLQJ BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB'HVFULSWLRQ RI H[DPSOH BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB6RPH WLSVBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7KH H[DPSOH WKURXJK 6,6BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBDecomposition_____________________________________________97.3.1. Gate7.3.2. LUTMapping_________________________________________________11commands_______________________________________127.3.3. Post-processing7.3.4. Programmable Logic Block Generation_____________________________14ÃÃ,QWURGXFWLRQAfter a circuit has been optimized using Logic Optimization tools, the next step is to bring the circuit closer to implementation by using the available information about implementation technology. This step is called Technology Mapping. This step involves converting the abstract description (FSM or Boolean functions) of the circuit to a network of limited type of components, normally from a library of components. Due to this reason, Technology Mapping is also sometimes referred as Library Binding. This step involves, selecting components from the library and forming a network of these components. Normally the objectives in Technology Mapping are to have the final implementation using a minimum number of components or to minimize the area of the implementation.Technology mapping to an FPGA results in the final implementation suitable for a specific FPGA type from a specific company. This is because the internal architecture of FPGAs from different companies is quite different. The internal architectures of various FPGAs from the same company also differ depending on the component series. For example, XILINX 4000 series FPGA has different type of logic blocks as compared to 3000 series. There are two further steps after a circuit has been converted to a network of blocks of a FPGA. These steps are called 3ODFHPHQW and 5RXWLQJ. In the placement step, the logic blocks in the network are assigned specific physical blocks within the FPGA. In the routing step, the used logic blocks are connected using programmable interconnection resources.In this laboratory, we are only concerned with the first step, which is converting the abstract design to a network of logic blocks for Xilinx FPGA family.'RFXPHQWV QHHGHG IRU WKLV ODEAmong the documents from the first lab you will need the document from UCLA (University of California Los Angeles), which describes the extension of SIS for technology mapping. In this document we recommend you to skip the first part and start reading the part starting with a header “Commands provided by UCLA FPGA Mapping Package”. This documents can be found in Appendix A of this lab manual.A “hand-in” form that you have to fill in to pass the lab is also given. That hand in form and this lab manual can be found in Pingpong.5HFRPPHQGHG SUHSDUDWLRQV IRU WKLV ODETo be able to use the lab time more efficient we recommend you to study the document from UCLA the part mentioned in section 2 “Documents needed for this lab”. It is also recommended that you complete the task described in section 6.1 “Task 1 Making scripts for technology mapping” before the lab.ÃÃ6KRUW LQWURGXFWLRQ WR )3*$VFPGAs are one family of programmable logic circuits. An FPGA contains programmable logic blocks and programmable interconnection between the blocks. The programmable blocks are called CLBs (Complex Logic Block). The CLBs contain one or more LUTs (Look Up Table). A LUT is a combinatory device with some inputs and one output. It can be programmed to realize any Boolean function. The CLB can be programmed so the output of the LUTs goes to the output of the CLB direct or via a flip-flop. This can be done individually for every LUT. The inputs to the CLB are connected to the inputs in the LUTs. If the CLB contains more than one LUT, some inputs to the CLB may be connected to inputs in more than one LUT.To connect outputs and inputs of CLBs to other CLBs and to the ports of a chip the programmable interconnection part is used. In this lab we are not going to deal with this. We are only going to map logic into fit CLBs. We will use some old FPGAs, Xilinx3000 – series and Xilinx4000 – series. For our purpose we don’t gain anything by using newer ones. The CLBs in both series has two LUTs. The LUTs in Xilinx3000 – series has four inputs and in Xilinx4000 – series they have five inputs.The picture below shows an example of a simple CLB. The CLBs we will use in this lab looks a little different.,QIRUPDWLRQ DERXW &/%V XVHG LQ WKLV ODEAs written in the previous section the LUTs in Xilinx 3000-series have four inputs each and in Xilinx 4000-series the LUTs have five inputs each. The parameter “-k” used in many technology-mapping commands should specify number of inputs to one LUT.ÃÃ7DVNV7DVN 0DNLQJ VFULSWV IRU WHFKQRORJ\ PDSSLQJIn this task you should prepare scripts for technology mapping. Make one script containing technology-mapping commands, which makes optimization with respect to area minimization for mapping to Xilinx 3000-series. Make another script doing the same but for minimizing the depth of the circuit. Copy those scripts and modify the copies to work for Xilinx 4000-series. You don’t need to put the final commands “match_3k” and “match_4k” into the scripts. You can write those commands in the SIS-prompt when you need them instead.Fill in the scripts in the “hand-in” form.7DVN 7HFKQRORJ\ PDSSLQJ RI PXOWLSOLHUIn this task you should use your multiplier from the previous lab and make technology mapping in some different ways. In this lab you should alter the following parameters:• You can either use technology-independent optimization before you make technology mapping or you can skip technology-independent optimization. When you are making technology-independent optimization in this task you should use “rugged-script”• You can optimize for area or for depth. To do this you should use your scripts from the previous task.• You can technology-map for either Xilinx 3000-series or Xilinx 4000-series.The alternatives enumerated above makes eight different combinations of optimizations. Make those and fill in the required results in the “hand-in” form. There are also some questions in the “hand-in” form you should answer.7DVN 7HFKQRORJ\ PDSSLQJ RI *UD\ FRGH FRQYHUWHUIn this task you should use the “Gray-code to binary converter” you have made in the previous lab. The task is to technology-map it so it fits into two CLBs in Xilinx 3000-series. Do this and answer the questions in the “hand-in” form!7DVN 7HFKQRORJ\ PDSSLQJ RI D EHQFKPDUNIn this task you should technology-map the benchmark “t481.pla”. You should map it so that it only requires five LUTs in Xilinx 3000-series. This is the goal of this task and you decide what should be done to get there. Answer the questions in the “hand-in”-form!$Q H[DPSOH RI 7HFKQRORJ\ PDSSLQJ'HVFULSWLRQ RI H[DPSOHTo describe an example of technology mapping, an FSM to control one traffic light is used. This traffic-light controller is nothing that can be used in traffic rather it can be used to show a traffic light fitting in a fair. The controller is made as a Moore-machine.ÃÃThe FSM has three inputs. The first input let the traffic-light run in normal mode if it’s “0”, and in a mode with twinkle amber (amber ≈ yellow) if it is “1”. In the normal mode the traffic light is red, green or it is on its way between. If the second input is “1”, when the traffic light is green, it is forced to red via amber. If the third input is “1”, when the traffic light is red, it is forced to green via red_amber.The outputs from the FSM are signals to the three lamps. It is in the order green, amber and red, and “1” means on.The state-diagram below shows the system.ÃÃA description of this in kiss-format is shown below:.start_kiss.i 3.o 300- green green 10001- green amber 1001-- green twinkle_amber 1000-- amber red 0101-- amber twinkle_dark 0100-0 red red 0010-1 red red_amber 0011-- red twinkle_amber 0010-- red_amber green 0111-- red_amber twinkle_amber 0110-- twinkle_amber red 0101-- twinkle_amber twinkle_dark 0100-- twinkle_dark amber 0001-- twinkle_dark twinkle_amber 000.end_kiss.endThis file is available as “/home/beto/public/logic_synthesis/traf.kiss” in the UNIX-system.6RPH WLSVIt’s good to use commands like “print_stats” and “print_level” to see what is happening between the different steps in the optimization and mapping process. Also remember that “write_blif” can give some useful information in some cases.7KH H[DPSOH WKURXJK 6,6First we make the technology independent optimization. (That is what the first laboratory was about.) We use “state_minimize”, “state_assign” and then run “rugged-script”. We then get: UC Berkeley SIS with UCLA FPGA Extension (compiled 2-Apr-98 at 11:09 PM) VLV! UHDGBNLVV WUDI NLVV.start_kissVLV! VWDWHBPLQLPL]HRunning stamina, written by June Rho, University of Colorado at Boulder Number of states in original machine : 6Number of states in minimized machine : 5VLV! VWDWHBDVVLJQRunning nova, written by Tiziano Villa, UC BerkeleyWarning: network ‘SISEAAa29918’, node "v0" does not fanoutWarning: network ‘SISEAAa29918’, node "v1" does not fanoutWarning: network ‘SISEAAa29918’, node "v2" does not fanoutVLV! VRXUFH UXJJHGVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1ÃÃ.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 0100-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_100 1.names OUT_0 LatchOut_v4 OUT_201 1.names v6.1 v6.2 LatchOut_v5 v6.011- 11-0 1.names IN_0 IN_1 OUT_1 OUT_2 LatchOut_v5 v6.10-1-- 10--1- 100--0 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 v6.2--00 10011 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5 .outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_1ÃÃ10- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.endThe key-word “.exdc” means that the following blif-description is the don’t-care-set. The description above is the optimized description of the function where don’t-cares are forced to one and zero to make the function as small as possible.*DWH 'HFRPSRVLWLRQIn the description of technology mapping from UCLA, it’s written that command“tech_decomp” should be run before “dmig”-command is run. The parameter “-k 4” in the “dmig”-command is chosen to 4 because the plan is to map this to an FPGA with 4-input LUTs.VLV! WHFKBGHFRPS D RVLV! GPLJ NVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 0100-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_1ÃÃ00 1.names OUT_0 LatchOut_v4 OUT_201 1.names [21] [22] v6.01- 1-1 1.names [25] [26] [27] v6.11-- 1-1- 1--1 1.names [23] [24] v6.21- 1-1 1.names v6.1 LatchOut_v5 [21]10 1.names v6.1 v6.2 [22]11 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 [23]0011 1.names LatchOut_v4 LatchOut_v5 [24]00 1.names IN_0 IN_1 LatchOut_v5 [25]000 1.names IN_0 OUT_2 [26]01 1.names IN_0 OUT_1 [27]01 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5 .outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.endÃÃ/87 0DSSLQJWhen gate decomposition is done there are some commands to choose between, which map the function to LUTs (Look Up Tables).VLV! GDJPDS NVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 0100-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_100 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_201- 1-11 1.names [21] [22] v6.01- 1-1 1.names [25] [26] [27] v6.11-- 1-1- 1--1 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 v6.2--00 10011 1.names LatchOut_v5 [25] [26] [27] [21]01-- 1ÃÃ0-1- 10--1 1.names v6.2 [25] [26] [27] [22]11-- 11-1- 11--1 1.names IN_0 IN_1 LatchOut_v5 [25]000 1.names IN_0 LatchOut_v3 LatchOut_v4 LatchOut_v5 [26]001- 10-11 1.names IN_0 LatchOut_v3 LatchOut_v5 [27]000 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5.outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.end3RVW SURFHVVLQJ FRPPDQGVThe post-processing command “mpack” can for some cases merge two LUTs into one LUT. VLV! PSDFN NVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 010ÃÃ0-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_100 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_201- 1-11 1.names [21] [22] v6.01- 1-1 1.names [25] [26] [27] v6.11-- 1-1- 1--1 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 v6.2--00 10011 1.names LatchOut_v5 [25] [26] [27] [21]01-- 10-1- 10--1 1.names v6.2 [25] [26] [27] [22]11-- 11-1- 11--1 1.names IN_0 IN_1 LatchOut_v5 [25]000 1.names IN_0 LatchOut_v3 LatchOut_v4 LatchOut_v5 [26]001- 10-11 1.names IN_0 LatchOut_v3 LatchOut_v5 [27]000 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5 .outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1ÃÃ.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.end3URJUDPPDEOH /RJLF %ORFN *HQHUDWLRQIn our installation of SIS it is possible to map to Xilinx 3000 and 4000 –series.VLV! PDWFKB N Y##PI=3 #PO=3 #LUT=11 #CLB=6 #LEVEL=3#0001: ( OUT_2 , v6.2 )#0002: ( OUT_1 , [26] )#0003: ( OUT_0 , [27] )#0004: ( v6.1 , [21] )#0005: ( v6.0 , [25] )#0006: ( [22] ) sis> match_3k -vThe argument “-v” makes it print the list about which LUTs should be in the same CLB. $SSHQGL[$SSHQGL[ $+--------------------------------------------------------------------------+ | RASP_SYN: LUT-Based FPGA Technology Mapping Package (Release B 1.0) | | -- Synthesis Core of the UCLA RASP Systems | +--------------------------------------------------------------------------+ | Copyright (C) 1991-1997 the Regents of University of California | +--------------------------------------------------------------------------+ | Authors: Eugene Ding, VLSI CAD Lab, UCLA CS Dept. <eugene@> | | Yean-Yow Hwang, VLSI CAD Lab, UCLA CS Dept.<yeanyow@>| | Chang Wu, VLSI CAD Lab, UCLA CS Dept. <changwu@> | | Songjie Xu, VLSI CAD Lab, UCLA CS Dept. <sxu@> | | Project Director: Prof. Jason Cong, UCLA CS Dept. <cong@> | +--------------------------------------------------------------------------+ | This release includes the following mapping algorithms: | | DAG_Map version 1.0 | | FlowMap version 2.1 | | FlowMap-r version 2.0 | | FlowSYN version 2.0 | | CutMap version 1.2 | | ZMap version 1.0 | | TurboMap version 1.0+--------------------------------------------------------------------------+ -------------------<0> ACKNOWLEDGEMENTÃÃ-------------------The FlowMap and CutMap and TurboMap packages are integrated into the SIS system and uses many of the routines provided by SIS. The SIS system was developed in UC Berkeley Electronic Research Lab.--------------------------------------<1> RELEASE AGREEMENT AND CONTACT INFO--------------------------------------Please refer to "release.statement".-----------<2> CONTENT-----------sis -- binary of SIS compiled with FlowMap andCutMap packages.doc -- this file.release.statement -- to be read first.rasp_syn -- a csh script of FPGA mappingselect -- mapping result selectorThis release contains programs primarily developed by September 1997. More functions will be added to future release when they are stablized. It runs on Sun SPARCstation under SunOS 4.1.3 and Solaris.Some commands are not included in the release due to nondisclosure agreement.RASP_SYN package provides a complete solution to SRAM-based FPGA mapping engine. The entire flow of RASP_SYN is:1. gate decomposition to get K-bounded circuit, where K is thefanin limit of LUTs of the target architecture2. generic LUT mapping3. post-processing mainly for area reduction4. architecture specific mapping.RASP_SYN comes with a user-friendly csh script for the ease of use. However, you can modify the script or write your own based on your specific needs.------------------------<3> TECHNICAL REFERENCES------------------------J. Cong, Y. Ding, "An Optimal Technology Mapping Algorithm for DelayOptimization in Lookup-Table based FPGA Designs," IEEE Trans. on CAD, Vol. 13, No. 1, Jan. 1994, pp. 1-12.J. Cong, Y. Ding, "On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping," IEEE Trans. on VLSI Systems, Vol 2., No. 2, June 1994,pp. 137-148.J. Cong, Y. Ding, T. Gao, K. Chen, "LUT-Based FPGA Technology Mappingunder Arbitrary Net-Delay Models," Computers & Graphics,Vol.18, No.4, 1994, 507-516.J. Cong, Y. Ding, "Beyond the Combinatorial Limit in Depth Minimization for LUT-Based FPGA Designs," Proc. 1993 IEEE/ACM Int’l Conf. on CAD,Santa Clara, CA, Nov. 1993, pp. 110-114.K.Chen, J.Cong, Y.Ding, A.Kahng, P.Trajmar, "DAG-MAP: Graph-BasedÃÃFPGA Technology Mapping for Delay Optimization," IEEE Design & Testof Computers, Sept. 1992J. Cong, J. Peck, Y. Ding, "RASP: A General Logic Synthesis System forSRAM-based FPGAs," Proc. ACM 4th Int’l Symp. on FPGA, pp. 137-143, 1996J. Cong, Y. Hwang, "Simultaneous Depth and Area Minimization in LUT-BasedFPGA Mapping," Proc. ACM 3rd Int’l Symp. on FPGA, Feb. 1995, pp. 68-74.J. Cong, Y. Hwang, "Structural Gate Decomposition for Depth-OptimalTechnology Mapping in LUT-based FPGA Designs," Proc. ACM/IEEE 33rdDesign Automation Conf., pp. 726-729, 1996.J. Cong, C. Wu, "An Improved Algorithm for Performance Optimal TechnologyMapping with Retiming in LUT-Based FPGA Design," Proc. IEEE InternalConference on Computer Design, pp. 572-578, 1996Xilinx, FPGA Data Book, 1994---------<4> USAGE---------4.1 Running with a super scriptSuper Script of UCLA FPGA MappingUsage: rasp_syn circuit -sis path -k k -device xc3k/xc4k -algo algo -relax r -objective area/delay/tradeoff/allRasp_syn is a csh script for an easy usage of UCLA FPGA Mapping algorithms.In default, the input is in EQN format with extension .eqn. The output isan LUT network with/without matching information in EQN format as well.Please keep the program "select" in the current directory.To use other data formats as BLIF or SLIF which are supported by SIS of UCB, please set FMT in rasp_syn script to blif or slif and use .blif or .slifas the name extension of the input file. The output format will be changed automatically, except the CLB matching file format, which will be keptin EQN format. For Xilinx XC3K/XC4K CLBs, the CLB clustering informationwill be presented as:#CLB_number: (lut1, lut2)lut1 = ..lut2 = ..There are two ways to run rasp_syn:1. Running with single given mapping algorithmThe algorithm must be specified with option -algo algorithm. The targetis K-LUT. The output circuit is in circuit.k in EQN format.2. Running with multiple algorithmsRasp_syn can run all the built-in algorithms automatically and returnthe best result (in terms of area or delay) or a set of resultsbased on area-delay tradeoff or all the results for you.To run multiple algorithms, you simply do not specify any algorithm with-algo option.OptionsÃÃ-sis Specify the path of sis. The default is sis and the pathmust be specified in the environment.-k Used only in single algorithm mode. K is the input numberof LUTs. The output is in circuit.k.-device Used only in multi-algorithm mode. This is the default mode. The current supported devices are:xc3k Xilinx XC3000 Familyxc4k Xilinx XC4000 Family-algo Specify the mapping algorithm in single algorithm mode.The current supported algorithms are:flowmap: FlowMapflowmap-r: FlowMap-rflowsyn: FlowSYNcutmap: CutMapzmap: ZMap for delayzma: ZMap for area-relax Used only in single algorithm mode with FlowMap-r.R is the depth relaxation.-objective Used only in multi-algorithm mode. The objective can be:area: Area first. This is the default objective.delay: Depth firsttradeoff: Area-delay tradeoffall: All the results4.2 Running SIS without the super scriptSIS is a complete logic synthesis package. All of the following commands have been built in SIS which can be run directly from SIS.Commands provided by UCLA FPGA Mapping Package--------------------------------------------------------------------1. Gate Decomposition Commands* dmig [ -k <K_value> ] [ -f ]Decompose a simple gate network into a K-bounded network(i.e. each gate has no more than K inputs), orcomplex gates into K-bounded gates with -f option.For obtaining a simple gate network, use sis command"tech_decomp -a 1000 -o 1000."-k specifies max. gate input size K, with a default value 2.-f decompose complex gates in the network* dogma [ -k <K_value> ]Decompose a simple gate network into a 2-bounded networksuch that flowmap, cutmap, or zmap can obtain a best (small) depth.-k specifies the LUT input size K, with a default value 5.--------------------------------------------------------------------2. LUT Mapping Commands* dagmap [ -k <K_value> ]Map a K-bounded network into a K-LUT network of small depthÃÃ(might not be optimal).-k specifies the LUT input size K, with a default value 5.* flowmap [ -k <K_value> ] [-r <R_value> ] [ -s <S_value> ]Map a K-bounded network into a K-LUT network of optimal depth,or within the optimal depth plus R.Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K, with a default value 5.-r specifies the relaxed depth value R.If -r is not used, every node is at its optimal depth,-r 0 will trade depth on non-critical paths for a smaller area(the LUT network still has an optimal depth),-r R will allow depth to increase by R (then dfmap is called toreduce the area).-s specifies the cone input size S for which resynthesis of conesare performed for a smaller LUT network depth.* dfmap [ -k <K_value> ]Map a K-bounded network into a K-LUT network of optimal areaWITHOUT any node duplication.It is used after flowmap -r and mffc_shrink, and is followedby a LUT packing procedure. For example, we use dfmap in"flowmap -k 5 -r 1; mffc_shrink -k 5; dfmap -k 5; greedy_pack -k 5"-k specifies the LUT input size K, with a default value 5.* cutmap [ -k <K_value> ] [-x ]Map a K-bounded network into a K-LUT network of optimal depthwith simultaneous area minimization.Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K, with a default value 5.-x specifies depth relaxation on non-critical paths.* zmap [ -k <K_value> ] [-c ]Map a K-bounded network into a K-LUT network of optimal depthwith simultaneous area minimization (cut enumeration approach).Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K, with a default value 5.-c will minimize area only with no bound on depth* turbomap [ -k <K_value> ] [-c <clock_value> ] [ -a <area_reduction> ]Map a K-bounded network into a K-LUT network with the minimum clockperiod. Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K,default value: 5.-c specifies an upper-bound on the clock period,-1: no upper-bound, (default)。
NI ELVIS II系列产品规格说明说明书
Arbitrary Waveform Generator/Analog Output
Number of channels.........................2
DAC resolution................................16 bits
DNL.................................................±1 LSB
Maximum working voltage for analog inputs (signal + common mode) ................ ±11 V of AIGND
CMRR (DC to 60 Hz) ..................... 90 dB
Source..............................................AI<0..15>, ScopeCH0, ScopeCH1
Small signal bandwidth (–3 dB)......1.2 MHz
Input FIFO size................................4095 samples
Scanlist memory ..............................4095 entries
Data B signal stream, programmed I/O
FPGA的LVDS介绍和xilinx原语的使用方法中文说明
FPGA的LV DS介绍和x i linx原语的使用方法中文说明低压差分传送技术是基于低压差分信号(Low Volt-agc Differe ntialsignali ng)的传送技术，从一个电路板系统内的高速信号传送到不同电路系统之间的快速数据传送都可以应用低压差分传送技术来实现，其应用正变得越来越重要。
低压差分信号相对于单端的传送具有较高的噪声抑制功能，其较低的电压摆幅允许差分对线具有较高的数据传输速率，消耗较小的功率以及产生更低的电磁辐射。
LVDS：Low Voltage Differe ntialSignali ng，低电压差分信号。
LVDS传输支持速率一般在155Mbps（大约为77MH Z）以上。
LVDS是一种低摆幅的差分信号技术，它使得信号能在差分PCB线对或平衡电缆上以几百Mbps的速率传输，其低压幅和低电流驱动输出实现了低噪声和低功耗。
差分信号抗噪特性从差分信号传输线路上可以看出，若是理想状况，线路没有干扰时，在发送侧，可以形象理解为：IN= IN+ —IN-在接收侧，可以理解为：IN+ —IN- =OUT所以：OUT = IN在实际线路传输中，线路存在干扰，并且同时出现在差分线对上，在发送侧，仍然是：IN = IN+ —IN-线路传输干扰同时存在于差分对上，假设干扰为q，则接收则：(IN+ + q) —(IN- + q) = IN+ —IN- = OUT所以：OUT = IN噪声被抑止掉。
上述可以形象理解差分方式抑止噪声的能力。
From: 美国国家半导体的《LVDS用户手册》P9FPGA中的差分管脚为了适用于高速通讯的场合，现在的FPGA都提供了数目众多的LVDS接口。
如Spartan-3E系列FPG A提供了下列差分标准：LVDSBus LVDSmini-LVDSRSDSDiffere ntialHSTL (1.8V, Types I and III)Differe ntialSSTL (2.5V and 1.8V, Type I)2.5V LVPECLinputs所拥有的差分I/O管脚数目如下From:Spartan-3E FPGA Family:Complet e Data Sheet p5I/O管脚的命名方式：From:Spartan-3E FPGA Family:Complet e Data Sheet p164From:Spartan-3E FPGA Family:Complet e Data Sheet p18 Spartan-3E系列FPG A器件差分I/O接口输入工作的特性参数:From:Spartan-3E FPGA Family:Complet e Data Sheet p126 Spartan-3E系列FPG A器件差分I/O接口输出工作的特性参数:From:Spartan-3E FPGA Family:Complet e Data Sheet p127Xilinx公司差分原语的使用（原语，其英文名字为P rimiti ve，是Xilinx针对其器件特征开发的一系列常用模块的名字，用户可以将其看成Xilin x公司为用户提供的库函数，类似于C+ +中的“cout”等关键字，是芯片中的基本元件，代表FPGA中实际拥有的硬件逻辑单元，如LUT，D触发器，RAM等，相当于软件中的机器语言。
Xilinx Product_Selection_Guide
Zynq™-7000 Extensible Processing Platform ............................................................................ 2 7 series FPGAs ................................................................................................................................................ 3 Virtex®-6 FPGAs .............................................................................................................................................. 6 Spartan®-6 FPGAs ........................................................................................................................................ 7 Virtex-5 FPGAs ............................................................................................................................................... 8 Virtex-4 FPGAs ............................................................................................................................................ 10 Extended Spartan-3A FPGAs .............................................................................................................. 11 Spartan-3 and -3E FPGAs .....................................................................................................................12 Xilinx CPLD Products ...............................................................................................................................13 Configuration Storage Solutions ........................................................................................................14 Xilinx ISE® Design Suite .........................................................................................................................16 Aerospace & Defense ...............................................................................................................................17 Automotive ...................................................................................................................................................... 23 Xilinx Boards & Kits .................................................................................................................................. 27 Xilinx IP Cores, Reference Designs, and Instructor Led Training Courses ............ 30 Xilinx Productivity Advantage ............................................................................................................. 31
CommScope LGX和1RU分裂器产品指南说明书
specification guideSinglemode devicesOverviewPassive optical components can have a significant impact on the efficiency of communication network rollouts. The incorporation of fiber-optic splitters reduces the number of fibers in the network—decreasing both the footprint and investment cost of network rollouts. In existing networks, these components allow capacity upgrades at a relatively low cost without additional construction work.Advantages·Low insertion loss ·Consistent performance ·Small footprint ·Excellent uniformity ·Low PDL Applications·Passive optical networks (PONs)—FTTH and FTTx ·Telecommunications networks·CATV / MSOsCommScope’s LGX and 1RU splitter portfolio is based on planar lightwave circuit (PLC) technology used to split and combine light. The LGX and 1RU housings support a variety of split ratios: 1:N and 2:N configurations where N=1 to 64. LGX and 1RU configurations are released with LC/APC, LC/UPC, SC/APC, and SC/UPC connectors.CommScope’s portfolio of LGX and 1RU splitters meets OSP operating temperature and environment requirements of -40°C to +70°C.LGX and 1RU products are tested to GR-63-CORE packaging requirements and IEC 61300-2-1, 61300-2-4, 61300-2-5, 61300-2-9, 61300-2-19, 61300-2-21, 61300-2-22, 61300-2-4 and 61300-2-45.LGX and 1RU splitter optical performanceExample of LGX Module with LC adapters Example of 1RU Panel with SC adaptersHousing types and dimensionsLGX rack mounting solutionsFeatures:·The LGX 4RU back-to-back chassis holds 14 single-width LGX modules per side or seven dual-width LGX modules per side ·Maximum density of 28 single-width LGX modules or 14 dual-width LGX modules ·19-in. or 23-in. rack mount· 2.5-in., 5-in., or 8-in. recess mounting options ·Dimensions (H x W x D): 6.9 x 17 x 15 inches·LGX pass-through module: Pass-through modules (qty. 2 required) can be mounted anywhere in chassis to allow cables from rear modules to pass to front of chassis.Features:·Maximum density of 14 single-width LGX modules or 7 dual-width LGX modules ·19-in. rack mount·Dimensions (H x W x D): 132.5 x 482 x 235 mm Features:·Holds three single-width LGX modules ·19-inch rack mount·Dimensions (H x W x D): 1.7 x 18.9 x 8.9 inches / 44 x 481 x 225 mm4RU back-to-back chassis3RU chassis1RU chassisCommScope pushes the boundaries of communicationstechnology with game-changing ideas and ground-breakingdiscoveries that spark profound human achievement.We collaborate with our customers and partners to design,create and build the world’s most advanced networks. It is ourpassion and commitment to identify the next opportunity andrealize a better tomorrow. Discover more at Visit our website or contact your local CommScope representative for more information.© 2023 CommScope, Inc. All rights reserved. CommScope and the CommScope logo are registered trademarks of CommScope and/or its affiliates in the U.S. and other countries. For additional trademark information see https:///trademarks. All product names, trademarks and registered trademarks are property of their respective owners.。
华邦(winbond)产品手册
PRODUCT GUIDE ==Winbond、ISSI 授权香港及中国代理== 8 位单片宽工作电压系列
型号 ROM 型式 ROM RAM I/O 脚 外扩存储 器空间 64K 工作电压 定时器/ 计数器 3 封装 Int 特殊功能 PDIP 6 CMOS 通用功能 特殊 I/O 口 /INT2, /INT3,WDT 特殊 I/O 口 /INT2, /INT3,WDT 16 KB 掩膜 ROM W78L54 掩膜 16K 256 32/36 64K 5.5V - 1.8V 3 8 特殊 I/O 口 /INT2,/INT3,WDT W78L801 掩膜 4K 256 36 64K 5.5V - 1.8V 2 12 特殊 I/O 口,P1 口 退出省电方式 WDT 可多次编程,特殊 I/O 口 / INT2, /INT3, WDT 可多次编程特殊 I/O 口 / INT2, /INT3, WDT 可多次编程特殊 I/O 口 / INT2, /INT3, WDT 可多次编程,可在线编程 特殊 I/O 口/ INT2, /INT3 可多次编程,可在线编程 W78LE516 Flash EPROM 64K 512 32/36 64K 5.5V - 2.4V 3 8 特殊 I/O 口,/ INT2, /INT3, 可多次编程,可在线编程 W78LE365 Flash EPROM 64K 1280 32/36 64 K 5.5V - 2.4V 3 8 特殊 I/O 口/ INT2, /INT3,WTD,PWM 特殊 I/O 口 W78LE812 Flash EPROM 8K 256 36 64K 5.5V - 2.4V 3 14 P1 口退出省电方式 WDT,UART 40 44 44 40 44 44 40 44 44 40 44 44 40 44 44 40 PLCC 44 PQFP 44
MB简介
利用MicroBlaze构建基本的嵌入式系统。通过标准总线接口—LMB总线和OPB总线的IP核，MicroBlaze就可以和各种外设IP核相连。
在EDK中，每一个外设IP模块都有自己的软件函数库。利用Libgen工具，将所需外设函数数库的头文件添加进工程中，通过调用这些函数可以操作和控制这些外设。例如对串口的操作如下：
//初始化串口，设置波特率等参数，清空发送和接收缓冲，禁止中断；
XuartLite_Initialize(&UART，XPAR_MYUARTLITE_DEVICE_ID);
（2）处理器本机总线（PLB）
PLB接口为指令和数据一侧提供独立的32位地址和64位数据总线。PLB支持具有PLB总线接口的主机和从机通过PLB信号连接来进行读写数据的传输。总线架构支持多主从设备。每一个PLB主机通过独立的地址总线、读数据总线和写数据总线与PLB连接。PLB从机通过共享但分离的地址总线、读数据总线和写数据总线与PLB连接，对于每一个数据总线都有一个复杂的传输控制和状态信号。为了允许主机通过竞争来获得总线的所有权，有一个中央判决机构来授权对PLB的访问。
利用系统的硬件模型以及RAM块的组织结构文件、ELF文件和用户结束文件，应用FPGA综合实现工具（如Xilinx XST）进行综合，然后下载生成的配置BIT文件
到目标板上。利用EDK中提供的GDB调试工具可以进行程序调试。有两种调试方法：软件仿真和硬件调试。软件仿真可以进行程序的功能调试，在开发工具内部就可以进行，不需要硬件支持。硬件调试就是通过JTAG接口或串口（可在硬件设计时选择），连接到目标板上的应用系统中的XMD调试接口，将软件程序下载到系统中进行调试。本课题使用的目标板上的主芯片为Xilinx Spartan IIE 30万门的FPGA，系统时钟为50MHz。实际运行完全满足设计要求。
Xilinx-FPGA配置的一些细节
Xilinx FPGA配置的一些细节2010年07月03日星期六 14:260 参考资料(1) Xilinx: Development System Reference Guide. dev.pdf, v10.1在Xilinx的doc目录下有。
(2) Xilinx: Virtex FPGA Series Configuration and Readback. XAPP138 (v2.8) March 11, 2005在Xilinx上有，.xilinx./bvdocs/appnotes/xapp138.pdf(3)Xilinx: Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode.XAPP502 (v1.5) December 3, 2007在Xilinx上有，.xilinx./bvdocs/appnotes/xapp502.pdf注：此外xapp139和xapp151也是和配置相关的。
(4)Xilinx: Virtex-4 Configuration Guide. UG071 (v1.5) January 12, 2007(5) Tell me about the .BIT file format.：.fpga-faq./FAQ_Pages/0026_Tell_me_about_bit_files.htm1 Xilinx配置过程主要讲一下Startup Sequence。
Startup Sequence由8个状态组成.除了7是固定的之外，其它几个的顺序是用户可设置的，而且Wait for DCM和DCI是可选的。
其中默认顺序如下：这些在ISE生成bit文件时通过属性页设定。
这几个状态的具体含义如下：Release_DONE : DONE信号变高GWE : 使能CLB和IOB，FPGA的RAMs和FFs可以改变状态GTS : 激活用户IO，之前都是高阻。
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试验4创建基本应用程序介绍在这个实验中我们创建一个基本的应用程序。
通过这个程序控制以GPIO 为连接IP的LED接口上去。
实验中，通过LibGen创建MSS文件。
目的完成本次实验，我们希望达到以下目标：•编写一个访问外围设备IP基本应用程序•利用XPS生成一个MSS文件•生成一个位文件•下载并在硬件上进行检验步骤前三个实验为处理器系统定义了硬件。
这个实验由几个步骤组成，包括访问一个外设的基本应用软件的编写。
打开工程步骤1创建在d:\Lab\下创建lab4mb文件夹。
可以按照前三个实验的流程创建一个工程，也可以直接把lab3mb内的文件拷贝至此目录。
打开该工程。
创建 BSP 步骤2n双击microblaze_0 ，打开Software Platform Settings对话框，图 4-1p在Software Platform标签中, 可以为每一个外设选择驱动级别。
同时可以为处理器选择OS内核，这里我们选择standalone。
图 4-2. 处理器设置标签p点击Processor, Drivers Parameters, an Interrupt Handlers标签并指定以下参数Processor Parameters: Instancecompiler – mb-gccarchiver – mb-arEXTRA_COMPILER_FLAGS – -gxmdstub_peripheral – noneCORE_CLOCK_FREQ_HZ – 50000000Driver Parameters: InstanceLeave Blank图4-3. Processor, Driver Parameters, and Interrupt Handlers 标签q点击 Library/OS Parameters标签Figure 10c-4. Library/OS Parameters Tab of the Software Platform Settings for the microblaze_0 Instancer在Current Value区域中选择RS232为stdin和stdout. 这将指定 UART设备作为基本输入输出端口。
其实在我们的lab1mb试验中的Base System Builder 阶段这些就已经做过了如果系统没有要指定为stdin和stdout的设备，则选择 None。
因为我们的试验没有用到动态分配内存函数，所以保持need_xil_malloc的value 为 false。
r点击OK双击System标签下的 system.mss文件打开MSS文件，如下图所示：图 4-5. 系统标签页p XPS 已把在外设选项（Peripheral Options）中配置的参数写入了system.mss。
q点击 Tools → Generate Libraries 或按钮，运行LibGen，生成BSP库文件创建基本C程序步骤 3在Application标签页中添加工程，以实现对数码管的驱动在Applications标签页中双击Software Projects，打开New Project对话框。
图 4-6.新建应用工程p输入工程名称MyProj，单击OK.p点击File → New，建立新的文本图 4-7. XPS文本编辑器第一步，为所需的函数添加头文件，所有的头文件都已在LibGen过程中保存在microblaze_0/include 路径下了.q添加C代码•#include "xparameters.h"–定义了系统外设的地址•#include "xgpio.h"–定义了Xilinx General Purpose I/O 通用接口所需的API函数r点击 File → Save As，出现保存对话框s建立新的文件夹名为code,作为lab4mb工程所需c代码的保存路径图4-8. 另存为对话框t把system.c加入工程。
t然后向此c文件添加主函数：main() {程序的编写使用C语言，方法与编写通用的单片机程序类似，可采用对地址赋值的方式也可采用API函数的方式。
相关的知识可参见EDK附带的各种手册和帮助文档，所有这些内容可在EDK\doc\路径下找到。
n在开始菜单选择Start → Programs → Xilinx Platform Studio 6.3i → Documentation →EDK 6.3 Reference & User Guideso下拉一些，选择Driver Reference Guide打开xilinx_drivers.htm页面.o选择Driver API Links打开器件驱动APIr选择gpio v2.00. ，与之相关的API函数帮助内容便可打开。
相关的程序建立我们不再赘述，因为BSB（Base System Buider）向导以主动为我们建立了一个简单的GPIO初始化及读写程序，作如下简单分析：•XGpio_Initialize初始化函数需要两个参数： InstancePtr 是XGpio 器件的指针（指针的含义参见相关的C语言教程），它指向了XGpio 所对应的端口，若要想熟练使用XGpio API，则必须掌握好此指针•DeviceId 器件序号是唯一性的无重复的器件识别号，这个参数可在xparameters.h 文件中找到s定义一个XGpio类型的变量gp_out. 将被调用为Xgpio_Initialize第一个参数，使用时如下：XGpio_Initialize(&gp_out,u双击microblaze_0：Generated Header：xparameters.h 如下图 4 -9. 双击Generated Header :mi…/in…/xparameters.h头文件•xparameters.h文件是在LibGen过程中创建的，它提供了各个器件的宏信息。
在xparameters.h中找到此条信息#define XPAR_PUSH_BUTTONS_6BIT_DEVICE_ID 0•XPAR_PUSH_BUTTONS_6BIT_DEVICE_ID 即可被用作XGpio_Initializ函数的第二个参数其余的API诸如：XGpio_DiscreteWrite（），XGpio_SetDataDirection等函数都可以参考相关的手册。
接下来，我们不使用系统自创建的程序也不使用API的方式，我们使用简单的地址赋值的方式，即访问硬件的通用方式。
此程序可在d:\Lab\labsource\lab4mb.c中拷贝几个关键地方如下：上面的插图显示了所需的头文件以及定义了7段数码管的端口地址。
上面的插图显示的内如：Xuint8 类型的指针用以指向7段数码管的端口。
上面的一段程序是模拟时钟的程序，由于microblaze 内部不含Timer/Count ，若要实现时钟功能则必须添加Timer/Count 的IP核或通过软件延时循环来实现，在这里，我们用几个for语句实现了软件延时，以周期性的驱动数码管。
指令的执行时间参考microblaze 处理器的使用手册。
运行Tools—>Generate Linker Script图4-10生成连接脚本文件点击Generate生成连接脚本文件。
选择Application标签页, 把我们写好的程序拷贝至我们建立的工程下，并右键单击此工程，选择Mark to initialize BRAM.，然后点击编译此工程。
图 4-11. Applications 标签页下载并测试步骤 5连接好目标板，创建Bit文件，并下载.n点击Tools → Download或图标，下载bit文件—>>若修改了C代码，则重新编译并点击图标，即可更新Bit文件o下载成功后，数码管会显示时钟ConclusionXPS可以用来定义，开发，集成嵌入式系统所需的各种软的硬的组件。
可以为各种外设和接口定制器件驱动，XPS同时创建MSS文件从侧面来描述整个系统的软件构成. 器件的专用函数如API 都可被编译用来生成目标代码，同时目标代码又可用来生成可立即执行文件，在已配置好硬件系统的目标板上执行。
完整的MHS 文件# ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 7.1 Build EDK_H.10.4# Sun Jul 24 07:51:44 2005# Target Board: 依元素科技发展有限公司 DigitalSword-HL-SPⅢ评估板 Rev 1.0# Family: spartan3# Device: XC3S200# Package: PQ208# Speed Grade: -4# Processor: Microblaze# System clock frequency: 50.000000 MHz# Debug interface: On-Chip HW Debug Module# On Chip Memory : 8 KB# ############################################################################## PARAMETER VERSION = 2.1.0PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = INPORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = OUTPORT sys_clk_pin = sys_clk_s, DIR = IN, SIGIS = CLKPORT sys_rst_pin = sys_rst_s, DIR = INPORT Push_Buttons_6Bit_GPIO_in = Push_Buttons_6Bit_GPIO_in, VEC = [0:5], DIR = IPORT SEGLED_digit = SEGLED_digit, VEC = [0:4], DIR = OPORT SEGLED_segment = SEGLED_segment, VEC = [0:7], DIR = OBEGIN microblazePARAMETER INSTANCE = microblaze_0PARAMETER HW_VER = 4.00.aPARAMETER C_DEBUG_ENABLED = 1PARAMETER C_NUMBER_OF_PC_BRK = 2PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1BUS_INTERFACE DLMB = dlmbBUS_INTERFACE ILMB = ilmbBUS_INTERFACE DOPB = mb_opbBUS_INTERFACE IOPB = mb_opbPORT CLK = sys_clk_sPORT DBG_CAPTURE = DBG_CAPTURE_sPORT DBG_CLK = DBG_CLK_sPORT DBG_REG_EN = DBG_REG_EN_sPORT DBG_TDI = DBG_TDI_sPORT DBG_TDO = DBG_TDO_sPORT DBG_UPDATE = DBG_UPDATE_sENDBEGIN opb_v20PARAMETER INSTANCE = mb_opbPARAMETER HW_VER = 1.10.cPARAMETER C_EXT_RESET_HIGH = 0PORT SYS_Rst = sys_rst_sPORT OPB_Clk = sys_clk_sENDBEGIN opb_mdmPARAMETER INSTANCE = debug_modulePARAMETER HW_VER = 2.00.aPARAMETER C_MB_DBG_PORTS = 1PARAMETER C_USE_UART = 1PARAMETER C_UART_WIDTH = 8PARAMETER C_BASEADDR = 0x41400000 PARAMETER C_HIGHADDR = 0x4140ffffBUS_INTERFACE SOPB = mb_opbPORT OPB_Clk = sys_clk_sPORT DBG_CAPTURE_0 = DBG_CAPTURE_s PORT DBG_CLK_0 = DBG_CLK_sPORT DBG_REG_EN_0 = DBG_REG_EN_sPORT DBG_TDI_0 = DBG_TDI_sPORT DBG_TDO_0 = DBG_TDO_sPORT DBG_UPDATE_0 = DBG_UPDATE_s ENDBEGIN lmb_v10PARAMETER INSTANCE = ilmbPARAMETER HW_VER = 1.00.aPARAMETER C_EXT_RESET_HIGH = 0PORT SYS_Rst = sys_rst_sPORT LMB_Clk = sys_clk_sENDBEGIN lmb_v10PARAMETER INSTANCE = dlmbPARAMETER HW_VER = 1.00.aPARAMETER C_EXT_RESET_HIGH = 0PORT SYS_Rst = sys_rst_sPORT LMB_Clk = sys_clk_sENDBEGIN lmb_bram_if_cntlrPARAMETER INSTANCE = dlmb_cntlrPARAMETER HW_VER = 1.00.bPARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fffBUS_INTERFACE SLMB = dlmbBUS_INTERFACE BRAM_PORT = dlmb_port ENDBEGIN lmb_bram_if_cntlrPARAMETER INSTANCE = ilmb_cntlrPARAMETER HW_VER = 1.00.bPARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fffBUS_INTERFACE SLMB = ilmbBUS_INTERFACE BRAM_PORT = ilmb_port ENDBEGIN bram_blockPARAMETER INSTANCE = lmb_bramPARAMETER HW_VER = 1.00.aBUS_INTERFACE PORTA = ilmb_portBUS_INTERFACE PORTB = dlmb_portENDBEGIN opb_uartlitePARAMETER INSTANCE = RS232PARAMETER HW_VER = 1.00.bPARAMETER C_BAUDRATE = 9600PARAMETER C_DATA_BITS = 8PARAMETER C_ODD_PARITY = 0PARAMETER C_USE_PARITY = 0PARAMETER C_CLK_FREQ = 50000000PARAMETER C_BASEADDR = 0x40600000 PARAMETER C_HIGHADDR = 0x4060ffffBUS_INTERFACE SOPB = mb_opbPORT OPB_Clk = sys_clk_sPORT RX = fpga_0_RS232_RXPORT TX = fpga_0_RS232_TXENDBEGIN opb_gpioPARAMETER INSTANCE = Push_Buttons_6Bit PARAMETER HW_VER = 3.01.bPARAMETER C_GPIO_WIDTH = 6PARAMETER C_ALL_INPUTS = 1PARAMETER C_BASEADDR = 0x40000000 PARAMETER C_HIGHADDR = 0x4000ffffBUS_INTERFACE SOPB = mb_opbPORT OPB_Clk = sys_clk_sPORT GPIO_in = Push_Buttons_6Bit_GPIO_in ENDBEGIN opb_timerPARAMETER INSTANCE = TimerPARAMETER HW_VER = 1.00.bPARAMETER C_BASEADDR = 0x41c00000PARAMETER C_HIGHADDR = 0x41c0ffffBUS_INTERFACE SOPB = mb_opbPORT OPB_Clk = sys_clk_sPORT CaptureTrig0 = net_gndENDBEGIN opb_7segledPARAMETER INSTANCE = SEGLEDPARAMETER HW_VER = 1.00.aPARAMETER C_BASEADDR = 0x800a0000PARAMETER C_HIGHADDR = 0x800affffBUS_INTERFACE SOPB = mb_opbPORT digit = SEGLED_digitPORT segment = SEGLED_segmentPORT OPB_Clk = sys_clk_sEND。