KSZ9031RNX datasheet
KSZ8795 Evaluation Board 用户指南说明书
KSZ8795-POE-EVAL Board(KSZ8795CLX+KSZ9031RNX)Demo Evaluation Board User’s GuideKSZ8795 Family Integrated 5-port Managed Switch with 4 10/100 Copper Ports and Port 5 Gigabit port Rev 1.0 January 2015Table of contents1.0 Introduction (4)2.0 Features (4)3.0 Evaluation Kit Contents (4)4.0 Hardware Description (5)4.1 Strap in Mode (6)4.2 Feature Setting Jumpers (7)4.3 SPI Mode (8)4.4 10/100 Ethernet Ports (8)4.4 10/100/1000 Gigabit Ports (8)4.5 LED indicators (9)5.0 Software Tools Description (10)5.1 Introducing Application Software Tools (10)5.2 Window Driver Installation First (10)5.3 Installation Application Software Tools (13)5.4 DOS SPI Tool (15)5.5 Window SPI Software Tool (16)5.6 LinkMD Software Tool (17)6.0 Reference Documents (19)7.0 Bill of Material (19)8.0 Schematics (19)List of Figures and TablesFigure 1 KSZ8795-POE-EVAL Board (5)Figure 2 KSZ8795-POE-EVAL Board Block Diagram (6)Table 1 General Setting Jumpers (7)Table 2 Power Setting Jumpers (7)Table 3 LED Modes (9)Revision History1.0 IntroductionThe KSZ8795 family is Micrel Operations new generation integrated 5-port switch with Gigabit up-link. The KSZ8795CLX is one of KSZ8795 family. KSZ8795CLX contains four MAC/PHYs for four copper ports and one GMAC5 interface with configurable GMII/RGMII/MII/RMII interfaces. The device had been designed with cost sensitive systems in mind but still offers a multitude of new features such as port based security ACL filtering, 802.1az EEE, LinkMD and so on. Also support port and tag based VLAN; QoS priority; SPI and MDC/MDIO interfaces for the registers access. The KSZ8795 family is an excellent choice in broadband gateway applications, integrated broadband router applications, industrial automatic, automotive, etc. fields and as a standalone switch. The KSZ8795-POE-EVAL board is designed to allow the user to experience Gigabit up-link with KSZ9031 Gigabit PHY to Gigabit port of any processor board directly, and can provide PoE PSE power to other four ports. Other rich feature set can be evaluated on this board. The evaluation board is highly configurable and easy to use.2.0 Features∙Micrel KSZ8795 Integrated 5-port 10/100 Managed Ethernet Switch∙ 4 RJ-45 Jacks for 10/100Base-T/TX Ethernet LAN with Corresponding Isolation Magnetics. ∙Auto MDI/MDIX on All Ports.∙Port 5 SW5-RGMII hook-up with a KSZ9031RNX GPHY and provide a Gigabit port.∙Easily set to different VDDIO of 3.3V, 2.5V and 1.8V by jumpers.∙ 1 USB Port Interface Configurable to Emulate an SPI Interface for all registers access by using Window GUI and DOS based software tools.∙ 2 LEDs per Port with 5 LED sets to indicate the Status and Activity for 4 fast Ethernet ports and1 Gigabit port.∙The board powered can be used by a 12V DC power supply.3.0 Evaluation Kit ContentsThe KSZ8795-POE-EVAL Evaluation kit includes the following:∙KSZ8795-POE-EVAL Evaluation Board Rev. 1.x∙KSZ8795-POE-EVAL Ev aluation Board User’s Guide Rev 1.x∙Micrel SPI Configuration Software tools∙KSZ8795-POE-EVAL Evaluation Board Schematics and BOM∙KSZ8795-POE-EVAL PCB file, Gerber file and IBIS model∙The software, reference schematics and other design information will be found in the Design Kit (Design Package) of the KSZ8795 Ethernet switch products on Micrel website.(Contact your Micrel FAE for the latest schematic).∙One 12V DC power supply.∙The USB cable is not included.4.0 Hardware DescriptionThe KSZ8795-POE-EVAL evaluation board is in a compact form factor and can sit on a bench near a computer with USB connector. There are two options for configuration: strap in mode; SPI mode and Strap-in mode that is easily done with on board jumper options. SPI mode is accomplished through a built in USB port interface. You can configure the KSZ8795 device on board by the USB port. Using Micrel SPI software and your PC, you can access the KSZ8795’s full feature set registers by the USB to SPI interface. The board also features RGMII to hook up a KSZ9031RNX as a Gigabit uplink for Gigabit port 5.The KSZ8795-POE-EVAL evaluation board is easy to use. There are programmable LED indicators for link and activity on all ports and a power LED. A manual reset button allows the user to reset the board without removing the power plug. A standard 12VDC power supply can be used by the power jack so that the user can supply power from any 110-240 Volt AC wall or bench socket.Figure 1 KSZ8795-POE-EVAL BoardFigure 2 KSZ8795-POE-EVAL Board Block Diagram4.1 Strap in ModeStrap in configuration mode is the quickest and easiest way to get started. In the default mode, the KSZ8795 acts as a stand-alone 4 port switch and one RGMII up-link. The user has to simply set the board’s configuration jumpers to the desired settings and apply power to the board. The user can also change jumper settings while power is applied to the board and press the convenient manual reset button for the new settings to take effect. Note that even if there is no external strap in values are set, internal pull up and pull down resistors will set the KSZ8795 default configuration. Section 4.1.1 covers each jumper on the board and describes its function.The KSZ8795 will start automatically after power up or reset.4.2 Feature Setting JumpersThe evaluation board provides jumpers to allow the user to easily set strap in configurations for the KSZ8795. Tables below describe the jumpers and their functions in the open or closed state.Table 1 General Setting JumpersTable 2 Power Setting Jumpers4.3 SPI ModeFrom SPI interface to the KSZ8795, use a USB to SPI converter that allows accessing all of the KSZ8795 features and registers. The user can easily access the SPI interface using a computer connected to the evaluation board’s USB port interface. Micrel provides a Windows GUI based program for the user to evaluate the KSZ8795’s full feature set. KSZ8795’s SP I interface will be able to access all static MAC table, the VLAN table, dynamic MAC address table, the MIB counters and all enhanced features.To prepare the KSZ8795CLXD-EVAL board for SPI mode configuration follow these steps:1. Copy the Micrel provided SPI interface software on your computer.2. KSZ8795-POE-EVAL board is fixed at SPI slave mode.3.Connect the computer’s USB port to the KSZ8795CLXD-EVAL board with a USB port cable.4.Connect the 12V DC power supply to J7 of the KSZ8795-POE-EVAL board.5.Open the Windows and navigate to the directory where the Window SPI file is stored. Click itsicon to invoke the software.6.Program the desired settings using the Micrel SPI interface software. See the softwareoperation description section for details.4.4 10/100 Ethernet PortsThere are five 10/100 Ethernet ports on the KSZ8795-POE-EVAL board. The ports J1, J2, J3 and J4 are the standard RJ45 connectors and using CAT-5 cables. Each port can be used as either an uplink or downlink. All ports support Auto-MDI/MDIX, so there is no need for cross over cables. J1 = RJ45 connector for port 1J2 = RJ45 connector for port 2J3 = RJ45 connector for port 3J4 = RJ45 connector for port 4JM1, JM2, JM3, JM4 and JS1, JS2, JS3, JS4 special connectors for Automotive used only.4.4 10/100/1000 Gigabit PortsThere is one KSZ9031RNX with 10/100/1000 Ethernet ports on the KSZ8795-POE-EVAL board. The ports RJ1 is the standard RJ45 connectors for port 5 and can connect to one Gigabit port of a processor platform by using CAT-5 cables. The port supports Auto-MDI/MDIX, so there is no need for the cross over cables.RJ1 = RJ45 connector for port 54.5 LED indicatorsEthernet Port LEDsThere are four columns of LED indicators on the board, one column for each of the four ports. The LED indicators are programmable to two different modes. You can program the LED mode through Register 11 bits [5:4]. The mode definitions are shown in Table below. There are two LEDs per port. The naming convention is “LEDx_y”, where “x” is the port number, and “y” is the number of the LED for that port.Table 3 LED ModesLED1_y are assigned to port 1LED2_y are assigned to port 2LED3_y are assigned to port 3LED4_y are assigned to port 4Gigabit Port LEDThe board also has a Gigabit port LED D3 to indicate the link-up speed for port 5.Green Color: 1G LinkRed Color: 100M LinkOrange Color: 10M LinkPower LEDThe board also has a power LED D7 for the 3.3V power supply. D7 LED indicates Power on and off.5.0 Software Tools Description5.1 Introducing Application Software ToolsThe Design Kit provides some software tools to support SPI access for all registers andMDC/MDIO access for MIIM registers. The installation file is located folders in the software tool directory within subdirectory of Window SPI_MDIO_Tools, this file name is MicrelSwitchPhyTool_x.xx.msi.5.2 Window Driver Installation FirstBefore use the Window based application software tool, the support drivers need to be installed to PC/Laptop first and this installation is just one times only. When connect one standard USB cable with type A and type B connectors between the evaluation board and PC computer first time, the Found New Hardware Wizard window will pop-up and then follow the instructions step by step as below.. Choose ‘No, not this time’ radio button and click the ‘Next’ button.Choose the ‘Install from a list or specific location (Advanced)’ radio button and click the ‘Next’ button.Click the ‘Include this location in the search’ check box, and use ‘Browse’ button to select the‘C:\MicrelEthernetChipConfig\D2XXDriver\CDM 2.02.04 WHQL Certified’ directory and click the ‘Next’ button. The window will install the drivers from this location.Click ‘Finish’ button. The Window will install another driver called ‘USB Serial Converter B’. After the drivers installed, Window Device Manager will show ‘USB Serial Converter A’ and ‘USB Serial Converter B’ as below figure. That means the installation successful.5.3 Installation Application Software ToolsIn the Design Kit, the installation file is located folders in the software tool directory within subdirectory of Window SPI_MDIO_Tools, this file name is MicrelSwitchPhyTool_x.xx.msi. Double click this file name, an installation Window will pop-up and then follow the instructions step by step as below.In this pop-up Window, this application software tools can be assigned to default Micrel directory in above window shown or is assigned to a specified folder what you want. Click ‘Next’ button, next Window will pop-up as below.Click ‘Next’ button to start the installation.Click ‘Close’ button to finish the installation. All application software tools are installed into the default Micrel directory or assigned directory in installation as below.5.4 DOS SPI ToolThis is a simple and powerful tool to access all register. The tool located in the default or assigned folder in the installation. There is an USBSPI.exe file which can be executed directly by clicking its icon. Before run the software tool, the SPI jumper setting should follows Table 5 in 4.3 SPI mode section and USB cable is plugged in both KSZ8795-POE-EVAL board and PC/Laptop. After click its icon, a DOS Window will pop up as follow:T ype a ‘help’ and press Enter, all commands will display as follows,For Read or Write registers, reg is the offset address of the register, value is Hex number.The ‘run file’ command can execute multiple commands by a script file, the script file is a .txt file which can be created by any edit tools.run xxxx.txt //will run the .txt script file.5.5 Window SPI Software ToolThis is a powerful tool to access all register. The tool located in the default or assigned folder in the installation. There is a MicrelSwitchConfigApp.exe file which can be executed directly by clicking its icon.Before run the software tool, the SPI jumper setting should follows Table 5 in 4.3 SPI mode section and USB cable should be plugged in both KSZ8795CLXD-EVAL board and PC/Laptop. After click its icon, a GUI Window will pop up as follow:The default is SPI interface to do switch configuration. From the device selection window to select any devices then press ‘Continue’ button or click ‘Continue’ button directly, the software tool can detect devices automatically. A control Window will be pop up as follow.All register can be read/ written in the window.The control Window includes all application registers, static MAC table, VLAN table, dynamic table and MIB counters that are supported by SPI. The software can save and open the configuration file as a back-up.5.6 LinkMD Software ToolThis is a simple and powerful tool to test Micrel LinkMD feature. The tool is in the installation folder. There is a LinkMDUSB.exe file which can be executed directly by clicking its icon.After click the icon of this executed file, a GUI Window will pop up as follow:Select one part and clik ‘Next’ button, using SPI interface and clik ‘Next’ button again, pop up a test windown as below:An example for CAT-5 cable diagnostic with open on port 1, just clic k ‘TEST’ button, a test result shows as below.The test result shows both MDIX mode for pair 3-6 and MDI mode for 1-2 pair. The detail LinkMD diagnostic testing configuration is described in the datasheet.6.0 Reference DocumentsKSZ8795CLX Data Sheets (Contact Micrel for Latest Datasheet), KSZ8795 Design Package includes all design information as a Design kit. The Design Kit will be found on Micrel website (Contact Micrel for the updates).7.0 Bill of MaterialPlease see the detail BOMs in the BOM folder of the hardware design package for theKSZ8795-POE-EVAL Boards.8.0 SchematicsPlease see the schematics of the evaluation board and reference design in the schematicsfolder of the hardware design package (Design kit) for the KSZ8795-POE-EVAL Board. Magnetics Vendors:See the datasheets for the recommendation.MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/ The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to thecustomer.Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a signi ficant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damagesresulting from such use or sale.© 2015 Micrel, Incorporated.。
KSA1010YTU;KSA1010OTU;KSA1010RTU;KSA1010Y;中文规格书,Datasheet资料
PNP Epitaxial Silicon TransistorAbsolute Maximum Ratings T C =25°C unless otherwise noted* PW ≤300µs, Duty Cycle ≤10%Symbol ParameterValue Units V CBO Collector-Base Voltage - 100V V CEO Collector-Emitter Voltage - 100V V EBO Emitter-Base Voltage - 7V I C Collector Current (DC) - 7A I CP *Collector Current (Pulse)- 15A I B Base Current- 3.5A P C Collector Dissipation (T C =25°C) 40W Collector Dissipation (T a =25°C) 1.5W T J Junction Temperature 150°C T STGStorage Temperature- 55 ~ 150°CKSA1010High Speed High Voltage Switching•Industrial Use•Complement to KSC23341.Base2.Collector3.Emitter1TO-220Pulse Test: PW≤350µs, Duty Cycle≤2% h FE Classification V BE(off) = 5V, L = 180µH ClampedV CEX(sus)2Collector-Emitter Sustaining Voltage I C = - 10A, I B1 = - 1AI B2 = 0.5A, V BE(off) = 5VL = 180µH, Clamped- 100VI CBO Collector Cut-off Current V CB = - 100V, I E = 0- 10µA I CER Collector Cut-off Current V CE = - 100V, R BE = 51ΩT C = 125°C- 1mAI CEX1Collector Cut-off Current V CE = - 100V, V BE(off) = 1.5V- 10µA I CEX2Collector Cut-off Current V CE = - 100V, V BE(off) = 1.5VT C = 125°C- 1mAI EBO Emitter Cut-off Current V EB = - 5V, I C= 0- 10uAh FE1 h FE2 h FE3* DC Current Gain V CE = - 5V, I C = - 0.5AV CE = - 5V, I C = - 3AV CE = - 5V, I C = - 5A404020200V CE(sat)* Collector-Emitter Saturation Voltage I C = - 5A, I B = - 0.5A- 0.6V V BE(sat)* Base-Emitter Saturation Voltage I C = - 5A, I B = - 0.5A- 1.5Vt ON Turn On Time V CC = - 50V, I C = - 5A,I B1 = - I B2 = - 0.5AR L = 10Ω0.5µst STG Storage Time 1.5µs t F Fall Time0.5µsClassification R O Yh FE240 ~ 8060 ~ 120100 ~ 200KSA1010KSA1010DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:TRADEMARKSThe following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body,or (b) support or sustain life, or (c) whose failure to performwhen properly used in accordance with instructions for useprovided in the labeling, can be reasonably expected to result in significant injury to the user.2. A critical component is any component of a life support device or system whose failure to perform can bereasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONS Definition of TermsDatasheet Identification Product Status DefinitionAdvance InformationFormative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.PreliminaryFirst ProductionThis datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.No Identification Needed Full ProductionThis datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.Obsolete Not In ProductionThis datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.A CEx™Bottomless™CoolFET™CROSSVOLT ™DenseTrench™DOME™EcoSPARK™E 2CMOS™EnSigna™FACT™FACT Quiet Series™FAST ®FASTr™FRFET™GlobalOptoisolator™GTO™HiSeC™ISOPLANAR™LittleFET™MicroFET™MICROWIRE™OPTOLOGIC™OPTOPLANAR™PACMAN™POP™Power247™PowerTrench ®QFET™QS™QT Optoelectronics™Quiet Series™SLIENT SWITCHER ®SMART START™STAR*POWER™Stealth™SuperSOT™-3SuperSOT™-6SuperSOT™-8SyncFET™TruTranslation™TinyLogic™UHC™UltraFET ®VCX™STAR*POWER is used under license分销商库存信息:FAIRCHILDKSA1010YTU KSA1010OTU KSA1010RTU KSA1010Y。
赛德凯斯电子KW系列匀胶机配件选型手册说明书
北京赛德凯斯电子有限责任公司KW系列匀胶机配件选型手册2014.11V1版SC-5-7(5mm-7mm)----------------------------------------1 SC-8-10(8mm-10mm)--------------------------------------2 SC-11-13(11mm-13mm)-----------------------------------3 SC-14-18(14mm-18mm)-----------------------------------4 SC-19-23(19mm-23mm)-----------------------------------5 SC-24-28(24mm-28mm一寸片托)-------------------------6 SC-29-33(29mm-33mm)-----------------------------------7 SC-34-38(34mm-38mm)-----------------------------------8 SC-39-43(39mm-43mm)-----------------------------------9 SC-44-48(44mm-48mm)----------------------------------10 SC-49-53(49mm-53mm二寸片托)------------------------11 SC-54-58(54mm-58mm)----------------------------------12 SC-59-63(59mm-63mm)----------------------------------13 SC-64-68(64mm-68mm)----------------------------------14 SC-70-74(70mm-74mm)----------------------------------15 SC-75-79(75mm-79mm三寸片托)------------------------16 SC-80-84(80mm-84mm)----------------------------------17 SC-85-89(85mm-89mm)----------------------------------18 SC-97-101(97mm-101mm四寸片托)----------------------19 SCS-9-13(9mm-13mm)------------------------------------20 SCS-14-18(14mm-18mm盖玻片)--------------------------21 SCS-19-23(19mm-23mm)----------------------------------22 SC-24-28-75-79(载玻片)------------------------------------23 SCL-5-44----------------------------------------------------24 SCH-44-68--------------------------------------------------25 SCH-70-84--------------------------------------------------26 SCH-80------------------------------------------------------27圆片直径：80-84mm 选择片托示意说明KW系列匀胶机配件内部编号i c s C o ., L t d适用于：方片边长范围85-89mm 圆片直径：85-89mm选择片托示意说明KW系列匀胶机配件内部编号n i c s C o ., L t dtL,.oCscino圆片直径：97mm-101mm标准4寸圆片片托选择片托示意说明KW系列匀胶机配件内部编号SC-97-101第 19 頁，共 27 頁适用于：方片边长范围19-23mmSCS-19-23选择片托示意说明KW系列匀胶机配件内部编号北京赛德凯斯电子有限责任公司 第 22 頁，共 27 頁适用于：用于客户定制 边长或直径44mm-68mm之间片子SCH-44-68选择片托示意说明KW系列匀胶机配件内部编号第 25 頁，共 27 頁SCH-70-84适用于：客户定制 边长或直径范围：70-84mm选择片托示意说明KW系列匀胶机配件内部编号第 26 頁，共 27 頁适用于：用于客户定制 边长或直径大于80mm以上片子SCH-80选择片托示意说明KW系列匀胶机配件内部编号第 27 頁，共 27 頁。
CS5361-KZZ;CS5361-KSZ;CS5361-DZZ;CS5361-KZZR;CS5361-KSZR;中文规格书,Datasheet资料
Copyright © Cirrus Logic, Inc. 2005CS5361114 dB, 192 kHz, Multi-Bit Audio A/D ConverterFeaturesz Advanced Multi-bit Delta-sigma Architecture z 24-bit Conversion z 114dB Dynamic Range z -105dB THD+Nz System Sampling Rates up to 192 kHz z 135 mW Power Consumptionz High-pass Filter and DC Offset Calibration z Supports Logic Levels Between 5 and 2.5V z Differential Analog Architecture z Overflow DetectionzPin-compatible with the CS5381General DescriptionThe CS5361 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analog-to-digital conversion, and anti-alias filtering. The CS5361generates 24-bit values for both left and right inputs in serial form at sample rates up to 192kHz per channel.The CS5361 uses a 5th-order, multi-bit, delta-sigma modulator followed by digital filtering and decimation.This removes the need for an external anti-alias filter.The ADC uses a differential architecture which provides excellent noise rejection.The CS5361 is ideal for audio systems requiring wide dy-namic range, negligible distortion, and low noise. These applications include A/V receivers, DVD-R, CD-R, digital mixing consoles, and effects processors.ORDERING INFORMATIONCS5361-KSZ -10° to 70°C 24-pin SOIC Lead Free CS5361-KZZ -10° to 70°C 24-pin TSSOP Lead Free CS5361-DZZ -40° to 85°C 24-pin TSSOP Lead Free CDB5361Evaluation BoardVoltage ReferenceSerial Output InterfaceDigital FilterHighPass FilterHigh Pass FilterDecimation Digital FilterDecimation DAC-+S/HDAC -+S/HAINR+SCLKSDOUT MCLKRST VQ LRCK AINR-AINL+AINL-FILT+I 2S/LJ M/SHPF MODE0MODE1REFGND V L MDIVLP FilterLP Filter∆Σ∆ΣOVFLFEB ‘05TABLE OF CONTENTS1.0 CHARACTERISTICS AND SPECIFICATIONS (4)Specified Operating Conditions (4)Absolute Maximum Ratings (4)Analog Characteristics (CS5361-KSZ/KZZ) (5)Analog Characteristics (CS5361-DZZ) (6)Digital Filter Characteristics (7)DC Electrical Characteristics (10)Digital Characteristics (10)Switching Characteristics - Serial Audio Port (11)2.0 PIN DESCRIPTIONS (14)3.0 TYPICAL CONNECTION DIAGRAM (15)4.0 APPLICATIONS (16)4.1 Operational Mode/Sample Rate Range Select (16)4.2 System Clocking (16)4.2.1 Slave Mode (16)4.2.2 Master Mode (17)4.3 Power-up Sequence (18)4.4 Analog Connections (18)4.5 High-pass Filter and DC Offset Calibration (19)4.6 Overflow Detection (19)4.6.1 OVFL Output Timing (19)4.7 Grounding and Power Supply Decoupling (19)4.8 Synchronization of Multiple Devices (19)5.0 PARAMETER DEFINITIONS (20)6.0 PACKAGE DIMENSIONS (21)7.0 REVISION HISTORY (23)LIST OF FIGURESFigure 1. Single Speed Mode Stopband Rejection (8)Figure 2. Single Speed Mode Transition Band (8)Figure 3. Single Speed Mode Transition Band (Detail) (8)Figure 4. Single Speed Mode Passband Ripple (8)Figure 5. Double Speed Mode Stopband Rejection (8)Figure 6. Double Speed Mode Transition Band (8)Figure 7. Double Speed Mode Transition Band (Detail) (9)Figure 8. Double Speed Mode Passband Ripple (9)Figure 9. Quad Speed Mode Stopband Rejection (9)Figure 10. Quad Speed Mode Transition Band (9)Figure 11. Quad Speed Mode Transition Band (Detail) (9)Figure 12. Quad Speed Mode Passband Ripple (9)Figure 13. Master Mode, Left Justified SAI (12)Figure 14. Slave Mode, Left Justified SAI (12)Figure 15. Master Mode, I2S SAI (12)Figure 16. Slave Mode, I2S SAI (12)Figure 17. OVFL Output Timing (12)Figure 18. Left Justified Serial Audio Interface (13)Figure 19. I2S Serial Audio Interface (13)Figure 20. OVFL Output Timing, I2S Format (13)Figure 21. OVFL Output Timing, Left-Justified Format (13)Figure 22. Typical Connection Diagram (15)Figure 23. CS5361 Master Mode Clocking (17)Figure 24. CS5361 Recommended Analog Input Buffer (18)LIST OF TABLESTable 1.CS5361 Mode Control (16)Table 2.CS5361 Slave Mode Clock Ratios (16)Table 3.CS5361 Common Master Clock Frequencies (17)Table 4.Revision History (23)1.0CHARACTERISTICS AND SPECIFICATIONSAll Min/Max characteristics and specifications are guaranteed over the specified operating conditions. Typical per-formance characteristics and specifications are derived from measurements taken at typical supply voltages and T A = 25°C.SPECIFIED OPERATING CONDITIONSGND = 0V, all voltages with respect to GND.ABSOLUTE MAXIMUM RATINGSGND = 0V, All voltages with respect to GND. (Note 1)Notes: 1.Operation beyond these limits may result in permanent damage to the device.Normal operation is not guaranteed at these extremes.2.Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCRlatch-up.3.The maximum over/under voltage is limited by the input current.ParameterSymbol Min Typ Max Unit DC Power Supplies:Positive Analog Positive Digital Positive LogicVA VD VL 4.753.12.37 5.03.33.3 5.255.255.25V V V Ambient Operating TemperatureCommercial (-KSZ/-KZZ) Automotive (-DZZ)T AC T AA-10-40--7085°C °CParameterSymbol Min Max Units DC Power Supplies:Analog Logic Digital VA VL VD -0.3-0.3-0.3+6.0+6.0+6.0V V V Input Current (Note 2)I in -10+10mA Analog Input Voltage (Note 3)V IN -0.7VA +0.7V Digital Input Voltage(Note 3)V IND -0.7VL +0.7V Ambient Operating Temperature (Power Applied)T A -50+95°C Storage TemperatureT stg-65+150°CANALOG CHARACTERISTICS (CS5361-KSZ/KZZ)Test conditions (unless otherwise specified): Input test signal is a 1kHz sine wave; measurement bandwidth is 10Hz to 20kHz.Notes: 4.Referred to the typical full-scale input voltage.5. Measured between AIN+ and AIN-ParameterSymbolMin Typ Max Unit Single Speed Mode Fs = 48kHzDynamic Range A-weightedunweighted108105114111--dB dBTotal Harmonic Distortion + Noise (Note 4)-1dB -20dB -60dBTHD+N----105-91-51-99--dB dB dB Double Speed Mode Fs = 96kHzDynamic Range A-weightedunweighted40kHz bandwidth unweighted108105-114111108---dB dB dBTotal Harmonic Distortion + Noise (Note 4)-1dB -20dB -60dB40kHz bandwidth -1dBTHD+N-----105-91-51-102-99---dB dB dB dB Quad Speed Mode Fs = 192kHzDynamic Range A-weightedunweighted40kHz bandwidth unweighted108105-114111108---dB dB dBTotal Harmonic Distortion + Noise (Note 4)-1dB -20dB -60dB40kHz bandwidth -1dBTHD+N-----105-91-51-102-99---dB dB dB dB Dynamic Performance for All Modes Interchannel Isolation -110-dB DC AccuracyInterchannel Gain Mismatch -0.1-dB Gain Error -2-2%Gain Drift -100-100ppm/°C Offset Error HPF enabledHPF disabled----0100LSB LSB Analog Input Characteristics Full-scale Input Voltage1.10*VA 1.13*VA1.15*VAVpp Input Impedance (Differential)(Note 5)7.5--k ΩCommon Mode Rejection RatioCMRR-82-dBANALOG CHARACTERISTICS (CS5361-DZZ)Test conditions (unless otherwise specified): Input test signal is a 1kHz sine wave; measurement bandwidth is 10Hz to 20kHz.Parameter Symbol Min Typ Max Unit Single Speed Mode Fs = 48kHzDynamic Range A-weightedunweighted 106103114111--dBdBTotal Harmonic Distortion + Noise(Note 4)-1dB-20dB-60dB THD+N----105-91-51-95--dBdBdBDouble Speed Mode Fs = 96kHzDynamic Range A-weightedunweighted40kHz bandwidth unweighted 106103-114111108---dBdBdBTotal Harmonic Distortion + Noise (Note 4)-1dB-20dB-60dB40kHz bandwidth -1dB THD+N-----105-91-51-102-95---dBdBdBdBQuad Speed Mode Fs = 192kHzDynamic Range A-weightedunweighted40kHz bandwidth unweighted 106103-114111108---dBdBdBTotal Harmonic Distortion + Noise (Note 4)-1dB-20dB-60dB40kHz bandwidth -1dB THD+N-----105-91-51-102-95---dBdBdBdBDynamic Performance for All ModesInterchannel Isolation-110-dB Interchannel Phase Deviation-0.0001-Degree DC AccuracyInterchannel Gain Mismatch-0.1-dB Gain Error-5-5% Gain Drift-100-100ppm/°COffset Error HPF enabledHPF disabled ----100LSBLSBAnalog Input CharacteristicsFull-scale Input Voltage 1.07*VA 1.13*VA 1.18*VA Vpp Input Impedance (Differential)(Note 5)7.5--kΩCommon Mode Rejection Ratio CMRR-82-dBDIGITAL FILTER CHARACTERISTICSNotes: 6.The filter frequency response scales precisely with Fs.7.Response shown is for Fs equal to 48kHz. Filter characteristics scale with Fs.ParameterSymbolMinTypMaxUnitSingle Speed Mode (2kHz to 51kHz sample rates)Passband (-0.1dB)(Note 6)0-0.47Fs Passband Ripple -0.1-0.035dB Stopband(Note 6)0.58--Fs Stopband Attenuation-95--dB Total Group Delay (Fs = Output Sample Rate)t gd-12/Fs -s Interchannel Phase Deviation-0.0001-DegDouble Speed Mode (50kHz to 102kHz sample rates)Passband (-0.1dB)(Note 6)0-0.45Fs Passband Ripple -0.1-0.035dB Stopband(Note 6)0.68--Fs Stopband Attenuation-92--dB Total Group Delay (Fs = Output Sample Rate)t gd-9/Fs -s Interchannel Phase Deviation-0.0001-DegQuad Speed Mode (100kHz to 204kHz sample rates)Passband (-0.1dB)(Note 6)0-0.24Fs Passband Ripple -0.1-0.035dB Stopband(Note 6)0.78--Fs Stopband Attenuation-92--dB Total Group Delay (Fs = Output Sample Rate)t gd-5/Fs -s Interchannel Phase Deviation -0.0001-DegHigh-pass Filter Characteristics Frequency Response -3.0dB -0.13dB (Note 7)-120--Hz Hz Phase Deviation @ 20Hz(Note 7)-10-Deg Passband Ripple --0dB Filter Settling Time105/FssFigure 1. Single Speed Mode Stopband Rejection Figure 2. Single Speed Mode Transition BandFigure 3. Single Speed Mode Transition Band (Detail )Figure 4. Single Speed Mode Passband RippleFigure 7. Double Speed Mode Transition Band (Detail)Figure 8. Double Speed Mode Passband RippleFigure 9. Quad Speed Mode Stopband Rejection Figure 10. Quad Speed Mode Transition BandA m p l i t u d e (dB )F re q u e n c y (n o rm a liz e d to F s )A m p li t u d e (d B )F re q u e n c y (n o rm a liz e d to F s )Figure 11. Quad Speed Mode Transition Band (Detail)Figure 12. Quad Speed Mode Passband RippleF re q u e n c y (n o rm a liz e d to F s )A m p l i t u d e (dB )A m p l i t u d e (dB )F re q u e n c y (n o rm a liz e d to F s )DC ELECTRICAL CHARACTERISTICSGND = 0V, all voltages with respect to ground. MCLK=12.288MHz; Master Mode.Notes:8.Power Down Mode is defined as RST = Low with all clocks and data lines held static.9.Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical ConnectionDiagram.DIGITAL CHARACTERISTICSTHERMAL CHARACTERISTICSParameterSymbol Min Typ Max Unit Power Supply Current VA = 5V (Normal Operation)VL,VD = 5V VL,VD = 3.3V I A I D I D ---17.52214.521.527.517mA mA mA Power Supply CurrentVA = 5V (Power-Down Mode) (Note 8)VL,VD = 5VI A I D --100100--µA µA Power Consumption (Normal Operation)VA, VD, VL = 5V VA = 5V, VL, VD = 3.3V(Power-Down Mode)------1981351243161-mW mW mW Power Supply Rejection Ratio (1 kHz)(Note 9)PSRR-65-dB V Q Nominal Voltage Output ImpedanceMaximum allowable DC current source/sink --- 2.5250.01---Vk ΩmA Filt+ Nominal Voltage Output ImpedanceMaximum allowable DC current source/sink---5150.01---Vk ΩmAParameterSymbol Min Typ Max Units High-Level Input Voltage (% of VL)V IH 70%--V Low-Level Input Voltage(% of VL)V IL --30%V High-Level Output Voltage at I o = 100µA (% of VL)V OH 70%--V Low-Level Output Voltage at I o = 100µA (% of VL)V OL --15%V OVFL Current SinkI ovfl -- 4.0mA Input Leakage Current (all pins except SCLK and LRCK)I in -10-10µA Input Leakage Current (SCLK and LRCK)I in-25-25µAParameterSymbolMin Typ Max Unit Allowable Junction Temperature--135°C Junction to Ambient Thermal Impedance(Multi-layer PCB) TSSOP (Multi-layer PCB) SOIC (Single-layer PCB) TSSOP (Single-layer PCB) SOICθJA-TM θJA-SM θJA-TS θJA-SS----706010580----°C/W °C/W °C/W °C/W分销商库存信息:CIRRUS-LOGICCS5361-KZZ CS5361-KSZ CS5361-DZZ CS5361-KZZR CS5361-KSZR。
ARTIX-7 FPGA 开发平台 用户手册说明书
ARTIX-7FPGA开发平台用户手册AX7203REV1.2版芯驿电子科技（上海）有限公司黑金动力社区目录一、开发板简介 (5)二、FPGA核心板 (8)(一)简介 (8)(二)FPGA (9)(三)有源差分晶振 (11)(四)DDR3 (13)(五)QSPI Flash (17)(六)LED灯 (19)(七)复位按键 (20)(八)JTAG接口 (20)(九)电源接口 (21)(十)扩展接口 (22)(十一)电源 (28)(十二)结构图 (30)三、扩展板 (31)(一)简介 (31)(二)千兆以太网接口 (32)(三)PCIe x4接口 (35)(四)HDMI输出接口 (37)(五)HDMI输入接口 (39)(六)SD卡槽 (41)(七)USB转串口 (42)(八)EEPROM24LC04 (43)(九)扩展口 (44)(十)JTAG接口 (48)(十一)XADC接口（默认不安装） (49)(十二)按键 (51)(十三)LED灯 (52)(十四)供电电源 (53)黑金ARTIX-7系列的高端FPGA开发平台（型号：AX7203）正式发布了，为了让您对此开发平台可以快速了解，我们编写了此用户手册。
这款ARTIX-7FPGA开发平台采用核心板加扩展板的模式，方便用户对核心板的二次开发利用。
在底板设计上我们设计了丰富的外围接口，比如一路PCIex4接口，两路千兆以太网接口，一路HDMI输出接口，一路HDMI输入接口，Uart接口，SD卡接口等等。
满足用户各种PCIe高速数据传输，视频图像处理和工业控制的要求，是一款"全能级“的FPGA开发平台。
为高速视频传输，网络和PCIe通信及数据处理的前期验证和后期应用提供了可能。
相信这样的一款产品非常适合从事FPGA开发的学生、工程师等群体。
一、开发板简介在这里，对这款AX7203FPGA开发平台进行简单的功能介绍。
开发板的整个结构，继承了我们一贯的核心板+扩展板的模式来设计的。
nichicon FW series DATA SHEET
3300
332 10 × 20 1170 12.5 × 20 1420 12.5 × 25 1700 16 × 25 1950 16 × 35.5 2220 18 × 35.5 2360 20 × 40 2700 25 × 50 2900
4700
472 12.5 × 20 1350 12.5 × 25 1800 16 × 25 2100 16 × 31.5 2360 18 × 35.5 2490 20 × 40 2900 22 × 50 3400
Series name Type
Please refer to page 21, 22, 23 about the formed or taped product spec. Please refer to page 3 for the minimum order quantity.
Dimension table in next page.
Printed with black color letter on Gold sleeve.
D+ MAX. B P ± 0.5
Radial Lead Type
Sleeve (P.E.T.)
Bd
Pressure relief vent
(B 6.3up)
L+ MAX.
15MIN
4MIN
(mm)
BD
5
6.3
tan δ
Rated voltage (V) tan δ (MAX.)
6.3 0.28
10 0.24
16 0.20
25 0.16
35 0.14
50 0.12
For capacitance of more than 1000µF, add 0.02 for every increase of 1000µF.
TL-4096UCL Line scan camera Instruction Manual
1/ 18(ver.0.3) Line scan cameraInstruction ManualModel: TL-4096UCLTAKENAKA SENSOR GROUPTAKENAKA SYSTEM CO.,LTD.□H e a d O f f i c e86-66 Nomizo-cho Otsuka Yamashina-ku 607-8135 Kyoto JAPANTEL:+81-75-593-9300 FAX +81-75-593-9790□C a m e r a D e p t. 4F Matsumasa Bld.1-17-14 Ogaya Otsu Shiga 520-2144 JAPANTEL:+81-77-545-4331 FAX +81-77-545-4335□I mag e Inspect ion Dept.86-66 Nomizo-cho Otsuka Yamashina-ku 607-8135 Kyoto JAPANTEL:+81-75-593-9300 FAX +81-75-593-9790□T o k y o O f f i c e 2F MK Bldg. 2-2-19 Sotokanda Chiyoda-ku 101-0021 Tokyo JAPANTEL :+81-3-3255-0361FAX:+81-3-3255-0362TAKENAKA SYSTEM CO.,LTD. URL http://www.takex-system.co.jp/2 / 18 Table of Contents1. Outline (3)2. Features (3)3.Applications (3)4. CCD image sensor ........................................... (3)5.Specifications (4)6. Camera I/O (4)6-1. Connector pin assignment of the Power connector6-2. Connector pin assignment of the Camera Link connector7. How to change settings (6)8. Timing chart (7)9. Serial communication protocol (8)10. Exposure control (12)11. Setup steps of Hyper terminal (13)12. Notes (17)13. External dimensions (18)3 / 181. Outline● CCD line scan camera with 4096 pixels of image sensor and of 50MHz data rate. ● Video signal is output complying with Camera Link standard (Base Configuration).2. Features● It can perform high-speed inspection with 4096 image pixels at 50MHz data rate.● GAIN and OFFSET characteristics, 8/10 bit format etc. can be easily changed with RS232C command from capture board.● The equipment operates with a single DC12V power source.● Reduction in size and weight has been realized by adopting original circuit and mechanism design. ● Since the output signal level hardly vary among the ODD and EVEN pixels, It can display crisp image. ●Exposure control function is incorporated.3. Applications● Image processing device for Image inspection.● Foreign substance detector on high-speed production line ● Surface inspection apparatus of sheet-like object . ●Pinhole detector4. CCD image sensorThe CCD image sensor Is characterized by 10μm square sized pixel, effective 4096 pixels, and high-speed and high-sensitivity characteristic features.Charges accumulated in single-row photo diodes are output thorough two shift registers, respectively.(No.1 for ODD numbered charges, No.2 for EVEN numbered charges) Each shift register operates at the rate of 25MHz.D 2PORT A Block diagram of CCDdevice D 2D 2D 7D 7S 1S 2S 3S 5D 7D 7D 9D 9D 9S 5S 5S 5Photo diode Shift gate CCD analog shift register Shift gate CCD analog shift register Output buffer OS1PORT B OS2Output buffer 1～4095(ODD)2～4096(EVEN)Spectral responsivity4 / 185. Specifications6. Camera I / O6-1 Power connectorConnector panelCamera Link connectorPower connectorPower indicatorPower connector pin assignment654321Power connector (HR10A-7P-6S HIROSE) (Pin arrangement viewed from the outside of the camera)5 / 186-2 Camera Link connectorConforming cable 3M madeCf. 14B26-SZLB-＊00-0LC (＊m)※14B26-SZ3B-＊00-04C (＊m)※Flex resistance cableBit assignment of Base Configuration8 Bit: 10Bit:1261413Camera Link connector pin-out6 / 187. How to change settingsThe ODD/EVEN video signal gain and the camera gain are changeable as needed by removing the camera cover,.7-1 Fine adjustment of ODD/EVEN video signal gainGain adjustment of ODD/EVEN video signal is not normally needed, as it has been set before shipment. However, when it is needed, make a fine adjustment following the diagram below.7-2 How to change camera GAINThe camera gain has been set to “×4” as a factory default. It can double the gain using the built-in GAIN switch.Select “×1” when high-quality image is needed, and select “×8” when high sensitivity is needed even if image quality degrades. Select “×2 to ×6” depending on the degree.SW No.8: ON EXT SYNCOFF AUTO EXT SYNC(When the period of EXT SYNC is less than 1msec, it is automatically changed to INT SYNC.)OFF ← VR1: Pixel No.2 to 4096 (EVEN number) Fine control volume for gain7 / 188. Timing chart000STROBE (25MHz)EX SYNC In (CC1IN)LINE VALIDPIXEL DATA PORT A (OS1)1～4095(ODD)Dummy Signal(16pixels)1Line Output Period (2074CLOCK)TL-4096UCLTiming Chart0059clock8C L OC KPIXEL DATA PORT B (OS2)2～4096(EVEN)000000Effective Data period9. Serial communication protocolOperation under the RS232C communication(1)Selection of output bit format 8/10 bit(2)SYNC system switchingAUTO When EXT SYNC is not designated, it automatically switches to INT SYNC.EXT.SYNC EXT. SYNC operation onlyINT. SYNC INT. SYNC operation only※SYNC period is determined from the following equation.SYNC period = Minimum period + n ×aWhereInternal sync(sync=2) n= expt (exposure time)a= 12.8μsec …10.24μsec …(3) Exposure control system switching (Refer to the time chart on P.12)Line period exposure Exposure during periodic timeFixed time exposure Exposure during pre-set timePulse width exposure Exposure during the pulse width of EXT.SYNC(4) GAIN switchingSelection of GAIN position 1,2,3,…………8 ×Selection of GAIN position for each channel ODD/EVEN adjustment(5) Adjustment of OFFSETOFFSET adjustment for each channel (ODD/EVEN)[Network transmission setting]Baud rate :9600bpsData Length :8bitStart Bit :1bitStop Bit :1bitParity :NonXon / Xoff Control :Non[Communication overall]1. ViewingTo view the status of the camera.e.g. Id? <CR> To view the camera ID.2. SettingTo set the status of the camera.e.g. sync=1 <CR> To set SYNC system to EXT.SYNC[Glossary][ ] ……omissible<CR> ……carriage returnN ……arbitrary numeral indicating some valueA ……arbitrary numeral indicating GAIN positionX ……arbitrary numeral indicating channelGain position……GAIN position of the cameraChannel …….Channel to specify the GAIN control device for each CCD output line EEPROM …….EEPROM incorporated in the camera[Notes]・Command name must be lower-case. Upper-case character is not valid.・Input character must be one-byte character. Double-byte character is not valid.・Blank is not valid.・Line feed code is indicated by “CR(0x0D)”. And also “LF(0×0A)” and “CR+LF” are usable. However returning line feed code must be CR only.<When in use of Hyper terminal>・Retyping is required in case of inputting error .(Correction by cursor movement is not valid.)[ Description of exceptional case]＊NG is returned when in command input error or in inputting nonexistent command.e.g. : Command input error (Gain position No. is not designated. )Input: ch1gain=96Output: NGe.g. : Input of nonexistent commandInput: chakeOutput: NG＊NE is returned when in numeric entry error.e.g. : Input error (Input value is beyond the setting range.)Input: gainpos=96Output: NEe.g. : Input error (Input value is beyond the setting range.)Input: ch1gain1=2000Output: NE＊NC is returned when in inputting invalid value under the condition that the ctrl setting (DIP-SW setting) is 0.e.g. :Input: ch1gain=9 (at ctrl=0)Output: NC＊TO is returned when a command input period overruns the time-out period (15 sec.).e.g. :Input: gainpo (No CR entry)Output: TO＊” ? ” at the bottom of Command is omissiblee.g. :Input: idOutput: 010. Exposure controlEXT.SYNC INLVALPIXEL DATAST-1Exposure timeST-1DATA output durationS T-2ST-2DATA output duration ST OU T-1ST OU T-2S T-3ST-0DATA output durationS T OUT -0ST-3DATA output durationST O UT-2Exposure timeExposure time11.Setup steps of Hyper terminal.[Setup of Hyper terminal ]1)Select “Start”→“Programs”→”Accessories”→”Communications”→”Hyper Terminal”2)The windows will appear with the picture below.3)When the next picture appears, enter any name.(e.g. GMA_RS232C)Then click the “OK” button.4)When the next picture appears, select “ COM? ” on Connect using.(? changes depending on the setting of the computer. )Then click the “OK” button.5)When the next picture appears, select each items as follows.(9600,8,None,1,Non)Then click the “OK” button.[Communication settings]Baud Rate : 9600bpsData Length : 8bitStart Bit : 1bitStop Bit : 1bitParity : NonXon/Xoff Control : Non6)The next picture will appear.7)Select [File]→[Properties]8)When the next picture appears, select “Settings” tag.9)When the next picture appears, click the “ASCII Setup” button.10)When the next picture appears, select each items as follows.(☑, ☑, 0, 0,☑, blank, blank)Then click the “OK” button.11)The screen display will return to the screen of 9).Then click the OK button.12)End of setup.Confirm the connection of the camera ,enter “check” on the screen belowand then send it out.If “OK” is displayed on the screen, communication processing has been completed.13) Select “Start”→“Programs”→”Accessories”→”Communications”→”Hyper Terminal”→”(＊1) ”, when to launchthe Hyper terminal again with the same settings after having exited the above screen.＊1………The name which was entered at section 3)11. NotesPrecautions for use■Do not make an impact on the equipment.■Do not lag the equipment with heat insulating agent. If the equipment is covered with heat insulating agent, It produces an increase in teｍperature and it causes the equipment to malfunction.(except for low-temperature environment use)■Take appropriate measures such as heat removal or cold removal to prevent dew condensation, when to move It to the place where temperature difference is extremely severe. Usage with dew condensation causes the equipment to malfunction.■When the equipment is not used for a long time, protect the imaging device from dust or scratch by attaching a lens cap. Do not store the equipment at the following places.・The place where is subjected to a lot of dust and moisture.・The place where is subjected to direct sunlight.・The place where is extremely hot or cold.・The place in the vicinity of an object which generates intensive electromagnetic field.・The place where is subjected to intensive vibration.■Please wipe off the dirt on the lens surface with a cotton swab preventing scratch to the lens surface.Use a soft cloth to clean up the camera body.■Use the equipment with a voltage within the range of specifications and do not connect the equipment to a power source that contains intense noise components. In such case, the image output from the camera may contains noise components.■Do not use the equipment in an environment subject to intense electromagnetic field.In such an environment, malfunction of the camera, disturbance of image and noise are caused by the field.■In case of the high-intensity object, it may happen that even the low intensity part is displayed whitely like a vertical streak above and below the high-intensity object. This phenomenon is called “smear”. However it is the problem specific to CCD and it is not the camera-related failure.■In case of the linear object, jagged picture may be displayed. Also in case of the pinstripe or checkered pattern, annual rings- like picture may be displayed. However these are also the problem specific to CCD and it is not the camera-related failure.■The lighting using a commercial power source may cause a perceptible flicker at higher shutter speed.In cases like this, consider to adjust shutter speed setting of the camera or to use the DC lighting or high- frequency lighting.Attention■All rights on this manual reserved.■The specifications and operational details described in the manual are subject to change for performance improvement or other reasons without notice.12.External dimensions。
Datasheet MLX90614 中文 数据手册 rev008
10-位 PWM 输出模式是连续输出所测物体温度的标准配置，测量物体的温度范围为-20…120 °C，分辨 率为 0.14 °C。PWM 通过修改 EEPROM 内 2 个单元的值，实际上可以根据需求调整至任何温度范围，而这对 出厂校准结果并无影响。
传感器的测量结果均出厂校准化，数据接口为数字式的 PWM 和 SMBus(System Management Bus) 输出。
作为标准，PWM 为 10 位，且配置为-20˚C 至 120 ˚C 内，分辨率为 0.14 ˚C 的连续输出。
传感器出厂默认，上电复位时为 SMBus 通信。
3901090614 Rev 008
PWM 引脚也可配置为热继电器(输入是 To)，这样可以实现简单且性价比高的恒温控制器或温度报警(冰 点/沸点)应用，其中的温度临界值是用户可编程的。在 SMBus 系统里，这个功能可以作为处理器的中断信号， 以此触发读取主线上从动器的值，并确定精度条件。
传感器有两种供电电压选择：5V 或 3V(电池供电)。其中，5V 也可简便的从更高供电电压(例如 8 至 16V)上通过外接元件调制。(具体请参考“应用信息”)
MLX90614 connection to SMBus
图 1: 典型应用电路
2 概述
MLX90614 是一款用于非接触式的红外温度传感器，集成 了红外探测热电堆芯片与信号处理专用集成芯片，全部封装 在 TO-39。
低噪声放大器、17 位 ADC 和强大的 DSP 处理单元的全 集成，使传感器实现了高精度，高分辨率的测量。
科尔摩根AKM 同步伺服电机 选型指南说明书
K O L L M O R G E N | A K o l l m o r g e n C O M PA N Y欢迎来到科尔摩根官方微信科尔摩根3目录u AKM ™ 同步伺服电机4u AKD ™ 伺服驱动器8u AKM ™ 各种选件12u AKM ™ 防水型和食品级防水型电机13u AKM ™ 系统综述14u AKM ™ 图纸和性能数据AKM1x 16AKM2x 20AKM3x24AKM4x 28AKM5x 34AKM6x 40AKM7x 44AKM8x48u L 10 轴承疲劳寿命和轴负载53u 反馈选件56u 抱闸选件60u 伺服电机连接器选件61u 型号命名67u MOTIONEERING ® Online71科尔摩根A K M 同步伺服电机选型指南克服设计、采购和时间障碍科尔摩根明白：帮助原始设备制造商的工程师克服障碍，可以显著提高其工作成效。
因而，我们主要通过如下三种方式来提供帮助：集成标准和定制产品在很多情况下，理想方案都不是一成不变的。
我们拥有专业应用知识，可以根据全面的产品组合来修改标准产品或开发全定制解决方案，从而为设计奠定良好的基础。
提供运动控制解决方案而不仅仅是部件在各公司减少供应商数量和工程人力的过程中，他们需要一家能够提供多种集成解决方案的全系统供应商。
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datasheet_AK09911
ShortDatasheet-E-00 -2-
ቤተ መጻሕፍቲ ባይዱ
2014/1
[AK09911]
3. Table of Contents
1. Features ..............................................................................................................................1 2. Overview..............................................................................................................................2 3. Table of Contents.................................................................................................................3 4. Circuit Configration ..............................................................................................................4 4.1. Block Diagram ..............................................................................................................4 4.2. Block Function ..............................................................................................................4 4.3. Pin Function ..................................................................................................................5 5. Overall Characteristics ........................................................................................................6 5.1. Absolute Maximum Ratings ..........................................................................................6 5.2. Recommended Operating Conditions ..........................................................................6 5.3. Electrical Characteristics ..............................................................................................6 5.3.1. DC Characteristics .................................................................................................6 5.3.2. AC Characteristics .................................................................................................7 5.3.3. Analog Circuit Characteristics ................................................................................8 5.3.4. I2C Bus Interface ....................................................................................................9 6. Function Explanation .........................................................................................................12 6.1. Power States ...............................................................................................................12 6.2. Reset Functions ..........................................................................................................12 6.3. Operation Mode ..........................................................................................................13 7. Example of Recommended External Connection .............................................................14 8. Package.............................................................................................................................15 8.1. Marking .......................................................................................................................15 8.2. Pin Assignment ...........................................................................................................15 8.3. Outline Dimensions.....................................................................................................16 8.4. Recommended Foot Print Pattern ..............................................................................16 9. Relationsip between the Magnetic Field and Output Code ..............................................17
INIC3619_Datasheet_V1.00
Revision 1.00 August 14, 2013 Initio Corporation
Revision 1.00
Page 1 of 28
INIC-3619 Datasheet _______________________________________________________________________________
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INIC-3619 Datasheet _______________________________________________________________________________
INIC-3619 USB 3.0 SATA Bridge Datasheet
Contents
1 Introduction.......................................................................................................................................................................4 1.1 Feature Summary.......................................................................................................................................................4 1.2 Firmware Support..........................
MLX90614红外温度计数据表
传感器测量的温度为视场里所有物体温度的平均值。MLX90614 室温下的标准精度为±0.5ºC。医疗应用版本的 传感器可在人体温度范围内达到±0.1ºC 的精度。
在应用设计中需要注意上述精度是当传感器在热平衡和等温条件下才能保证和达到的。(传感器封装里没有温差) 封装内部的温差会影响温度计测量的精度，如下因素会造成温差：传感器背部的热电子，传感器背部或旁边的 加热器/冷却器， 或当热/冷物体靠近传感器，不仅会加热传感元件，而且会加热温度计封装。
数据表 30/03/2009
MLX90614Axx: Vdd=4.5...5.5V
J1
1 MLX90614
SCL
SCL
U1
Vz
SDA
PWM 2 SDA
Vss 4
Vdd GND
Vdd C1 3
CON1
0.1uF
C1 value and type may differ
in different applications
7.1MLX90614Axx........................................................................................................................................................................................... 7 7.2MLX90614Bxx, MLX90614Dxx ................................................................................................................................................................. 9 8 详细描述......................................................................................................................................................................................................... 11 8.1 模块图表 ................................................................................................................................................................................................. 11 8.2 信号处理原理 .......................................................................................................................................................................................... 11 8.3 模块描述 ................................................................................................................................................................................................. 12
Eaton 9SX11KI 商品说明说明书
Eaton 9SX11KIEaton 9SX UPS, 11 kVA, 10 kW, Input: Hardwired, Outputs: Hardwired, Rack/tower, 6UGeneral specificationsEaton 9SX UPS 9SX11KI74317204021370 cm 44 cm 26 cm 78 kg 2 year CE Marked TUVIEC/EN 62040-1 IEC/EN 62040-2 CE EACEaton 9SX 11000iProduct Name Catalog Number UPCProduct Length/Depth Product Height Product Width Product Weight Warranty Compliances Certifications Model CodeSealed, lead-acidView runtime graphHot-swappable battery modules 2012 V / 7 AhYes Hardwired230V10 kW0.9200/208/220/230/240/250 V +/- 1%Sine wave230V default (200/208/220/230/240/250V) 21Online/Double-conversion11 kVAHardwired/fixed connection230V default (200/208/220/230/240/250V) 50/60 Hz>.99176-276 V (100-276 V with derating)NoBattery typeRuntime graphBattery replacement Battery quantityBattery managementBattery ratingExtended battery capability ReceptacleVoltageWattageOutput power factorOutput voltage rangeOutput waveformOutput nominal voltageVoltage distortion output (linear load) - max Feed typeTopologyVA ratingInput connection Input nominal voltage Nominal frequency Input power factor Input voltage range Includes network card CommunicationABM & Temperaturecompensated chargingmethod (user selectable)Automatic battery testDeep discharge protectionAutomatic recognition ofexternal battery unitsUSB port (HID compliant)Serial port (RS232)Mini terminal block forremote On/OffMini-terminal block forremote power offDry contacts (4 outputs,relay, DB9)40-70 HzNoMultilingual graphical LCD display YesOne slot for optional communication card Eaton Intelligent Power Manager, Eaton Intelligent Power Protector Other3000 m <50 dB at 1 meter 0° to 40°C (32° to 104°F)0-95% non-condensingFree standing model 1YesYes BlackInput frequency range Ethernet interface User interfacePotential free switch contact Expansion slotsSoftware compatibilityType of interface Altitude Noise level Temperature range Relative humidity Construction type Package contents Phase (output)Internal bypass Auto shutdown function Color Power ModuleExtended battery module (EBM)USB cable Serial cableBattery cable with comms for automatic battery cabinet recognition(2) Supports for tower mounting Link plate Safety instructions Quickstart guideEaton Corporation plc Eaton House30 Pembroke Road Dublin 4, Ireland © 2023 Eaton. All rights reserved. Eaton is a registered trademark.All other trademarks areproperty of their respective owners./socialmedia95No1NoEaton UPS and battery services Eaton UPS Services Quick Guide 2021EU declaration of conformity Eaton 9SX UPS Eaton 9SX-9PX UPS - 8-11 kVA-EBM 240V - Installation and user manualEaton 9SX UPS - 5/6/8/11 kVA - DatasheetEfficiency Rack mounting kit Phase (input)Hot swap power BrochuresCompliance informationManuals and user guidesTechnical data sheets。
KSZ9021RN to KSZ9031RNX Migration Guide
KSZ9021RN to KSZ9031RNXMigration GuideRev. 1.1IntroductionThis document summarizes the hardware pin and software register differences for migrating from an existing board design using the KSZ9021RN PHY to a new board design using the KSZ9031RNX PHY. For hardware and software details, consult reference schematic and data sheet of each respective device.Data sheets and support documentations can be found on Micrel’s web site at: .Differences SummaryTable 1 summarizes the supported device attribute differences between KSZ9021RN and KSZ9031RNX PHY devices.Device Attribute KSZ9021RN KSZ9031RNXReduced Gigabit Media Independent Interface (RGMII) RGMII Version 1.3 (power-up default) using off-chip data-to-clock delays with register options to:•Set on-chip (RGMII Version 2.0) delays•Make adjustments and corrections to TXand RX timing pathsRGMII Version 2.0 (power-up default) using on-chip data-to-clock delays with register options to:•Set off-chip (RGMII Version 1.3) delays•Make adjustments and corrections to TXand RX timing pathsTransceiver (AVDDH)Voltage3.3V only 3.3V or 2.5V (commercial temperature only)Digital I/O (DVDDH)Voltage3.3V or 2.5V 3.3V, 2.5V or 1.8VIndirect Register Access Proprietary (Micrel defined) –Extended Registers IEEE defined –MDIO Manageable Device (MMD) RegistersEnergy-Detect Power-Down (EDPD) Mode Not Supported Supported for further power consumptionreduction when cable is disconnected; Disabledas the power-up default and enable using MMDregisterIEEE 802.3azEnergy Efficient Ethernet (EEE) Mode Not Supported Supported with:•Low Power Idle (LPI) mode for1000Base-T and 100Base-TX•Transmit Amplitude reduction for10Base-T (10Base-Te)•Associated MMD registers for EEEWake-on-LAN (WOL) Not Supported Supported with:•Wake-up using detection of Link Status,Magic Packet, or Custom-Packet•PME_N interrupt output signal•Associated MMD registers for WOL Table 1. Summary of Device Attribute Differences between KSZ9021RN and KSZ9031RNXPin DifferencesTable 2 summarizes the pin differences between KSZ9021RN and KSZ9031RNX PHY devices. Pin #KSZ9021RNKSZ9031RNXPin NameType Pin FunctionPin NameTypePin Function1 AVDDH P 3.3V analog V DD AVDDH P 3.3V/2.5V (commercial temp only) analog V DD 12 AVDDH P 3.3V analog V DD AVDDH P 3.3V/2.5V (commercial temp only) analog V DD 13VSS_PSGndDigital groundNC–No connectThis pin is not bonded and can be connected to digital ground for footprint compatibility with the Micrel KSZ9021RN Gigabit PHY.16 DVDDH P3.3V / 2.5V digital V DD DVDDH P 3.3V, 2.5V, or 1.8V digital V DD_I/O 17 LED1 /PHYAD0I/OLED Output:Programmable LED1 OutputConfig Mode:The pull-up/pull-down value is latched as PHYAD[0] during power-up / reset.LED1 /PHYAD0 /PME_N1I/O LED1 output:Programmable LED1 outputConfig mode:The voltage on this pin issampled and latched during the power-up/reset process to determine the value of PHYAD[0].PME_N output:Programmable PME_N output (pin option 1). This pin function requires an external pull-up resistor to DVDDH (digital V DD_I/O ) in a range from 1.0k Ω to 4.7k Ω. When asserted low, this pin signals that a WOL event has occurred.When WOL is not enabled, this pin function behaves as per the KSZ9021RN pin definition.This pin is not an open-drain for all operating modes.34 DVDDH P3.3V / 2.5V digital V DD DVDDH P 3.3V, 2.5V, or 1.8V digital V DD_I/O38 INT_N O Interrupt OutputThis pin provides aprogrammable interrupt output and requires an external pull-up resistor to DVDDH in the range of 1K to 4.7K ohms for active low assertion.INT_N/O Interrupt OutputThis pin provides aprogrammable interrupt output and requires an external pull-up resistor to DVDDH in the range of 1K to 4.7K ohms for active low assertion.This pin is an open-drain.PME_N2 PME_N output: Programmable PME_N output (pin option 2). When asserted low, this pin signals that a WOL event has occurred.When WOL is not enabled, this pin function behaves as per the KSZ9021RN pin definition. This pin is not an open-drain for all operating modes.40 DVDDH P 3.3V / 2.5V digital V DD DVDDHP3.3V, 2.5V, or 1.8V digitalV DD_I/O47 AVDDH P 3.3V analog V DD NC–NoconnectThis pin is not bonded and canbe connected to AVDDH powerfor footprint compatibility withthe Micrel KSZ9021RN GigabitPHY.48 ISET I/O Set transmit output levelConnect a 4.99KΩ 1%resistor to ground on thispin. ISET I/O Set the transmit output levelConnect a 12.1kΩ 1% resistorto ground on this pin.Table 2. Pin Differences between KSZ9021RN and KSZ9031RNXStrapping Option DifferencesThere is no strapping pin difference between KSZ9021RN and KSZ9031RNX.Register Map DifferencesThe register space within the KSZ9021RN and KSZ9031RNX consists of direct-access registers and indirect-access registers.Direct-access RegistersThe direct-access registers comprise of IEEE-Defined Registers (0h – Fh) and Vendor-Specific Registers (10h – 1Fh). Between the KSZ9021RN and KSZ9031RNX, the direct-access registers and their bits have the same definitions, except for the following registers in Table 3.Direct-access RegisterKSZ9021RN KSZ9031RNXName Description Name Description3h PHYIdentifier2 Bits [15:10] (part of OUI) – same asKSZ9031RNXBits [9:4] (model number) – unique forKSZ9021RNBits [3:0] (revision number) – uniquedepending on chip revision PHY Identifier 2 Bits [15:10] (part of OUI) – same asKSZ9021RNBits [9:4] (model number) – unique forKSZ9031RNXBits [3:0] (revision number) – uniquedepending on chip revisionBh ExtendedRegister –Control Indirect Register AccessSelect read/write control andpage/address of Extended RegisterReserved ReservedDo not change the default value ofthis registerCh ExtendedRegister –Data Write Indirect Register AccessValue to write to Extended RegisterAddressReserved ReservedDo not change the default value ofthis registerDh ExtendedRegister –Data Read Indirect Register AccessValue read from Extended RegisterAddressMMD Access –ControlIndirect Register AccessSelect read/write control and MMDdevice addressEh Reserved ReservedDo not change the default value ofthis register MMD Access –Register/DataIndirect Register AccessValue of register address/data for theselected MMD device address1Fh, bit [1] Software Reset 1 = Reset chip, except all registers0 = Disable resetReserved ReservedTable 3. Direct-access Register Differences between KSZ9021RN and KSZ9031RNXIndirect-access RegistersThe indirect register mapping and read/write access are completely different for the KSZ9021RN (uses Extended Registers) and KSZ9031RNX (uses MMD Registers). Refer to respective devices’ data sheets for details.Indirect registers provide access to the following commonly used functions:•1000Base-T link-up time control (KSZ9031RNX only)• Pin strapping status• Pin strapping override•Skew adjustments for RGMII clocks, control signals, and datao Resolution of skew steps are different between KSZ9021RN and KSZ9031RNX•Energy-Detect Power-Down Mode enable/disable (KSZ9031RNX only)•Energy Efficient Ethernet function (KSZ9031RNX only)•Wake-on-LAN function (KSZ9031RNX only)Revision HistoryRevision Date Summary of ChangesMigration Guide created1.0 12/7/121.1 6/7/13 Indicate PME_N1 (pin 17) for KSZ9031RNX is not an open-drain.Indicate INT_N (pin 38) is an open-drain for KSZ9021RN, but is not an open-drain for KSZ9031RNX.Indicate direct-access register 1Fh, bit [1] difference.。
ksz8851
KSZ8851-16MLL/MLLISingle-Port Ethernet MAC Controllerwith 8-Bit or 16-Bit Non-PCI InterfaceRev. 2.0General DescriptionThe KSZ8851M-series is a single-port controller chip witha non-PCI CPU interface and is available in 8-bit and 16-bit bus designs. This datasheet describes the 48-pin LQFPKSZ8851-16MLL for applications requiring high-performance from single-port Ethernet Controller with 8-bitor 16-bit generic processor interface. The KSZ8851-16MLL offers the most cost-effective solution for addinghigh-throughput Ethernet connectivity to traditionalembedded systems.The KSZ8851-16MLL is a single chip, mixed analog/digitaldevice offering Wake-on-LAN technology for effectivelyaddressing Fast Ethernet applications. It consists of a FastEthernet MAC controller, an 8-bit or 16-bit generic hostprocessor interface and incorporates a unique dynamicmemory pointer with 4-byte buffer boundary and a fullyutilizable 18KB for both TX (allocated 6KB) and RX(allocated 12KB) directions in host buffer interface.The KSZ8851-16MLL is designed to be fully compliant withthe appropriate IEEE 802.3 standards. An industrialtemperature-grade version of the KSZ8851-16MLL, theKSZ8851-16MLLI is also available (see “OrderingInformation” section).LinkMD®Physical signal transmission and reception are enhancedthrough the use of analog circuitry, making the designmore efficient and allowing for lower-power consumption.The KSZ8851-16MLL is designed using a low-powerCMOS process that features a single 3.3V power supplywith options for 1.8V, 2.5V or 3.3V VDD I/O. The deviceincludes an extensive feature set that offers managementinformation base (MIB) counters and CPU control/datainterfaces with single shared data bus timing.The KSZ8851-16MLL includes unique cable diagnosticsfeature called LinkMD®. This feature determines the lengthof the cabling plant and also ascertains if there is an openor short condition in the cable. Accompanying softwareenables the cable length and cable conditions to beconveniently displayed. In addition, the KSZ8851-16MLLsupports Hewlett Packard (HP) Auto-MDIX therebyeliminating the need to differentiate between straight orcrossover cables in applications.Functional DiagramFigure 1. KSZ8851-16MLL/MLLI Functional DiagramFeatures•Integrated MAC and PHY Ethernet Controller fully compliant with IEEE 802.3/802.3u standards •Designed for high performance and high throughput applications•Supports 10BASE-T/100BASE-TX•Supports IEEE 802.3x full-duplex flow control and half-duplex backpressure collision flow control •Supports DMA-slave burst data read and write transfers•Supports IP Header (IPv4)/TCP/UDP/ICMP checksum generation and checking•Supports IPv6 TCP/UDP/ICMP checksum generation and checking•Automatic 32-bit CRC generation and checking •Simple SRAM-like host interface easily connects to most common embedded MCUs.•Supports multiple data frames for transmit and receive without address bus and byte-enable signals •Supports both Big- and Little-Endian processors •Larger internal memory with 12K Bytes for RX FIFO and 6K Bytes for TX FIFO. Programmable low, highand overrun watermark for flow control in RX FIFO •Shared data bus for Data, Address and Byte Enable •Efficient architecture design with configurable host interrupt schemes to minimize host CPU overhead and utilization•Powerful and flexible address filtering scheme •Optional to use external serial EEPROM configuration for MAC address•Single 25MHz reference clock for both PHY and MAC •HBM ESD Rating 6kVPower Modes, Power Supplies, and Packaging •Single 3.3V power supply with options for 1.8V, 2.5V and 3.3V VDD I/O•Built-in integrated 3.3V or 2.5V to 1.8V low noise regulator (LDO) for core and analog blocks •Enhanced power management feature with energy detect mode and soft power-down mode to ensurelow-power dissipation during device idle periodsComprehensive LED indicator support for link, activity and 10/100 speed (2 LEDs) - User programmable •Low-power CMOS design•Commercial Temperature Range: 0o C to +70o C •Industrial Temperature Range: –40o C to +85o C •Flexible package options available in 48-pin (7mm x 7mm) LQFP KSZ8851-16MLL or 128-pin PQFPKSZ8851-16/32MQL Additional FeaturesIn addition to offering all of the features of a Layer 2 controller, the KSZ8851-16MLL offers:•Flexible 8-bit and 16-bit generic host processor interfaces with same access time and single bustiming to any I/O registers and RX/TX FIFO buffers •Supports to add two-byte before frame header in order for IP frame content with double word boundary •Micrel LinkMD® cable diagnostic capabilities to determine cable length, diagnose faulty cables, anddetermine distance to fault• Wake-on-LAN functionality– Incorporates Magic Packet™, wake-up frame, network link state, and detection of energy signaltechnology•HP Auto MDI-X™ crossover with disable/enable option •Ability to transmit and receive frames up to 2000 bytes Network Features•10BASE-T and 100BASE-TX physical layer support •Auto-negotiation: 10/100 Mbps full and half duplex • Adaptive equalizer• Baseline wander correctionApplications• Video/Audio Distribution Systems•High-end Cable, Satellite, and IP set-top boxes •Video over IP and IPTV•Voice over IP (VoIP) and Analog Telephone Adapters (ATA)•Industrial Control in Latency Critical Applications •Home Base Station with Ethernet Connection •Industrial Control Sensor Devices (Temperature, Pressure, Levels, and Valves)•Security, Motion Control and Surveillance Cameras Markets• Fast Ethernet• Embedded Ethernet• Industrial Ethernet• Embedded SystemsOrdering InformationPart Number Temperature Range Package Lead FinishLQFP Pb-Free KSZ8851-16MLL 0o C to 70o C 48-PinKSZ8851-16MLLI –40o C to +85o C 48-PinLQFP Pb-Free KSZ8851-16MLL-Eval Evaluation Board for the KSZ8851-16MLLRevision HistoryRevision Date Summary of Changes1.0 06/30/2008 First released Information.1.1 2/13/2009 Improved EDS Rating up to 6KV, revised Ordering Information and Updated Table contentand description.2.0 8/31/2009 Change revision ID from “0” to “1” in CIDER (0xc0) register. Update pins 8, 14 and 29description for 1.8V VDD_IO supply. To add the command write (CMD=1) address indexregister in order for software to read back the CMD register value. To enable software reador write external EEPROM.ContentsPin Configuration (10)Pin Description (11)Strapping Options (13)Functional Description (14)Functional Overview (14)Power Management (14)Normal Operation Mode (14)Energy Detect Mode (14)Soft Power Down Mode (15)Power Saving Mode (15)Wake-on-LAN (15)Detection of Energy (15)Detection of Linkup (15)Wake-up Packet (15)Magic Packet™ (16)Physical Layer Transceiver (PHY) (16)100BASE-TX Transmit (16)100BASE-TX Receive (17)PLL Clock Synthesizer (Recovery) (17)Scrambler/De-scrambler (100BASE-TX only) (17)10BASE-T Transmit (17)10BASE-T Receive (17)MDI/MDI-X Auto Crossover (17)Straight Cable (18)Crossover Cable (18)Auto Negotiation (19)LinkMD® Cable Diagnostics (20)Access (20)Usage (20)Media Access Control (MAC) Operation (21)Inter Packet Gap (IPG) (21)Back-Off Algorithm (21)Late Collision (21)Flow Control (21)Half-Duplex Backpressure (22)Address Filtering Function (22)Clock Generator (23)Bus Interface Unit (BIU) (23)Supported Transfers (23)Physical Data Bus Size (23)Little and Big Endian Support (23)Asynchronous Interface (24)BIU Summation (24)Queue Management Unit (QMU) (24)Transmit Queue (TXQ) Frame Format (24)Frame Transmitting Path Operation in TXQ (26)Driver Routine for Transmit Packet from Host Processor to KSZ8851-16MLL (26)Receive Queue (RXQ) Frame Format (29)Frame Receiving Path Operation in RXQ (29)Driver Routine for Receive Packet from KSZ8851-16MLL to Host Processor (30)EEPROM Interface (31)Loopback Support (32)Near-end (Remote) Loopback (32)Far-end (Local) Loopback (32)CPU Interface I/O Registers (33)I/O Registers (33)Internal I/O Registers Space Mapping (34)Register Map: MAC, PHY and QMU (40)Bit Type Definition (40)0x00 – 0x07: Reserved (40)Chip Configuration Register (0x08 – 0x09): CCR (40)0x0A – 0x0F: Reserved (40)Host MAC Address Registers: MARL, MARM and MARH (40)Host MAC Address Register Low (0x10 – 0x11): MARL (41)Host MAC Address Register Middle (0x12 – 0x13): MARM (41)Host MAC Address Register High (0x14 – 0x15): MARH (41)0x16 – 0x1F: Reserved (41)On-Chip Bus Control Register (0x20 – 0x21): OBCR (41)EEPROM Control Register (0x22 – 0x23): EEPCR (42)Memory BIST Info Register (0x24 – 0x25): MBIR (42)Global Reset Register (0x26 – 0x27): GRR (42)0x28 – 0x29: Reserved (43)Wakeup Frame Control Register (0x2A – 0x2B): WFCR (43)0x2C – 0x2F: Reserved (43)Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0 (43)Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1 (43)Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 (44)Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 (44)Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 (44)Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3 (44)0x3C – 0x3F: Reserved (44)Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0 (44)Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1 (44)Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 (45)Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 (45)Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 (45)Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3 (45)0x4C – 0x4F: Reserved (45)Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0 (45)Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1 (46)Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 (46)Wakeup Frame 2 Byte Mask 1 Register (0x56 – 0x57): WF2BM1 (46)Wakeup Frame 2 Byte Mask 2 Register (0x58 – 0x59): WF2BM2 (46)Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3 (46)0x5C – 0x5F: Reserved (46)Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC0 (46)Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC1 (47)Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0 (47)Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1 (47)Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2 (47)Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3 (47)0x6C – 0x6F: Reserved (47)Transmit Control Register (0x70 – 0x71): TXCR (47)Transmit Status Register (0x72 – 0x73): TXSR (48)Receive Control Register 1 (0x74 – 0x75): RXCR1 (48)Receive Control Register 2 (0x76 – 0x77): RXCR2 (50)TXQ Memory Information Register (0x78 – 0x79): TXMIR (50)0x7A – 0x7B: Reserved (50)Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR (50)Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR (51)TXQ Command Register (0x80 – 0x81): TXQCR (52)RXQ Command Register (0x82 – 0x83): RXQCR (52)TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR (53)RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR (53)0x88 – 0x8B: Reserved (54)RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR (54)RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR (54)Interrupt Enable Register (0x90 – 0x91): IER (54)Interrupt Status Register (0x92 – 0x93): ISR (55)0x94 – 0x9B: Reserved (56)RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR (56)TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR (57)MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0 (57)MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1 (57)MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2 (57)MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3 (57)0xA8 – 0xAF: Reserved (58)Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR (58)Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR (58)Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR (58)0xB6 – 0xBF: Reserved (58)Chip ID and Enable Register (0xC0 – 0xC1): CIDER (58)0xC2 – 0xC5: Reserved (58)Chip Global Control Register (0xC6 – 0xC7): CGCR (58)Indirect Access Control Register (0xC8 – 0xC9): IACR (59)0xCA – 0xCF: Reserved (59)Indirect Access Data Low Register (0xD0 – 0xD1): IADLR (59)Indirect Access Data High Register (0xD2 – 0xD3): IADHR (59)Power Management Event Control Register (0xD4 – 0xD5): PMECR (59)Go-Sleep & Wake-Up Time Register (0xD6 – 0xD7): GSWUTR (61)PHY Reset Register (0xD8 – 0xD9): PHYRR (61)0xDA – 0xDF: Reserved (61)0xE0 – 0xE3: Reserved (61)PHY 1 MII-Register Basic Control Register (0xE4 – 0xE5): P1MBCR (61)PHY 1 MII-Register Basic Status Register (0xE6 – 0xE7): P1MBSR (62)PHY 1 PHY ID Low Register (0xE8 – 0xE9): PHY1ILR (63)PHY 1 PHY ID High Register (0xEA – 0xEB): PHY1IHR (63)PHY 1 Auto-Negotiation Advertisement Register (0xEC – 0xED): P1ANAR (63)PHY 1 Auto-Negotiation Link Partner Ability Register (0xEE – 0xEF): P1ANLPR (64)0xF0 – 0xF3: Reserved (64)Port 1 PHY Special Control/Status, LinkMD (0xF4 – 0xF5): P1SCLMD (64)Port 1 Control Register (0xF6 – 0xF7): P1CR (65)Port 1 Status Register (0xF8 – 0xF9): P1SR (66)0xFA – 0xFF: Reserved (67)MIB (Management Information Base) Counters (68)Additional MIB Information (69)Absolute Maximum Ratings(1) (70)Operating Ratings(2) (70)Electrical Characteristics(4, 5) (70)Timing Specifications (72)Asynchronous Read and Write Timing (72)Auto Negotiation Timing (73)Reset Timing (74)EEPROM Timing (75)Selection of Isolation Transformers (76)Selection of Reference Crystal (76)Package Information (77)Acronyms and Glossary (78)Figure 1. KSZ8851-16MLL/MLLI Functional Diagram (1)Figure 2. 48-Pin LQFP (10)Figure 3. Typical Straight Cable Connection (18)Figure 4. Typical Crossover Cable Connection (19)Figure 5. Auto Negotiation and Parallel Operation (20)Figure 6. KSZ8851-16MLL 8-Bit and 16-Bit Data Bus Connections (24)Figure 7. Host TX Single Frame in Manual Enqueue Flow Diagram (27)Figure 8. Host TX Multiple Frames in Auto- Enqueue Flow Diagram (28)Figure 9. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram (30)Figure 10. PHY Port 1 Near-end (Remote) and Host Far-end (Local) Loopback Paths (32)Figure 11. Asynchronous Cycle (72)Figure 12. Auto Negotiation Timing (73)Figure 13. Reset Timing (74)Figure 14. EEPROM Read Cycle Timing Diagram (75)Figure 15. 48-Pin (7mm x 7mm) LQFP (77)Table 1. Internal Function Blocks Status (14)Table 2. MDI/MDI-X Pin Definitions (18)Table 3. Address Filtering Scheme (22)Table 4. Bus Interface Unit Signal Grouping (23)Table 5. Frame Format for Transmit Queue (25)Table 6. Transmit Control Word Bit Fields (25)Table 7. Transmit Byte Count Format (25)Table 8. Registers Setting for Transmit Function Block (26)Table 9. Frame Format for Receive Queue (29)Table 10. Registers Setting for Receive Function Block (29)Table 11. KSZ8851-16MLL EEPROM Format (31)Table 12. Format of MIB Counters (68)Table 13. Port 1 MIB Counters Indirect Memory Offsets (69)Table 14. Electrical Characteristics (71)Table 15. Asynchronous Cycle Timing Parameters (72)Table 16. Auto Negotiation Timing Parameters (73)Table 17. Reset Timing Parameters (74)Table 18. EEPROM Timing Parameters (75)Table 19. Transformer Selection Criteria (76)Table 20. Qualified Single Port Magnetics (76)Table 21. Typical Reference Crystal Characteristics (76)Pin ConfigurationFigure 2. 48-Pin LQFPPin DescriptionPin NumberPin NameTypePin Function1 P1LED1 Ipu/O2 P1LED0 OpuProgrammable LED output to indicate port activity/status. LED is ON when output is LOW; LED is OFF when output is HIGH.Port 1 LED indicators 1defined as follows:Chip Global Control Register: CGCR bit [9]0 (Default)1P1LED1 100BT ACT P1LED0 LINK/ACTLINK1. Link = LED On; Activity = LED Blink; Link/Act = LED On/Blink;Speed = LED On (100BASE-T); LED Off (10BASE-T)Config Mode: The P1LED1 pull-up/pull-down value is latched as 16/8-bit mode duringpower-up / reset. See “Strapping Options” section for details3 PME OpuPower Management Event (default active low): It is asserted (low or high depends on polarity set in PMECR register) when one of the wake-on-LAN events is detected by KSZ8851-16MLL. The KSZ8851-16MLL is requesting the system to wake up from low power mode. 4 INTRN OpuInterrupt: An active low signal to host CPU to indicate an interrupt status bit is set, this pin need an external 4.7K pull-up resistor. 5 RDN IpuRead Strobe Not Asynchronous read strobe, active low to indicate read cycle. 6 WRN IpuWrite Strobe Not Asynchronous write strobe, active low to indicate write cycle. 7 DGND GndDigital ground 8 VDD_CO1.8 P1.8V regulator output . This 1.8V output pin provides power to pins 14 (VDD_A1.8) and 29 (VDD_D1.8) for core VDD supply.If VDD_IO is set for 1.8V then this pin should be left floating, pins 14 (VDD_A1.8) and 29 (VDD_D1.8) will be sourced by the external 1.8V supply that is tied to pins 27, 38 and 46 (VDD_IO) with appropriate filtering.9 EED_IO Ipd/OIn/Out Data from/to external EEPROM. Config Mode: The pull-up/pull-down value is latched as with/without EEPROM during power-up / reset. See “Strapping Options” section for details 10 EESK Ipd/OEEPROM Serial Clock A 4μs (OBCR[1:0]=11 on-chip bus speed @ 25MHz) or 800ns (OBCR[1:0]=00 on-chip bus speed @ 125MHz) serial output clock cycle to load configuration data from the serial EEPROM.Config Mode: The pull-up/pull-down value is latched as big/little endian mode during power-up / reset. See “Strapping Options” section for details 11 CMD IpdCommand Type This command input decides the SD[15:0] shared data bus access information.When command input is low, the access of shared data bus is for data access in 16-bit mode shared data bus SD[15:0] or in 8-bit mode shared data bus SD[7:0].When command input is high, the access of shared data bus is for address A[7:2] access at shared data bus SD[7:2], byte enable BE[3:0] at SD[15:12] and the SD[11:8] is “don’t care” in 16-bit mode. It is for address A[7:0] access at SD[7:0] in 8-bit mode.Pin NumberPin Name Type Pin Function12CSNIpuChip Select NotChip select for the shared data bus access enable, active Low.13 AGND Gnd Analog ground 14VDD_A1.8P1.8V analog power supply from VDD_CO1.8 (pin 8) with appropriate filtering. If VDD_IO is 1.8V, this pin must be supplied power from the same source as pins 27, 38 and 46 (VDD_IO) with appropriate filtering.15 EECS Opd EEPROM Chip SelectThis signal is used to select an external EEPROM device.16 RXP1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential). 17 RXM1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential). 18 AGND Gnd Analog ground.19 TXP1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential). 20 TXM1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential). 21 VDD_A3.3 P 3.3V analog VDD input power supply with well decoupling capacitors. 22ISETOSet physical transmits output current.Pull-down this pin with a 3.01K 1% resistor to ground.23 RSTN Ipu Reset NotHardware reset pin (active Low). This reset input is required minimum of 10ms low after stable supply voltage 3.3V. 24 X1 I 25 X2 O25MHz crystal or oscillator clock connection.Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator and X2 is a no connect.Note: Clock requirement is ±50ppm for either crystal or oscillator. 26 DGND Gnd Digital ground 27 VDD_IO P 3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors. 28 DGND Gnd Digital ground29VDD_D1.8P1.8V digital power supply from VDD_CO1.8 (pin 8) with appropriate filtering. If VDD_IO is1.8V, this pin must be supplied power from the same source as pins 27, 38 and 46 (VDD_IO) with appropriate filtering.30 SD15 I/O (pd)Shared Data Bus bit 15. Data D15 access when CMD=0. Byte Enable 3 at double-word boundary access (BE3, 4th byte enable and active high) in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus mode.31 SD14 I/O (pd)Shared Data Bus bit 14. Data D14 access when CMD=0. Byte Enable 2 at double-word boundary access (BE2, 3rd byte enable and active high) in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus mode.32 SD13 I/O (pd)Shared Data Bus bit 13. Data D13 access when CMD=0. Byte Enable 1 at double-word boundary access (BE1, 2nd byte enable and active high) in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus mode.33 SD12 I/O (pd)Shared Data Bus bit 12. Data D12 access when CMD=0. Byte Enable 0 at double-word boundary access (BE0, 1st byte enable and active high) in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus mode.34 SD11 I/O (pd) Shared Data Bus bit 11. Data D11 access when CMD=0. Don’t care when CMD=1. This pin must be tied to GND in 8-bit bus mode.35 SD10 I/O (pd) Shared Data Bus bit 10. Data D10 access when CMD=0. Don’t care when CMD=1. This pin must be tied to GND in 8-bit bus mode.36SD9I/O (pd)Shared Data Bus bit 9. Data D9 access when CMD=0. Don’t care when CMD=1. This pin must be tied to GND in 8-bit bus mode.37 DGND Gnd Digital groundPin Number Pin Name Type Pin Function38 VDD_IO P 3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.39 SD8 I/O (pd) Shared Data Bus bit 8. Data D8 access when CMD=0. Don’t care when CMD=1. This pinmust be tied to GND in 8-bit bus mode.40 SD7 I/O (pd) Shared Data Bus bit 7. Data D7 access when CMD=0. Address A7 access when CMD=1.41 SD6 I/O (pd) Shared Data Bus bit 6. Data D6 access when CMD=0. Address A6 access when CMD=1.42 SD5 I/O (pd) Shared Data Bus bit 5. Data D5 access when CMD=0. Address A5 access when CMD=1.43 SD4 I/O (pd) Shared Data Bus bit 4. Data D4 access when CMD=0. Address A4 access when CMD=1.44 SD3 I/O (pd) Shared Data Bus bit 3. Data D3 access when CMD=0. Address A3 access when CMD=1.45 SD2 I/O (pd) Shared Data Bus bit 2. Data D2 access when CMD=0. Address A2 access when CMD=1.46 VDD_IO P 3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.47 SD1 I/O (pd) Shared Data Bus bit 1. Data D1 access when CMD=0. In 8-bit mode, this is address A1access when CMD=1. In 16-bit mode, this is “Don’t care” when CMD=1.48 SD0 I/O (pd) Shared Data Bus bit 0. Data D0 access when CMD=0. In 8-bit mode, this is address A0access when CMD=1. In 16-bit mode, this is “Don’t care” when CMD=1.Legend:P = Power supply Gnd = GroundI/O = Bi-directional I = Input O = Output.Ipd = Input with internal pull-down (58K ±30%).Ipu = Input with internal pull-up (58K ±30%).Opd = Output with internal pull-down (58K ±30%).Opu = Output with internal pull-up (58K ±30%).Ipu/O = Input with internal pull-up (58K ±30%) during power-up/reset; output pin otherwise.Ipd/O = Input with internal pull-down (58K ±30%) during power-up/reset; output pin otherwise.I/O (pd) = Input/Output with internal pull-down (58K ±30%).Strapping OptionsPin Number Pin Name Type Pin Function1 P1LED1 Ipu/O 8 or 16-bit bus mode select during power-up / reset:NC or Pull-up (default ) = 16-bit busPull-down = 8-bit busThis pin value is also latched into register CCR, bit 6/7.9 EED_IO Ipd/O EEPROM select during power-up / reset:Pull-up = EEPROM presentNC or Pull-down (default ) = EEPROM not presentThis pin value is latched into register CCR, bit 9.10 EESK Ipd/O Endian mode select during power-up / reset:Pull-up = Big EndianNC or Pull-down (default) = Little EndianThis pin value is latched into register CCR, bit 10.When this pin is no connect or tied to GND, the bit 11 (Endian mode selection) inRXFDPR register can be used to program either Little (bit11=0 default) Endian mode orBig (bit11=1) Endian mode.Note: Ipu/O = Input with internal pull-up (58K ±30%) during power-up/reset; output pin otherwise.Ipd/O = Input with internal pull-down (58K ±30%) during power-up/reset; output pin otherwise.Pin strap-ins are latched during power-up or reset.Functional DescriptionThe KSZ8851-16MLL is a single-chip Fast Ethernet MAC/PHY controller consisting of a 10/100 physical layer transceiver (PHY), a MAC, and a Bus Interface Unit (BIU) that controls the KSZ8851-16MLL via an 8-bit or 16-bit host bus interface. The KSZ8851-16MLL is fully compliant to IEEE802.3u standards.Functional OverviewPower ManagementThe KSZ8851-16MLL supports enhanced power management feature in low power state with energy detection to ensure low-power dissipation during device idle periods. There are four operation modes under the power management function which is controlled by two bits in PMECR (0xD4) register as shown below:PMECR[1:0] = 00 Normal Operation ModePMECR[1:0] = 01 Energy Detect ModePMECR[1:0] = 10 Soft Power Down ModePMECR[1:0] = 11 Power Saving ModeTable 1 indicates all internal function blocks status under four different power management operation modes.Power Management Operation ModesKSZ8851-16MLLFunction Blocks Normal Mode Power Saving Mode Energy Detect Mode Soft Power Down ModeInternal PLL Clock Enabled Enabled Disabled Disabled Tx/Rx PHY Enabled Rx unused block disabled Energy detect at Rx Disabled MAC Enabled Enabled Disabled Disabled Host Interface Enabled Enabled Disabled DisabledTable 1. Internal Function Blocks StatusNormal Operation ModeThis is the default setting bit[1:0]=00 in PMECR register after the chip power-up or hardware reset (pin 67). When KSZ8851-16MLL is in this normal operation mode, all PLL clocks are running, PHY and MAC are on and the host interface is ready for CPU read or write.During the normal operation mode, the host CPU can set the bit[1:0] in PMECR register to transit the current normal operation mode to any one of the other three power management operation modes.Energy Detect ModeThe energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8851-16MLL is not connected to an active link partner. For example, if cable is not present or it is connected to a powered down partner, the KSZ8851-16MLL can automatically enter to the low power state in energy detect mode. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851-16MLL can automatically power up to normal power state in energy detect mode.Energy detect mode consists of two states, normal power state and low power state. While in low power state, the KSZ8851-16MLL reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The energy detect mode is entered by setting bit[1:0]=01 in PMECR register. When the KSZ8851-16MLL is in this mode, it will monitor the cable energy. If there is no energy on the cable for a time longer than pre-configured value at bit[7:0] Go-Sleep time in GSWUTR register, KSZ8851-16MLL will go into a low power state. When KSZ8851-16MLL is in low power state, it will keep monitoring the cable energy. Once the energy is detected from the cable and is continuously presented for a time longer than pre-configured value at bit[15:8] Wake-Up time in GSWUTR register, the KSZ8851-16MLL will enter either the normal power state if the auto-wakeup enable bit[7] is set in PMECR register or the normal operation mode if both auto-wakeup enable bit[7] and wakeup to normal operation mode bit[6] are set in PMECR register.The KSZ8851-16MLL will also assert PME output pin if the corresponding enable bit[8] is set in PMECR (0xD4) register or。
BQ20Z90EVM-001;中文规格书,Datasheet资料
User's GuideSLUU234–February2006 bq20z90EVM-001SBS1.1Impedance Track™TechnologyThis evaluation module(EVM)is a complete evaluation system for thebq20z90/bq29330/bq29412battery management system.The EVM includes onebq20z90/bq29330/bq29412circuit module,a current sense resistor,two thermistors,anEV2300PC interface board for gas gauge interface,a PC USB cable,andWindows™-based PC software.The circuit module includes one bq20z90integratedcircuit(IC),one bq29330IC,one bq29412IC,and all other onboard componentsnecessary to monitor and predict capacity,perform cell balancing,monitor criticalparameters,protect the cells from overcharge,over discharge,short circuit,andovercurrent in2-,3-or4-series cell Li-ion or Li-polymer battery packs.The circuitmodule connects directly across the cells in a battery.With the EV2300interface boardand software,the user can read the bq20z90data registers,program the chipset fordifferent pack configurations,log cycling data for further evaluation,and evaluate theoverall functionality of the bq20z90/bq29330/bq29412solution under different chargeand discharge conditions.Contents1Features (3)2bq20z90/bq29330-Based Circuit Module (3)3bq20z90/bq29330Circuit Module Schematic (4)4Circuit Module Physical Layouts and Bill of Materials (5)5EVM Hardware and Software Setup (9)6Troubleshooting Unexpected Dialog Boxes (9)7Hardware Connection (10)8Operation (11)9Calibration Screen (14)10Pro(Advanced)Screen (16)Trademarks (17)List of Figures1bq20z90EVM-001Layout(Silk Screen) (5)2Top Assembly (5)3Top Layer (6)4Bottom Layer (6)5Bottom Assembly (6)6Schematic (8)7bq20z90bq29330Circuit Module Connection to Cells and System Load/Charger (10)8SBS Data Screen (11)9Data Flash Screen,1st Level Safety Class (12)10Calibration Screen (15)11Pro(Advanced)Screen (16)List of Tables1Ordering Information (3)2Components and Flash-Memory Settings for Different Precharge Modes (5) 3Bill of Materials (7)4Performance Specification Summary (9)5Circuit Module to EV2300Connections (10)1Features1.1Kit Contents1.2Ordering Information2bq20z90/bq29330-Based Circuit Module 2.1Circuit Module Connections Features•Complete evaluation system for the bq20z90SBS1.1-compliant advanced gas gauge with Impedance Track™Technology,bq29330analog front end(AFE)and protection IC,and bq29412independent overvoltage protection IC•Populated circuit module for quick setup•PC software and interface board for easy evaluation•Software that allows data logging for system analysis•bq20z90/bq29330/bq29412circuit module•EV2300PC interface board•Software CD with the evaluation software•Connection cable to interface board•Set of support documentation•EV2300USB interface boardTable1.Ordering InformationEVM PART NUMBER CHEMISTRY CONFIGURATION CAPACITYbq20z90EVM-001Li-ion2,3,or4cell AnyThe bq20z90/bq29330/bq29412-based circuit module is a complete and compact example solution of abq20z90and bq29330circuit for battery management and protection of Li-ion or Li-polymer packs.The circuit module incorporates a bq20z90battery monitor IC,bq29330AFE and protection IC,bq29412 independent overvoltage protection IC,and all other components necessary to accurately predict the capacity of2-,3-,or4-series cells.Contacts on the circuit module provide the following connections:•Direct connection to the cells:1N(BAT-),1P,2P,3P,4P(BAT+)•To the serial communications port(SMBC,SMBD)•The system load and charger connect across PACK+and PACK-•To the system-present pin(SYS PRES) bq20z90/bq29330Circuit Module Schematic2.2Pin DescriptionsPIN NAME DESCRIPTION1N-ve connection of first(bottom)cell1P+ve connection of first(bottom)cell2P+ve connection of second cell3P+ve connection of third cell4P+ve connection of fourth(top)cellSMBC Serial communication port clockSMBD Serial communication data portSYS PRES System present pin(if low,system is present)PACK-Pack negative terminalVSS Pack negative terminalPACK+Pack positive terminal3bq20z90/bq29330Circuit Module SchematicThis section contains information for modifying and choosing a precharge mode forbq20z90/bq29330/bq29412implementation.3.1SchematicThe schematic follows the bill of materials in this user's guide.3.2Modifications for Choosing Particular Precharge ModeIn order to charge,the charge FET(CHG-FET)must be turned on to create a current path.When theV(BAT)is0V and CHG-FET=ON,the V(PACK)is as low as the battery voltage.In this case,the supplyvoltage for the device is too low to operate.This function has three possible configurations,and thebq29330can be easily configured according to the application needs.The three modes are0-V Charge FET mode,Common FET mode,and Precharge FET mode.1.0-V Charge FET mode-Dedicates a precharge current path using an additional FET(ZVCHG-FET)tosustain the PACK+voltage level.mon FET mode-Does not use a dedicated precharge FET.The charge FET(CHG-FET)is set toON state as default.3.Precharge FET mode-Dedicates a precharge current path using an additional open-drain(OD)pindrive FET(PCHG-FET)to sustain the PACK+voltage level.To use a particular mode of charging with the EVM,add or remove some elements shown in Table2,and use the given settings of DF.Configuration,ZVCHG1,0.3.3Testing Fuse-Blowing Circuit4Circuit Module Physical Layouts and Bill of Materials4.1BoardLayoutCircuit Module Physical Layouts and Bill of MaterialsTable ponents and Flash-Memory Settings for Different PrechargeModesMODE RESISTORS PRECHG FETZVCHG1ZVCHG010-V Chg R18,R23Q300(default)2Common FET R20Q2013PrechargeR19,R23Q31about precharge operation and mode choices,see the bq29330data sheet at To prevent the loss of board functionality during the fuse-blowing test,the actual chemical fuse is not provided in the circuit.FET Q4drives TP4low if a fuse-blow condition occurs;so,monitoring TP4can be used to test this condition.Fuse placement on the application board is shown in the bq20z90data sheet reference-board schematic.This section contains the board layout,bill of materials,and assembly drawings for the bq20z90/bq29330/bq29412circuit module.This section shows the dimensions,PCB layers (Figure 1through Figure 5),and assembly drawing for the bq20z90/bq29330module. Circuit Module Physical Layouts and Bill of MaterialsFigure3.Top LayerCircuit Module Physical Layouts and Bill of Materials 4.2Bill of Materials and SchematicTable3.Bill of MaterialsCount Ref Des Description Size MFG Part No.20C1,C2,C3,C4,Capacitor,ceramic,0.1µF50V,X7R,20%0603Any STDC6,C7,C8,C9,C10,C11,C13,C16,C18,C19,C20,C21,C22,C23,C26,C271C14Capacitor,ceramic,0.22µF,50V,X7R,20%0603Any STD1C15Capacitor,ceramic,4.7µF,25V,X7R,10%1206Any STD2C24,C28Capacitor,ceramic,0.47µF,16V,X7R,20%0603Any STD1C25Capacitor,ceramic,4.7µF,10V,X7R,20%0603Any STD2C5,C17Capacitor,ceramic,1.0µF,50V,X7R,20%0805Any STD3D1,D2,D3Diode,switching,150-mA,75-V,350mW SOT23Vishay-Liteon BAS162D4,D10Diode,dual,Zener,5.6V,300mW SOT23Vishay-Telefunken AZ23C5V65D5,D6,D7,D8,Diode,LED,green,Gullwing,GW type,200.120×0.087Panasonic LN1361C D9mA,7.5mcd Typ1J1Header,friction lock assembly,4-pin right0.400×0.500Molex22-05-3041angle1Q1MOSFET,P-ch,20V,1.3A,0.16ΩSOT23Fairchild NDS331N2Q2,Q4MOSFET,N-ch,30V,10A,Rds16mΩSO8Fairchild FDS6690S1Q3MOSFET,P-ch,30V,8.0-A,20-mΩSO8Siliconix Si4435DY1Q5MOSFET,Nch,50V,0.22A,6ΩSOT23Fairchild BSS13812R1,R2,R3,R4,Resistor,chip,100Ω,1/16W,5%0603STD STDR5,R25,R26,R28,R32,R33,R37,R382R13,R24Resistor,chip,3.01mΩ,1/16W,5%0603STD STD1R14Resistor,chip,300-Ω,1-W,10%2512WSL=2512-xx3R15,R18,R22Resistor,chip,5.1kΩ,1/16W,5%0603STD STD0R19Resistor,chip,5.1kΩ,1/16W,5%0603STD STD3R17,R35,R36Resistor,chip,1mΩ,1/16W,5%0603STD STD1R23Resistor,chip,100kΩ,1/16W,5%0603STD STD0R20Resistor,chip,100kΩ,1/16W,5%0603STD STD1R21Resistor,chip,0.010Ω,1-W,xx%2512Vishay WSL-2512-0201R29Resistor,chip,1kΩ,1/16W,5%0603STD STD2R30,R40Resistor,chip,8.45kΩ,1/16W,1%0603STD STD2R31,R39Resistor,chip,61.9kΩ,1/16W,1%0603STD STD4R6,R11,R12,Resistor,chip,220kΩ,1.16W,5%0603STD STDR346R7,R8,R9,R10,Resistor,chip,1kΩ,1.16W,5%0603STD STDR16,R272RT1,RT2Thermistor,10kΩ0.095×0.150Sematec NTC103AT1SW1Switch,push button,momentary,N.O.low5mm×5mm Panasonic EVQPLCxxxxprofile2TB1,TB4Terminal block,3pin,6A,3,5mm0.41×0.25OST ED15152TB2,TB3Terminal block,2pin,6A,3,5mm0.27×0.25OST ED15141TP1Test point,black,thru hole color keyed0.100×0.100Keystone50011TP2Test point,red,thru hole color keyed0.100×0.100Keystone50001TP2Test point,white,thru hole color keyed0.100×0.100Keystone50021U1IC,voltage protection for2,3,or4cell Li-Ion,SSOP-08TI bq29412DCT2nd protection,4.45V,OVP1U2IC,2-3,or4cell series protection control AFE TSSOP30TI bq29330DBT1U3IC,impedance track advanced gas gauge TSSOP30TI bq20z90DBT Circuit Module Physical Layouts and Bill of MaterialsFigure6.Schematic4.3bq20z90/bq29330/bq29412Circuit Module Performance Specification Summary5EVM Hardware and Software Setup5.1System Requirements5.2Software Installation6Troubleshooting Unexpected Dialog BoxesEVM Hardware and Software SetupThis section summarizes the performance specifications of the bq20z90/bq29330/bq29412circuit module.Table 4.Performance Specification SummarySpecificationMin Typ Max Units Input voltage Pack+to Pack–61525V Charge and discharge current27AThis section describes how to install the bq20z90EVM-001PC software,and how to connect the different components of the EVM.The bq20z90EVSW software requires Windows 2000or Windows XP.Drivers for Windows 98SE areprovided,but Microsoft no longer supports Windows 98;and there may be issues in Windows 98with USB driver support.The EV2300USB drivers have been tested for Windows 98SE,but no assurance is made for problem-free operation with specific system configurations.Find the latest software version in the bq20z90tool folder onUse the following steps to install the bq20z90EVSW software:1.Copy the files from the CD into the temporary directory you selected,open the archive TI USB DRVRS.zip,and extract its contents in a subdirectory/drivers.Choose preserve directory structure option when extracting.Alternatively,run SETUP.EXE from the same directory.2.Plug the EV2300into a USB port.3.Wait until system prompt new hardware found appears.Choose select location manually ,and use the browse button to point to subdirectory TIUSBWin2K-XP-1.4.Answer continue to the warning that drivers are not certified with Microsoft.5.After installation finishes,another system prompt new hardware found appears.Repeat procedure above,but point to subdirectory TIUSBWin2K-XP-26.Answer continue to the warning that drivers are not certified with Microsoft.Installation of drivers is now finished.7.For Windows 98,point to directory TIUSBWin98.8.Return to the temporary directory where you extracted files;double-click on the Setup.exe icon to install EV Software.If files were downloaded from the Web:1.Open the archive containing the installation package,and copy its contents in a temporary directory.2.Follow the preceding steps 1-8.Ensure that the files were extracted from the zip file using the Preserve Folder names option.Ensure that all the files were extracted from the zip file.The user that is downloading the files must be logged in as the administrator.The driver is not signed,so the administrator must allow installation of unsigned drivers in the operating system policy.7Hardware Connection7.1Connecting the bq20z90/bq29330/bq29412Circuit Module to a BatteryPack7.2PC Interface ConnectionHardware ConnectionThe bq20z90EVM-001comprises three hardware components:the bq20z90/bq29330/bq29412circuit module,the EV2300PC interface board,and the PC.Figure 7shows how to connect the bq20z90/bq29330/bq29412circuit module to the cells and system The cells should be connected in the following order:1.4-Cell Pack:1N (BAT-),1P,and 2P (see Section2.1for definitions).2.3-Cell Pack:1N (BAT-),1P,2P,and then connect 4P and 3P together.3.2-Cell Pack:1N (BAT-),1P,and then connect 4P,3P,and 2P togetherTo start charge or discharge test,connect PRES pin to PACK-pin to set SYS PRES state.To test sleep mode,disconnect the PRES pin.Figure 7.bq20z90bq29330Circuit Module Connection to Cells and System Load/ChargerThe following steps configure the hardware for interface to the PC:1.Connect the bq20z90/bq29330-based smart battery to the EV2300using wire leads as shown in Table 5.Table 5.Circuit Module to EV2300Connectionsbq20z90/bq29330-Based BatteryEV2300SMBD SMBD SMBC SMBC VSSGND2.Connect the PC USB cable to the EV2300and the PC USB port.The bq20z90EVM-001is now set up for operation.分销商库存信息: TIBQ20Z90EVM-001。
基于FPGA的多接口检测PCB单板系统设计
基于 FPGA的多接口检测 PCB单板系统设计摘要：基于近些年来，工业技术的迅速更新换代，工业设备的发展越来越迅捷。
各式各样的接口协议层出不穷。
为了满足各式工业设备在生产过程中的参数检测需求与降低检测成本的客观需要，本文设计了一种基于现场可编辑门阵列（Field Programmable Gate Array，FPGA），可用于多接口采集传输数据的需要。
实验表明，该接口板数据读取接受准确，接口设计合理，可以满足设备参数检测需求。
通过模块化设计，可最大限度发挥FPGA的优势所在，具有较高的实际应用价值。
关键词：现场可编辑门阵列数据检测 PCB 模块化随着现代工业技术的高速发展，基于各种接口的广泛工业应用，降低工业检测需求成本的问题也已经逐渐成为行业焦点。
同一件检测设备对于不同工业设备之间的检测成本不仅包含其自身损耗的成本，也包括在检测过程中损耗的时间成本与人员成本。
为了尽可能的降低甚至解决这样一种现状与问题，研究多接口的检测设备显得至关重要。
在传统的检测设备中，多采用单片机、ARM作为整个检测系统的主控核心，使用现场可编程门整列（Field Programmable Gate Array，FPGA）来进行数据的采集、处理、运算、传输，可实现快速执行指令的优点，此外还具有带宽高，信号处理能力强等优点。
[1-3]可以实现多接口检测设备的具体功能。
综上，为了满足多接口的检测系统设计需求，本文提出了一种以FPGA为主控芯片的多接口PCB单板检测系统，采用FPGA可大幅提升数据处理与收发能力，充分发挥FPGA灵活、高速的处理特点。
具有良好的项目使用性与后续可扩展性。
1 系统框架与工作原理系统使用Xilinx公司Kintex®-7系列的XC7K325T-2FFG900I作为控制核心，。
现场可编辑逻辑门阵列选用XILINX公司的XC7K325T-2FFG900I Kintex®-7系列FPGA。
KSZ9031MNX+YT18-3001S
Red
3X1
R21 1K
3X1
R22 1K
3X1
R23 1K
3X1
R24 1K
3X1
R25 1K
Solid Color : 10M Link Blinking : Link off Activity (RX, TX)
(1.2V Analog) (3.3V Analog)
R10
R11 JP5 MDIO_MII MDIO_USB JP6 MDC_MII MDC_USB
4.7K
4.7K INT_N
TP3 INT_N
1 2 3
MDIO_MII MDIO_USB MDC_MII MDC_USB
(6) (8) (6) (8)
D D D D 6 5 2 1 R1 10K 2 1 D1 BAV16W-7 SOD-123
DVDDH
R2 10K
DVDDH
R3 10K
DVDDH
R4 10K
DVDDH
R5 10K
PCB heat sink 1x1 inch copper ground
G
JP1
1 2 3 RXD3
JP2
1 2 3 RXD2
CRS COL (6) (6)
AGNDH ISET NC XI XO AVDDL_PLL LDO_O TX_CLK RESET_N CLK125_NDO DVDDL INT_N / PME_N2 COL MDIO MDC CRS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
MODE[3:0] 1000-1111
Description reserved
DVDDL
KSZ9031RNX
2016 Microchip Technology Inc.DS00002117C_CN 第1页特性•单芯片10/100/1000 Mbps 以太网收发器，适用于IEEE 802.3应用•RGMII 时序支持符合RGMII 版本2.0规范的片上延时，具有外部延时编程选项，并可对TX 和RX 时序路径进行调整和修正•具有3.3V/2.5V/1.8V 容差I/O 的RGMII•能够自动选择最高链路建立速率（10/100/1000Mbps ）和双工（半/全）的自动协商功能•用于差分对的片上端接电阻•可在单3.3V 电源下工作的片上LDO 控制器—只需要一个外部FET 来为内核产生1.2V 电压•支持高达16 KB 的巨型帧•125 MHz 参考时钟输出•用于在电缆断开连接时降低功耗的能量检测掉电模式•支持局域网唤醒（WOL ），并具备强大的自定义数据包检测功能•经AEC-Q100认定满足汽车应用要求（KSZ9031RNXUA ，KSZ9031RNXVA ）•适用于链路、活动和速率的可编程LED 输出•基线漂移修正•LinkMD 基于TDR 的电缆诊断，可用于识别有故障的铜缆布线•支持参数化NAND 树，可用于检测芯片I/O 与电路板之间的故障•可用于诊断目的的环回模式•自动MDI/MDI-X 交叉，可在任意工作速率下检测和修正对交换•自动检测和修正对交换、对偏斜和对极性•用于PHY 寄存器配置的MDC/MDIO 管理接口•中断引脚选项•掉电和省电模式•工作电压-内核（DVDDL 、AVDDL 和AVDDL_PLL ）：1.2V （外部FET 或稳压器）-VDD I/O （DVDDH ）：3.3V 、2.5V 或1.8V -收发器（AVDDH ）：3.3V 或2.5V （商业级温度范围）•48引脚QFN （7 mm × 7 mm ）封装目标应用•激光/网络打印机•网络附加存储（Network Attached Storage ，NAS ）•网络服务器•板载千兆局域网（Gigabit LAN on Motherboard ，GLOM ）•宽带网关•千兆SOHO/SMB 路由器•IPTV •IP 机顶盒•游戏主机•三重播放（数据、语音和视频）媒体中心•媒体转换器KSZ9031RNX具有RGMII 支持的千兆以太网收发器KSZ9031RNX致客户我们旨在提供最佳文档供客户正确使用Microchip产品。
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KSZ9031RNXGigabit Ethernet Transceiverwith RGMII SupportData Sheet Rev. 1.0LinkMD is a registered trademark of Micrel, Inc.General DescriptionThe KSZ9031RNX is a completely integrated triple-speed (10Base-T/100Base-TX/1000Base-T) Ethernet physical-layer transceiver for transmission and reception of data on standard CAT-5 unshielded twisted pair (UTP) cable.The KSZ9031RNX provides the Reduced Gigabit Media Independent Interface (RGMII) for direct connection to RGMII MACs in Gigabit Ethernet processors and switches for data transfer at 10/100/1000Mbps.The KSZ9031RNX reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core.The KSZ9031RNX offers diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ9031 I/Os and theboard. The LinkMD ®TDR-based cable diagnostic identifies faulty copper cabling. Remote and local loopback functions verify analog and digital data paths.The KSZ9031RNX is available in a 48-pin, lead-free QFN package (see “Ordering Information”).Data sheets and support documentation are available on Micrel’s web site at: .Features• Single-chip 10/100/1000Mbps IEEE 802.3 compliant Ethernet transceiver• RGMII timing supports on-chip delay according to RGMII Version 2.0, with programming options forexternal delay and making adjustments and corrections to TX and RX timing paths• RGMII with 3.3V/2.5V/1.8V tolerant I/Os• Auto-negotiation to automatically select the highest link-up speed (10/100/1000Mbps) and duplex (half/full) • On-chip termination resistors for the differential pairs • On-chip LDO controller to support single 3.3V supply operation – requires only one external FET to generate 1.2V for the core• Jumbo frame support up to 16KB• 125MHz reference clock output• Energy detect power-down mode for reduced power consumption when the cable is not attached• Energy Efficient Ethernet (EEE) support with low-power idle (LPI) mode and clock stoppage for 100Base-TX/ 1000Base-T and transmit amplitude reduction with 10Base-Te option• Wake-on-LAN (WOL) support with robust custom-packet detectionFunctional DiagramFeatures (Continued)•Programmable LED outputs for link, activity, and speed•Baseline wander correction•LinkMD TDR-based cable diagnostic to identify faulty copper cabling•Parametric NAND tree support to detect faults between chip I/Os and board•Loopback modes for diagnostics•Automatic MDI/MDI-X crossover to detect and correct pair swap at all speeds of operation•Automatic detection and correction of pair swaps, pair skew, and pair polarity•MDC/MDIO management interface for PHY register configuration•Interrupt pin option•Power-down and power-saving modes•Operating voltages– Core (DVDDL, AVDDL, AVDDL_PLL):1.2V (external FET or regulator)– VDD I/O (DVDDH):3.3V, 2.5V, or 1.8V– Transceiver (AVDDH):3.3V or 2.5V (commercial temp)•Available in a 48-pin QFN (7mm x 7mm)package Applications•Laser/Network printer•Network attached storage (NAS) •Network server•Gigabit LAN on motherboard (GLOM) •Broadband gateway•Gigabit SOHO/SMB router•IPTV•IP set-top box•Game console•Triple-play (data, voice, video) media center •Media converterOrdering InformationNote:1. Contact factory for lead time.Revision HistoryRevision Date Summary of Changes 1.0 10/31/12 Data sheet createdContentsGeneral Description (1)Features (1)Functional Diagram (1)Features (Continued) (2)Applications (2)Ordering Information (2)Revision History (3)Contents (4)List of Figures (7)List of Tables (8)Pin Configuration (9)Pin Description (10)Strapping Options (15)Functional Overview (16)Functional Description: 10Base-T/100Base-TX Transceiver (17)100Base-TX Transmit (17)100Base-TX Receive (17)Scrambler/De-Scrambler (100Base-TX only) (17)10Base-T Transmit (17)10Base-T Receive (17)Functional Description: 1000Base-T Transceiver (18)Analog Echo-Cancellation Circuit (18)Automatic Gain Control (AGC) (18)Analog-to-Digital Converter (ADC) (19)Timing Recovery Circuit (19)Adaptive Equalizer (19)Trellis Encoder and Decoder (19)Functional Description: 10/100/1000 Transceiver Features (19)Auto MDI/MDI-X (19)Pair-Swap, Alignment, and Polarity Check (20)Wave Shaping, Slew-Rate Control, and Partial Response (20)PLL Clock Synthesizer (20)Auto-Negotiation (20)RGMII Interface (22)RGMII Signal Definition (23)RGMII Signal Diagram (23)RGMII Pad Skew Registers (23)RGMII In-Band Status (27)MII Management (MIIM) Interface (27)Interrupt (INT_N) (28)Single-LED Mode (28)Tri-color Dual-LED Mode (28)Loopback Mode (29)Local (Digital) Loopback (29)Remote (Analog) Loopback (30)LinkMD® Cable Diagnostic (31)NAND Tree Support (31)Power Management (32)Energy-Detect Power-Down Mode (32)Software Power-Down Mode (32)Chip Power-Down Mode (32)Energy Efficient Ethernet (EEE) (32)Transmit Direction Control (MAC-to-PHY) (33)Receive Direction Control (PHY-to-MAC) (34)Registers Associated with EEE (36)Wake-On-LAN (36)Magic-Packet Detection (36)Customized-Packet Detection (36)Link Status Change Detection (37)Typical Current/Power Consumption (38)Transceiver (3.3V), Digital I/Os (3.3V) (38)Transceiver (3.3V), Digital I/Os (1.8V) (38)Transceiver (2.5V), Digital I/Os (2.5V) (39)Transceiver (2.5V), Digital I/Os (1.8V) (39)Register Map (40)Standard Registers (42)IEEE Defined Registers – Descriptions (42)Vendor-Specific Registers – Descriptions (48)MMD Registers (52)MMD Registers – Descriptions (53)Absolute Maximum Ratings(1) (62)Operating Ratings(2) (62)Electrical Characteristics(3) (62)Timing Diagrams (65)RGMII Timing (65)Auto-Negotiation Timing (66)MDC/MDIO Timing (67)Power-Up/Power-Down/Reset Timing (68)Reset Circuit (69)Reference Circuits – LED Strap-In Pins (70)Reference Clock – Connection and Selection (71)Magnetic – Connection and Selection (72)Package Information (75)Figure 1. KSZ9031RNX Block Diagram (16)Figure 2. KSZ9031RNX 1000Base-T Transceiver Block Diagram – Single Channel (18)Figure 3. Auto-Negotiation Flow Chart (21)Figure 4. KSZ9031RNX RGMII Interface (23)Figure 5. Local (Digital) Loopback (29)Figure 6. Remote (Analog) Loopback (30)Figure 7. LPI Mode (Refresh Transmissions and Quiet Periods) (33)Figure 8. LPI Transition – RGMII (1000Mbps) Transmit (33)Figure 9. LPI Transition – RGMII (100Mbps) Transmit (34)Figure 10. LPI Transition – RGMII (1000Mbps) Receive (35)Figure 11. LPI Transition – RGMII (100Mbps) Receive (35)Figure 12. RGMII v2.0 Specification (Figure 3 – Multiplexing and Timing Diagram) (65)Figure 13. Auto-Negotiation Fast Link Pulse (FLP) Timing (66)Figure 14. MDC/MDIO Timing (67)Figure 15. Power-Up/Power-Down/Reset Timing (68)Figure 16. Recommended Reset Circuit (69)Figure 17. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output (69)Figure 18. Reference Circuits for LED Strapping Pins (70)Figure 19. 25MHz Crystal/Oscillator Reference Clock Connection (71)Figure 20. Typical Gigabit Magnetic Interface Circuit (72)Figure 21. Recommended Land Pattern, 48-Pin (7mm x 7mm) QFN (74)Table 1. MDI/MDI-X Pin Mapping (19)Table 2. Auto-Negotiation Timers (22)Table 3. RGMII Signal Definition (23)Table 4. RGMII Pad Skew Registers (24)Table 5. Absolute Delay for 5-bit Pad Skew Setting (25)Table 6. Absolute Delay for 4-bit Pad Skew Setting (26)Table 7. RGMII In-Band Status (27)Table 8. MII Management Frame Format for the KSZ9031RNX (27)Table 9. Single-LED Mode – Pin Definition (28)Table 10. Tri-color Dual-LED Mode – Pin Definition (28)Table 11. NAND Tree Test Pin Order for KSZ9031RNX (31)Table 12. Typical Current/Power Consumption – Transceiver (3.3V), Digital I/Os (3.3V) (38)Table 13. Typical Current/Power Consumption – Transceiver (3.3V), Digital I/Os (1.8V) (38)Table 14. Typical Current/Power Consumption – Transceiver (2.5V), Digital I/Os (2.5V) (39)Table 15. Typical Current/Power Consumption – Transceiver (2.5V), Digital I/Os (1.8V) (39)Table 16. Standard Registers Supported by KSZ9031RNX (40)Table 17. MMD Registers Supported by KSZ9031RNX (41)Table 18. Portal Registers (Access to Indirect MMD Registers) (52)Table 19. RGMII v2.0 Specification (Timing Specifics from Table 2) (65)Table 20. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters (66)Table 21. MDC/MDIO Timing Parameters (67)Table 22. Power-Up/Power-Down/Reset Timing Parameters (68)Table 23. Reference Crystal/Clock Selection Criteria (71)Table 24. Magnetics Selection Criteria (73)Table 25. Compatible Single-Port 10/100/1000 Magnetics (73)(Top View)Pin Number Pin Name Type(1)Pin Function1 AVDDH P 3.3V/2.5V (commercial temp only) analog V DD2 TXRXP_A I/O Media Dependent Interface[0], positive signal of differential pair1000Base-T mode:TXRXP_A corresponds to BI_DA+ for MDI configuration and BI_DB+ forMDI-X configuration, respectively.10Base-T/100Base-TX mode:TXRXP_A is the positive transmit signal (TX+) for MDI configuration andthe positive receive signal (RX+) for MDI-X configuration, respectively.3 TXRXM_A I/O Media Dependent Interface[0], negative signal of differential pair1000Base-T mode:TXRXM_A corresponds to BI_DA– for MDI configuration and BI_DB– forMDI-X configuration, respectively.10Base-T/100Base-TX mode:TXRXM_A is the negative transmit signal (TX–) for MDI configuration andthe negative receive signal (RX–) for MDI-X configuration, respectively.4 AVDDL P 1.2V analog V DD5 TXRXP_B I/O Media Dependent Interface[1], positive signal of differential pair1000Base-T mode:TXRXP_B corresponds to BI_DB+ for MDI configuration and BI_DA+ forMDI-X configuration, respectively.10Base-T/100Base-TX mode:TXRXP_B is the positive receive signal (RX+) for MDI configuration andthe positive transmit signal (TX+) for MDI-X configuration, respectively.6 TXRXM_B I/O Media Dependent Interface[1], negative signal of differential pair1000Base-T mode:TXRXM_B corresponds to BI_DB– for MDI configuration and BI_DA– forMDI-X configuration, respectively.10Base-T/100Base-TX mode:TXRXM_B is the negative receive signal (RX–) for MDI configuration andthe negative transmit signal (TX–) for MDI-X configuration, respectively.7 TXRXP_C I/O Media Dependent Interface[2], positive signal of differential pair1000Base-T mode:TXRXP_C corresponds to BI_DC+ for MDI configuration and BI_DD+ forMDI-X configuration, respectively.10Base-T/100Base-TX mode:TXRXP_C is not used.8 TXRXM_C I/O Media Dependent Interface[2], negative signal of differential pair1000Base-T mode:TXRXM_C corresponds to BI_DC– for MDI configuration and BI_DD– forMDI-X configuration, respectively.10Base-T/100Base-TX mode:TXRXM_C is not used.9 AVDDL P 1.2V analog V DD10 TXRXP_D I/O Media Dependent Interface[3], positive signal of differential pair1000Base-T mode:TXRXP_D corresponds to BI_DD+ for MDI configuration and BI_DC+ forMDI-X configuration, respectively.10Base-T/100Base-TX mode:TXRXP_D is not used.11 TXRXM_D I/O Media Dependent Interface[3], negative signal of differential pair1000Base-T mode:TXRXM_D corresponds to BI_DD– for MDI configuration and BI_DC– forMDI-X configuration, respectively.10Base-T/100Base-TX mode:TXRXM_D is not used.12 AVDDH P 3.3V/2.5V (commercial temp only) analog V DD13 NC – No connectThis pin is not bonded and can be connected to digital ground forfootprint compatibility with the Micrel KSZ9021RN Gigabit PHY.14 DVDDL P 1.2V digital V DD15 LED2/PHYAD1 I/O LED output: Programmable LED2 outputConfig mode: The pull-up/pull-down value is latched as PHYAD[1] duringpower-up/reset. See the “Strapping Options” section for details.The LED2 pin is programmed by the LED_MODE strapping option (pin 41), and is defined as follows:Single-LED ModeLink Pin State LED DefinitionLink off H OFFLink on (any speed) L ONTri-Color Dual-LED ModeLink/ActivityPin State LED DefinitionLED2 LED1 LED2 LED1 Link off H H OFF OFF1000 Link / No activity L H ON OFF1000 Link / Activity (RX, TX) Toggle H Blinking OFF100 Link / No activity H L OFF ON100 Link / Activity (RX, TX) H Toggle OFF Blinking10 Link / No activity L L ON ON10 Link / Activity (RX, TX) Toggle Toggle Blinking BlinkingFor tri-color dual-LED mode, LED2 works in conjunction with LED1 (pin 17) toindicate 10Mbps link and activity.16 DVDDH P 3.3V, 2.5V, or 1.8V digital V DD_I/O17 LED1/PHYAD0/PME_N1 I/O LED1 output: Programmable LED1 outputConfig mode: The voltage on this pin is sampled and latched during the power-up/reset process to determine the value of PHYAD[0]. See the“Strapping Options” section for details.PME_N output: Programmable PME_N output (pin option 1). This pin functionrequires an external pull-up resistor to DVDDH (digital V DD_I/O)in a range from 1.0kΩ to 4.7kΩ. When asserted low, this pinsignals that a WOL event has occurred.The LED1 pin is programmed by the LED_MODE strapping option (pin 41), and is defined as follows.Single-LED ModeActivity Pin State LED DefinitionNo activity H OFFActivity (RX, TX) Toggle BlinkingTri-Color Dual-LED ModeLink/ActivityPin State LED DefinitionLED2 LED1 LED2 LED1 Link off H H OFF OFF1000 Link / No activity L H ON OFF1000 Link / Activity (RX, TX) Toggle H Blinking OFF100 Link / No activity H L OFF ON100 Link / Activity (RX, TX) H Toggle OFF Blinking10 Link / No activity L L ON ON10 Link / Activity (RX, TX) Toggle Toggle Blinking BlinkingFor tri-color dual-LED mode, LED1 works in conjunction with LED2 (pin 15) toindicate 10Mbps link and activity.18 DVDDL P 1.2V digital V DD19 TXD0 I RGMII mode: RGMII TD0 (Transmit Data 0) input20 TXD1 I RGMII mode: RGMII TD1 (Transmit Data 1) input\21 TXD2 I RGMII mode: RGMII TD2 (Transmit Data 2) input22 TXD3 I RGMII mode: RGMII TD3 (Transmit Data 3) input23 DVDDL P 1.2V digital V DD24 GTX_CLK I RGMII mode: RGMII TXC (Transmit Reference Clock) input25 TX_EN I RGMII mode: RGMII TX_CTL (Transmit Control) input26 DVDDL P 1.2V digital V DD27 RXD3/MODE3 I/O RGMII mode: RGMII RD3 (Receive Data 3) outputConfig mode: The pull-up/pull-down value is latched as MODE3 duringpower-up/reset. See the “Strapping Options” section for details.28 RXD2/MODE2 I/O RGMII mode: RGMII RD2 (Receive Data 2) outputConfig mode: The pull-up/pull-down value is latched as MODE2 duringpower-up/reset. See the “Strapping Options” section for details.29 VSS Gnd Digital ground30 DVDDL P 1.2V digital V DD31 RXD1/MODE1 I/O RGMII mode: RGMII RD1 (Receive Data 1) outputConfig mode: The pull-up/pull-down value is latched as MODE1 duringpower-up/reset. See the “Strapping Options” section for details.32 RXD0/MODE0 I/O RGMII mode: RGMII RD0 (Receive Data 0) outputConfig mode: The pull-up/pull-down value is latched as MODE0 duringpower-up/reset. See the “Strapping Options” section for details.33 RX_DV/CLK125_EN I/O RGMII mode: RGMII RX_CTL (Receive Control) outputConfig mode: Latched as CLK125_NDO Output Enable duringpower-up/reset. See the “Strapping Options” section for details.34 DVDDH P 3.3V, 2.5V, or 1.8V digital V DD_I/O35 RX_CLK/PHYAD2 I/O RGMII mode: RGMII RXC (Receive Reference Clock) outputConfig mode: The pull-up/pull-down value is latched as PHYAD[2] duringpower-up/reset. See the “Strapping Options” section for details.36 MDC Ipu Management data clock inputThis pin is the input reference clock for MDIO (pin 37).37 MDIO Ipu/O Management data input/outputThis pin is synchronous to MDC (pin 36) and requires an external pull-up resistorto DVDDH (digital V DD_I/O) in a range from 1.0kΩ to 4.7kΩ.38 INT_N/PME_N2 O Interrupt output: Programmable interrupt output, with register 1Bh as the InterruptControl/Status register, for programming the interrupt conditionsand reading the interrupt status. Register 1Fh, bit [14] setsthe interrupt output to active low (default) or active high.PME_N output: Programmable PME_N output (pin option 2). When assertedlow, this pin signals that a WOL event has occurred.For Interrupt (when active low) and PME functions, this pin requires an externalpull-up resistor to DVDDH (digital V DD_I/O)in a range from 1.0kΩ to 4.7kΩ.39 DVDDL P 1.2V digital V DD40 DVDDH P 3.3V, 2.5V, or 1.8V digital V DD_I/O41 CLK125_NDO/LED_MODE I/O 125MHz clock outputThis pin provides a 125MHz reference clock output option for use by the MAC.Config mode: The pull-up/pull-down value is latched as LED_MODE duringpower-up/reset. See the “Strapping Options” section for details.42 RESET_N Ipu Chip reset (active low)Hardware pin configurations are strapped-in at the de-assertion (rising edge) ofRESET_N. See the “Strapping Options” section for more details.43 LDO_O O On-chip 1.2V LDO controller outputThis pin drives the input gate of a P-channel MOSFET to generate 1.2V for thechip’s core voltages. If the system provides 1.2V and this pin is not used, it can beleft floating.44 AVDDL_PLL P 1.2V analog V DD for PLL45 XO O 25MHz crystal feedbackThis pin is a no connect if an oscillator or external clock source is used.46 XI I Crystal / Oscillator/ External Clock input25MHz ±50ppm tolerance47 NC – No connectThis pin is not bonded and can be connected to AVDDH power for footprintcompatibility with the Micrel KSZ9021RN Gigabit PHY.48 ISET I/O Set the transmit output levelConnect a 12.1kΩ 1% resistor to ground on this pin.PADDLE P_GND Gnd Exposed paddle on bottom of chipConnect P_GND to ground.Note:1. P = Power supply.Gnd = Ground.I = Input.O = Output.I/O = Bi-directional.Ipu = Input with internal pull-up (see “Electrical Characteristics” for value).Ipu/O = Input with internal pull-up (see “Electrical Characteristics” for value)/Output.Strapping OptionsPin Number Pin Name Type(1)Pin Function35 15 17 PHYAD2PHYAD1PHYAD0I/OI/OI/OThe PHY address, PHYAD[2:0], is sampled and latched at power-up/reset and isconfigurable to any value from 0 to 7. Each PHY address bit is configured as follows:Pull-up = 1Pull-down = 0PHY address bits [4:3] are always set to ‘00’.27283132 MODE3MODE2MODE1MODE0I/OI/OI/OI/OThe MODE[3:0] strap-in pins are sampled and latched at power-up/reset as follows:MODE[3:0] Mode0000 Reserved – not used0001 Reserved – not used0010 Reserved – not used0011 Reserved – not used0100 NAND tree mode0101 Reserved – not used0110 Reserved – not used0111 Chip power-down mode1000 Reserved – not used1001 Reserved – not used1010 Reserved – not used1011 Reserved – not used1100 RGMII mode – advertise 1000Base-T full-duplex only1101 RGMII mode – advertise 1000Base-T full- and half-duplex only1110 RGMII mode – advertise all capabilities (10/100/1000 speedhalf-/full-duplex), except 1000Base-T half-duplex1111 RGMII mode – advertise all capabilities (10/100/1000 speedhalf-/full-duplex)33 CLK125_EN I/O CLK125_EN is sampled and latched at power-up/reset and is defined as follows:Pull-up = Enable 125MHz clock outputPull-down = Disable 125MHz clock outputPin 41 (CLK125_NDO) provides the 125MHz reference clock output option for use bythe MAC.41 LED_MODE I/O LED_MODE is latched at power-up/reset and is defined as follows:Pull-up = Single-LED modePull-down = Tri-color dual-LED modeNote:1. I/O = Bi-directional.Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven during power-up or reset, and consequently cause the PHY strap-in pins on the RGMII signals to be latched to an incorrect configuration. In this case, Micrel recommends adding external pull-ups/pull-downs on the PHY strap-in pins to ensure the PHY is configured to the correct pin strap-in mode.Functional OverviewThe KSZ9031RNX is a completely integrated triple-speed (10Base-T/100Base-TX/1000Base-T) Ethernet physical layer transceiver solution for transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP) cable. Its on-chip proprietary 1000Base-T transceiver and Manchester/MLT-3 signaling-based 10Base-T/100Base-TX transceivers are all IEEE 802.3 compliant.The KSZ9031RNX reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core.On the copper media interface, the KSZ9031RNX can automatically detect and correct for differential pair misplacements and polarity reversals, and correct propagation delays and re-sync timing between the four differential pairs, as specified in the IEEE 802.3 standard for 1000Base-T operation.The KSZ9031RNX provides the RGMII interface for direct and seamless connection to RGMII MACs in Gigabit Ethernet processors and switches for data transfer at 10/100/1000Mbps.Figure 1 shows a high-level block diagram of the KSZ9031RNX.Figure 1. KSZ9031RNX Block DiagramFunctional Description: 10Base-T/100Base-TX Transceiver100Base-TX TransmitThe 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT-3 encoding and transmission.The circuitry starts with a parallel-to-serial conversion, which converts the RGMII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format then transmitted in MLT-3 current output. The output current is set by an external 12.1kΩ 1% resistor for the 1:1 transformer ratio.The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX transmitter.100Base-TX ReceiveThe 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT-3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Because the amplitude loss and phase distortion are a function of the cable length, the equalizer must adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations.Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit compensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit converts the MLT-3 format back to NRZI. The slicing threshold is also adaptive.The clock-recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the RGMII format and provided as the input data to the MAC. Scrambler/De-Scrambler (100Base-TX only)The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI) and baseline wander. Transmitted data is scrambled using an 11-bit wide linear feedback shift register (LFSR). The scrambler generates a 2047-bit non-repetitive sequence, then the receiver de-scrambles the incoming data stream using the same sequence as at the transmitter.10Base-T TransmitThe 10Base-T output drivers are incorporated into the 100Base-TX drivers to allow for transmission with the same magnetic. The drivers perform internal wave-shaping and pre-emphasis, and output signals with a typical amplitude of 2.5V peak for standard 10Base-T mode and 1.75V peak for energy-efficient 10Base-Te mode. The 10Base-T/10Base-Te signals have harmonic contents that are at least 31dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.10Base-T ReceiveOn the receive side, input buffer and level-detecting squelch circuits are used. A differential input receiver circuit and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 300mV or with short pulse widths to prevent noises at the receive inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ9031RNX decodes a data frame. The receiver clock is maintained active during idle periods between receiving data frames.Auto-polarity correction is provided for the receive differential pair to automatically swap and fix the incorrect +/– polarity wiring in the cabling.Functional Description: 1000Base-T TransceiverThe 1000Base-T transceiver is based-on a mixed-signal/digital-signal processing (DSP) architecture, which includes the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancellers, cross-talk cancellers, precision clock recovery scheme, and power-efficient line drivers.Figure 2shows a high-level block diagram of a single channel of the 1000Base-T transceiver for one of the four differential pairs.Figure 2. KSZ9031RNX 1000Base-T Transceiver Block Diagram – Single ChannelAnalog Echo-Cancellation CircuitIn 1000Base-T mode, the analog echo-cancellation circuit helps to reduce the near-end echo. This analog hybrid circuit relieves the burden of the ADC and the adaptive equalizer.This circuit is disabled in 10Base-T/100Base-TX mode.Automatic Gain Control (AGC)In 1000Base-T mode, the automatic gain control (AGC) circuit provides initial gain adjustment to boost up the signal level. This pre-conditioning circuit is used to improve the signal-to-noise ratio of the receive signal.Analog-to-Digital Converter (ADC)In 1000Base-T mode, the analog-to-digital converter (ADC) digitizes the incoming signal. ADC performance is essential to the overall performance of the transceiver.This circuit is disabled in 10Base-T/100Base-TX mode.Timing Recovery CircuitIn 1000Base-T mode, the mixed-signal clock recovery circuit together with the digital phase-locked loop is used to recover and track the incoming timing information from the received data. The digital phase-locked loop has very low long-term jitter to maximize the signal-to-noise ratio of the receive signal.The 1000Base-T slave PHY must transmit the exact receive clock frequency recovered from the received data back to the 1000Base-T master PHY. Otherwise, the master and slave will not be synchronized after long transmission. This also helps to facilitate echo cancellation and NEXT removal.Adaptive EqualizerIn 1000Base-T mode, the adaptive equalizer provides the following functions:•Detection for partial response signaling•Removal of NEXT and ECHO noise•Channel equalizationSignal quality is degraded by residual echo that is not removed by the analog hybrid because of impedance mismatch. The KSZ9031RNX uses a digital echo canceller to further reduce echo components on the receive signal.In 1000Base-T mode, data transmission and reception occurs simultaneously on all four pairs of wires (four channels). This results in high-frequency cross-talk coming from adjacent wires. The KSZ9031RNX uses three NEXT cancellers on each receive channel to minimize the cross-talk induced by the other three channels.In 10Base-T/100Base-TX mode, the adaptive equalizer needs only to remove the inter-symbol interference and recover the channel loss from the incoming data.Trellis Encoder and DecoderIn 1000Base-T mode, the transmitted 8-bit data is scrambled into 9-bit symbols and further encoded into 4D-PAM5 symbols. The initial scrambler seed is determined by the specific PHY address to reduce EMI when more than one KSZ9031RNX is used on the same board. On the receiving side, the idle stream is examined first. The scrambler seed, pair skew, pair order, and polarity must be resolved through the logic. The incoming 4D-PAM5 data is then converted into 9-bit symbols and de-scrambled into 8-bit data.Functional Description: 10/100/1000 Transceiver FeaturesAuto MDI/MDI-XThe Automatic MDI/MDI-X feature eliminates the need to determine whether to use a straight cable or a crossover cable between the KSZ9031RNX and its link partner. This auto-sense function detects the MDI/MDI-X pair mapping from the link partner, and assigns the MDI/MDI-X pair mapping of the KSZ9031RNX accordingly.Table 1 shows the KSZ9031RNX 10/100/1000 pin configuration assignments for MDI/MDI-X pin mapping.Pin (RJ-45 pair)MDI MDI-X1000Base-T 100Base-TX 10Base-T 1000Base-T 100Base-TX 10Base-TTXRXP/M_A (1,2) A+/– TX+/– TX+/– B+/– RX+/– RX+/– TXRXP/M_B (3,6) B+/– RX+/– RX+/– A+/– TX+/– TX+/– TXRXP/M_C (4,5) C+/– Not used Not used D+/– Not used Not used TXRXP/M_D (7,8) D+/– Not used Not used C+/– Not used Not usedTable 1. MDI/MDI-X Pin Mapping。