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DS91M040TSQ中文资料

May 13, 2008 DS91M040125 MHz Quad M-LVDS TransceiverGeneral DescriptionThe DS91M040 is a quad M-LVDS transceiver designed for driving / receiving clock or data signals to / from up to four multipoint networks.M-LVDS (Multipoint LVDS) is a new family of bus interface devices based on LVDS technology specifically designed for multipoint and multidrop cable and backplane applications. It differs from standard LVDS in providing increased drive cur-rent to handle double terminations that are required in multi-point applications. Controlled transition times minimize re-flections that are common in multipoint configurations due to unterminated stubs. M-LVDS devices also have a very large input common mode voltage range for additional noise margin in heavily loaded and noisy backplane environments.A single DS91M040 channel is a half-duplex transceiver that accepts LVTTL/LVCMOS signals at the driver inputs and con-verts them to differential M-LVDS signal levels. The receiver inputs accept low voltage differential signals (LVDS, BLVDS, M-LVDS, LVPECL and CML) and convert them to 3V LVC-MOS signals. The DS91M040 supports both M-LVDS type 1 and type 2 receiver inputs.Features■DC - 125 MHz / 250 Mbps low jitter, low skew, low power operation■Wide Input Common Mode Voltage Range allows up to ±2V of GND noise■Conforms to TIA/EIA-899 M-LVDS Standard■Pin selectable M-LVDS receiver type (1 or 2)■Controlled transition times (2.0 ns typ) minimize reflections ■8 kV ESD on M-LVDS I/O pins protects adjoining components■Flow-through pinout simplifies PCB layout■Small 5 mm x 5 mm LLP-32 space saving package Applications■Multidrop / Multipoint clock and data distribution■High-Speed, Low Power, Short-Reach alternative to TIA/ EIA-485/422■Clock distribution in AdvancedTCA (ATCA) and MicroTCA (μTCA) backplanesTypical Application30042202© 2008 National Semiconductor DS91M040 125 MHz Quad M-LVDS TransceiverOrdering InformationOrder Number Receiver Input FunctionPackage TypeDS91M040TSQType 1 or 2Quad M-LVDS TranscieverLLP-32Connection Diagram30042201Logic Diagram30042203 2D S 91M 040Pin DescriptionsNumber Name I/O, Type Description1, 3, 5, 7RO O, LVCMOS Receiver output pin.26, 28, 13, 15RE I, LVCMOS Receiver enable pin: When RE is high, the receiver is disabled.When RE is low, the receiver is enabled. There is a 300 kΩ pullupresistor on this pin.25, 27, 14, 16DE I, LVCMOS Driver enable pin: When DE is low, the driver is disabled. WhenDE is high, the driver is enabled. There is a 300 kΩ pulldownresistor on this pin.2, 4, 6, 8DI I, LVCMOS Driver input pin.31, DAP GND Power Ground pin and pad.17, 19, 21, 23A I/O, M-LVDS Non-inverting driver output pin/Non-inverting receiver input pin 18, 20, 22, 24B I/O, M-LVDS Inverting driver output pin/Inverting receiver input pin11, 12, 29, 30VDDPower Power supply pin, +3.3V ± 0.3V32FSEN1I, LVCMOS Failsafe enable pin with a 300 kΩ pullup resistor. This pinenables Type 2 receiver on inputs 0 and 2.FSEN1 = L --> Type 1 receiver inputsFSEN1 = H --> Type 2 receiver inputs9FSEN2I, LVCMOS Failsafe enable pin with a 300 kΩ pullup resistor. This pinenables Type 2 receiver on inputs 1 and 3.FSEN2 = L --> Type 1 receiver inputsFSEN2 = H --> Type 2 receiver inputs10MDE I, LVCMOS Master enable pin. When MDE is H, the device is powered up.When MDE is L, the device overrides all other control and powersdown.M-LVDS Receiver TypesThe EIA/TIA-899 M-LVDS standard specifies two differenttypes of receiver input stages. A type 1 receiver has a con-ventional threshold that is centered at the midpoint of the inputamplitude, VID /2. A type 2 receiver has a built in offset that is100mV greater then VID /2. The type 2 receiver offset acts asa failsafe circuit where open or short circuits at the input willalways result in the output stage being driven to a low logicstate.30042240FIGURE 1. M-LVDS Receiver Input Thresholds DS91M040Absolute Maximum Ratings (Note 4)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Power Supply Voltage −0.3V to +4V LVCMOS Input Voltage −0.3V to (V DD + 0.3V)LVCMOS Output Voltage −0.3V to (V DD + 0.3V)M-LVDS I/O Voltage −5.5V to +5.5V M-LVDS Output Short Circuit Current Duration Continuous Junction Temperature +140°C Storage Temperature Range −65°C to +150°C Lead Temperature Range Soldering (4 sec.)+260°C Maximum Package Power Dissipation @ +25°C SQ Package 833 mW Derate SQ Package 6.67 mW/°C above +25°C Package Thermal Resistance θJA +150°C/W θJC +63.8°C/WESD Susceptibility HBM (Note 1)≥8 kV MM (Note 2)≥250V CDM (Note 3)≥1250VNote 1:Human Body Model, applicable std. JESD22-A114C Note 2:Machine Model, applicable std. JESD22-A115-A Note 3:Field Induced Charge Device Model, applicable std.JESD22-C101-CRecommended Operating ConditionsMin Typ Max Units Supply Voltage, V DD3.0 3.3 3.6V Voltage at Any Bus Terminal−1.4 +3.8V (Separate or Common-Mode)Differential Input Voltage V ID 2.4V LVTTL Input Voltage High V IH 2.0 V DD V LVTTL Input Voltage Low V IL 0 0.8V Operating Free Air Temperature T A −40+25+85°CDC Electrical Characteristics(Notes 5, 6, 7, 9)Over recommended operating supply and temperature ranges unless otherwise specified.Symbol ParameterConditionsMin Typ Max Units M-LVDS Driver |V AB |Differential output voltage magnitudeR L = 50Ω, C L = 5 pF 480 650mV ΔV AB Change in differential output voltage magnitude between logic statesFigures 2, 4−500+50mV V OS(SS)Steady-state common-mode output voltageR L = 50Ω, C L = 5 pF 0.3 1.6 2.1V |ΔV OS(SS)|Change in steady-state common-mode outputvoltage between logic states Figures 2, 30 +50mV V A(OC)Maximum steady-state open-circuit output voltage Figure 50 2.4V V B(OC)Maximum steady-state open-circuit output voltage0 2.4V V P(H)Voltage overshoot, low-to-high level output (Note 12)R L = 50Ω, C L = 5pF, C D = 0.5 pF Figures 7, 81.2V SSV V P(L)Voltage overshoot, high-to-low level output (Note 12)−0.2V SSV I IH High-level input current (LVTTL inputs)V IH = 2.0V -15 15μA I IL Low-level input current (LVTTL inputs)V IL = 0.8V -15 15μA V CL Input Clamp Voltage (LVTTL inputs)I IN = -18 mA -1.5 V I OS Differential short-circuit output current (Note 8)Figure 6-43 43mA M-LVDS ReceiverV IT+Positive-going differential input voltage threshold See Function Tables Type 1 1650mV Type 2 100150mV V IT−Negative-going differential input voltage threshold See Function Tables Type 1−5020 mV Type 25094 mV V OH High-level output voltage (LVTTL output)I OH = −8mA 2.4 2.7 V V OL Low-level output voltage (LVTTL output)I OL = 8mA 0.280.4V I OZ TRI-STATE output currentV O = 0V or 3.6V−10 10μA I OSRShort-circuit receiver output current (LVTTL output)V O = 0V-50-90mA 4D S 91M 040Symbol ParameterConditionsMin Typ Max Units M-LVDS Bus (Input and Output) PinsI ATransceiver input/output currentV A = 3.8V, V B = 1.2V 32µA V A = 0V or 2.4V, V B = 1.2V −20 +20µA V A = −1.4V, V B = 1.2V−32 µA I BTransceiver input/output currentV B = 3.8V, V A = 1.2V 32µA V B = 0V or 2.4V, V A = 1.2V −20 +20µA V B = −1.4V, V A = 1.2V−32 µA I AB Transceiver input/output differential current (I A − I B )V A = V B , −1.4V ≤ V ≤ 3.8V −4 +4µA I A(OFF)Transceiver input/output power-off currentV A = 3.8V, V B = 1.2V,DE = V CC = 1.5V32µA V A = 0V or 2.4V, V B = 1.2V,DE = V CC = 1.5V −20 +20µA V A = −1.4V, V B = 1.2V,DE = V CC = 1.5V−32 µA I B(OFF)Transceiver input/output power-off currentV B = 3.8V, V A = 1.2V,DE = V CC = 1.5V32µA V B = 0V or 2.4V, V A = 1.2V,DE = V CC = 1.5V −20 +20µA V B = −1.4V, V A = 1.2V,DE = V CC = 1.5V−32 µA I AB(OFF)Transceiver input/output power-off differential current (I A(OFF) − I B(OFF))V A = V B , −1.4V ≤ V ≤ 3.8V,V DD = 1.5V, DE = 1.5V −4 +4µA C A Transceiver input/output capacitance V DD = OPEN7.8 pF C B Transceiver input/output capacitance7.8 pF C AB Transceiver input/output differential capacitance 3 pF C A/BTransceiver input/output capacitance balance (C A /C B )1SUPPLY CURRENT (V CC )I CCD Driver Supply Current R L = 50Ω, DE = H, RE = H 6775mA I CCZ TRI-STATE Supply Current DE = L, RE = H 2226mA I CCR Receiver Supply Current DE = L, RE = L 3238mA I CCPDPower Down Supply CurrentMDE = L35mANote 4:“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.Note 5:The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.Note 6:Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V OD and ΔV OD .Note 7:Typical values represent most likely parametric norms for V DD = +3.3V and T A = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed.Note 8:Output short circuit current (I OS ) is specified as magnitude only, minus sign indicates direction only.Note 9:C L includes fixture capacitance and C D includes probe capacitance.DS91M040Switching Characteristics(Notes 10, 11, 17)Over recommended operating supply and temperature ranges unless otherwise specified.SymbolParameterConditionsMin Typ Max Units DRIVER AC SPECIFICATIONS t PLH Differential Propagation Delay Low to High R L = 50Ω, C L = 5 pF, 1.5 3.3 5.5ns t PHL Differential Propagation Delay High to Low C D = 0.5 pF 1.5 3.3 5.5ns t SKD1Pulse Skew (Notes 12, 13)Figures 7, 8 30125ps t SKD2Channel-to-Channel Skew (Notes 12, 14) 100200ps t SKD3Part-to-Part Skew (Notes 12, 15) 0.8 1.6ns t SKD4Part-to-Part Skew (Notes 12, 16) 4ns t TLH Rise Time (Note 12)1.22.03.0ns t THL Fall Time (Note 12)1.22.03.0ns t PZH Enable Time (Z to Active High)R L = 50Ω, C L = 5 pF, 7.511.5ns t PZL Enable Time (Z to Active Low )C D = 0.5 pF 8.011.5ns t PLZ Disable Time (Active Low to Z)Figures 9, 10 7.011.5ns t PHZ Disable Time (Active High to Z)7.011.5ns RECEIVER AC SPECIFICATIONSt PLH Propagation Delay Low to High C L = 15 pF 1.5 3.0 4.5ns t PHL Propagation Delay High to Low Figures 11, 12, 13 1.5 3.1 4.5ns t SKD1A Pulse Skew (Receiver Type 1)(Notes 12, 13)55325ps t SKD1B Pulse Skew (Receiver Type 2)(Notes 12, 13)475800ps t SKD2Channel-to-Channel Skew (Notes 12, 14) 60300ps t SKD3Part-to-Part Skew (Notes 12, 15) 0.6 1.2ns t SKD4Part-to-Part Skew (Notes 12, 16) 3ns t TLH Rise Time (Note 12) 0.3 1.1 1.6ns t THL Fall Time (Note 12)0.30.65 1.6ns t PZH Enable Time (Z to Active High)R L = 500Ω, C L = 15 pF 3 5.5ns t PZL Enable Time (Z to Active Low)Figures 14, 15 3 5.5ns t PLZ Disable Time (Active Low to Z) 3.5 5.5ns t PHZ Disable Time (Active High to Z) 3.5 5.5ns GENERIC AC SPECIFICATIONSt WKUP Wake Up Time (Note 12)(Master Device Enable (MDE) time) 500ms f MAXMaximum Operating Frequency (Note 12)125MHzNote 10:The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.Note 11:Typical values represent most likely parametric norms for V DD = +3.3V and T A = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed.Note 12:Specification is guaranteed by characterization and is not tested in production.Note 13:t SKD1, |t PLHD − t PHLD |, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel.Note 14:t SKD2, Channel-to-Channel Skew, is the difference in propagation delay (t PLHD or t PHLD ) among all output channels.Note 15:t SKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to devices at the same V DD and within 5°C of each other within the operating temperature range.Note 16:t SKD4, Part-to-Part Skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t SKD4 is defined as |Max − Min| differential propagation delay.Note 17:C L includes fixture capacitance and C D includes probe capacitance.Note 18:Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subracted geometrically. 6D S 91M 040Test Circuits and Waveforms30042214FIGURE 2. Differential Driver Test Circuit30042224FIGURE 3. Differential Driver Waveforms30042222FIGURE 4. Differential Driver Full Load Test Circuit30042212FIGURE 5. Differential Driver DC Open Test CircuitDS91M04030042225FIGURE 6. Differential Driver Short-Circuit Test Circuit30042216FIGURE 7. Driver Propagation Delay and Transition Time Test Circuit30042218FIGURE 8. Driver Propagation Delays and Transition Time Waveforms 8D S 91M 04030042219FIGURE 9. Driver TRI-STATE Delay Test Circuit30042221FIGURE 10. Driver TRI-STATE Delay Waveforms30042215FIGURE 11. Receiver Propagation Delay and Transition Time Test Circuit DS91M04030042217FIGURE 12. Type 1 Receiver Propagation Delay and Transition Time Waveforms30042223FIGURE 13. Type 2 Receiver Propagation Delay and Transition Time Waveforms30042213FIGURE 14. Receiver TRI-STATE Delay Test Circuit 10D S 91M 040DS91M04030042220FIGURE 15. Receiver TRI-STATE Delay WaveformsTruth TablesDS91M040 Transmitting InputsOutputsRE DE DI B A X H H L H X H L H L XLXZZX — Don't care condition Z — High impedance stateDS91M040 as Type 1 ReceivingInputsOutput FSEN RE DE A − BRO L L L ≥ +0.05V H L L L ≤ −0.05VL L L L 0V X LHLXZX — Don't care condition Z — High impedance state DS91M040 as Type 2 ReceivingInputs Output FSEN RE DE A − BR H L L ≥ +0.15V H H L L ≤ +0.05VL H L L 0V L HHLXZX — Don't care condition Z — High impedance stateDS91M040 Type 1 Receiver Input Threshold Test VoltagesApplied Voltages Resulting Differential InputVoltageResulting Common-ModeInput VoltageReceiver OutputV IA V IB V ID V ICM R 2.400V 0.000V 2.400V 1.200V H 0.000V 2.400V −2.400V 1.200V L 3.800V 3.750V 0.050V 3.775V H 3.750V 3.800V −0.050V 3.775V L −1.350V −1.400V 0.050V −1.375V H −1.400V−1.350V−0.050V−1.375VLH — High Level L — Low LevelOutput state assumes that the receiver is enabled (RE = L)DS91M040 Type 2 Receiver Input Threshold Test VoltagesApplied Voltages Resulting Differential InputVoltageResulting Common-ModeInput VoltageReceiver OutputV IA V IB V ID V IC R 2.400V 0.000V 2.400V 1.200V H 0.000V 2.400V −2.400V 1.200V L 3.800V 3.650V 0.150V 3.725V H 3.800V 3.750V 0.050V 3.775V L −1.250V −1.400V 0.150V −1.325V H −1.350V−1.400V0.050V−1.375VLH — High Level L — Low LevelOutput state assumes that the receiver is enabled (RE = L) 12D S 91M 040Typical Performance30042250 Driver Rise Time as a Function of Temperature30042251 Driver Fall Time as a Function of Temperature30042258 Driver Output Signal Amplitude as a Function ofResistive Load30042252Driver Propagation Delay (tPLHD) as a Function ofTemperature30042253Driver Propagation Delay (tPHLD) as a Function ofTemperatureDS91M04030042254Driver Power Supply Current as a Function of Frequency30042255Receiver Power Supply Current as a Function ofFrequency30042256Receiver Propagation Delay (tPLHD) as a Function ofInput Common Mode Voltage30042257Receiver Propagation Delay (tPHLD) as a Function ofInput Common Mode Voltage 14D S 91M 040Physical Dimensions inches (millimeters) unless otherwise notedOrder Number DS91M040TSQSee NS package Number SQA32A(See AN-1187 for PCB Design and Assembly Recommendations) DS91M040NotesD S 91M 040 125 M H z Q u a d M -L V D S T r a n s c e i v e rFor more National Semiconductor product information and proven design tools, visit the following Web sites at:ProductsDesign SupportAmplifiers /amplifiers WEBENCH /webench Audio/audio Analog University /AU Clock Conditioners /timing App Notes /appnotes Data Converters /adc Distributors /contacts Displays /displays Green Compliance /quality/green Ethernet /ethernet Packaging/packaging Interface /interface Quality and Reliability /quality LVDS/lvds Reference Designs /refdesigns Power Management /power Feedback /feedback Switching Regulators /switchers LDOs /ldo LED Lighting /led PowerWise/powerwise Serial Digital Interface (SDI)/sdiTemperature Sensors /tempsensors Wireless (PLL/VCO)/wirelessTHE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.LIFE SUPPORT POLICYNATIO NAL’S PRO DUCTS ARE NO T AUTHO RIZED FO R USE AS CRITICAL CO MPO NENTS IN LIFE SUPPO RT DEVICES O R SYSTEMS WITHO UT THE EXPRESS PRIO R WRITTEN APPRO VAL O F THE CHIEF EXECUTIVE O FFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders.Copyright© 2008 National Semiconductor CorporationFor the most current product information visit us at National Semiconductor Americas Technical Support CenterEmail: support@ Tel: 1-800-272-9959National Semiconductor Europe Technical Support CenterEmail: europe.support@ German Tel: +49 (0) 180 5010 771English Tel: +44 (0) 870 850 4288National Semiconductor Asia Pacific Technical Support Center Email: ap.support@National Semiconductor Japan Technical Support Center Email: jpn.feedback@。

LF398M中文资料

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
LF398/LF398A
0˚C to +70˚C
Storage Temperature Range
−65˚C to +150˚C
Input Voltage
Equal to Supply Voltage
Logic To Logic Reference
Differential Voltage (Note 3)
Electrical Characteristics
The following specifcations apply for −VS + 3.5V ≤ VIN ≤ +VS − 3.5V, +VS = +15V, −VS = −15V, TA = Tj = 25˚C, Ch = 0.01 µF, RL = 10 kΩ, LOGIC REFERENCE = 0V, LOGIC HIGH = 2.5V, LOGIC LOW = 0V unless otherwise specified.
0.5
2
4
0.5
4
Ω
6
Ω
“HOLD” Step, (Note 6) Supply Current, (Note 5) Logic and Logic Reference Input Current
Tj = 25˚C, Ch = 0.01 µF, VOUT = 0 Tj≥25˚C Tj = 25˚C

UPC4574G2-E1中文资料

UPC4574G2-E1中⽂资料The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.DATA SHEETDocument No. G15977EJ4V0DS00 (4th edition)Date Published March 2004 N CP(K) Printed in JapanThe mark shows major revised points.1987DESCRIPTIONThe µPC4574 is an ultra low noise, high slew rate quad operational amplifier specifically designed for audio, instrumentation, and communication circuits. The low noise and high frequency capabilities make it ideal for preamps and active filters for instrumentation and professional audio.FEATURESUltra low noise High slew rate Wide bandwidthInternal frequency compensationORDERING INFORMATIONPart NumberPackageµPC4574C µPC4574C(5) 14-pin plastic DIP (7.62 mm (300)) 14-pin plastic DIP (7.62 mm (300)) µPC4574G2 µPC4574G2(5) 14-pin plastic SOP (5.72 mm (225)) 14-pin plastic SOP (5.72 mm (225))EQUIVALENT CIRCUIT (1/4 Circuit)I I I NVVPIN CONFIGURATION (Top View)OUT 4I I4I N4V ?I N3I I3OUT 3OUT 1I I1I N1V +I N2I I2OUT 2PC4574C, 4574C(5), 4574G2, 4574G2(5)µData Sheet G15977EJ4V0DS2ABSOLUTE MAXIMUM RATINGS (T A = 25°C)Parameter SymbolRatings Unit Voltage between V +and V ? Note1V +V0.3 to +36VDifferential Input Voltage V ID ±30 V Input VoltageNote2V IV ??0.3 to V ++0.3 V Output VoltageNote3V OV ??0.3 to V + +0.3VC Package Note4570 mW Power Dissipation G2 PackageNote5P T 550 mW Output Short Circuit DurationNote610 sec Operating Ambient Temperature T A ?20 to +80 °C Storage TemperatureT stg55 to +125°CNotes 1. Reverse connection of supply voltage can cause destruction.2. The input voltage should be allowed to input without damage or destruction. Even during the transition periodof supply voltage, power on/off etc., this specification should be kept. The normal operation will establish when the both inputs are within the Common Mode Input Voltage Range of electrical characteristics.3. This specification is the voltage which should be allowed to supply to the output terminal from externalwithout damage or destructive. Even during the transition period of supply voltage, power on/off etc., this specification should be kept. The output voltage of normal operation will be the Output Voltage Swing of electrical characteristics.4. Thermal derating factor is –7.6 mW/°C when ambient temperature is higher than 50°C.5. Thermal derating factor is –5.5 mW/°C when ambient temperature is higher than 25°C.6. Pay careful attention to the total power dissipation not to exceed the absolute maximum ratings, Note 4 andNote 5.RECOMMENDED OPERATING CONDITIONSParameter Symbol MIN. TYP. MAX. UnitSupply Voltage V ± ±4 ±16 V Output Current I O±10 mASource Resistance R S 50k ?Capacitive Load (A V = +1)C L 100 pFµPC4574C, µPC4574G2±Notes 7. Input bias currents flow out from IC. Because each currents are base current of PNP-transistor on input stage.8.This current flows irrespective of the existence of use.Data Sheet G15977EJ4V0DS 3µPC4574C(5), µPC4574G2(5)±Notes 7. Input bias currents flow out from IC. Because each currents are base current of PNP-transistor on input stage.8.This current flows irrespective of the existence of use.4Data Sheet G15977EJ4V0DSMEASUREMENT CIRCUITFig.1 Total Harmonic Distortion Measurement CircuitnFig.3 Flat Noise Measurement Circuit (FLAT+JIS A)V O = 40 dB x V n100 V n =V O40 dBData Sheet G15977EJ4V0DS 5Data Sheet G15977EJ4V0DS6TYPICAL PERFORMANCE CHARACTERISTICS (T A = 25°C, TYP.) T A - Operating Ambient Temperature - ?CPOWER DISSIPATIONP T - T o t a l P o w e r D i s s i p a t i o n - m W800600400200020*********20406080100120110010 k 1 M 1 k 10100 k 10 Mf - Frequency - HzOPEN LOOP FREQUENCY RESPONSEA V - O p e n L o o p V o l t a g e G a i n - d BV ± = ±15 V202040608021.510.50?0.5?1?1.5?2T A - Operating Ambient Temperature - ?CINPUT OFFSET VOLTAGEV I O - I n p u t O f f s e t V o l t a g e - m V= ±15 VV ±each 5 samples data806040200?20550530510490470450T A - Operating Ambient Temperature - ?CINPUT BIAS CURRENTI B - I n p u t B i a s C u r r e n t - n A= ±15 VV ±f - Frequency - HzLARGE SIGNAL FREQUENCY RESPONSE V o m - O u t p u t V o l t a g e S w i n g - V p -p 01020301001 k 10 k 100 k 1 M 10 MV = ±15 V±R L = 10 k ?I O - Output Current - mAOUTPUT CURRENT LIMITV O - O u t p u t V o l t a g e - V±±5±10±15T A - Operating Ambient Temperature - ?CSUPPLY CURRENTI C C - S u p p l y C u r r e n t - m A12963204020060800V = ±15 V±SUPPLY CURRENTI C C - S u p p l y C u r r e n t - m A12963±10±20V - Supply Voltage - V±Data Sheet G15977EJ4V0DS7COMMON MODE INPUT VOLTAGE RANGE V I C M - C o m m o n M o d e I n p u t V o l t a g e R a n g e - V 20100±10±20V - Supply Voltage - V±VOLTAGE FOLLOWER PULSE RESPONSE V O - O u t p u t V o l t a g e - V10551002468t - Time - sµV = ±15 V ±A V = 1R L = 2 k ?INPUT NOISE VOLTAGE (FLAT + JIS A)V n - I n p u t N o i s e V o l t a g e - V r .m .s .1001010.1101001 k10 k100 kR S - Source Resistance - ?V = ±15 V±µf - Frequency - HzINPUT EQUIVALENT NOISE VOLTAGE DENSITY e n - I n p u t E q u i v a l e n t N o i s e V o l t a g e D e n s i t y - n V / H z20468100 1 k10 k 100 k10±R S = 100 VTOTAL HARMONIC DISTORTIONT H D - T o t a l H a r m o n i c D i s t o r t i o n - %10.0010.010.10.000110100 1 k10 k 100 kf - Frequency - HzV = ±15 V ±V O = 3 V r.m.s.A V = 1R L = 2 k ?Data Sheet G15977EJ4V0DS8PACKAGE DRAWINGS (Unit: mm)14-PIN PLASTIC DIP (7.62 mm (300))ITEM MILLIMETERS A 19.22±0.22.14 MAX.F I J D 1.32±0.12G 3.6±0.3C B 2.54 (T.P.)0.50±0.10R 0~15°H 0.51 MIN.K 7.62 (T.P.)L 6.4±0.23.554.3±0.2N 0.25NOTES1. Each lead centerline is located within 0.25 mm ofits true position (T.P.) at maximum material condition.2. ltem "K" to center of leads when formed parallel.P14C-100-300B1-3M 0.25+0.10?0.05Data Sheet G15977EJ4V0DS9ITEM B C I 14-PIN PLASTIC SOP (5.72 mm (225))D E G H J PMILLIMETERS 1.27 (T.P.)1.42 MAX.A 10.2±0.264.4±0.10.1±0.10.426.5±0.21.49+0.08?0.071.1±0.163°+7°?3°NOTEEach lead centerline is located within 0.1 mm ofits true position (T.P.) at maximum material condition.F 1.59+0.21?0.2K L M N 0.6±0.20.170.10.10+0.08?0.07S14GM-50-225B, C-6RECOMMENDED SOLDERING CONDITIONSThe µPC4574 should be soldered and mounted under the following recommended conditions.For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative.For technical information, see the following website.Semiconductor Device Mount Manual (/doc/015a7dda76a20029bd642de6.html/pkg/en/mount/index.html)Type of Surface Mount DeviceµPC4574G2, 4574G2(5): 14-pin plastic SOP (5.72 mm (225))Process ConditionsSymbol Infrared Ray Reflow Peak temperature: 230°C or below (Package surface temperature),Reflow time: 30 seconds or less (at 210°C or higher),Maximum number of reflow processes: 1 time.IR30-00-1Vapor Phase Soldering Peak temperature: 215°C or below (Package surface temperature),Reflow time: 40 seconds or less (at 200°C or higher),Maximum number of reflow processes: 1 time.VP15-00-1Wave Soldering Solder temperature: 260°C or below, Flow time: 10 seconds or less,Maximum number of flow processes: 1 time,Pre-heating temperature: 120°C or below (Package surface temperature).WS60-00-1Partial Heating Method Pin temperature: 300°C or below,Heat time: 3 seconds or less (Per each side of the device).–Caution Apply only one kind of soldering condition to a device, except for "partial heating method", or thedevice will be damaged by heat stress.Type of Through-hole DeviceµPC4574C, 4574C(5): 14-pin plastic DIP (7.62 mm (300))Process ConditionsWave Soldering (only to leads) Solder temperature: 260°C or below, Flow time: 10 seconds or less.Partial Heating Method Pin temperature: 300°C or below,Heat time: 3 seconds or less (per each lead).Caution For through-hole device, the wave soldering process must be applied only to leads, and make sure that the package body does not get jet soldered.Data Sheet G15977EJ4V0DS10The information in this document is current as of March, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of N EC Electronics products. N ot all products and/or types are available in every country. Please check with an N EC Electronics sales representative for availability and additional information.No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features.NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific".The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application."Standard":Computers, office equipment, communications equipment, test and measurement equipment, audioand visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special":Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disastersystems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific":Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, lifesupport systems and medical equipment for life support, etc.The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application.(Note)(1)"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes itsmajority-owned subsidiaries.(2)"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (asdefined above).M8E 02. 11-1。

M12L64164A资料

元器件交易网
ESMT
SDRAM
M12L64164A
1M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock DQM for masking Auto & self refresh 15.6 μ s refresh interval
Write Enable Data Input / Output Mask Data Input / Output Power Supply / Ground Data Output Power / Ground No Connection
INPUT FUNCTION
Active on the positive going edge to sample all inputs Disables or enables device operation by masking or enabling all inputs except CLK , CKE and L(U)DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior new command. Disable input buffers for power down in standby.

2KBP08M中文资料

2KBP005M thru 2KBP10M, 3N253 thru 3N259Document Number 8853208-Jul-05Vishay Semiconductors1Glass Passivated Single-Phase Bridge RectifierMajor Ratings and CharacteristicsI F(AV) 2 A V RRM 50 V to 1000 VI FSM 60 A I R 5 µA V F 1.1 V T j max.150 °CFeatures•UL Recognition file number E54214 •Ideal for printed circuit board •High surge current capability •High case dielectric strength •Solder Dip 260 °C, 40 secondsTypical ApplicationsGeneral purpose use in ac-to-dc bridge full wave rec-tification for Switching Power Supply, Home Appli-ances, Office Equipment, and Telecommunication applicationsMechanical DataCase: KBPMEpoxy meets UL-94V-0 Flammability ratingTerminals: Silver plated (E4 Suffix) leads, solderable per J-STD-002B and JESD22-B102D Polarity: As marked on bodyMaximum RatingsRatings at 25 °C ambient temperature unless otherwise specified.ParameterSymbols 2KBP005M2KBP 01M 2KBP 02M 2KBP 04M 2KBP 06M 2KBP 08M 2KBP 10M Units3N2533N2543N2553N2563N2573N2583N259Maximum repetitive peak reverse voltage V RRM 50 100 200 400 600 8001000 V Maximum RMS voltage V RMS 35 70 140 280 420 560 700 V Maximum DC blocking voltageV DC 50 100 200 400 600 800 1000 VMax. average forward output rectified current at T A = 55 °CI F(AV) 2.0A Peak forward surge current single half sine-wave superimposed on rated load I FSM 60 A Rating for fusing (t < 8.3 ms)I 2t 15A 2sec Operating junction and storage temperature rangeT J , T STG- 55 to + 165°C2KBP005M thru 2KBP10M, 3N253 thru 3N259Vishay SemiconductorsElectrical CharacteristicsRatings at 25 °C ambient temperature unless otherwise specified.Thermal CharacteristicsRatings at 25 °C ambient temperature unless otherwise specified.ParameterT est conditionSymbols2KBP 005M 2KBP 01M 2KBP 02M 2KBP 04M 2KBP 06M 2KBP 08M 2KBP 10M Units3N2533N2543N2553N2563N2573N2583N259Maximum instantaneous forward voltage drop per legat 3.14 AV F 1.1V Maximum DC reversecurrent at rated DC blocking voltage per legT A = 25 °C T A = 125 °C I R 5.0500µATypical junction capacitance per legat 4.0 V , 1 MHz C J25pF2KBP005M thru 2KBP10M, 3N253 thru 3N259Document Number 8853208-Jul-05Vishay Semiconductors3Package outline dimensions in inches (millimeters)Figure 4. Typical Reverse Leakage Characteristics Per Leg。

RA30H4047M中文资料

MITSUBISHI RF MOSFET MODULERA30H4047M400-470MHz 30W 12.5V MOBILE RADIOELECTROSTATIC SENSITIVE DEVICEOBSERVE HANDLING PRECAUTIONSDESCRIPTIONThe RA30H4047M is a 30-watt RF MOSFET Amplifier Module for 12.5-volt mobile radios that operate in the 400- to 470-MHz range.The battery can be connected directly to the drain of the enhancement-mode MOSFET transistors. Without the gate voltage (V GG =0V), only a small leakage current flows into the drain and the RF input signal attenuates up to 60 dB. The output power and drain current increase as the gate voltage increases. With a gate voltage around 4V (minimum), output power and drain current increases substantially. The nominal output power becomes available at 4.5V (typical) and 5V (maximum). At V GG =5V, the typical gate current is 1 mA.This module is designed for non-linear FM modulation, but may also be used for linear modulation by setting the drain quiescent current with the gate voltage and controlling the output power with the input power.FEATURES• Enhancemen- Mode MOSFET Transistors (I DD ≅0 @ V DD =12.5V, V GG =0V)• P out >30W, ηT >40% @ V DD =12.5V, V GG =5V, P in =50mW • Broadband Frequency Range: 400-470MHz• Low-Power Control Current I GG =1mA (typ) at V GG =5V • Module Size: 66 x 21 x 9.88 mm• Linear operation is possible by setting the quiescent drain current with the gate voltage and controlling the output power with the input powerORDERING INFORMATION:ORDER NUMBER SUPPLY FORM RA30H4047M-E01RA30H4047M-01(Japan - packed without desiccator)Antistatic tray, 10 modules/tray1 RF Input (Pin )2 Gate Voltage (VGG ), Power Control3 Drain Voltage (V DD ), Battery4 RF Output (P out )5 RF Ground (Case)SALES CONTACTJAPAN:Mitsubishi Electric Corporation Semiconductor Sales Promotion Department 2-2-3 Marunouchi, Chiyoda-kuTokyo, Japan 100Email: sod.sophp@hq.melco.co.jp Phone: +81-3-3218-4854Fax: +81-3-3218-4861GERMANY:Mitsubishi Electric Europe B.V. SemiconductorGothaer Strasse 8D-40880 Ratingen, Germany Email: @ Phone: +49-2102-486-0Fax: +49-2102-486-3670HONG KONG:Mitsubishi Electric Hong Kong Ltd. Semiconductor Division41/F. Manulife Tower, 169 Electric Road North Point, Hong KongEmail: scdinfo@ Phone: +852 2510-0555Fax: +852 2510-9822 FRANCE:Mitsubishi Electric Europe B.V. Semiconductor25 Boulevard des BouvetsF-92741 Nanterre Cedex, France Email: @ Phone: +33-1-55685-668Fax: +33-1-55685-739SINGAPORE:Mitsubishi Electric Asia PTE Ltd Semiconductor Division307 Alexandra Road#3-01/02 Mitsubishi Electric Building, Singapore 159943Email: semicon@ Phone: +65 64 732 308Fax: +65 64 738 984 ITALY:Mitsubishi Electric Europe B.V. SemiconductorCentro Direzionale Colleoni, Palazzo Perseo 2, Via ParacelsoI-20041 Agrate Brianza, Milano, Italy Email: @ Phone: +39-039-6053-10Fax: +39-039-6053-212TAIWAN:Mitsubishi Electric Taiwan Company, Ltd., Semiconductor Department9F, No. 88, Sec. 6Chung Shan N. RoadTaipei, Taiwan, R.O.C.Email: metwnssi@ Phone: +886-2-2836-5288Fax: +886-2-2833-9793 U.K.:Mitsubishi Electric Europe B.V. SemiconductorTravellers Lane, Hatfield Hertfordshire, AL10 8XB, England Email: @ Phone: +44-1707-278-900Fax: +44-1707-278-837U.S.A.:Mitsubishi Electric & Electronics USA, Inc. Electronic Device Group1050 East Arques AvenueSunnyvale, CA 94085Email: customerservice@ Phone: 408-730-5900Fax: 408-737-1129CANADA:Mitsubishi Electric Sales Canada, Inc. 4299 14th AvenueMarkham, Ontario, Canada L3R OJ2 Phone: 905-475-7728Fax: 905-475-1918AUSTRALIA:Mitsubishi Electric Australia, Semiconductor Division348 Victoria Road Rydalmere, NSW 2116 Sydney, AustraliaEmail: semis@ Phone: +61 2 9684-7210+61 2 9684 7212+61 2 9684 7214+61 3 9262 9898 Fax: +61 2 9684-7208+61 2 9684 7245元器件交易网。

MM74HC594中文资料

Logic Diagram
MM74HC594

2
元器件交易网
MM74HC594
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operation Conditions
Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD)
General Description
This high speed shift register utilizes advanced silicon-gate CMOS technology. This device possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating—plastic “N” package: −12 mW/°C from 65°C to 85°C.

MIL-PRF-19500中文资料

MIL-PRF-19500/376E 31 August 2000SUPERSEDINGMIL-PRF-19500/376D 21 August 1998PERFORMANCE SPECIFICATIONSEMICONDUCTOR DEVICE, TRANSISTOR, NPN, SILICON, LOW-POWERTYPES 2N2484, 2N2484UA, 2N2484UB, JAN, JANTX, JANTXV, JANS, JANHC, AND JANKCThis specification is approved for use by all Departments and Agencies of the Department of Defense.1. SCOPE1.1 Scope. This specification covers the performance requirements for NPN, silicon, low-power transistors. Four levels of product assurance is provided for each device type as specified in MIL-PRF-19500. Two levels of product assurance are provided for die.1.2 Physical dimensions. See figure 1 (similar to T0-18), figures 2 and 3 (surface mount case outlines UA and UB), and figures 4 and 5 (die).1.3 Maximum ratings.P TV CBOV EBOV CEOI CT J and T STGR θJAR θJCTypesT A = +25°CmWV dc V dc V dc mA dc °C °C/W °C/W 2N2484500 (1)6066050-65 to +2003251462N2484UA 650 (2)6066050-65 to +2002101602N2484UB500 (1)6066050-65 to +200325146(1)Derate linearly at 3.08 mW/°C above T A = +37.5°C (2)Derate linearly at 4.76 mW/°C above T A = +63.5°C. 1.4 Primary electrical characteristics.h feC obo|h fe |2V CE(sat) (1)LimitsV CE = 5 V dc I C = 1 mA dc f = 1 kHzI E = 0V CB = 5 V dc 100 kHz ≤ f ≤ 1 MHzI C = 500 µA dc V CE = 5 V dc f = 30 MHzI C = 1.0 mA dc I B = 0.1 mA dcMin Max250900pF5.02.07.0V dc 0.3(1) Pulsed (see 4.5.1).AMSC N/AFSC 5961DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.The documentation and process conversion measures necessary to comply with this revision shall be completed by 31 November 2000.INCH-POUND Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Defense Supply Center, Columbus, ATTN: DSCC/VAC,Post Office Box 3990, Columbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.2Dimensions Symbol Inches Millimeters NoteMin Max Min Max CD .178.195 4.52 4.95CH .170.210 4.32 5.33HD .209.230 5.31 5.84LC .100 TP 2.54 TP 6LD .016.0210.410.537,8LL .500.75012.7019.057,8LU .016.0190.410.487,8L1---.050--- 1.277,8L2.250--- 6.35---7,8Q ---.040---0.865TL .028.0480.71 1.223,4TW .036.0460.91 1.173r ---.010---0.2510α45° TP 45° TP6NOTES:1.Dimension are in inches.2.Metric equivalents are given for general information only.3.Beyond r (radius) maximum, TW shall be held for a minimum length of .011 (0.28 mm).4.Dimension TL measured from maximum HD.5.Body contour optional within zone defined by HD, CD, and Q.6.Leads at gauge plane .054 +.001 -.000 inch (1.37 +0.03 -0.00 mm) below seating plane shallbe within .007 inch (0.18 mm) radius of true position (TP) at maximum material condition (MMC) relative to tab at MMC.7.Dimension LU applies between L 1 and L 2. Dimension LD applies between L 2 and LLminimum. Diameter is uncontrolled in L 1 and beyond LL minimum.8.All three leads.9.The collector shall be internally connected to the case.10.Dimension r (radius) applies to both inside corners of tab.11.In accordance with ANSI Y14.5M, diameters are equivalent to φx symbology.12.Lead 1 = emitter, lead 2 = base, lead 3 = collector.FIGURE 1. Physical dimensions (similar to TO-18).3DimensionsSymbol Inches Millimeters Note Min Max Min Max A .061.075 1.55 1.903A1.029.0410.74 1.04B1.022.0280.560.71B2.075 REF 1.91 REF B3.006.0220.150.565D .145.155 3.68 3.93D1.045.055 1.14 1.39D2.0375 BSC .952 BSC D3---.155--- 3.93E .215.225 5.46 5.71E3---.225--- 5.71L1.032.0480.81 1.22L2.072.088 1.83 2.23L3.003.0070.080.185NOTES:1.Dimensions are in inches.2.Metric equivalents are given for general information only.3.Dimension "A" controls the overall package thickness. When a window lid is used, dimension "A" mustincrease by a minimum of .010 inch (0.254 mm) and a maximum of .040 inch (1.020 mm).4.The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown onthe drawing.5.Dimensions "B3" minimum and "L3" minimum and the appropriately castellation length define anunobstructed three-dimensional space traversing all of the ceramic layers in which a castellation was designed. (Castellations are required on bottom two layers, optional on top ceramic layer.) Dimension "B3" maximum and "L3" maximum define the maximum width and depth of the castellation at any point on its surface. Measurement of these dimensions may be made prior to solder dipping.6.Lead 4 = no connection.FIGURE 2. Physical dimensions, surface mount (2N2484UA).4DimensionsInches Millimeters NotesLtrMin.Max.Min.Max.A .046.0560.97 1.42A1.017.0350.430.89B1.016 .024 0.41 0.61 3D .085 .108 2.41 2.74 D1 .071 .079 1.81 2.01 D2 .035 .039 0.89 0.99 D3E .115 .128 2.82 3.25 E3 L1.022.0380.560.964NOTES:1.Dimensions are in inches.2.Metric equivalents are given for general information only.3.Dimensions B2 and B3 are identical to B14.Dimension L2 is identical to L1.FIGURE 3. Physical dimensions, surface mount (2N2484UB).5A- versionNOTES:1.Die size...............................................0.015 x 0.019 inches ± 0.001 inch2.Die thickness.......................................0.010 ± 0.0015 inches3.Top metal............................................Aluminum 15,000Å minimum, 18,000Å nominal4.Back metal..........................................A.Gold 2,500Å minimum, 3,000Å nominalB.Eutectic Mount – No Gold5.Backside.............................................Collector6.Bonding pad........................................B = 0.003 inches, E = 0.004 inches diameter7.Passivation.........................................Si 3N 4 (Silicon Nitride) 2kÅ min, 2.2kÅ nom.FIGURE 4. Physical dimensions, JANHC and JANKC die, A - version.B - versionDie size:.....................................................0.018 x 0.018 inchesDie thickness:............................................0.008 ± 0.0016 inchesBase pad:..................................................0.0025 inches diameterEmitter pad:...............................................0.003 inches diameterBack metal:................................................Gold, 6500 ± 1950 ÅTop metal:.................................................Aluminum, 19500 ± 2500 ÅBack side:..................................................Collector Glassivation:..............................................SiO2, 7500 ± 1500 ÅFIGURE 5. Physical dimensions, JANHC and JANKC die, B - version.61.4 Primary electrical characteristics.NFI C = 10 µA dc, V CE = 5 V dcR g = 10 kΩh FE2h FE5f = 100 Hz f = 1000 Hz f = 10 kHz V CE = 5 V dcI C = 10 µA dc V CE = 5 V dc I C = 1 mA dcMin Max dB7.5dB3dB22005002508002. APPLICABLE DOCUMENTS2.1 General. The documents listed in this section are specified in sections 3 and 4 of this specification. This section does not include documents cited in other sections of this specification or recommended for additional information or as examples. While every effort has been made to ensure the completeness of this list, document users are cautioned that they must meet all specified requirements documents cited in sections 3 and 4 of this specification, whether or not they are listed.2.2 Government documents.2.2.1 Specifications, standards, and handbooks. The following specifications, standards, and handbooks form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation (see 6.2).SPECIFICATIONDEPARTMENT OF DEFENSEMIL-PRF-19500 - Semiconductor Devices, General Specification for.STANDARDDEPARTMENT OF DEFENSEMIL-STD-750 - Test Methods for Semiconductor Devices.(Unless otherwise indicated, copies of the above specifications, standards, and handbooks are available from the Document Automation and Production Services (DAPS), Building 4D (DPM-DODSSP), 700 Robbins Avenue, Philadelphia, PA 19111-5094.)2.3 Order of precedence. In the event of a conflict between the text of this document and the references cited herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained.73. REQUIREMENTS3.1 General. The requirements for acquiring the product described herein shall consist of this document and MIL-PRF-19500.3.2 Qualification. Devices furnished under this specification shall be products that are manufactured by a manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturer’s list (QML) before contract award (see4.2 and 6.3).3.3 Abbreviations, symbols, and definitions. Abbreviations, symbols, and definitions used herein shall be as specified in MIL-PRF-19500.3.4 Interface and physical dimensions. The interface and physical dimensions shall be as specified in MIL-PRF-19500 and figures 1, 2, 3, 4, and 5 herein.3.4.1 Lead finish. Unless otherwise specified, lead finish shall be solderable in accordance with MIL-PRF-19500, and herein.3.5 Marking. Marking shall be in accordance with MIL-PRF-19500. At the option of the manufacturer, marking may be omitted from the body, but shall be retained on the initial container.3.6 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in 1.3, 1.4, and table I.3.7 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table I herein.3.8 Workmanship. Semiconductor devices shall be processed in such a manner as to be uniform in quality and shall be free from other defects that will affect life, serviceability, or appearance.4. VERIFICATION4.1 Classification of inspections. The inspection requirements specified herein are classified as follows:a. Qualification inspection (see 4.2).b. Screening (see 4.3).c. Conformance inspection (see 4.4).4.2 Qualification inspection. Qualification inspection shall be in accordance with MIL-PRF-19500 and as specified herein.4.2.1. JANHC and JANKC Qualification. JANHC and JANKC qualification inspection shall be in accordance with MIL-PRF-19500.84.3 Screening (JANS, JANTX, and JANTXV levels only). Screening shall be in accordance with table IV of MIL-PRF-19500, and as specified herein. The following measurements shall be made in accordance with table I herein. Devices that exceed the limits of table I herein shall not be acceptable.Screen (see tableIVMeasurementof MIL-PRF-19500)JANS level JANTX and JANTXV levels 3c Thermal impedance (see 4.3.2)Thermal impedance (see 4.3.2)9I CBO2, h FE4Not applicable1048 hours minimum48 hours minimum11I CBO2; h FE4;∆I CBO2 = 100% of initial value or 2 nA dc,whichever is greater.∆h FE4 = ±15%I CBO2 ,h FE412See 4.3.1240 hours minimum See 4.3.180 hours minimum13Subgroups 2 and 3 of table I herein;∆I CBO2 = 100% of initial value or 2 nA dc,whichever is greater;∆h FE4 = ±15%Subgroup 2 of table I herein;∆I CBO2 = 100% of initial value or 2 nA dc, whichever is greater;∆h FE4 = ±25%4.3.1 Power burn-in conditions. Power burn-in conditions are as follows: V CB = 10 to 30 V dc:Power shall be applied to achieve T J = 135°C minimum and a minimum power dissipation = 75 percent of maximum rated P T (see 1.3). T A = room ambient as defined in 4.5 of MIL-STD-750.NOTE: No heat sink or forced air cooling on the devices shall be permitted.4.3.2 Thermal impedance (ZθJX measurements). The ZθJX measurements shall be performed in accordance with method 3131 of MIL-STD-750.a. I M measurement current-------------5 mA.b. I H forward heating current -----------50 mA (min).c. t H heating time -------------------------25 - 30 ms.d. t md measurement delay time ------60 µs max.e. V CE collector-emitter voltage ------10 V dc minimum.The maximum limit for ZθJX under these test conditions are ZθJX (max) = 150°C/W for 2N2484, ZθJX (max) = 67°C/W for 2N2484UA and 2N2484UB.94.4 Conformance inspection. Conformance inspection shall be in accordance with MIL-PRF-19500, and as specified herein. If alternate screening is being performed in accordance with MIL-PRF-19500, a sample of screened devices shall be submitted to and pass the requirements of group A1 and A2 inspection only (table VIb, group B, subgroup 1 is not required to be performed again if group B has already been satisfied in accordance with 4.4.2).4.4.1 Group A inspection. Group A inspection shall be conducted in accordance with MIL-PRF-19500 and table I herein.4.4.2 Group B inspection. Group B inspection shall be conducted in accordance with the conditions specified for subgroup testing in table VIa (JANS) of MIL-PRF-19500 and 4.4.2.1. Electrical measurements (end-points) shall be in accordance with group A, subgroup 2 herein. Delta requirements shall be in accordance with table III herein. See 4.4.2.2 for JAN, JANTX, and JANTXV group B testing. Electrical measurements (end-points) and delta requirements for JAN, JANTX, and JANTXV shall be after each step in 4.4.2.2 and shall be in accordance with group A, subgroup 2 herein. Delta requirements shall be after each step and shall be in accordance with table III herein.4.4.2.1 Group B inspection, table VIa (JANS) of MIL-PRF-19500.Subgroup Method ConditionB41037V CB = 10 V dcB5 1027V CB = 10 V dc; T A = +125°C ±25°C for 96 hours with P T adjusted according to the chosen T A to give T J = +275°C minimum. Optionally, the test may be conducted forminimum 216 hours with P T adjusted to achieve T J = 225°C minimum, sample size (foroption) n = 45, c = 0. In this case, the ambient temperature shall be adjusted such that aminimum 75 percent of maximum rated P T (see 1.3) is applied to the device under test.(Note: If a failure occurs, resubmission shall be at the test conditions of the originalsample.)4.4.2.2 Group B inspection, (JAN, JANTX, and JANTXV). Separate samples may be used for each step. In the event of a group B failure, the manufacturer may pull a new sample at double size from either the failed assembly lot or from another assembly lot from the same wafer lot. If the new “assembly lot” option is exercised, the failed assembly lot shall be scrapped.Step Method Condition11039Steady-state life: Test condition B, 340 hours, V CB = 10 -30 V dc, T J = 150°C min.,external heating of the device under test to achieve T J = +150°C minimum is allowedprovided that a minimum of 75% of rated power is dissipated. No heat sink or forced-aircooling on the devices shall be permitted. n = 45 devices, c = 021039The steady state life test of step 1 shall be extended to 1,000 hours for each die design.Samples shall be selected from a wafer lot every twelve months of wafer production.Group B, step 2 shall not be required more than once for any single wafer lot. n = 45,c = 0.31032High-temperature life (non-operating), t = 340 hours, T A = +200°C. n = 22, c = 0.104.4.2.3 Group B sample selection. Samples selected from group B inspection shall meet all of the following requirements:a.For JAN, JANTX, and JANTXV, samples shall be selected randomly from a minimum of three wafers (orfrom each wafer in the lot) from each wafer lot. For JANS, samples shall be selected from each inspection lot. See MIL-PRF-19500.b.Must be chosen from an inspection lot that has been submitted to and passed group A, subgroup 2conformance inspection. When the final lead finish is solder or any plating prone to oxidation at hightemperature, the samples for life test (subgroups B4 and B5 for JANS, and group B for JAN, JANTX, and JANTXV) may be pulled prior to the application of final lead finish.4.4.3 Group C inspection, Group C inspection shall be conducted in accordance with the conditions specified for subgroup testing in table VII of MIL-PRF-19500, and in 4.4.3.1 (JANS).and 4.4.3.2 (JAN, JANTX, and JANTXV) herein for group C testing. Electrical measurements (end-points) shall be in accordance with group A, subgroup 2 herein. Delta requirements shall be in accordance with table III herein.4.4.3.1 Group C inspection, table VII (JANS) of MIL-PRF-19500.Subgroup Method ConditionC22036Test condition E (not applicable to UA and UB suffix devices).C610261,000 hours at V CB = 10 -30 V dc; power shall be applied to achieve T J = 150°C minimum and a minimum power dissipation P D = 75 percent of maximum rated P T as defined in 1.3herein.4.4.3.2 Group C inspection, table VII (JAN, JANTX, and JANTXV) of MIL-PRF-19500.Subgroup Method ConditionC2 2036Test condition E (not applicable to UA and UB suffix devices).C6Not applicable.4.4.3.3 Group C sample selection. Samples for subgroups in group C shall be chosen at random from any inspection lot containing the intended package type and lead finish procured to the same specification which is submitted to and passes group A tests for conformance inspection. Testing of a subgroup using a single device type enclosed in the intended package type shall be considered as complying with the requirements for that subgroup.4.4.4 Group E inspection. Group E inspection shall be performed for qualification or re-qualification only. The tests specified in table II herein must be performed to maintain qualification.4.5 Method of inspection. Methods of inspection shall be as specified in the appropriate tables and as follows.4.5.1 Pulse measurements. Conditions for pulse measurement shall be as specified in section 4 of MIL-STD-750.1112TABLE I. Group A inspection.MIL-STD-750LimitInspection 1/MethodConditionsSymbolMinMaxUnitSubgroup 1 2/Visual and mechanical examination 3/2071n = 45 devices, c = 0Solderability 3/ 4/2026n = 15 leads, c = 0Resistance to solvents 3/ 4/ 5/1022n = 15 devices, c = 0Temperature cycling 3/ 4/1051Test condition C, 25 cycles.n = 22 devices, c = 0 Hermetic seal 4/1071n = 22 devices, c = 0Fine leak Gross leakElectrical measurements 4/Group A, subgroup 2Bond strength 3/ 4/2037Precondition T A = +250°C at t = 24 hrs or T A = 300°C at t = 2 hrs; n = 11 wires, c = 0Subgroup 2Collector to emitter breakdown voltage3011Bias condition D; I C = 10 mA dc pulsed (see 4.5.1)V (BR)CEO 60V dcCollector to base cutoff current 3036Bias condition D; V CB = 60 V dc I CBO110µA dc Emitter to base cutoff current 3061Bias condition D; V EB = 6 V dc I EBO110µA dc Collector to base cutoff current 3036Bias condition D; V CB = 45 V dc I CBO25nA dc Collector to emitter cutoff current3041Bias condition D; V CE = 5 V dc I CEO 2nA dc Emitter to base cutoff current 3061Bias condition D; V EB = 5 V dc I EBO22nA dc Collector to emitter cutoff current3041Bias condition C; V CE = 45 V dc I CES 5nA dcForward-current transfer ratio3076V CE = 5 V dc; I C = 1 µA dch FE145See footnote at end of table.13TABLE I. Group A inspection - Continued.MIL-STD-750LimitInspection 1/MethodConditionsSymbolMinMaxUnitSubgroup 2 - continued.Forward-current transfer ratio 3076V CE = 5 V dc; I C = 10 µA dc h FE2200500Forward-current transfer ratio 3076V CE = 5 V dc; I C = 100 µA dc h FE3225675Forward-current transfer ratio 3076V CE = 5 V dc; I C = 500 µA dc h FE4250800Forward-current transfer ratio 3076V CE = 5 V dc; I C = 1 mA dc h FE5250800Forward-current transfer ratio 3076V CE = 5 V dc; I C = 10 mA dc pulsed (see 4.5.1)h FE6225800Collector to emitter voltage (saturated)3071I C = 1.0 mA dc; I B = 100 µA dc V CE(sat)0.3V dc Base emitter voltage (nonsaturated)3066Test condition B; V CE = 5 V dc;I C = 100 µA dcV BE(ON)0.50.7V dcSubgroup 3High-temperature operation T A = +150°CCollector to base cutoff current 3036Bias condition D; V CB = 45 V dc I CBO310µA dcLow-temperature operation T A = -55°CForward-current transfer ratio 3076V CE = 5 V dc; I C = 10 µA dch FE735Subgroup 4Magnitude of common emitter small-signal short-circuit forward-current transfer ratio 3306V CE = 5 V dc; I C = 50 µA dc;f = 5 MHz|h fe |13.0Magnitude of common emitter small-signal short-circuitforward- current transfer ratio 3306V CE = 5 V dc; I C = 500 µA dc;f = 30 MHz|h fe |2 2.07.0Small-signal open-circuit output admittance3216V CE = 5 V dc; I C = 1.0 mA dc;f = 1 kHzh oe 40µmhosSmall-signal open- circuit reverse-voltage transfer ratio 3211V CE = 5 V dc; I C = 1.0 mA dc;f = 1 kHzh re 8.0 x 10-4Small-signal short- circuit input impedance3201V CE = 5 V dc; I C = 1 mA dc;f = 1 kHzh ie3.524k ΩSee footnote at end of table.14TABLE I. Group A inspection - Continued.MIL-STD-750LimitInspection 1/MethodConditionsSymbolMinMaxUnitSubgroup 4 - continued.Small-signal short- circuit forward current transfer ratio 3206V CE = 5 V dc; I C = 1 mA dc;f = 1 kHzh fe 250900Open circuit output capacitance3236V CB = 5 V dc; I E = 0;100 kHz ≤ f ≤ 1 MHz C obo 5.0pFInput capacitance (output open-circuited)3240V EB = 0.5 V dc; I C = 0;100 kHz ≤ f ≤ 1 MHzC ibo 6.0pF Noise figure3246f = 100 Hz; V CE = 5 V dc; I C = 10µA dc; Rg = 10 k Ω;NF17.5dBNoise figure 3246 f = 1 kHz; V CE = 5 V dc; I C = 10µA dc; R g = 10 k Ω;NF23dBNoise figure 3246 f = 10 kHz; V CE = 5 V dc; I C = 10µA dc; R g = 10 k Ω;NF32dBNoise figure (wideband)3246Noise bandwidth = 10 Hz to 15.7kHz; V CE = 5 V dc; I C = 10 µA dc;R g = 10 k Ω;NF43dBSubgroups 5 and 6Not applicable Subgroup 7 4/Decap internal visual (design verification)2075n = 1 device, c = 01/For sampling plan see MIL-PRF-19500.2/For resubmission of failed subgroup A1, double the sample size of the failed test or sequence of tests. Afailure in group A, subgroup 1 shall not require retest of the entire subgroup. Only the failed test shall be rerun upon submission.3/Separate samples may be used.4/Not required for JANS devices.5/Not required for laser marked devices.TABLE II. Group E inspection (all quality levels) - For qualification only.Inspection MIL-STD-750QualificationMethod ConditionsSubgroup 1Temperature cycling (air to air)Hermetic sealFine leakGross leak Electrical measurements Subgroup 2 Intermittent lifeElectrical measurements Subgroup 3Not applicable Subgroup 4Not applicable Subgroup 5Not applicable 105110711037Test condition C, 500 cyclesSee group A, subgroup 2 and table III herein.Intermittent operation life: V CB = 10 V dc ,6,000 cycles.See group A, subgroup 2 and table III herein.12 devicesc = 045 devicesc = 015TABLE III. Groups B and C delta measurements. 1/ 2/ 3/Step Inspection MIL-STD-750Symbol Limit UnitMethod Conditions1Forward-current transfer ratio 3076V CE = 5 V dc; I C = 500µA dc; pulsed see 4.5.14/∆h FE4±25 percent change frominitial recorded reading2.Collector to emittervoltage (saturated)3071I C = 1.0 mA dc; I B = 100µA dc∆V CE(sat)4/ 5/±50 mV dc change frompreviously measured value.3.Collector to emittercutoff current 3041Bias condition C;V CB = 45 V dc∆I CES4/100 percent of initial valueor 2 nA dc, whichever isgreater.1/The delta measurements for group B, table VIa (JANS) of MIL-PRF-19500 are as follows:a.Subgroup 4, see table III herein, step 2.b.Subgroup 5, see table III herein, steps 1 and 3.2/The delta measurements for 4.4.2.2 herein (group B, JAN, JANTX, and JANTXV) are as follows: Steps 2 and 3 of table III shall be performed after each step in 4.4.2.2 herein.3/The delta measurements for group C, table VII of MIL-PRF-19500 are as follows: Subgroup 6, see table III herein, steps 1 and 3 for JANS, step 1 for JAN, JANTX, and JANTXV.4/Devices which exceed the group A limits for this test shall not be accepted.5/Applies to JANS level only.165. PACKAGING5.1 Packaging. For acquisition purposes, the packaging requirements shall be as specified in the contract or order (see6.2). When actual packaging of materiel is to be performed by DoD personnel, these personnel need to contact the responsible packaging activity to ascertain requisite packaging requirements. Packaging requirements are maintained by the Inventory Control Points' packaging activity within the Military Department or Defense Agency, or within the Military Departments' System Command. Packaging data retrieval is available from the managing Military Departments' or Defense Agency's automated packaging files, CD-ROM products, or by contacting the responsible packaging activity.6. NOTES(This section contains information of a general or explanatory nature that may be helpful, but is not mandatory.)6.1 Intended use. The notes specified in MIL-PRF-19500 are applicable to this specification.6.2 Acquisition requirements. Acquisition documents should specify the following:a.Title, number, and date of this specification.b.Issue of DoDISS to be cited in the solicitation, and if required, the specific issue of individual documentsreferenced (see 2.2.1).c.Lead formation and finish may be specified (see 3.4.1).d.Type designation and product assurance level.e.Packaging requirements (see 5.1).6.3 Qualification. With respect to products requiring qualification, awards will be made only for products which are, at the time of award of contract, qualified for inclusion in Qualified Manufacturers List QML-19500 whether or not such products have actually been so listed by that date. The attention of the contractors is called to these requirements, and manufacturers are urged to arrange to have the products that they propose to offer to the Federal Government tested for qualification in order that they may be eligible to be awarded contracts or orders for the products covered by this specification. Information pertaining to qualification of products may be obtained from Defense Supply Center, Columbus, ATTN: DSCC-VQE, P.O. Box 3990, Columbus, OH 43216-5000.6.4 Suppliers of JANHC die. The qualified JANHC suppliers with the applicable letter version (example JANHCA1N645-1) will be identified on the QML.JANC ordering informationPIN Manufacturer43611341562N2484JANHCA2N2484JANHCB2N2484JANKCA2N2484JANKCB2N24846.5 Changes from previous issue. Marginal notations are not used in this revision to identify changes with respect to the previous issue due to the extensiveness of the changes.17。

M74VHC1GT08DFT2G中文资料

MC74VHC1GT082−Input AND Gate/CMOS Logic Level ShifterThe MC74VHC1GT08 is an advanced high speed CMOS 2−input AND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.The device input is compatible with TTL−type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input,allowing the device to be used as a logic−level translator from 3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V CMOS Logic while operating at the high−voltage power supply.The MC74VHC1GT08 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHC1GT08 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when V CC = 0 V . These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch,battery backup, hot insertion, etc.Features•High Speed: t PD = 3.5 ns (Typ) at V CC = 5 V•Low Power Dissipation: I CC = 1 m A (Max) at T A = 25°C •TTL−Compatible Inputs: V IL = 0.8 V; V IH = 2 V•CMOS−Compatible Outputs: V OH > 0.8 V CC ; V OL < 0.1 V CC @Load •Power Down Protection Provided on Inputs and Outputs •Balanced Propagation Delays•Pin and Function Compatible with Other Standard Logic Families •Chip Complexity: FETs = 64; Equivalent Gates = 15•Pb−Free Packages are AvailableV CCIN B IN AOUT YGNDIN A IN BOUT Y &Figure 1. Pinout (Top View)Figure 2. Logic Symbol12345PIN ASSIGNMENT123GND IN B IN A 45V CCOUT Y L L H HL H L HFUNCTION TABLEInputsOutput AB L L L HY See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.ORDERING INFORMATIONMARKING DIAGRAMSSC−88A/SOT−353/SC−70DF SUFFIX CASE 419ATSOP−5/SOT−23/SC−59DT SUFFIXCASE 4831515VT = Device Code M = Date Code*G = Pb−Free Package*Date Code orientation and/or position may vary depending upon manufacturing location.(Note: Microdot may be in either location)15VT M G G MMAXIMUM RATINGSSymbol CharacteristicsValue Unit V CC DC Supply Voltage −0.5 to +7.0V V IN DC Input Voltage −0.5 to +7.0V V OUT DC Output Voltage V CC = 0High or Low State−0.5 to 7.0−0.5 to V CC + 0.5V I IK Input Diode Current −20mA I OK Output Diode Current V OUT < GND; V OUT > V CC+20mA I OUT DC Output Current, per Pin +25mA I CC DC Supply Current, V CC and GND +50mA P D Power dissipation in still air SC−88A, TSOP−5200mW q JA Thermal resistanceSC−88A, TSOP−5333°C/W T L Lead temperature, 1 mm from case for 10 s 260°C T J Junction temperature under bias +150°C T stg Storage temperature −65 to +150°C V ESDESD Withstand VoltageHuman Body Model (Note 1)Machine Model (Note 2)Charged Device Model (Note 3)> 2000> 200N/A VI LatchupLatchup Performance Above V CC and Below GND at 125°C (Note 4)±500mAStresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.Tested to EIA/JESD22−A114−A2.Tested to EIA/JESD22−A115−A3.Tested to JESD22−C101−A4.Tested to EIA/JESD78RECOMMENDED OPERATING CONDITIONSSymbol CharacteristicsMin Max Unit V CC DC Supply Voltage 3.0 5.5V V IN DC Input Voltage 0.0 5.5V V OUT DC Output VoltageV CC = 0High or Low State0.00.0 5.5V CC V T A Operating Temperature Range −55+125°C t r , t fInput Rise and Fall TimeV CC = 3.3 V ± 0.3 V V CC = 5.0 V ± 0.5 V 0010020ns/VDevice Junction Temperature versus Time to 0.1% Bond FailuresJunction Temperature °CTime, Hours Time, Years801,032,200117.890419,30047.9100178,70020.411079,6009.412037,000 4.213017,800 2.01408,9001.011101001000TIME, YEARSN O R M A L I Z E D F A I L U R E R A T EFigure 3. Failure Rate vs. Time Junction TemperatureDC ELECTRICAL CHARACTERISTICSSymbol Parameter Test Conditions V CC(V)T A = 25°C T A≤ 85°C−55 ≤ T A≤ 125°CUnit Min Typ Max Min Max Min MaxV IH Minimum High−LevelInput Voltage 3.04.55.51.42.02.01.42.02.01.42.02.0VV IL Maximum Low−LevelInput Voltage 3.04.55.50.530.80.80.530.80.80.530.80.8VV OH Minimum High−LevelOutput VoltageV IN = V IH or V IL V IN = V IH or V ILI OH = −50 m A3.04.52.94.43.04.52.94.42.94.4VV IN = V IH or V ILI OH = −4 mAI OH = −8 mA3.04.52.583.942.483.802.343.66VV OL Maximum Low−LevelOutput VoltageV IN = V IH or V IL V IN = V IH or V ILI OL = 50 m A3.04.50.00.00.10.10.10.10.10.1VV IN = V IH or V ILI OL = 4 mAI OL = 8 mA3.04.50.360.360.440.440.520.52VI IN Maximum InputLeakage Current V IN = 5.5 V or GND0 to5.5±0.1±1.0±1.0m AI CC Maximum QuiescentSupply CurrentV IN = V CC or GND 5.5 1.02040m AI CCT Quiescent SupplyCurrentInput: V IN = 3.4 V 5.5 1.35 1.50 1.65mAI OPD Output LeakageCurrentV OUT = 5.5 V0.00.5 5.010m A AC ELECTRICAL CHARACTERISTICS C load = 50 pF, Input t r = t f= 3.0 nsSymbol Parameter Test ConditionsT A = 25°C T A≤ 85°C−55 ≤ T A≤ 125°CUnit Min Typ Max Min Max Min Maxt PLH, t PHL Maximum PropagationDelay, Input A or B to YV CC = 3.3 ± 0.3 V C L = 15 pFC L = 50 pF4.15.98.812.310.514.012.516.5nsV CC = 5.0 ± 0.5 V C L = 15 pFC L = 50 pF3.54.25.97.97.09.09.011.0C IN Maximum Input Capaci-tance5.5101010pFC PD Power Dissipation Capacitance (Note 5)Typical @ 25°C, V CC = 5.0 VpF115.C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.Average operating current can be obtained by the equation: I CC(OPR) = C PD V CC f in + I CC. C PD is used to determine the no−load dynamic power consumption; P D = C PD V CC2 f in + I CC V CC.*Includes all probe and jig capacitanceC L *GNDInput A or BOutput YV OLV OH Figure 4. Switching WaveformsFigure 5. Test CircuitORDERING INFORMATIONDevicePackageShipping †MC74VHC1GT08DFT1SC−88A / SOT−353 / SC−703000 / Tape & ReelM74VHC1GT08DFT1G SC−88A / SOT−353 / SC−70(Pb−Free)MC74VHC1GT08DFT2SC−88A / SOT−353 / SC−70M74VHC1GT08DFT2G SC−88A / SOT−353 / SC−70(Pb−Free)MC74VHC1GT08DTT1TSOP−5 / SOT−23 / SC−59M74VHC1GT08DTT1GTSOP−5 / SOT−23 / SC−59(Pb−Free)†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.PACKAGE DIMENSIONSNOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.419A−01 OBSOLETE. NEW STANDARD 419A−02.4.DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.DIM A MIN MAX MIN MAX MILLIMETERS1.802.200.0710.087INCHES B 1.15 1.350.0450.053C 0.80 1.100.0310.043D 0.100.300.0040.012G 0.65 BSC 0.026 BSC H −−−0.10−−−0.004J 0.100.250.0040.010K 0.100.300.0040.012N 0.20 REF 0.008 REF S2.00 2.200.0790.087SC−88A, SOT−353, SC−70CASE 419A−02ISSUE J*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*PACKAGE DIMENSIONSTSOP−5CASE 483−02ISSUE FNOTES:1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.2.CONTROLLING DIMENSION: MILLIMETERS.3.MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.4.DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.5.OPTIONAL CONSTRUCTION: ANADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY .DIM MIN MAX MILLIMETERS A 3.00 BSC B 1.50 BSC C 0.90 1.10D 0.250.50G 0.95 BSC H 0.010.10J 0.100.26K 0.200.60L 1.25 1.55M 0 10 S2.503.00__ǒmm inchesǓ*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*2X2XON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。

T8XX-XXXH中文资料

®1/11Table 1: Main FeaturesDESCRIPTIONAvailable either in through-hole or surface-mount packages, the BTA08, BTB08 and T8 triac series is suitable for general purpose AC switching. They can be used as an ON/OFF function in applica-tions such as static relays, heating regulation, in-duction motor starting circuits... or for phase control operation in light dimmers, motor speed controllers,...The snubberless versions (BTA/BTB...W and T8series) are specially recommended for use on inductive loads, thanks to their high commutation performances.Logic level versions are designed to interface directly with low power drivers such as microcontrollers.By using an internal ceramic pad, the BTA series provides voltage insulated tab (rated at 2500V RMS ) complying with UL standards (file ref.:E81734).Symbol Value Unit I T(RMS)8A V DRM /V RRM 600 and 800V I GT (Q 1)5 to 50mABTA08, BTB08 and T8 Series8A TRIAC SREV. 6February 2006SNUBBERLESS™, LOGIC LEVEL & STANDARDTable 2: Order CodesPart Number Marking BTA08-xxxxxRG See page table 8 onpage 10BTB08-xxxxxRG T8xx-xxxG T8xx-xxxH T8xx-xxxBBTA08, BTB08 and T8 Series2/11Table 3: Absolute Maximum Ratings Tables 4: Electrical Characteristics (T j = 25°C, unless otherwise specified)■SNUBBERLESS and Logic Level (3 quadrants)Symbol ParameterValue Unit I T(RMS)RMS on-state current (full sine wave)IPAK/D 2PAK/DPAK/TO-220AB T c = 110°C 8ATO-220AB Ins.T c = 100°C I TSM Non repetitive surge peak on-state current (full cycle, T j initial = 25°C) F = 50 Hz t = 20 ms 80A F = 60 Hz t = 16.7 ms84I ²t I ²t Value for fusingt p = 10 ms 36A ²s dI/dt Critical rate of rise of on-state cur-rent I G = 2 x I GT , t r ≤ 100 ns F = 120 Hz T j = 125°C 50A/µs I GM Peak gate currentt p = 20 µsT j = 125°C 4A P G(AV)Average gate power dissipation T j = 125°C1W T stg T jStorage junction temperature rangeOperating junction temperature range- 40 to + 150- 40 to + 125°CSymbol Test ConditionsQuad-rantT8BTA08 / BTB08Unit T810T835TW SW CW BW I GT (1)V D = 12 V R L = 30 ΩI - II -III MAX.10355103550mA V GT I - II - III MAX.1.3V V GD V D = V DRM R L = 3.3 k ΩT j = 125°C I - II - IIIMIN.0.2V I H (2)I T = 100 mA MAX.153510153550mA I L I G = 1.2 I GTI - III MAX.255010255070mAII306015306080dV/dt (2)V D = 67 %V DRM gate open T j = 125°CMIN.4040020404001000V/µs (dI/dt)c (2)(dV/dt)c = 0.1 V/µs T j = 125°CMIN.5.4- 3.5 5.4--A/ms(dV/dt)c = 10 V/µs T j = 125°C2.8- 1.5 2.98--Without snubber T j = 125°C- 4.5-- 4.57BTA08, BTB08 and T8 Series3/11■Standard (4 quadrants)Table 5: Static Characteristics Table 6: Thermal resistance Symbol Test ConditionsQuadrant BTA08 / BTB08Unit C B I GT (1)V D = 12 V R L = 30 ΩI - II - III IV MAX.255050100mA V GT ALL MAX. 1.3V V GD V D = V DRM R L = 3.3 k Ω T j = 125°C ALLMIN.0.2V I H (2)I T = 500 mA MAX.2550mA I L I G = 1.2 I GTI - III - IVMAX.4050mA II80100dV/dt (2)V D = 67 %V DRM gate open T j = 125°CMIN.200400V/µs (dV/dt)c (2)(dI/dt)c = 5.3 A/ms T j = 125°C MIN.510V/µsSymbol Test ConditionsValueUnit V T (2)I TM = 11 A t p = 380 µs T j = 25°C MAX. 1.55V V to (2)Threshold voltage T j = 125°C MAX.0.85V R d (2)Dynamic resistance T j = 125°C MAX.50m ΩI DRM I RRMV DRM = V RRMT j = 25°C MAX.5µA T j = 125°C1mANote 1: minimum I GT is guaranted at 5% of I GT max.Note 2: for both polarities of A2 referenced to A1.Symbol ParameterValue Unit R th(j-c)Junction to case (AC)IPAK / D 2PAK / DPAK / TO-220AB 1.6°C/WTO-220AB Insulated 2.5R th(j-a)Junction to ambientS = 1 cm ²D 2PAK 45°C/WS = 0.5 cm ²DPAK70TO-220AB / TO-220AB Insulated 60IPAK100S = Copper surface under tab.BTA08, BTB08 and T8 Series4/11Figure 1: Maximum power dissipation versus RMS on-state current (full cycle)Figure 2: RMS on-state current versus case temperature (full cycle)Figure 3: RMS on-state current versus ambient temperature (printed circuit board FR4, copper thickness: 35µm) (full cycle)Figure 4: Relative variation of thermal impedance versus pulse durationFigure 5: On-state characteristics (maximum values)Figure 6: Surge peak on-state current versus number of cyclesBTA08, BTB08 and T8 Series5/11Figure 7: Non-repetitive surge peak on-state current for a sinusoidal pulse with width t p < 10 ms and corresponding value of I 2tFigure 8: Relative variation of gate trigger current, holding current and latching current versus junction temperature (typical values)Figure 9: Relative variation of critical rate of decrease of main current versus (dV/dt)c (typical values) (Snubberless & L ogic level types)Figure 10: Relative variation of critical rate of decrease of main current versus (dV/dt)c (typical values) (Standard types)Figure 11: Relative variation of critical rate of decrease of main current versus junction temperatureFigure 12: DPAK and D 2P AK Thermal resistance junction to ambient versus copper surface under tab (printed circuit board FR4, copper thickness:35µm)BTA08, BTB08 and T8 Series6/11Figure 13: Ordering Information Scheme (BTA08 and BTB08 series)Figure 14: Ordering Information Scheme (T8 series)Table 7: Product SelectorPart NumberVoltage (xxx)Sensitivity Type Package 600 V 800 V BTA/BTB08-xxxB X X 50 mA Standard TO-220AB BTA/BTB08-xxxBW X X 50 mA Snubberless TO-220AB BTA/BTB08-xxxC X X 25 mAStandard TO-220AB BTA/BTB08-xxxCW X X 35 mA Snubberless TO-220AB BTA/BTB08-xxxSW X X 10 mA Logic level TO-220AB BTA/BTB08-xxxTW X X 5 mA Logic Level TO-220AB T810-xxxG X X 10 mA Logic Level D2PAK T810-xxxH X X 10 mA Logic Level IPAK T835-xxxB X X 35 mA Snubberless DPAK T835-xxxG X X 35 mA Snubberless D 2PAK T835-xxxHXX35 mASnubberlessIPAKBTB: non insulated TO-220AB packageBTA08, BTB08 and T8 Series Figure 15: D2PAK Package Mechanical DataFigure 16: D2PAK Foot Print Dimensions(in millimeters)7/11BTA08, BTB08 and T8 SeriesFigure 17: DPAK Package Mechanical DataFigure 18: DPAK Foot Print Dimensions (in millimeters)8/11BTA08, BTB08 and T8 Series9/11BTA08, BTB08 and T8 Series10/11In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: .Table 8: Ordering InformationOrdering type Marking Package Weight Base qtyDelivery modeBTA/BTB08-xxxyzRGBTA/BTB08-xxxyzTO-220AB 2.3 g 50Tube T8yy-xxxG T8yyxx D 2PAK 1.5 g 50Tube T8yy-xxxG-TR T8yyxx 1000Tape & reel T8yy-xxxB T8yyxx DPAK 0.3 g 75Tube T8yy-xxxB-TR T8yyxx 2500Tape & reel T8yy-xxxHT8yyxxIPAK0.4 g75TubeNote: xxx = voltage, yy = sensitivity, z = typeTable 9: Revision HistoryDate Revision Description of ChangesApr-20025A Last update.13-Feb-20066TO-220AB delivery mode changed from bulk to tube.ECOPACK statement added.元器件交易网BTA08, BTB08 and T8 Series Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequencesof use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grantedby implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subjectto change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are notauthorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronics.All other names are the property of their respective owners© 2006 STMicroelectronics - All rights reservedSTMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America11/11。

K9K4G08Q0M资料

GENERAL DESCRIPTION
Offered in 512Mx8bit or 256Mx16bit, the K9XXGXXXXM is 4G bit with spare 128M bit capacity. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typical 300µs on the 2112byte(X8 device) or 1056-word(X16 device) page and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device) or 64K-word(X16 device) block. Data in the data page can be read out at 50ns cycle time per byte(30ns, only X8 3.3v device) or word(X16 device). The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9XXGXXXXM′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9XXGXXXXM is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. An ultra high density solution having two 4Gb stacked with two chip selects is also available in standard TSOPI package.

M24C04-W1BN6T中文资料

1/25October 2005M24C16, M24C08M24C04, M24C02, M24C0116Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I²C Bus EEPROMFEATURES SUMMARY■Two-Wire I²C Serial Interface Supports 400kHz Protocol ■Single Supply Voltage:– 2.5 to 5.5V for M24Cxx-W – 1.8 to 5.5V for M24Cxx-R ■Write Control Input■BYTE and PAGE WRITE (up to 16 Bytes)■RANDOM and SEQUENTIAL READ Modes ■Self-Timed Programming Cycle ■Automatic Address Incrementing ■Enhanced ESD/Latch-Up Protection ■More than 1 Million Erase/Write Cycles ■More than 40-Year Data Retention ■Packages–ECOPACK® (RoHS compliant)Table 1. Product ListReference Part NumberM24C16M24C16-W M24C16-R M24C08M24C08-W M24C08-R M24C04M24C04-W M24C04-R M24C02M24C02-W M24C02-R M24C01M24C01-W M24C01-RM24C16, M24C08, M24C04, M24C02, M24C01TABLE OF CONTENTSFEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Device internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4DEVICE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Acknowledge in Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242/253/25M24C16, M24C08, M24C04, M24C02, M24C01SUMMARY DESCRIPTIONThese I²C-compatible electrically erasable pro-grammable memory (EEPROM) devices are orga-nized as 2048/1024/512/256/128x 8 (M24C16,M24C08, M24C04, M24C02 and M24C01).In order to meet environmental requirements, ST offers these devices in ECOPACK® packages.ECOPACK® packages are Lead-free and RoHS compliant.ECOPACK is an ST trademark. ECOPACK speci-fications are available at: .I²C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The devic-es carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I²C bus definition.The device behaves as a slave in the I²C protocol,with all memory operations synchronized by the serial clock. Read and Write operations are initiat-ed by a Start condition, generated by the bus mas-ter. The Start condition is followed by a Device scribed in Table 3.), terminated by an acknowl-edge bit.When writing data to the memory, the device in-serts an acknowledge bit during the 9th bit time,following the bus master’s 8-bit transmission.When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.Table 2. Signal NamesDevice internal resetIn order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up (continuous rise of V CC ),the device will not respond to any instructions until the V CC has reached the Power On Reset threshold voltage (this threshold is lower than the V CC min. operating voltage defined in DC and AC PARAMETERS ). When V CC has passed over the POR threshold, the device is reset and is in Standby Power mode. At Power-down (continuous decay of V CC ), as soon as V CC drops from the normal operating voltage to below the Power On Reset threshold voltage, the device stops responding to any instruction sent to it.Prior to selecting and issuing instructions to the memory, a valid and stable V CC voltage must be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t W ).Note: 1.NC = Not Connected2.See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.E0, E1, E2Chip Enable SDA Serial Data SCL Serial Clock WCWrite Control V CC Supply Voltage V SSGroundM24C16, M24C08, M24C04, M24C02, M24C014/25SIGNAL DESCRIPTIONSerial Clock (SCL).This input signal is used to strobe all data in and out of the device. In applica-tions where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to V CC . (Figure 5. indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchro-nization is not employed, and so the pull-up resis-tor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.Serial Data (SDA).This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Se-rial Data (SDA) to V CC . (Figure 5. indicates how the value of the pull-up resistor can be calculated).Chip Enable (E0, E1, E2).These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to V CC or V SS , to establish the Device Select Code as shown in Figure 4.for protecting the entire contents of the memory from inadvertent write operations. Write opera-tions are disabled to the entire memory array when nected, the signal is internally read as V IL , and Write operations are allowed.Select and Address bytes are acknowledged,Data bytes are not acknowledged.M24C16, M24C08, M24C04, M24C02, M24C01Table 3. Device Select CodeDevice Type Identifier1Chip Enable2,3RWb7b6b5b4b3b2b1b0M24C01 Select Code1010E2E1E0RWM24C02 Select Code1010E2E1E0RWM24C04 Select Code1010E2E1A8RWM24C08 Select Code1010E2A9A8RWM24C16 Select Code1010A10A9A8RW Note: 1.The most significant bit, b7, is sent first.2.E0, E1 and E2 are compared against the respective external pins on the memory device.3.A10, A9 and A8 represent most significant bits of the address.5/25M24C16, M24C08, M24C04, M24C02, M24C016/25DEVICE OPERATIONThe device supports the I²C protocol. This is sum-marized in Figure 6.. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver.The device that controls the data transfer is known as the bus master, and the other as the slave de-vice. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24Cxx device is always a slave in all communication.Start ConditionStart is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition,and will not respond unless one is given.Stop ConditionStop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driv-en High. A Stop condition terminates communica-tion between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal Write cycle.Acknowledge Bit (ACK)The acknowledge bit is used to indicate a success-ful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.Data InputDuring data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL).For correct device operation, Serial Data (SDA)must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driv-en Low.Memory AddressingTo start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 3.(on Serial Data (SDA), most significant bit first).The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address”(E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is 1010b.Each device is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the val-ue on the Chip Enable (E0, E1, E2) inputs. How-ever, those devices with larger memory capacities (the M24C16, M24C08 and M24C04) need more address bits. E0 is not available for use on devices that need to use address line A8; E1 is not avail-able for devices that need to use address line A9,and E2 is not available for devices that need to use address line A10 (see Figure 3. and Table 3. for details). Using the E0, E1 and E2 inputs, up to eight M24C02 (or M24C01), four M24C04, two M24C08 or one M24C16 devices can be connect-ed to one I²C bus. In each case, and in the hybrid cases, this gives a total memory capacity of 16Kbits, 2KBytes (except where M24C01 devic-es are used).The 8th set to 1 for Read and 0 for Write operations.If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Stand-by mode.Table 4. Operating ModesNote: 1.X = V IH or V IL .ModeRW bit WC 1Bytes Initial SequenceCurrent Address Read 1X 1START , Device Select, RW = 1Random Address Read 0X 1START , Device Select, RW = 0, Address 1X reST ART, Device Select, RW = 1Sequential Read 1X ≥ 1Similar to Current or Random Address Read Byte Write 0V IL 1START , Device Select, RW = 0Page WriteV IL≤ 16START , Device Select, RW = 0M24C16, M24C08, M24C04, M24C02, M24C01Figure 7. Write Mode Sequences with WC=1 (data write inhibited)Following a Start condition the bus master sends a Device Select Code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8., and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a Stop condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and the de-vice does not respond to any requests.Byte WriteAfter the Device Select code and the address byte, the bus master sends one data byte. If the ad-dressed location is Write-protected, by Write Con-trol (WC) being driven High (during the period from byte), the device replies to the data byte with NoAck, as shown in Figure 7., and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by gener-ating a Stop condition, as shown in Figure 8.. Page WriteThe Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way.The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If the addressed loca-ing driven High (during the period from the Start7/25M24C16, M24C08, M24C04, M24C02, M24C018/25condition until the end of the address byte), the de-vice replies to the data bytes with NoAck, as shown in Figure 7., and the locations are not mod-ified. After each byte is transferred, the internalbyte address counter (the 4 least significant ad-dress bits only) is incremented. The transfer is ter-minated by the bus master generating a Stop condition.M24C16, M24C08, M24C04, M24C02, M24C01During the internal Write cycle, the device discon-nects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (t w) is shown in Table 13. and Table 14., but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master.The sequence, as shown in Figure 9., is:–Step 1: the bus master issues a Start condition followed by a Device Select Code (the firstbyte of the new instruction).–Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and thebus master goes back to Step 1. If the device has terminated the internal Write cycle, itresponds with an Ack, indicating that thedevice is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).9/25M24C16, M24C08, M24C04, M24C02, M24C0110/25Read OperationsRead operations are performed independently of The device has an internal address counter which is incremented each time a byte is read.Random Address ReadA dummy Write is first performed to load the ad-dress into this address counter (as shown in Fig-ure 10.) but without sending a Stop condition.Then, the bus master sends another Start condi-tion, and repeats the Device Select Code, with the Read/Write bit (RW) set to 1. The device acknowl-edges this, and outputs the contents of the ad-dressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.Current Address ReadFor the Current Address Read operation, following a Start condition, the bus master only sends a De-to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condi-tion, as shown in Figure 10., without acknowledg-ing the byte.Sequential ReadThis operation can be used after a Current Ad-dress Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the de-vice continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10.. The output data comes from consecutive address-es, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h.Acknowledge in Read ModeFor all Read commands, the device waits, aftereach byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device termi-nates the data transfer and switches to its Stand-by mode.INITIAL DELIVERY STATEThe device is delivered with all bits in the memory array set to 1 (each byte contains FFh).11/2512/25MAXIMUM RATINGStressing the device outside the ratings listed in Table 5. may cause permanent damage to the de-vice. These are stress ratings only, and operation of the device at these, or any other conditions out-side those indicated in the Operating sections of this specification, is not implied. Exposure to Ab-solute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.Table 5. Absolute Maximum RatingsNote: pliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, andthe European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU2.AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)Symbol ParameterMin.Max.Unit T A Ambient Operating Temperature –40125°C T STG Storage Temperature–65150°C T LEAD Lead T emperature during Soldering 1°C V IO Input or Output range –0.50 6.5V V CC Supply Voltage–0.50 6.5V V ESDElectrostatic Discharge Voltage (Human Body model) 2–40004000V13/25DC AND AC PARAMETERSThis section summarizes the operating and mea-surement conditions, and the DC and AC charac-teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de-rived from tests performed under the Measure-ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame-ters.Table 6. Operating Conditions (M24Cxx-W)Table 7. Operating Conditions (M24Cxx-R)Table 8. DC Characteristics (M24Cxx-W, Device Grade 6)Note: 1.The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.Symbol ParameterMin.Max.Unit V CC Supply Voltage2.5 5.5V T AAmbient Operating T emperature (Device Grade 6)–4085°C Ambient Operating T emperature (Device Grade 3)–40125°CSymbol ParameterMin.Max.Unit V CC Supply Voltage1.8 5.5V T AAmbient Operating T emperature–4085°CSymbol ParameterTest Condition(in addition to those in Table 6.)Min.Max.Unit I LI Input Leakage Current(SCL, SDA, E0, E1,and E2)V IN = V SS or V CC± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CCSupply CurrentV CC =5V , f c =400kHz (rise/fall time < 30ns)2mA V CC =2.5V , f c =400kHz (rise/fall time < 30ns)1mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 5V 1µA V IN = V SS or V CC , V CC = 2.5V0.5µA V IL Input Low Voltage (1)–0.450.3V CC V V IH Input High Voltage (1)0.7V CCV CC +1V V OLOutput Low VoltageI OL = 2.1mA, V CC = 2.5V0.4V14/25Table 9. DC Characteristics (M24Cxx-W, Device Grade 3)Note: 1.The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.Table 10. DC Characteristics (M24Cxx-R)Note: 1.The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.Table 11. AC Measurement ConditionsSymbol ParameterTest Condition(in addition to those in Table 6.)Min.Max.Unit I LI Input Leakage Current(SCL, SDA, E0, E1,and E2)V IN = V SS or V CC± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CCSupply CurrentV CC =5V , f C =400kHz (rise/fall time < 30ns)3mA V CC =2.5V , f C =400kHz (rise/fall time < 30ns)3mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 5V 5µA V IN = V SS or V CC , V CC = 2.5V2µA V IL Input Low Voltage (1)–0.450.3V CC V V IH Input High Voltage (1)0.7V CCV CC +1V V OLOutput Low VoltageI OL = 2.1mA, V CC = 2.5V0.4VSymbol ParameterTest Condition(in addition to those in Table 7.)Min.Max.Unit I LI Input Leakage Current(SCL, SDA, E0, E1,and E2)V IN = V SS or V CC± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CC Supply CurrentV CC =1.8V , f c =400kHz (rise/fall time < 30ns)0.8mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 1.8V0.3µA V IL Input Low Voltage (1) 2.5V ≤ V CC –0.450.3V CC V 1.8V ≤ V CC < 2.5V–0.450.25V CC V V IH Input High Voltage (1)0.7V CC V CC +1V V OLOutput Low VoltageI OL = 0.7mA, V CC = 1.8V 0.2VSymbol ParameterMin.Max.Unit C LLoad Capacitance 100pF Input Rise and Fall Times 50ns Input Levels0.2V CC to 0.8V CC V Input and Output Timing Reference Levels0.3V CC to 0.7V CCV15/25Table 12. Input ParametersNote: 1.T A = 25°C, f = 400kHz2.Sampled only, not 100% tested.Symbol Parameter 1,2Test ConditionMin.Max.Unit C IN Input Capacitance (SDA)8pF C IN Input Capacitance (other pins)6pF Z WCL WC Input Impedance V IN < 0.3V 1570k ΩZ WCH WC Input Impedance V IN > 0.7V CC 500k Ωt NSPulse width ignored(Input Filter on SCL and SDA)Single glitch100nsTable 13. AC Characteristics (M24Cxx-W)Test conditions specified in Table 6. and Table 11.Symbol Alt.Parameter Min.Max.Unitf C f SCL Clock Frequency400kHzt CHCL t HIGH Clock Pulse Width High600ns t CLCH t LOW Clock Pulse Width Low1300nst DL1DL2 2t F SDA Fall Time20300ns t DXCX t SU:DAT Data In Set Up Time100ns t CLDX t HD:DA T Data In Hold Time0ns t CLQX t DH Data Out Hold Time200ns t CLQV 3t AA Clock Low to Next Data Valid (Access Time)200900ns t CHDX 1t SU:ST A Start Condition Set Up Time600ns t DLCL t HD:ST A Start Condition Hold Time600ns t CHDH t SU:STO Stop Condition Set Up Time600ns t DHDL t BUF Time between Stop Condition and Next Start Condition1300ns t W 4t WR Write Time5ms Note: 1.For a reSTART condition, or following a Write cycle.2.Sampled only, not 100% tested.3.To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.4.Previous devices bearing the process letter “L” in the package marking guarantee a maximum write time of 10ms. For more infor-mation about these devices and their device identification, please ask your ST Sales Office for Process Change Notices PCN MPG/ EE/0061 and 0062 (PCEE0061 and PCEE0062).Table 14. AC Characteristics (M24Cxx-R)Test conditions specified in Table 7. and Table 10.Symbol Alt.Parameter Min. 4Max. 4Unitf C f SCL Clock Frequency400kHzt CHCL t HIGH Clock Pulse Width High600ns t CLCH t LOW Clock Pulse Width Low1300nst DL1DL2 2t F SDA Fall Time20300ns t DXCX t SU:DAT Data In Set Up Time100ns t CLDX t HD:DA T Data In Hold Time0ns t CLQX t DH Data Out Hold Time200ns t CLQV 3t AA Clock Low to Next Data Valid (Access Time)200900ns t CHDX 1t SU:ST A Start Condition Set Up Time600ns t DLCL t HD:ST A Start Condition Hold Time600ns t CHDH t SU:STO Stop Condition Set Up Time600ns t DHDL t BUF Time between Stop Condition and Next Start Condition1300ns t W t WR Write Time10ms Note: 1.For a reSTART condition, or following a Write cycle.2.Sampled only, not 100% tested.3.To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.4.This is preliminary information.16/2517/25PACKAGE MECHANICALTable 15. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical DataSymb.mm inchesTyp.Min.Max.Typ.Min.Max.A 5.330.210A10.380.015A2 3.30 2.92 4.950.1300.1150.195 b0.460.360.560.0180.0140.022 b2 1.52 1.14 1.780.0600.0450.070 c0.250.200.360.0100.0080.014 D9.279.0210.160.3650.3550.400 E7.877.628.260.3100.3000.325 E1 6.35 6.107.110.2500.2400.280e 2.54––0.100––eA7.62––0.300––eB10.920.430 L 3.30 2.92 3.810.1300.1150.15018/25Note:Drawing is not to scale.Table 16. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical DataSymb.mm inchesTyp.Min.Max.Typ.Min.Max.A 1.35 1.750.0530.069A10.100.250.0040.010B0.330.510.0130.020C0.190.250.0070.010D 4.80 5.000.1890.197E 3.80 4.000.1500.157e 1.27––0.050––H 5.80 6.200.2280.244h0.250.500.0100.020L0.400.900.0160.035α0°8°0°8°N88CP0.100.00419/25Note: 1.Drawing is not to scale.2.The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to V SS. It must not be allowed to be connected toany other voltage or signal line on the PCB, for example during the soldering process.Table 17. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², DataSymbolmm inchesTyp.Min.Max.Typ.Min.Max.A0.550.500.600.0220.0200.024 A10.000.050.0000.002 b0.250.200.300.0100.0080.012D 2.000.079D2 1.55 1.650.0610.065 ddd0.050.002E 3.000.118E20.150.250.0060.010 e0.50––0.020––L0.450.400.500.0180.0160.020 L10.150.006 L30.300.012N8820/25。

M81019FP中文资料

Absolute Maximum Ratings, Ta = 25°C unless otherwise speciﬁed
Characteristics High Side Floating Supply Absolute Voltage High Side Floating Supply Offset Voltage High Side Floating Supply Voltage (VBS = VB – VS) High Side Output Voltage Low Side Fixed Supply Voltage Power Ground Low Side Output Voltage Logic Input Voltage (HIN, LIN, FO_RST) FO Input/Output Voltage CIN Input Voltage Allowable Offset Voltage Slew Rate Package Power Dissipation (Ta = 25°C, On Board) Linear Derating Factor (Ta > 25°C, On Board) Junction to Case Thermal Resistance Junction Temperature Operation Temperature Storage Temperature Symbol VB VS VBS VHO VCC VNO VLO VIN VFO VCIN dVs/dt Pd Kθ Rth(j-c) Tj Topr Tstg M81019FP -0.5 ~ 1224 VB-24 ~ VB+0.5 -0.5 ~ 24 VS-0.5 ~ VB+0.5 -0.5 ~ 24 VCC-24 ~ VCC+0.5 VNO-0.5 ~ VCC+0.5 -0.5 ~ VCC+0.5 -0.5 ~ VCC+0.5 -0.5 ~ VCC+0.5 ±50 ~1.6 ~16 ~60 -20 ~ 150 -20 ~ 125 -40 ~ 150 Units Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts V/ns Watts mW/°C � � ��

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12 Clintonville Road, Northford, CT 06472-1610 USA • Tel: (203) 484-7161 • Fax: (203) 484-7118Specifications are for information only, are not intended for installation purposes, and are subject to change without notice. No responsibility is assumed by Gamewell-FCI for their use.9020-0466 Rev. E2 page 1 of 37100 SeriesFeaturesListed per ANSI/UL 864 9th Edition 120 or 240 VAC (optional) input line voltage Front panel programming with day/night sensitivity adjustments80-character alpha-numeric displayOne or two Style 4 (Class “B”) signaling line circuits. Style 6 (Class “A”) with optional CAOM Module Two Style Y (Class “B”) regulated notification appliance circuits rated for 1.5 amp. each. Style Z (Class “A”) with optional CAOM ModuleSuitable for pre-action deluge applications with optional MCOM ModulePeriodic trouble reminderIndividual sensor drift compensationDual-stage maintenance alerts (“dirty” and “very dirty”)Multilevel sensor sensitivity adjustments (front panel programmable)continued on the next page7100 SeriesSIGNALINGS186********7165-0694:219 (7100)7300-0694:231 (LCD-7100)7300-0694:241 (LDM-7100)An ISO 9000-2000 CompanyGAMEWELL-FCI12 Clintonville Road, Northford, CT 06472-1610 USA • Tel: (203) 484-7161 • Fax: (203) 484-71189020-0466 Rev. E2 page 2 of Description (Continued)Remote Station, Proprietary, and Central Station fire alarm systems. It allows ample space for wiring and room for bat-teries up to 7 A/H capacity.•Features (Continued)•Alarm verification per individual sensor•Positive alarm sequence for sensors or monitor modules•Four levels of system access using six (6), digit pass-words with up to five (5), user passwords per Level •Duplicate and extra address indications•March time (60 or 120 BPM)/temporal pattern/coded fours/California Code/user-defined zone coding •Cross zoning•System configuration programming and 280 event log stored in non-volatile memory•Fan restart with sequential restart delay•Upload/download of panel configuration between panel and FCP-7100 program (password protected feature)•Up to sixty-four (64), 7100 panels in the E3 Broadband network with an optional INI-7100 ModuleOptional AccessoriesLCD-7100The LCD-7100 remote serial display offers an 80-character alphanumeric readout for the remote display of all system events. It duplicates all the information on the 7100 Series panel display and provides key switch protected functions such as System Reset, Alarm Acknowledge, Trouble Acknowledge, Signal Silence, and Drill Test.LEDs on the LCD-7100 indicate Alarm, Supervisory, Sys-tem Trouble, Power Fault, Systems Silenced, NAC#1, and NAC#2 Silenced conditions.The LCD-7100 can be surface or semi-flush mounted on a standard four-gang electrical box. It can be installed up to 4,000 feet (1,219 m) from the main control panel. The 7100Series fire alarm control panel supports up to five (5),remote LCD-7100 annunciators using one pair of twisted,non-shielded 18 AWG min. wire or serial communication and uses another pair of 16 AWG min. for operating volt-age.(For additional information, refer to the LCD-7100 data sheet, Part Number: 9020-0486).LDM-7100The LED Driver Module (LDM-7100) is designed to mount in a UL Listed remote annunciator and provides outputs for remote panel switches and thirty-three (33), remote LEDs.Three (3), LDM-7100 modules may be installed in a single annunciator for a total of ninety-nine (99), LEDs per annun-ciator. This combination may be repeated up to five times for a total of fifteen (15), LDM-7100 panels installed at up to five (5), different locations. Maximum distances of up to 4,000 feet (1,219 m) can be achieved using one pair of twisted, non-shielded wire for serial communication and using another pair of straight-lay wire for operating voltage.(For additional information, refer to the LDM-7100 data sheet, Part Number: 9020-0519).•CAOMThe Class “A” Optional Module (CAOM) allows Style Y and Z (Class “B” and “A”) operation for both Notification Appli-ance Circuits and allows Style 4 and 6 (Class “B” and “A”)for both Signaling Line Circuits. It also provides disconnect switches for each signaling line circuit and a common dis-connect switch for both notification appliance circuits.•MCOMThe Municipal Connection Option Module (MCOM) pro-vides three (3) choices of outputs. It can be configured as a Municipal Circuit (City Box) output. It may also be set to serve as a Reverse Polarity output with a nominal voltage output of 24 VDC at 0.012 amp. maximum alarm and supervisory current. The MCOM’s third option provides a releasing solenoid output rated at:•24 VDC nominal voltage.•0.005 amp. supervisory current.•0.710 amp. maximum alarm current.• 2 ohms maximum line resistance.PTRMThe Printer Transient Module (PTRM) provides RS-232Isolator/Transient protection for the 7100’s RS-232 port (BSM connector J2). It is used in conjunction with a serial printer applied to the RS-232 port for permanent record keeping.•INI-7100The Intelligent Network Interface Module allows the 7100Series fire alarm control panel to become the platform of a peer-to-peer, token ring, self-regenerative network com-prised of up to sixty-four (64), 7100 panels.GAMEWELL-FCI12 Clintonville Road, Northford, CT 06472-1610 USA • Tel: (203) 484-7161 • Fax: (203) 484-7118 9020-0466 Rev. E2 page 3 of 3SpecificationsPrimary Input Power120 VAC, 50/60 Hz @ 2.0 amps. or 240 VAC, 50/60 Hz @ 1.0 amp.Output Power 4 amps. @ 24 VDC (total)Non-resettable Power:1.0 amp. max.1.0 amp. max. from both circuitsResettable Power: 1.0 amp. max. Two (2) NotificationAppliance Circuits:1.5 amp. each @ 24 VDC Current:Supervisory Alarm 7100-1 (One SLC)0.065 amp.0.085 amp. 7100-1D (One SLC w/DACT)0.085 amp.0.105 amp. 7100-2 (Two SLC)0.065 amp.0.085 amp. 7100-2D(Two SLC w/DACT)0.085 amp.0.105 amp. LCD-7100.012 amp..023 amp. LDM-7100.012 amp..023 amp.(All LEDs lit)INI-7100-UTP ,-FO 0.040 amp.0.040 amp.OperatingTemperature:32° - 120° F (0° - 49° C)Relative Humidity:85 % (non-condensing)Battery Charger Capacity:31 A/H (Cabinet accommodates12 A/H size batteries)Alarm & Trouble Relay Contacts:Form “C”, 2 amps. @ 24 VDC(resistive)Ordering InformationSystems ModelDescription7100-17100 Addressable System, 1 SLC mounted in enclosureDimensions:19 3/8” x 19 3/8” (49 x 49 cm) Enclosure 7100-1D 7100 Addressable FACP w/DACT, 1 SLC mounted in enclosureDimensions:19 3/8” x 19 3/8” (49 x 49 cm) EnclosureBasic KitsBK-7100-2Basic System Kit, 2 SLC(BSM, Keypad Display, Transformer)BK-7100-2D Basic System Kit w/DACT, 2 SLC BK-7100-2-240V Basic System Kit, 2 SLC, 240 VAC BK-7100-2D-240V Basic System Kit w/DACT, 2 SLCCabinetsEN-7100Enclosure (replacement)CS-7100M Metal Door (replacement)7100-ENCL-M 7100 EnclosureDimensions:16.9” H x 14.4” W x 3” D l (43 H x 37 W x 7.7 D cm)NS-7100B NS-7100R Enclosure, E3 Series Broadband, black Enclosure,E3 Series Broadband, red Dimensions:19 3/8” H x 19 3/8” W x 4” D (49 H x 49 W x 10 D cm)Ordering Information (Continued)Optional ModulesLCD-7100Remote Serial Annunciator, LCD Display (80-character) Dimensions: 4.25” H x 8.25” W x 1.90”(43 H x 37 W x 7.7 D cm)LDM-7100Remote LED Driver Module Dimensions:6” W x 4.50” (15.2 x 11.4 cm)CAOMClass A Option Combination Module with disconnect switches for both signaling line circuits and notification appliance circuitsMCOMMunicipal Connection Option Module for local energy city box reverse polar-ity signaling, or releasing solenoid PTRMPrinter Transient ModuleINI-7100-FO Intelligent Network Interface Module, Fiber-OpticINI-7100-UTPIntelligent Network Interface Module, Unshielded, Twisted-PairReplacement PartsT-7100Transformer, 120 VAC input (replace-ment)T-7100-240Transformer, 240 VAC input (replace-ment)BSM-7100-1Replacement board for 7100-1BSM-7100-1DReplacement board for 7100-1D。