SCAN18245TSSC资料

© 2000 Fairchild Semiconductor Corporation DS010961
October 1991Revised May 2000
SCAN18245T Non-Inverting Transceiver with 3-STATE Outputs
SCAN18245T
Non-Inverting Transceiver with 3-STATE Outputs
General Description
The SCAN18245T is a high speed, low-power bidirectional line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented output enable and direc-tion control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS),and Test Clock (TCK).
Features
s IEEE 1149.1 (JTAG) Compliant s Dual output enable control signals
s 3-STATE outputs for bus-oriented applications s 9-bit data busses for parity applications
s Reduced-swing outputs source 32 mA/sink 64 mA s Guaranteed to drive 50Ω transmission line to TTL input levels of 0.8V and 2.0V s TTL compatible inputs
s 25 mil pitch SSOP (Shrink Small Outline Package)s Includes CLAMP and HIGHZ instructions s Member of Fairchild’s SCAN Products
Ordering Code:
Devices also available in T ape and Reel. Specify by appending the suffix letter “X ” to the ordering code.
Connection Diagram Pin Descriptions
Order Number Package Number
Package Description
SCAN18245TSSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Pin Names Description
A1(0–8)Side A1 Inputs or 3-STATE Outputs B1(0–8)Side B1 Inputs or 3-STATE Outputs A2(0–8)Side A2 Inputs or 3-STATE Outputs B2(0–8)Side B2 Inputs or 3-STATE Outputs G1, G2Output Enable Pins DIR1, DIR2
Direction of Data Flow Pins
2
S C A N 18245T
Truth Table
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Functional Description
The SCAN18245 consists of two sets of nine non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Direction pins (DIR1 and DIR2) LOW enables data from B Ports to A Ports, when
HIGH enables data from A Ports to B Ports. The Output Enable pins (G1 and G2) when HIGH disables both A and B Ports by placing them in a high impedance condition.
Block Diagrams
A1, B1, G1 and DIR1
Note: BSR stands for Boundary Scan Register.A2, B2, G2 and DIR2
Note: BSR stands for Boundary Scan Register.
Tap Controller
Inputs A1 (0–8)B1 (0–8)
Inputs A2 (0–8)B2 (0–8)
G1DIR1G2DIR2L L H ←H L L H ←H L L L ←L L L L ←L L H H →H L H H →H L H L →
L L H L →
L H
X
Z
Z
H
X
Z
Z
SCAN18245T
Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their loca-
tion. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control sys-
tem data. (See IEEE Standard 1149.1 Figure 10–11 for a
further description of scan cell TYPE1 and Figure 10–12 for
a further description of scan cell TYPE2.)
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will acti-
vate their respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition
Logic 0
The INSTRUCTION register is an eight-bit register which
captures the value 00111101.
The two least significant bits of this captured value (01) are
required by IEEE Std 1149.1. The upper six bits are unique
to the SCAN18245T device. SCAN CMOS Test Access
Logic devices do not include the IEEE 1149.1 optional
identification register. Therefore, this unique captured
value can be used as a “pseudo ID” code to confirm that
the correct device is placed in the appropriate location in
the boundary scan chain.
Instruction Register Scan Chain Definition
MSB → LSB
Scan Cell TYPE1
Scan Cell TYPE2
Instruction Code Instruction
00000000EXTEST
10000001SAMPLE/PRELOAD
10000010CLAMP
00000011HIGHZ
All Others BYPASS
4
S C A N 18245T
Boundary-Scan Register
Scan Chain Definition (80 Bits in Length)
SCAN18245T
Boundary-Scan Register Definition Index
Bit No.Pin Name Pin No.Pin Type Scan Cell Type Bit No.Pin Name Pin No.Pin Type Scan Cell Type 79DIR13Input TYPE1Control Signals 35B102Input TYPE1B1–in
78G154
Input TYPE134B114Input TYPE177AOE 1Internal TYPE233B125Input TYPE176BOE 1Internal TYPE232B137Input TYPE175DIR226Input TYPE131B148Input TYPE174G231Input TYPE130B1510Input TYPE173AOE 2Internal TYPE229B1611Input TYPE172BOE 2Internal TYPE228B1713Input TYPE171A1055Input TYPE1A1–in
27B1814Input TYPE170A1153Input TYPE126B2015Input TYPE1B2–in 69A1252Input TYPE125B2116Input TYPE168A1350Input TYPE124B2218Input TYPE167A1449Input TYPE123B2319Input TYPE166A1547Input TYPE122B2421Input TYPE165A1646Input TYPE121B2522Input TYPE164A1744Input TYPE120B2624Input TYPE163A1843Input TYPE119B2725Input TYPE162A2042Input TYPE1A2–in 18B2827Input TYPE161A2141Input TYPE117A1055Output TYPE2A1–out 60A2239Input TYPE116A1153Output TYPE259A2338Input TYPE115A1252Output TYPE258A2436Input TYPE114A1350Output TYPE257A2535Input TYPE113A1449Output TYPE256A2633Input TYPE112A1547Output TYPE255A2732Input TYPE111A1646Output TYPE254A2830Input TYPE110A1744Output TYPE253B102Output TYPE2B1–out 9A1843Output TYPE252B114Output TYPE28A2042Output TYPE2A2–out 51B125Output TYPE27A2141Output TYPE250B137Output TYPE26A2239Output TYPE249B148Output TYPE25A2338Output TYPE248B1510Output TYPE24A2436Output TYPE247B1611Output TYPE23A2535Output TYPE246B1713Output TYPE22A2633Output TYPE245B1814Output TYPE21A2732Output TYPE244B2015Output TYPE2B2–out 0
A28
30
Output
TYPE2
43B2116Output TYPE242B2218Output TYPE241B2319Output TYPE240B2421Output TYPE239B2522Output TYPE238B2624Output TYPE237B2725Output TYPE236
B28
27Output
TYPE2
6
S C A N 18245T
Absolute Maximum Ratings (Note 1)
Recommended Operating Conditions
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with-out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of SCAN circuits outside databook specifications.
DC Electrical Characteristics
Supply Voltage (V CC )−0.5V to +7.0V
DC Input Diode Current (I IK )V I = −0.5V −20 mA V I = V CC +0.5V
+20 mA DC Output Diode Current (I OK )V O = −0.5V −20 mA V O = V CC +0.5V +20 mA
DC Output Voltage (V O )
−0.5V to V CC +0.5V
DC Output Source/Sink Current (I O )±70 mA DC V CC or Ground Current Per Output Pin ±70 mA Junction Temperature SSOP
+140°C
Storage Temperature −65°C to +150°C
ESD (Min)
2000V
Supply Voltage (V CC )SCAN Products 4.5V to 5.5V Input Voltage (V I )0V to V CC Output Voltage (V O )0V to V CC
Operating Temperature (T A )−40°C to +85°C
Minimum Input Edge Rate ∆V/∆t 125 mV/ns
V IN from 0.8V to 2.0V V CC @ 4.5V, 5.5V
Symbol Parameter
V CC T A = +25°C T A = −40°C to +85°C Units Conditions (V)Typ Guaranteed Limits
V IH Minimum HIGH 4.5 1.5 2.0 2.0V V OUT = 0.1V Input Voltage 5.5 1.5 2.0 2.0or V CC −0.1V V IL Maximum LOW 4.5 1.50.80.8V V OUT = 0.1V Input Voltage 5.5 1.5
0.80.8or V CC −0.1V V OH
Minimum HIGH 4.5 3.15 3.15V I OUT = −50 µA Output Voltage 5.5 4.15 4.15(Note 2)
4.5 2.4 2.4V V IN = V IL or V IH
5.5 2.4 2.4
I OH = −32 mA 4.5 2.4V V IN = V IL or V IH 5.5
2.4I OH = −24 mA V OL
Maximum LOW 4.50.10.1V I OUT = 50 µA Output Voltage 5.50.10.1(Note 2)
4.50.550.55V V IN = V IL or V IH
5.50.550.55
I OL = 64 mA 4.50.55V V IN = V IL or V IH 5.5
0.55I OL = 48 mA I IN Maximum Input Leakage Current 5.5±0.1±1.0µA V I = V CC , GND I IN
Maximum Input Leakage
5.5
2.8
3.6µA V I = V CC TDI, TMS
−385−385µA V I = GND Minimum Input Leakage
5.5−160−160µA V I = GND I OLD Minimum Dynamic 5.5
9494mA V OLD = 0.8V Max I OHD Output Current (Note 3)−40
−40mA
V OHD = 2.0V Min I OZT
Maximum I/O 5.5±0.6±6.0µA
V I (OE) = V IL , Leakage Current
V IH V I = V CC , GND V O = V CC , GND
I OS Output Short Circuit Current 5.5−100−100mA (min)V O = 0V I CC
Maximum Quiescent 5.516.088µA V O = HIGH Supply Current
TDI, TMS = V CC 5.5
750
820
µA
V O = HIGH TDI, TMS = GND
SCAN18245T
DC Electrical Characteristics (Continued)
Note 2: All outputs loaded; thresholds associated with output under test.Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Noise Specifications
Note 4: Worst case package.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched LOW and one output held LOW.Note 6: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched HIGH and one output held HIGH.Note 7: Maximum number of data inputs (n) switching. (n-1) input switching 0V to 3V. Input under test switching 3V to threshold (V ILD ).
AC Electrical Characteristics
Normal Operation
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V.
Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Symbol Parameter
V CC T A = +25°C T A = −40°C to +85°C Units Conditions (V)Typ
Guaranteed Limits
I CCt
Maximum I CC Per Input
5.5 2.0 2.0mA V I = V CC –2.1V V I = V CC –2.1V 5.5
2.15
2.15
mA
TDI/TMS Pin, test one with the other floating
Symbol Parameter
V CC T A = +25°C T A = −40°C to +85°C
Units (V)Typ Guaranteed Limits V OLP Maximum HIGH Output Noise 5.0 1.0 1.5V (Note 5)(Note 6)
V OLV Minimum LOW Output Noise 5.0−0.6−1.2V (Note 5)(Note 6)V OHP Maximum Overshoot 5.0V OH +1.0V OH +1.5V (Note 4)(Note 6)V OHV Minimum V CC Droop 5.0V OH −1.0V OH −1.8V (Note 4)(Note 6)
V IHD Minimum HIGH Dynamic Input 5.5 1.6 2.0 2.0V Voltage Level (Note 4)(Note 7)V ILD
Maximum LOW Dynamic Input 5.5
1.4
0.8
0.8
V
Voltage Level (Note 4)(Note 7)
Symbol Parameter
V CC
T A = +25°C T A =−40°C to +85°C
Units
(V)C L = 50 pF
C L = 50 pF (Note 8)Min Typ
Max Min Max t PLH ,Propagation Delay 5.0 1.67.9 1.68.5ns t PHL A to B, B to A 1.67.9 1.68.8t PLZ ,Disable Time 5.0 1.28.6 1.29.5ns t PHZ 1.28.5 1.29.0t PZL ,Enable Time
5.0
1.611.0 1.61
2.0ns t PZH
1.6
8.5
1.6
9.5
8
S C A N 18245T
AC Electrical Characteristics
Scan Test Operation
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V.
Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK.Note: All Propagation Delays involving TCK are measured from the falling edge of TCK.
Symbol Parameter
V CC
T A = +25°C T A =−40°C to +85°C
Units
(V)C L = 50 pF
C L = 50 pF (Note 9)Min Typ
Max Min Max t PLH ,Propagation Delay 5.0 2.813.2 2.814.5ns t PHL TCK to TDO 2.813.2 2.814.5t PLZ ,Disable Time 5.0 2.011.5 2.011.9ns t PHZ TCK to TDO 2.011.5 2.011.9t PZL ,Enable Time 5.0 2.414.5 2.415.8ns t PZH TCK to TDO 2.414.5 2.415.8t PLH ,Propagation Delay 5.0
4.018.0 4.019.8ns t PHL TCK to Data Out 4.018.0 4.019.8During Update-DR State t PLH ,Propagation Delay 4.0
18.6 4.020.2ns
t PHL TCK to Data Out 5.0 4.018.6 4.020.2During Update-IR State t PLH ,Propagation Delay 5.0
4.419.9 4.421.5ns
t PHL
TCK to Data Out 4.4
19.9
4.4
21.5
During Test Logic Reset State
t PLZ ,Propagation Delay 5.0 3.216.4 3.218.2ns
t PHZ TCK to Data Out 3.2
16.4 3.218.2During Update-DR State t PLZ ,Propagation Delay 5.0 2.818.0 2.819.3ns
t PHZ TCK to Data Out 2.8
18.0 2.819.3During Update-IR State t PLZ ,Propagation Delay 5.0 2.818.4 2.820.0ns
t PHZ
TCK to Data Out 2.8
18.4
2.8
20.0
During Test Logic Reset State
t PZL ,Propagation Delay 5.0 4.018.9 4.020.9ns
t PZH TCK to Data Out 4.0
18.9 4.020.9During Update-DR State t PZL ,Propagation Delay 5.0 3.219.9 3.221.7ns
t PZH TCK to Data Out 3.2
19.9 3.221.7During Update-IR State t PZL ,Propagation Delay 5.0 3.621.3 3.623.3ns
t PZH
TCK to Data Out 3.6
21.3
3.6
23.3
During Test Logic Reset State
SCAN18245T
AC Operating Requirements
Scan Test Operation
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V.
Note 11: Timing pertains to the TYPE1 BSR and TYPE2 BSR after the buffer (BSR 0–8, 9–17, 18–26, 27–35, 36–44, 45–53, 54–62, 63–71).Note 12: Timing pertains to BSR 74 and 78 only.Note 13: Timing pertains to BSR 75 and 79 only.Note 14: Timing pertains to BSR 72, 73, 76 and 77 only.
Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Symbol Parameter
V CC
T A = +25°C T A = −40°C to +85°C
Units
(V)C L = 50 pF
C L = 50 pF
(Note 10)Guaranteed Minimum t S Setup Time, H or L 5.00.00.0ns Data to TCK (Note 11)t H Hold Time, H or L 5.0 6.5 6.5ns TCK to Data (Note 11)t S Setup Time, H or L 5.00.00.0ns G1, G2 to TCK (Note 12)t H Hold Time, H or L 5.0 4.0 4.0ns TCK to G1, G2 (Note 12)t S Setup Time, H or L
5.00.00.0ns DIR1, DIR2 to TCK (Note 13)t H Hold Time, H or L
5.0
4.0
4.0
ns
TCK to DIR1, DIR2 (Note 13)t S
Setup Time, H or L ns
Internal AOE n , BOE n 5.0 1.0 1.0to TCK (Note 14)
t H
Hold Time, H or L 5.0 4.0 4.0ns
TCK to Internal AOE n , BOE n (Note 14)
t S Setup Time, H or L 5.07.07.0ns TMS to TCK t H Hold Time, H or L 5.0 2.0 2.0ns TCK to TMS t S Setup Time, H or L 5.0 1.0 1.0ns TDI to TCK t H Hold Time, H or L 5.0 3.5
3.5
ns
TCK to TDI t W
Pulse Width
5.0
ns
H 15.015.0L
5.0
5.0f MAX Maximum TCK 5.02525MHz Clock Frequency T PU Wait Time, 5.0100100ns Power Up to TCK T DN
Power Down 0.0
100
100
ms
Delay
10
S C A N 18245T
Extended AC Electrical Characteristics
Note 15: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)
Note 16: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only.Note 17: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 18: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Note 19: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.The specification applies to any outputs switching HIGH-to-LOW (t OSHL ), LOW-to-HIGH (t OSLH ), or any combination switching LOW-to-HIGH and/or HIGH-to-LOW.
Capacitance
Symbol
Parameter
T A = +25°C, V CC = 5.0V
T A = −40°C to +85°C Units
C L = 50 pF
V CC = 5.0V ± 0.5V 18 Outputs Switching
C L = 250 pF (Note 15)
(Note 16)Min
Typ
Max Min
Max t PLH,Propagation Delay 2.510.5 3.512.0ns t PHL Data to Output 2.510.5 3.5
13.5
t PZH ,Output Enable Time
2.510.5(Note 17)ns t PZL 2.51
3.5t PHZ,Output Disable Time 2.09.5(Note 18)
ns t PLZ 2.0
10.0t OSHL Pin to Pin Skew 0.5 1.0 1.0ns (Note 19)HL Data to Output t OSLH Pin to Pin Skew 0.5 1.0
1.0
ns (Note 19)
LH data to Output Symbol Parameter
Typ Units Conditions
C IN Input Pin Capacitance 4pF V CC = 5.0V C I/O Input/Output Capacitance 20pF V CC = 5.0V C PD
Power Dissipation Capacitance
41
pF
V CC = 5.0V
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1.Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.2. A critical component in any component of a life support
device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
元器件交易网
SCAN18245T Non-Inverting Transceiver with 3-STATE Outputs。